A time synchronization precision evaluation method and device of an SoC system

Abstract

The application provides a time synchronization precision evaluation method of a SoC system. The SoC system is provided with a plurality of cores, wherein a first core is configured to complete global time synchronization between the SoC system and an external clock source based on a time synchronization protocol. The time synchronization precision evaluation method comprises the following steps: a test host computer simultaneously sends a pulse signal to the first core and other cores in the SoC system; when the first core and the other cores detect the pulse signal, the current time information of each core is recorded respectively, and the current time information is kept as the event time of each core in the log information of the SoC system; and the test host computer requests to obtain the log information, calculates the time deviation between each other core and the first core according to the event time in the log information, and evaluates the time synchronization precision of the plurality of cores in the SoC system based on the time deviation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of time synchronization precision evaluation, and in particular to a time synchronization precision evaluation method and device for a SoC system. BACKGROUND

[0002] In the current market, the cross-domain fusion control in the automotive field is mostly implemented by using a SoC system chip architecture containing heterogeneous multi-cores. In a SoC system chip, each heterogeneous core uses system time in respective time synchronization, big data, ADAS function and log recording and the like. The SoC system as a whole acquires and synchronizes the global time from an external time source and transmits the global time between the cores of the internal chips. However, the transmission process itself introduces time errors, resulting in a problem of time synchronization deviation between the internal cores of the SoC multi-core system. The development and acceptance process of clock synchronization needs a suitable tool or method to measure and evaluate the time synchronization errors of the multi-cores in the system, so as to facilitate the developers to master and optimize the time synchronization precision of the multi-cores.

[0003] In the prior art, the SoC system mostly performs clock synchronization based on the PTP / gPTP time synchronization protocol of Ethernet. Usually, only one core of the multiple cores in the SoC system is connected to an external master clock, and the other cores are not directly physically connected to the external clock through Ethernet or the like. Therefore, the time synchronization test instrument or method in the prior art is difficult to be applied to the precision measurement of the time synchronization between the cores in the SoC system.

[0004] In order to overcome the above-mentioned defects in the prior art, there is an urgent need in the field for a time synchronization precision evaluation method and device for a SoC system, which is used to evaluate the time synchronization precision between the multiple cores in the SoC system, can flexibly configure the frequency of pulse triggering to observe the core-to-core time synchronization deviation under different time spans or operating temperatures, and has simple requirements for the writing of the underlying test code in the SoC, small code amount, low development difficulty, easy implementation and convenience for implementation. SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In order to overcome the above-mentioned defects existing in the prior art, the present application provides a time synchronization precision evaluation method of a SoC system, wherein a plurality of cores are arranged in the SoC system, and a first core is configured to complete global time synchronization between the SoC system and an external clock source based on a time synchronization protocol, the time synchronization precision evaluation method comprising: simultaneously sending a pulse signal to the first core and other cores in the SoC system by a test host computer; when the first core and the other cores detect the pulse signal, recording current time information of each core respectively, and keeping the current time information as event time of each core in log information of the SoC system; and the test host computer requests to obtain the log information, calculates time deviation of each of the other cores from the first core based on the event time in the log information, and evaluates time synchronization precision of the plurality of cores in the SoC system based on the time deviation.

[0007] In an embodiment, preferably, the time synchronization precision evaluation method further comprises: periodically sending the pulse signal to the first core and the other cores by the test host computer; when detecting the pulse signal each time, the first core and the other cores record the event time respectively, and the test host computer calculates the time deviation each time based on the event time; for each of the other cores, the test host computer calculates average time deviation of the core from the first core based on values of a plurality of the time deviations of the core, and evaluates time synchronization precision of the core based on the average time deviation.

[0008] In an embodiment, preferably, the test host computer calculates the time deviation each time based on the event time, comprising: calculating the time deviation each time based on the following formula:

[0009] ΔT n = A_Event_T n - R_Event_T n

[0010] wherein A_Event_T n is the event time recorded by the first core each time, R_Event_T n is the event time recorded by the other core each time, n is the number of times, and ΔT n is the time deviation each time; the test host computer calculates the average time deviation of the core from the first core based on values of a plurality of the time deviations of the core, comprising: when all ΔT n are non-negative or all are non-positive, calculating the average time deviation of the core based on the following formula:

[0011]

[0012] In an embodiment, preferably, the test host calculates the average time deviation of the core relative to the first core based on the values of the time deviations of the core, and further comprises: when ΔT n When both positive and negative values exist in the time deviations, and the positive values or the negative values are concentrated as the running time or the running temperature of the SoC system continuously changes, the average time deviation of each segment of the core is calculated based on the positive and negative signs of the time deviations as the dividing line.

[0013] In an embodiment, preferably, the time synchronization precision evaluation method provided by the application further comprises: selecting an adaptive periodic frequency for the test host according to the time span of observing the time deviation or the running temperature of the SoC system in different scenarios, so as to obtain the average time deviation by sending the pulse signal multiple times based on the periodic frequency.

[0014] Another aspect of the application also provides a time synchronization precision evaluation device of an SoC system, the SoC system being provided with a plurality of cores, wherein a first core is configured to complete global time synchronization of the SoC system and an external clock source based on a time synchronization protocol, the time synchronization precision evaluation device comprising: a memory; and a processor coupled with the memory, the processor being configured to: simultaneously send a pulse signal to the first core and other cores in the SoC system by a test host; when the first core and the other cores detect the pulse signal, respectively record current time information, and keep the current time information as event time in log information of the SOC system; and the test host requests to obtain the log information, calculates the time deviation of each of the other cores and the first core based on the event time in the log information, and evaluates the time synchronization precision of the plurality of cores in the SoC system based on the time deviation.

[0015] In an embodiment, preferably, the processor is further configured to: periodically send multiple pulse signals to the first core and the other cores by the test host; each time the pulse signal is detected, the first core and the other cores respectively record the event time, and the test host calculates the time deviation each time based on the event time; for each of the other cores, the test host calculates the average time deviation of the core relative to the first core based on the values of the time deviations of the core, and evaluates the time synchronization precision of the core based on the average time deviation.

[0016] In an embodiment, preferably, the processor is further configured to: calculate the time deviation each time based on the following formula:

[0017] ΔT n =A_Event_T nR_Event_T n

[0018] wherein A_Event_T n is the event time recorded by the first core at the corresponding time, R_Event_T n is the event time recorded by the other core at the same time, n is the time, ΔT n is the time deviation at the corresponding time; and when all ΔT n are non-negative or all are non-positive, the average time deviation of the core is calculated by the following formula:

[0019]

[0020] In an embodiment, preferably, the processor is further configured to: when multiple positive values and negative values exist simultaneously in ΔT n , and as the running time or running temperature of the SoC system continuously changes, the multiple positive values or multiple negative values are distributed in a concentrated manner, then the positive and negative signs of the time deviation are taken as a dividing line to respectively segmentally calculate the average time deviation of the core on each segment.

[0021] In an embodiment, preferably, the processor is further configured to: according to observing the time span of the time deviation or the running temperature of the SoC system under different scenarios, select an adaptive periodic frequency for the test host computer, so as to obtain the average time deviation according to sending multiple pulse signals based on the periodic frequency.

[0022] The present application also provides a computer readable medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the time synchronization precision evaluation method of the SoC system as described in any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above features and advantages of the present application can be better understood by reading the following detailed description of embodiments of the present application in conjunction with the drawings, in which: in the drawings, components are not necessarily drawn to scale, and components having similar related functions or features can have the same or similar reference labels.

[0024] Figure 1 is a method flowchart of a time synchronization precision evaluation method of an SoC system according to an aspect of the present application;

[0025] Figure 2 is a system architecture and time synchronization precision evaluation principle diagram of an SoC system according to an embodiment of the present application;

[0026] Figure 3is a schematic diagram of working principle of a multi-core multi-receiving pulse signal recording event time according to an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of relationship between inter-core synchronization time deviation and running time according to an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of relationship between inter-core synchronization time deviation and running temperature according to an embodiment of the present application; and

[0029] Figure 6 is a schematic diagram of device structure of a time synchronization precision evaluation device of a SoC system according to another aspect of the present application.

[0030] For the sake of clarity, a brief description of the reference signs used in the following description is given:

[0031] 201 test host computer

[0032] 202 SoC system

[0033] 203 first core

[0034] 204 second core

[0035] 205 external clock source

[0036] 206 SoC log system

[0037] 401 positive time deviation

[0038] 402 negative time deviation

[0039] 501 positive time deviation

[0040] 502 negative time deviation DETAILED DESCRIPTION

[0041] The present application is described in greater detail by way of specific embodiments as follows. Other advantages and effects of the present application will be readily appreciated by those skilled in the art from the following description with reference had to the accompanying drawings. Although the description of the present application will be introduced in conjunction with preferred embodiments, it is not intended that the present application be limited to only those embodiments. Rather, it is intended that the present application be broad in scope and cover all alternatives, modifications and equivalents included within the scope of the claims based on the present application. In order to provide a thorough understanding of the present application, numerous specific details are described in the following description. However, it will be understood by those skilled in the art that the present application can be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to unnecessarily obscure aspects of the present application.

[0042] In the description of the present application, it should be noted that unless specifically defined and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0043] In addition, "up", "down", "left", "right", "top", "bottom", "horizontal", "vertical" used in the following description should be understood as the orientation shown in the section and the related drawings. The relative terms are only for the convenience of description, and do not mean that the device described thereby needs to be manufactured or operated in a particular orientation, and therefore should not be understood as a limitation on the present application.

[0044] It can be understood that although the terms "first", "second", "third" and the like are used herein to describe various components, regions, layers and / or parts, these components, regions, layers and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers and / or parts. Therefore, the first component, region, layer and / or part discussed below can be referred to as the second component, region, layer and / or part without departing from some embodiments of the present application.

[0045] In order to overcome the above-mentioned defects existing in the prior art, the present application provides a time synchronization precision evaluation method and device of a SoC system, which is used for evaluating the time synchronization precision between multiple cores in the SoC system. The frequency of pulse triggering can be flexibly configured to observe the core-to-core time synchronization deviation under different time spans or operating temperatures. The method can also be used to calibrate the core-to-core time synchronization protocol through multi-scene testing, and the requirement for hardware modification is very small or no modification is required. The existing IO resources are reused. The requirement for writing the bottom test code in the SoC is simple, the code amount is small, the development difficulty is low, it is easy to implement and convenient to implement.

[0046] Figure 1 It is a method flow diagram of a time synchronization precision evaluation method of a SoC system according to an aspect of the present application.

[0047] Please refer to Figure 1 The SoC system provided by the present application is provided with multiple cores, wherein the first core is configured to complete the global time synchronization between the SoC system and the external clock source based on the time synchronization protocol. The time synchronization precision evaluation method 100 comprises:

[0048] Step 101: sending a pulse signal to the first core and other cores in the SoC system simultaneously by the test host computer;

[0049] Step 102: when the first core and the other cores detect the pulse signal, respectively record the current time information, and keep the current time information as the event time in the log information of the SOC system; and

[0050] Step 103: the test host computer requests to obtain the log information, calculates the time deviation of each other core and the first core according to the event time in the log information, and evaluates the time synchronization accuracy of the cores in the SoC system based on the time deviation.

[0051] In a preferred embodiment, further, the time synchronization accuracy evaluation method of the SoC system provided by the application can further include: periodically sending the pulse signal to the first core and the other cores by the test host computer; each time the pulse signal is detected, the first core and the other cores respectively record the event time, and the test host computer calculates the time deviation of each time based on the event time; for each other core, the test host computer calculates the average time deviation of the core relative to the first core based on the values of the time deviations of the core, and evaluates the time synchronization accuracy of the core based on the average time deviation.

[0052] The time synchronization accuracy evaluation method will be described in detail below. Figure 2 、 Figure 3 .

[0053] Figure 2 is a system architecture and time synchronization accuracy evaluation principle diagram of the SoC system according to an embodiment of the application.

[0054] As Figure 2 shown, the SoC system 202 includes a plurality of cores, for example, the first core 203 (A core) and the second core 204 (R core) in this embodiment, the A core is used for completing global time synchronization with the external clock source 205. The A core can be a microprocessor MPU, and the R core can be a microcontroller MCU, both of which receive the pulse signal sent by the test host computer 201 and record the respective event time in the log system. It is easily understood that the specific composition of the SoC system and the hardware type of the core are only exemplary described, and are not used to limit the protection scope of the application.

[0055] Then the test host computer 201 calculates the time deviation based on the event time in the log to evaluate the accuracy of time synchronization, which can be further referred to Figure 3 .

[0056] Figure 3FIG. 1 is a schematic diagram illustrating the working principle of a multi-core system for recording event times by receiving pulse signals multiple times according to an embodiment of the present invention.

[0057] like Figure 3 As shown, the time synchronization module of the first core 203 (i.e., A core) of the SoC system 202 synchronizes to the global time of the external clock source 205 through the time synchronization protocol, and then synchronizes the global time information to the second core 204 (R core) through the inter-core time synchronization protocol. Figure 2 After the first core 203 completes global time synchronization with the external clock source 205, the time synchronization accuracy evaluation method within the SoC system may include the following steps:

[0058] First, the test host computer 201 can periodically send multiple pulse signals to multiple cores of the SoC system 202, such as the first core 203 (A core) and the second core 204 (R core) through the IO hard line;

[0059] Then, when the bottom test code of the first core 203 (A core) and the second core 204 (R core) detects the pulse signal of the IO input, it records the event time at that time, for example, it can be recorded as A_Event_T n and R_Event_T n ;

[0060] At the same time, after each pulse signal is detected, the underlying test code of the A core and the R core also records the event time and other information into the SoC log system 206;

[0061] After N tests, the test host computer 201 requests to obtain the event time information in the SoC log system 206, calculates the time deviation of the core relative to the first core 203 based on the event time of each different core, and then calculates the average time deviation of the N times to evaluate the time synchronization accuracy.

[0062] It should be noted that the underlying test code here generally refers to event processing based on interrupts and the like, and its main purpose is to identify pulse events of the host computer in real time or near real time and record the corresponding event time, rather than to limit the scope of protection of the present invention.

[0063] Furthermore, in a preferred embodiment, the test host computer calculates the time deviation each time based on the event time, which may include: calculating the time deviation each time based on the following formula:

[0064] ΔT n =A_Event_T n -R_Event_T n

[0065] ΔTn= A_Event_Tn- R_Event_Tn, n = 1, 2, 3,..., N n is the event time recorded by the first core 203 at the corresponding time, R_Event_T n is the event time recorded by the second core 204 at the same time, n is the time, ΔT n is the time deviation at the corresponding time; the test host computer calculates the average time deviation of the second core 204 relative to the first core 203 based on the values of the time deviations of the core, which can include: when all ΔT n are non-negative values or all are non-positive values, the average time deviation of the core is calculated by the following formula:

[0066]

[0067] As a person skilled in the art can easily understand, when there are both positive values and negative values in the time deviations calculated by N times of testing, the method of adding and averaging will offset the positive and negative values, thereby affecting the accuracy of the time deviation calculation, and therefore the time synchronization precision evaluation method provided by the present application sets that the time deviations are summed and averaged again when all ΔT n are non-negative values or all are non-positive values. The method of obtaining the average value of the time deviation is only an exemplary description, which is intended to illustrate that the time synchronization method provided by the present application can improve the accuracy of the time synchronization evaluation work through multiple tests, and is not used to limit the protection scope of the present application. In fact, other mathematical methods for obtaining more accurate time deviations using multiple time deviation values can also be used, and these methods should also be included in the protection scope of the present application.

[0068] Further, in a preferred embodiment, the test host computer calculates the average time deviation of the core relative to the first core based on the values of the time deviations of the core, which can also include: when there are multiple positive values and negative values in ΔT n , and with the continuous change of the running time or the running temperature of the SoC system, the multiple positive values or the multiple negative values are concentratedly distributed, then the positive and negative signs of the time deviations are taken as the dividing limit to respectively calculate the average time deviation of the core on each segment.

[0069] The change of the time deviation values in multiple tests can be understood in combination with Figure 4 , Figure 5 .

[0070] Figure 4 is a schematic view of the change relationship between the inter-core synchronization time deviation and the running time according to an embodiment of the present application; Figure 5 is a schematic view of the change relationship between the inter-core synchronization time deviation and the running temperature according to an embodiment of the present application.

[0071] In Figure 4In the illustrated embodiment, as the running time increases, the time deviation values ΔT obtained by each test are all changed from positive values 401 to negative values 402 after a period of running. Figure 5 In the illustrated embodiment, when the running temperature is not more than 100℃, ΔT is all positive value 501, while when the running temperature is more than 110℃, ΔT is all negative value 502.

[0072] It is easy to understand that in the two embodiments, the positive and negative signs of the time deviation can be taken as the dividing boundary, and the average time deviation of the core in each segment is calculated respectively, so as to obtain more accurate time synchronization precision evaluation results.

[0073] On the basis of understanding that the time deviation will change with the running time or temperature, further, in a preferred embodiment, the time synchronization precision evaluation method of the SoC system provided by the application can also include: selecting an adaptive cycle frequency for the test host computer according to the time span of the observed time deviation or the running temperature of the SoC system under different scenarios, so as to obtain the average time deviation according to the sending of multiple pulse signals based on the cycle frequency, so as to more accurately evaluate the time synchronization precision, so that the precision evaluation method is more adaptive.

[0074] In addition, from the embodiment of Figure 4 , Figure 5 It can be seen from the embodiment that the time synchronization precision evaluation method of the SoC system provided by the application can also observe the time deviation between multiple cores of the SoC under different running time or running temperature scenarios, so as to facilitate understanding of the correlation between the time synchronization precision between the cores in the whole system and the running time or temperature, and further to provide preparation for subsequent development work.

[0075] Although the above methods are illustrated and described as a series of actions for the sake of simplicity of explanation, it should be understood and appreciated that the methods are not limited by the order of the actions, because according to one or more embodiments, some actions can occur in different orders and / or concurrently with other actions illustrated and described herein or not illustrated and described herein but can be understood by those skilled in the art.

[0076] According to another aspect of the application, an embodiment of a time synchronization precision evaluation device 600 based on an SoC system is also provided herein.

[0077] Figure 6 is a device structure schematic diagram of a time synchronization precision evaluation device of an SoC system according to another aspect of the application. As Figure 6As shown, the SoC system-based time synchronization accuracy assessment device 600 provided in this embodiment may include a memory 601 and a processor 602 coupled to the memory 601. The processor 602 may be configured to implement any of the above-mentioned SoC system-based time synchronization accuracy assessment methods.

[0078] According to another aspect of the present invention, an embodiment of a computer storage medium is also provided herein.

[0079] The computer storage medium stores a computer program, which, when executed by a processor, can implement any of the steps of the above-mentioned method for evaluating time synchronization accuracy based on a SoC system.

[0080] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0081] The processor described in this case can be implemented using electronic hardware, computer software or any combination thereof. Whether such processors are implemented as hardware or software will depend on the specific application and the overall design constraints imposed on the system. As an example, the processor presented in this disclosure, any part of the processor, or any combination of processors can be implemented with a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gating logic, a discrete hardware circuit, and other suitable processing components configured to perform the various functions described throughout this disclosure. The functionality of the processor presented in this disclosure, any part of the processor, or any combination of processors can be implemented with software executed by a microprocessor, a microcontroller, a DSP or other suitable platform.

[0082] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In the alternative, the processor and the storage medium can reside as discrete components in a user terminal.

[0083] In one or more exemplary embodiments, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0084] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for evaluating time synchronization accuracy of a SoC system, the SoC system comprising a plurality of cores, wherein a first core is configured to complete global time synchronization between the SoC system and an external clock source based on a time synchronization protocol, the method comprising: sending, by a test host computer, a pulse signal to the first core and other cores in the SoC system simultaneously; recording, by the first core and the other cores, current time information respectively when the pulse signal is detected, and maintaining the current time information as event time in log information of the SoC system; and requesting, by the test host computer, to obtain the log information, calculating time deviation between each of the other cores and the first core based on the event time in the log information, and evaluating time synchronization accuracy of the plurality of cores in the SoC system based on the time deviation. Further comprising: periodically sending, by the test host computer, the pulse signal to the first core and the other cores simultaneously multiple times; recording, by the first core and the other cores, the event time respectively each time the pulse signal is detected, and calculating, by the test host computer, the time deviation each time based on the event time; for each of the other cores, calculating, by the test host computer, average time deviation of the core relative to the first core based on values of a plurality of the time deviations of the core, and evaluating time synchronization accuracy of the core based on the average time deviation.

2. The time synchronization accuracy evaluation method of claim 1, wherein, calculating, by the test host computer, the time deviation each time based on the event time, comprises: calculating the time deviation each time based on the following formula: calculating, by the test host computer, the average time deviation of the core relative to the first core based on values of a plurality of the time deviations of the core, comprises: calculating, by the test host computer, the average time deviation of the core relative to the first core based on values of a plurality of the time deviations of the core, further comprises:

3. The time synchronization accuracy evaluation method of claim 2, wherein, Further comprising: selecting, by the test host computer, an appropriate periodicity according to a time span of observing the time deviation or a running temperature of the SoC system in different scenarios, and obtaining the average time deviation based on sending the pulse signal multiple times according to the periodicity. ΔT n = A_Event_T n - R_Event_T n wherein A_Event_T n is the event time recorded by the first core at the corresponding number, R_Event_T n is the event time recorded by the other core at the same number, n is the number, ΔT n is the time deviation at the corresponding number. 6.A device for evaluating time synchronization accuracy of a SoC system, the SoC system comprising a plurality of cores, wherein a first core is configured to complete global time synchronization between the SoC system and an external clock source based on a time synchronization protocol, the device comprising: a memory; and a processor coupled to the memory, the processor being configured to: send, by a test host computer, a pulse signal to the first core and other cores in the SoC system simultaneously; record, by the first core and the other cores, current time information respectively when the pulse signal is detected, and maintain the current time information as event time in log information of the SoC system; and request, by the test host computer, to obtain the log information, calculate time deviation between each of the other cores and the first core based on the event time in the log information, and evaluate time synchronization accuracy of the plurality of cores in the SoC system based on the time deviation. When ΔT n When all of the values are non-negative or non-positive, the average time deviation for the core is calculated using the following formula:

4. The time synchronization accuracy evaluation method of claim 3, wherein, ​ When ΔT n When there are multiple positive values and multiple negative values, and as the continuous change of the running time or running temperature of the SoC system, the multiple positive values or multiple negative values are distributed in a concentrated manner, then taking the positive and negative signs of the time deviation as the dividing boundary, the average time deviation of the core on each segment is calculated respectively.

5. The time synchronization accuracy evaluation method of claim 2, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ The test host computer requests to obtain the log information, calculates a time deviation of each of the other cores from the first core according to the event time in the log information, and evaluates the time synchronization accuracy of the cores in the SoC system based on the time deviation.

7. The time synchronization precision evaluation apparatus of claim 6, wherein The processor is further configured to: The test host computer periodically sends the pulse signal to the first core and the other cores at the same time for multiple times; Upon detecting the pulse signal each time, the first core and the other cores record the event time respectively, and the test host computer calculates the time deviation each time based on the event time; For each of the other cores, the test host computer calculates an average time deviation of the core from the first core based on the values of the time deviations of the core, and evaluates the time synchronization accuracy of the core based on the average time deviation.

8. The time synchronization precision evaluation apparatus of claim 7, wherein The processor is further configured to: The time deviation each time is calculated based on the following formula: ΔT n = A_Event_T n - R_Event_T n wherein A_Event_T n is the event time recorded by the first core at the corresponding number, R_Event_T n is the event time recorded by the other core at the same number, n is the number, ΔT n is the time deviation at the corresponding number; and When ΔT n When all of the values are non-negative or all of the values are non-positive, the average time deviation for the core is calculated using the following equation:

9. The time synchronization precision evaluation apparatus of claim 8, wherein, The processor is further configured to: when ΔT n When multiple positive values and multiple negative values exist simultaneously, and the multiple positive values or multiple negative values are distributed in clusters as the runtime or operating temperature of the SoC system continuously changes, the average time deviation of the core on each segment is calculated separately by taking the positive and negative signs of the time deviation as the dividing line.

10. The time synchronization precision evaluation apparatus of claim 7, wherein, The processor is further configured to: According to the time span of observing the time deviation or the running temperature of the SoC system in different scenarios, the test host computer selects an appropriate cycle frequency to obtain the average time deviation based on sending the pulse signal for multiple times at the cycle frequency.

11. A computer readable medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method for evaluating the time synchronization accuracy of the SoC system according to any one of claims 1-5.

Images