Light detection device

Abstract

The present technology relates to an imaging device and an electronic apparatus capable of reducing noise. The present invention includes a photoelectric conversion element, a conversion unit configured to convert a signal from the photoelectric conversion element into a digital signal, a bias circuit configured to supply a bias current for controlling a current flowing through an analog circuit in the conversion unit, and a control unit configured to control the bias circuit based on an output signal of the conversion unit. The control unit raises a voltage at a predetermined position of the analog circuit at the time of starting transfer of electric charges from the photoelectric conversion element. The conversion unit converts the signal from the photoelectric conversion element into the digital signal using a slope signal whose level monotonously decreases with time. The present technology can be applied to, for example, an imaging device.

Description

[0001] This application is a divisional application of patent application No. 201880067515.X, filed on October 9, 2018, entitled "Camera Apparatus and Electronic Device". Technical Field

[0002] This technology relates to camera devices and electronic devices, and specifically to camera devices and electronic devices capable of adaptively changing noise levels and capturing images with improved image quality. Background Technology

[0003] Typically, image sensors such as charge-coupled devices (CCDs) or complementary metal oxide semiconductors (CMOSs) are used in electronic devices with imaging capabilities (e.g., digital cameras or digital camcorders).

[0004] An image sensor has pixels in which photodiodes (PDs) for photoelectric conversion and multiple transistors are combined together, and an image is formed based on pixel signals output from multiple pixels arranged in a plane. Furthermore, the pixel signals output from the pixels are subjected to parallel A / D conversion, for example, by multiple analog-to-digital (AD) converters arranged for each pixel column, and then output.

[0005] Patent document 1 proposes a camera device that reduces power consumption and random noise.

[0006] Reference List

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2007-151170 Summary of the Invention

[0009] The problem to be solved by the present invention

[0010] The noise level of an image sensor is defined by thermal noise, 1 / f noise, and quantization noise. To reduce thermal noise, one could consider improving the gm of the circuitry, but this could lead to an increase in the current consumed by the analog circuitry, which could thus increase power consumption.

[0011] Furthermore, while 1 / f noise is sensitive to current, it is primarily determined by area and process technology, and taking these measures may increase costs. Quantization noise is uniquely determined by the resolution of the A / D converter, but in low light conditions, quantization noise is defined by the random noise of the image sensor itself and the quantization noise of the A / D converter. The thermal noise and 1 / f noise of the random noise depend on the amount of current consumed by the analog circuitry.

[0012] This technology was developed in view of the above circumstances, enabling the current consumed in the analog circuit to be adaptively and variably adjusted according to the output signal after AD conversion, thereby reducing power under high illumination and achieving low noise under low illumination.

[0013] Technical solutions to the problem

[0014] An imaging device according to one aspect of the present technology includes: a photoelectric conversion element; a conversion unit for converting a signal from the photoelectric conversion element into a digital signal; a bias circuit for providing a bias current for controlling the current flowing through an analog circuit in the conversion unit; and a control unit for controlling the bias circuit based on an output signal from the conversion unit, wherein, when the transfer of charge from the photoelectric conversion element begins, the control unit increases the voltage at a predetermined position of the analog circuit.

[0015] An electronic device according to one aspect of the present technology includes: a camera device, the camera device comprising: a photoelectric conversion element; a conversion unit for converting a signal from the photoelectric conversion element into a digital signal; a bias circuit for providing a bias current for controlling a current flowing through an analog circuit in the conversion unit; and a control unit for controlling the bias circuit based on an output signal from the conversion unit, wherein, when the transfer of charge from the photoelectric conversion element begins, the control unit increases the voltage at a predetermined position of the analog circuit.

[0016] An imaging device according to one aspect of the present technology includes: a photoelectric conversion element; a conversion unit for converting a signal from the photoelectric conversion element into a digital signal; a bias circuit for providing a bias current for controlling the current flowing through an analog circuit in the conversion unit; and a control unit for controlling the bias circuit based on an output signal from the conversion unit. Furthermore, when the transfer of charge from the photoelectric conversion element begins, the control unit increases the voltage at a predetermined location in the analog circuit.

[0017] An electronic device according to one aspect of the present technology includes a camera device.

[0018] Please note that the camera device and the electronic device may be independent devices or may be internal blocks that constitute a single device.

[0019] Beneficial effects of the present invention

[0020] According to one aspect of this technology, by adaptively and variably adjusting the current consumed by the analog circuit based on the output signal after AD conversion, it is possible to achieve low power consumption under high illumination and low noise under low illumination.

[0021] Note that the effects described herein are not necessarily limiting, and can be any of the effects described in this invention. Attached Figure Description

[0022] Figure 1 This is a diagram illustrating a schematic structure of the camera device according to the present invention.

[0023] Figure 2 This is a block diagram showing a detailed example of the construction of a pixel.

[0024] Figure 3 This is a block diagram showing a detailed construction example of a comparator circuit.

[0025] Figure 4 It is a diagram illustrating the detailed structure of a pixel circuit.

[0026] Figure 5 It is a timing diagram used to illustrate the operation of pixels.

[0027] Figure 6 It is a diagram used to illustrate the construction of a circuit that includes noise.

[0028] Figure 7 It is a diagram used to illustrate the construction of a circuit that includes noise.

[0029] Figure 8 It is a diagram used to illustrate the construction of a circuit that includes noise.

[0030] Figure 9 It is a diagram used to illustrate the construction of a circuit that includes noise.

[0031] Figure 10 This is a diagram used to illustrate the construction of a circuit including a decision unit.

[0032] Figure 11 This is a diagram used to illustrate the construction of the decision unit.

[0033] Figure 12 This is a diagram used to illustrate the construction of a bias circuit.

[0034] Figure 13 This is a diagram used to illustrate the construction of a DAC.

[0035] Figure 14 It is a diagram used to illustrate the waveform of the signal output from the DAC.

[0036] Figure 15 This is a diagram used to illustrate the construction of a bias circuit.

[0037] Figure 16 This is a diagram used to illustrate the generation of return charge from FD.

[0038] Figure 17 This is a diagram used to illustrate the generation of return charge from FD.

[0039] Figure 18 This is a diagram used to illustrate the construction of a bias circuit.

[0040] Figure 19 It is a timing diagram used to illustrate the operation of pixels.

[0041] Figure 20 This is a diagram used to illustrate the construction of a bias circuit.

[0042] Figure 21 It is a diagram used to illustrate the layout of the bias circuit.

[0043] Figure 22 It is a diagram used to illustrate the layout of the bias circuit.

[0044] Figure 23 This is a diagram used to illustrate the construction of a bias circuit.

[0045] Figure 24 It is a timing diagram used to illustrate the operation of pixels.

[0046] Figure 25 This is a diagram used to illustrate the construction of a bias circuit.

[0047] Figure 26 It is a diagram used to illustrate the timing of control.

[0048] Figure 27 This is a circuit diagram illustrating an example of the construction of a comparison circuit in the case of pixel sharing.

[0049] Figure 28 It is a diagram used to illustrate the timing of control.

[0050] Figure 29 This is a conceptual diagram of a camera device consisting of two stacked semiconductor substrates.

[0051] Figure 30 This is a diagram illustrating an example of a circuit structure in a camera device composed of two semiconductor substrates.

[0052] Figure 31This is a conceptual diagram of a camera device consisting of a stack of three semiconductor substrates.

[0053] Figure 32 This is a diagram illustrating an example of a circuit structure in a camera device composed of three semiconductor substrates.

[0054] Figure 33 This is a diagram used to illustrate other constructions of a circuit including a decision unit.

[0055] Figure 34 This is a diagram used to illustrate other constructions of a circuit including a decision unit.

[0056] Figure 35 This is a diagram used to illustrate other constructions of a circuit including a decision unit.

[0057] Figure 36 This is a diagram used to illustrate other constructions of a circuit including a decision unit.

[0058] Figure 37 This is a block diagram illustrating an example of the construction of a camera device as an electronic device according to the present invention.

[0059] Figure 38 This is a block diagram illustrating an example of a schematic construction of an in vivo information acquisition system.

[0060] Figure 39 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system.

[0061] Figure 40 This is a block diagram illustrating an example of the functional configuration of a camera and a CCU.

[0062] Figure 41 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0063] Figure 42 This is an explanatory diagram showing an example of the installation location of the camera unit. Detailed Implementation

[0064] The following describes the methods used to implement this technology (hereinafter referred to as embodiments).

[0065] <Illustrative example of a camera device>

[0066] Figure 1 A schematic structure of the camera device according to the present invention is shown.

[0067] Figure 1The imaging device 1 includes a pixel array unit 22, wherein pixels 21 are arranged in a two-dimensional array pattern on a semiconductor substrate 11 using, for example, silicon (Si) as the semiconductor. The pixel array unit 22 also includes a timecode transmission unit 23, which transmits timecode generated by a timecode generation unit 26 to each pixel 21. Then, surrounding the pixel array unit 22 on the semiconductor substrate 11, a pixel driving circuit 24, a D / A converter (DAC) 25, a timecode generation unit 26, a vertical driving circuit 27, an output unit 28, and a timing generation circuit 29 are formed.

[0068] As will be referred to later Figure 2 As explained, each of the pixels 21 arranged in a two-dimensional array pattern is equipped with a pixel circuit 41 and an ADC 42. Each pixel 21 generates a charge signal corresponding to the amount of light received by the light-receiving element (e.g., a photodiode) in the pixel, converts the charge signal into a digital pixel signal SIG, and outputs the pixel signal SIG.

[0069] Pixel driving circuit 24 drives pixel circuit 41 in pixel 21. Figure 2 DAC 25 acts as a generation unit for generating a reference signal (reference voltage signal) REF, and provides the generated reference signal REF to each pixel 21. The reference signal REF is a slope signal whose level (voltage) decreases monotonically with time. Time code generation unit 26 generates a time code used by each pixel 21 to convert the analog pixel signal SIG into a digital signal (AD conversion), and provides the time code to the corresponding time code transmission unit 23.

[0070] Multiple timecode generation units 26 are provided for the pixel array unit 22, and the number of timecode transmission units 23 in the pixel array unit 22 is the same as the number of timecode generation units 26. That is, there is a one-to-one correspondence between the timecode generation unit 26 and the timecode transmission unit 23 for transmitting the timecode generated by it.

[0071] The vertical drive circuit 27 is controlled based on the timing signal provided by the timing generation circuit 29, so that the output unit 28 outputs the digital pixel signal SIG generated in the pixel 21 in a predetermined order. The digital pixel signal SIG output from the pixel 21 is output from the output unit 28 to the outside of the imaging device 1. The output unit 28 performs predetermined digital signal processing as needed (e.g., black level correction processing for correcting black levels or correlated double sampling (CDS) processing, etc.), and then outputs the resulting signal to the outside.

[0072] The timing generation circuit 29 includes a timing generator for generating various timing signals, and provides the generated timing signals to the pixel driving circuit 24, DAC 25 and vertical driving circuit 27, etc.

[0073] The camera device 1 is constructed as described above. Note that, in Figure 1 As described above, it has been explained that all the circuits constituting the imaging device 1 are formed on a single semiconductor substrate 11. However, as will be explained later, the circuits constituting the imaging device 1 can be configured to be arranged separately on multiple semiconductor substrates 11.

[0074] <Detailed example of pixel construction>

[0075] Figure 2 This is a block diagram showing a detailed construction example of pixel 21.

[0076] Pixel 21 includes pixel circuit 41 and ADC (AD converter) 42.

[0077] The pixel circuit 41 outputs the charge signal corresponding to the received light quantity as an analog pixel signal SIG to the ADC 42. The ADC 42 converts the analog pixel signal SIG provided by the pixel circuit 41 into a digital signal.

[0078] The ADC 42 includes a comparator circuit 51 and a data storage unit 52.

[0079] The comparator circuit 51 compares the reference signal REF provided by the DAC 25 with the pixel signal SIG, and outputs the comparison result signal VCO as an output signal representing the comparison result. When the reference signal REF and the pixel signal SIG are the same (same voltage), the comparator circuit 51 inverts the output signal VCO.

[0080] The comparator circuit 51 includes a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback circuit (PFB) 63. (See later...) Figure 3 Detailed explanation.

[0081] In addition to receiving the output signal VCO from the comparator circuit 51, the data storage unit 52 also receives the WR signal, RD signal, and WORD signal from the vertical drive circuit 27. The WR signal indicates a pixel signal write operation, the RD signal indicates a pixel signal read operation, and the WORD signal is used to control the read timing of the pixel 21 during the pixel signal read operation. Furthermore, the timecode generated by the timecode generation unit 26 is provided via the timecode transmission unit 23.

[0082] The data storage unit 52 includes: a latch control circuit 71, which controls the write and read operations of the time code based on the WR signal and the RD signal; and a latch storage unit 72, which is used to store the time code.

[0083] During the timecode writing operation, the latch control circuit 71 causes the latch storage unit 72 to store the timecode provided by the timecode transmission unit 23, and updates the timecode every unit time when the Hi (high) output signal VCO is input from the comparator circuit 51.

[0084] Then, when the reference signal REF and the pixel signal SIG are the same (same voltage) and the output signal VCO provided by the comparator circuit 51 is inverted to Lo (low), the writing (updating) of the provided time code stops, and the time code finally stored in the latch memory unit 72 is retained in the latch memory unit 72. The time code stored in the latch memory unit 72 represents the time when the pixel signal SIG and the reference signal REF are equal, and represents the following data: this data indicates that the pixel signal SIG is the reference voltage at that time, that is, it represents the digitized light quantity value.

[0085] After the scanning of the reference signal REF is completed and the time code is stored in the latch memory 72 of all pixels 21 in the pixel array unit 22, the operation of pixel 21 changes from a write operation to a read operation.

[0086] During the timecode reading operation, when pixel 21 has reached its own reading timing based on the WORD signal controlling the reading timing, the latch control circuit 71 outputs the timecode (digital pixel signal SIG) stored in the latch memory unit 72 to the timecode transmission unit 23. The timecode transmission unit 23 sequentially transmits the provided timecode in the column direction (vertical direction) and provides the timecode to the output unit 28.

[0087] In the following text, in order to distinguish it from the time code written into the latch memory unit 72 in the time code write operation, the pixel signal SIG is the digitized pixel data of the reference voltage at this time, also referred to as the pixel data after AD conversion. The aforementioned digitized pixel data is the inverted time code when the output signal VCO read from the latch memory unit 72 in the time code read operation is inverted.

[0088] <First Construction Example of a Comparator Circuit>

[0089] Figure 3 This is a circuit diagram showing the detailed construction of the differential input circuit 61, voltage conversion circuit 62, and positive feedback circuit 63 that constitute the comparator circuit 51.

[0090] The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 in pixel 21 with the reference signal REF output from DAC 25, and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

[0091] The differential input circuit 61 includes: transistors 81 and 82 forming a differential pair; transistors 83 and 84 forming a current mirror; transistor 85 serving as a constant current source for providing a current Icm corresponding to the input bias current Vb; and transistor 86 for outputting the output signal HVO of the differential input circuit 61.

[0092] Transistors 81, 82, and 85 are composed of negative channel MOS (NMOS) transistors, while transistors 83, 84, and 86 are composed of positive channel MOS (PMOS) transistors.

[0093] In transistors 81 and 82 forming a differential pair, the reference signal REF output from DAC 25 is input to the gate of transistor 81, and the pixel signal SIG output from pixel circuit 41 in pixel 21 is input to the gate of transistor 82. The sources of transistors 81 and 82 are connected to the drain of transistor 85, and the source of transistor 85 is connected to a predetermined voltage VSS. <VDD2<VDD1)。

[0094] The drain of transistor 81 is connected to the gates of transistors 83 and 84, which form the current mirror circuit, as well as the drain of transistor 83. The drain of transistor 82 is connected to the drain of transistor 84 and the gate of transistor 86. The sources of transistors 83, 84, and 86 are connected to the first power supply voltage VDD1.

[0095] The voltage conversion circuit 62 includes, for example, an NMOS transistor 91. The drain of transistor 91 is connected to the drain of transistor 86 in the differential input circuit 61, the source of transistor 91 is connected to a predetermined connection point in the positive feedback circuit 63, and the gate of transistor 91 is connected to a bias voltage VBIAS.

[0096] The transistors 81 to 86 constituting the differential input circuit 61 are circuits that operate at a high voltage up to the first power supply voltage VDD1, and the positive feedback circuit 63 is a circuit that operates at a second power supply voltage VDD2 down to the first power supply voltage VDD1. The voltage conversion circuit 62 converts the output signal HVO input from the differential input circuit 61 into a low voltage signal (conversion signal) LVI that enables the positive feedback circuit 63 to operate, and provides it to the positive feedback circuit 63.

[0097] The bias voltage VBIAS only needs to be converted to a voltage that will not damage the transistors 101 to 105 of the positive feedback circuit 63, which operates at a constant voltage. For example, the bias voltage VBIAS can be the same as the second power supply voltage VDD2 of the positive feedback circuit 63 (VBIAS = VDD2).

[0098] The positive feedback circuit 63 outputs a comparison result signal that is inverted when the pixel signal SIG is higher than the reference signal REF, based on the conversion signal LVI obtained by converting the output signal HVO from the differential input circuit 61 into a signal corresponding to the second power supply voltage VDD2. Furthermore, when the output signal VCO, which is output as the comparison result signal, is inverted, the positive feedback circuit 63 increases the transition speed.

[0099] The positive feedback circuit 63 includes seven transistors 101 to 107. Here, transistors 101, 102, 104 and 106 are PMOS transistors, and transistors 103, 105 and 107 are NMOS transistors.

[0100] The source of transistor 91 (which is the output terminal of voltage conversion circuit 62) is connected to the drain of transistors 102 and 103, as well as the transistor... The source of transistor 101 is connected to the second power supply voltage VDD2, the drain of transistor 101 is connected to the source of transistor 102, and the gate of transistor 102 is connected to the drain of transistors 104 and 105. The drains of transistors 104 and 105 are also the output terminals of the positive feedback circuit 63.

[0101] The sources of transistors 103, 105, and 107 are all connected to a predetermined voltage VSS. An initialization signal INI is provided to the gates of transistors 101 and 103. A control signal TERM, which is the second input and not the switching signal LVI (the first input), is provided to the gates of transistors 106 and 107.

[0102] The source of transistor 106 is connected to the second power supply voltage VDD2, and the drain of transistor 106 is connected to the source of transistor 104. The drain of transistor 107 is connected to the output terminal of comparator circuit 51, and the source of transistor 107 is connected to a predetermined voltage VSS.

[0103] In the comparator circuit 51 constructed as described above, when the control signal TERM, which is the second input, is set to Hi, the output signal VCO can be set to Lo regardless of the state of the differential input circuit 61.

[0104] For example, when the voltage of the pixel signal SIG drops below the final voltage of the reference signal REF due to a brightness higher than expected (e.g., a sun image reflected in the view of the camera device 1), the output signal VCO of the comparison circuit 51 becomes Hi, and the comparison period ends, making it impossible for the data storage unit 52 controlled by the output signal VCO to fix the value and lose the AD conversion function.

[0105] To prevent the above situation from occurring, by inputting the Hi pulse control signal TERM at the end of the scan of the reference signal REF, the output signal VCO, which has not yet been inverted to Lo, can be forcibly inverted. Since the data storage unit 52 stores (latches) the timecode immediately preceding the forced inversion, therefore, when using... Figure 3 In this configuration, ADC 42 ultimately functions as an AD converter, which clamps the output value for brightness inputs above a certain level.

[0106] When the bias voltage VBIAS is controlled to Lo level, turning off transistor 91, and the initialization signal INI is set to Hi, the output signal VCO will become Hi regardless of the state of the differential input circuit 61. Therefore, by combining the forced Hi output of the output signal VCO with the forced Lo output via the control signal TERM, the output signal VCO can be set to any value regardless of the state of the preceding differential input circuit 61, the pixel circuit 41, and the DAC 25.

[0107] With this feature, for example, it is possible to test the circuitry after pixel 21 using only electrical signal input, without relying on the optical input of the camera device 1.

[0108] <Detailed Construction Example of Pixel Circuit>

[0109] Reference Figure 4 The detailed structure of pixel circuit 41 is explained. Figure 4 It shows that, apart from Figure 3 A detailed circuit diagram of the pixel circuit 41, excluding the differential input circuit 61 of the comparison circuit 51 shown.

[0110] The pixel circuit 41 includes a photodiode (PD) 121, a discharge transistor 122, a transmission transistor 123, a reset transistor 124, and an FD (floating diffusion layer) 125, which are photoelectric conversion elements.

[0111] Discharge transistor 122 is used when adjusting the exposure time. Specifically, if it is desired to turn on discharge transistor 122 at any time to start the exposure period, the charge accumulated in photodiode 121 is discharged. Therefore, the exposure period begins after discharge transistor 122 is turned off.

[0112] Transmission transistor 123 transfers the charge generated by photodiode 121 to FD 125. Reset transistor 124 resets the charge held in FD 125. FD 125 is connected to the gate of transistor 82 of differential input circuit 61. Therefore, transistor 82 of differential input circuit 61 also functions as an amplification transistor of pixel circuit 41.

[0113] The source of reset transistor 124 is connected to the gate of transistor 82 in differential input circuit 61 and FD 125, and the drain of reset transistor 124 is connected to the drain of transistor 82. Therefore, there is no fixed reset voltage for resetting the charge of FD 125. This is because: by controlling the circuit state of differential input circuit 61, the reset voltage for resetting FD 125 can be arbitrarily set using the reference signal REF, and the fixed-mode noise of the circuit is stored in FD 125, allowing its components to be eliminated through CDS operation.

[0114] <Pixel Unit Timing Diagram>

[0115] Reference Figure 5 Timing diagram explanation Figure 4 The operation of pixel 21 shown.

[0116] First, at time t1, the reference signal REF is set to the reset voltage V. rst And by turning on the reset transistor 124, the charge of FD 125 is reset, and the aforementioned reset voltage V rst Used to transfer the charge of FD 125 from the standby voltage V stb Reset to the reset voltage V rst Furthermore, at time t1, the initialization signal INI of the gates of transistors 101 and 103 provided to the positive feedback circuit 63 is set to Hi, and the positive feedback circuit 63 is set to the initial state.

[0117] At time t2, the reference signal REF is raised to a predetermined voltage V. u Then, the comparison between the reference signal REF and the pixel signal SIG begins (scanning of the reference signal REF). At this time, since the reference signal REF is greater than the pixel signal SIG, the output signal VCO is Hi.

[0118] At the same time t3 when the reference signal REF and the pixel signal SIG are determined, the output signal VCO is inverted (turns low). When the output signal VCO is inverted, as described above, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, the data storage unit 52 stores the time data (N bits DATA[1] to DATA[N]) at the time when the output signal VCO is inverted.

[0119] At time t4, when the signal writing period ends and the signal reading period begins, the voltage of the reference signal REF supplied to the gate of transistor 81 of comparator circuit 51 decreases to a level that turns off transistor 81 (standby voltage V). stb Therefore, the current consumption of the comparator circuit 51 during the signal reading period is suppressed.

[0120] At time t5, the WORD signal used to control the read timing changes to Hi, and the latch control circuit 71 of the data storage unit 52 outputs N-bit latch time signals DATA[1] to DATA[N]. The data acquired here is the P-phase data at the reset level when Correlated Double Sampling (CDS) processing is performed.

[0121] At time t6, the reference signal REF rises to the predetermined voltage V. u The initialization signal INI provided to the gates of transistors 101 and 103 is set to Hi, and the positive feedback circuit 63 is set to the initial state again.

[0122] At time t7, the transmission transistor 123 of the pixel circuit 41 is turned on by the Hi transmission signal TX, and the charge generated by the photodiode 121 is transferred to FD 125.

[0123] After the initialization signal INI returns low, the comparison between the reference signal REF and the pixel signal SIG (scanning of the reference signal REF) begins. At this time, since the reference signal REF is greater than the pixel signal SIG, the output signal VCO is Hi.

[0124] Then, at the same time t8 when the reference signal REF and the pixel signal SIG are determined, the output signal VCO is inverted (converted to low). When the output signal VCO is inverted, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, the data storage unit 52 stores time data (N bits DATA[1] to DATA[N]) at the time when the output signal VCO is inverted.

[0125] At time t9, when the signal writing period ends and the signal reading period begins, the voltage of the reference signal REF supplied to the gate of transistor 81 of comparator circuit 51 decreases to a level that turns off transistor 81 (standby voltage V). stb Therefore, the current consumption of the comparator circuit 51 during the signal reading period is suppressed.

[0126] At time t10, the WORD signal used to control the read timing changes to Hi, and N-bit latch time signals DATA[1] to DATA[N] are output from the latch control circuit 71 of the data storage unit 52. The data acquired here is the D-phase data of the signal level when Correlated Double Sampling (CDS) processing is performed. Time t11 is the same state as time t1 above, during which the next 1V (one vertical scan cycle) is driven.

[0127] Driven by the aforementioned pixel 21, firstly, P-phase data (reset level) is acquired and then read, followed by D-phase data (signal level).

[0128] Through the above operations, each pixel 21 of the pixel array unit 22 of the imaging device 1 can perform a global shutter operation, in which all pixels are simultaneously reset and all pixels are simultaneously exposed. Since all pixels can be exposed and read at the same time, there is no need to provide a holding part, which is usually provided in a pixel, to hold the charge until the charge is read. In addition, the construction of pixel 21 does not require a pixel selection transistor or the like for selecting the output pixel signal SIG, which is necessary for column-parallel readout type imaging devices.

[0129] By reference Figure 5 The driving of pixel 21 always controls the discharge transistor 122 to be turned off. However, as Figure 5 As shown by the dashed line, at the desired time, the discharge signal OFG is set to Hi, the discharge transistor 122 is temporarily turned on and then turned off, thereby setting an arbitrary exposure period.

[0130] <About Noise>

[0131] Incidentally, camera device 1 ( Figure 1 The noise level of an analog circuit is defined by thermal noise, 1 / f noise, and quantization noise. To reduce thermal noise, one could consider improving the circuit's gm, but this would increase the current consumed by the analog circuit and potentially increase power consumption.

[0132] Furthermore, while 1 / f noise is also sensitive to current, it is primarily determined by area and process technology, and targeted measures would increase costs. Quantization noise is uniquely determined by the resolution of the ADC 42, but in low light conditions, quantization noise is defined by the random noise of the image sensor itself (thermal noise or 1 / f noise) and the quantization noise of the ADC 42, and both thermal noise and 1 / f noise depend on the amount of current consumed by the analog circuitry.

[0133] Therefore, the following will further describe such a camera device 1: by adaptively and variably adjusting the current consumed by the analog circuit according to the output signal after AD conversion (the output signal from ADC 42), the camera device 1 can achieve low power consumption in high illumination and low noise in low illumination.

[0134] In the following description, noise will be illustrated and explained as follows. Figure 6 As shown, the predetermined circuit 301 is a circuit that includes noise. The noise is generated from resistors, capacitors, transistors, or other elements in the circuit 301. It is assumed that external control for noise reduction is performed on the circuit 301, which includes elements that may generate noise.

[0135] In this case, such as Figure 7 As shown, the following explanation is given by illustrating that noise is equivalently input-transformed, a predetermined noise level is given by the input, and circuit 302 itself is noise-free. Figure 7 In the circuit diagram shown, circuit 302 is a noise-free circuit. An adder unit 303 is provided outside circuit 302, and a predetermined noise amount is input to the adder unit 303. Since the adder unit 303 is connected to circuit 302, noise is supplied to circuit 302.

[0136] Refer again Figure 6 The circuit 301 shown, for example, changes in noise level when the current flowing through the transistor elements included in the circuit 301 changes. In other words, the noise level can be controlled by controlling the current flowing through the transistor elements. Therefore, as... Figure 8 As shown, a control flow circuit 301' is conceived (in order to...) Figure 6 The circuit 301 shown is distinguished by an apostrophe (indicated by an overscore) to control the current of the transistor elements in the circuit 301' to control the noise of the circuit 301'.

[0137] like Figure 9 As shown, this can be used as follows Figure 7 The noiseless circuit 302 shown is used to represent this. That is, refer to... Figure 9 The noise of circuit 302' can be controlled by controlling the amount of noise input to the noise-free circuit 302' (the amount of noise input to the adder unit 303).

[0138] As described above, noise such as thermal noise, 1 / f noise, and quantization noise is generated in the imaging device 1. The ADC 42 included in the imaging device 1 includes, for example, Figure 3 The multiple transistor elements are shown. Further explanation will be given regarding the imaging device 1A, which controls the amount of noise generated in the ADC 42 by controlling the current flowing through the aforementioned transistor elements, and thus captures images with improved image quality.

[0139] <Construction of a camera device for performing noise control>

[0140] Figure 10 This is a diagram illustrating the construction of a camera device for noise control, specifically showing an ADC 42 and its surrounding circuitry, including a structure for controlling the amount of noise generated in the ADC 42. To control the amount of noise generated in the ADC 42, a determination unit 401 is provided, which makes a determination based on the output from the ADC 42, as will be explained later.

[0141] As a result of the determination by the determination unit 401, the amount of noise supplied to the ADC 42 is controlled. As will be explained later, the amount of noise is controlled by controlling the current flowing through predetermined transistor elements in the ADC 42. The determination unit 401 functions as a control unit for controlling the current in the ADC 42.

[0142] The reset digital data and signal digital data are output from the ADC 42. The difference between the reset digital data and the signal digital data is calculated by the adder unit 402, and a signal of charge accumulated in the pixel circuit 41 (accumulated in the photodiode 121 in the pixel circuit 41) is generated and output as the output signal.

[0143] The output signal is also input to the determination unit 401. As will be described in detail later, the determination unit 401 determines the nature of the captured image (e.g., whether it is high illumination or low illumination) and controls the amount of noise based on the determination result.

[0144] Figure 11 This is a diagram illustrating a construction example of the determination unit 401. The determination unit 401 includes a determination value calculation unit 431, a comparison unit 432, a control table reference unit 433, and a selection unit 434.

[0145] The pixel signal output from ADC 42 is provided to the determination value calculation unit 431 of determination unit 401. The provided pixel signal can be the pixel value of the entire pixel area, the pixel value of a single pixel, or the pixel value representing a pixel composed of more than one pixel, etc.

[0146] A pixel consisting of one or more pixels can be, for example, a pixel arranged in a predetermined area of ​​a pixel array unit or an image plane phase difference pixel. Furthermore, such a pixel can be a representative pixel of all pixels in the area surrounding it, and the signal from the pixel serving as the representative pixel can be read before reading any pixels that are not the representative pixel. The determination unit 401 can then use the signal read from the representative pixel to make a determination.

[0147] The unit of the pixel signal input to the decision value calculation unit 431 can be matched with the unit to be controlled. For example, in the case of control on a unit of one pixel, the pixel signal is provided on a unit of one pixel.

[0148] That is, the precision of the determination unit 401 can be the entire pixel area, one pixel unit, or multiple pixel units.

[0149] The unit of the pixel signal input to the determination value calculation unit 431 can be each pixel, each column, each pixel block including a predetermined number of pixels, or all pixels, etc.

[0150] Furthermore, the control timing (the timing used for determination) can be constant (executed for each frame) or can be executed for every predetermined number of frames. The aforementioned control timing is, for example, the time when the pixel signal is input to the determination value calculation unit 431, the time when the determination unit 401 makes a determination, etc.

[0151] Note that, as will be explained later, the time at which the determination unit 401 makes a determination and the time at which it uses the result of the determination to control the current value, etc., may be different. Here, the time of making the determination will be referred to as the control time, and the explanation will continue.

[0152] Furthermore, in the case where an image is formed by multiple frames (subframes), control can be performed on each subframe, or control can be performed in predetermined subframes of multiple subframes.

[0153] For example, when using four subframes to generate one frame, each subframe can be controlled, or a predetermined subframe (e.g., the first subframe) among the four subframes can be controlled (controlling the other subframes to use the values ​​of the predetermined subframes).

[0154] The determination value calculation unit 431 uses the input pixel signal to calculate the average value, representative value, maximum value, etc., of the image on the screen, indicating whether the image is saturated. All of these values ​​can be calculated, or at least one of them can be calculated.

[0155] Note that the decision value calculated by the decision value calculation unit 431 can be calculated using pixel signals that have been pre-processed, such as defect correction.

[0156] The decision value from the decision value calculation unit 431 is provided to the comparison unit 432. A decision threshold is also provided to the comparison unit 432. The decision threshold can be configured to be provided externally to the decision unit 401, or it can be configured to be maintained or generated by the comparison unit 432. The decision threshold can be a fixed value, or it can be a variable value that changes according to predetermined conditions.

[0157] The comparison unit 432 compares the judgment value from the judgment value calculation unit 431 with the judgment threshold and provides the comparison result to the control table reference unit 433. The control table reference unit 433 refers to a control signal for noise control of the analog circuit, such as a current value table. This table is, for example, in which the comparison result is correlated with the current value.

[0158] The above table can be stored in the control table reference unit 433, or it can be stored outside the control table reference unit 433.

[0159] A reference value (e.g., current value), a forced control value, and a mode selection signal from the control table reference unit 433 are provided to the selection unit 434. In response to the mode selection signal, the selection unit 434 determines whether to perform forced control, and selects either the reference value or the forced control value from the control table reference unit 433 based on the determination result, and provides the selection result to each analog circuit (e.g., ADC 42).

[0160] <First Construction for Controlling the Current of Differential Input Circuit>

[0161] Figure 12 An example of the construction of the ADC 42 and its surrounding cells is shown, in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 12 Only the differential input circuit 61 in ADC 42 is shown. The bias circuit 501 is connected to the gate of transistor 85 and is used to control the current Icm flowing through transistor 85 in the differential input circuit 61.

[0162] The determination result of the determination unit 401 is provided to the bias circuit 501. The bias circuit 501 includes a plurality of transistors 511 and a current source 512. The bias circuit 501 is configured to change the current value of the connected differential input circuit 61 by changing the number of transistors used to constitute the plurality of transistors 511.

[0163] When the current flowing through the bias circuit 501 is Ipixbias, the channel length L of the transistor 511 is fixed, the channel width W (the size of the bias W) is Wpixbias, the size of the pixel current source W is Wcmbias, and the current Icm flowing through the transistor 85 is Icm = Ipixbias × (Wcmbias / Wpixbias).

[0164] That is, control can be achieved by utilizing the characteristic of a constant current density per unit W. Even if the current value is in the order of a digit [nA] on the differential input circuit 61 side, the above operation can still be performed due to the construction of the positive feedback circuit 63 in the subsequent stage (positive feedback construction).

[0165] In this way, by controlling the current flowing through the transistor (here, transistor 85) in the differential input circuit 61, the noise generated by transistor 85 (the entire circuit containing transistor 85) can be controlled.

[0166] For example, when shooting bright images (high-light images), even if the noise is high, the noise is considered to have a relatively small impact on image quality. Conversely, when shooting dark images (low-light images), if the noise is high, the noise is considered to have a significant impact on image quality.

[0167] Furthermore, the noise also depends on the current flowing through the transistor, and the noise decreases as the current increases.

[0168] For the reasons mentioned above, when the determination unit 401 determines that an image with high illumination is being captured, a determination value that controls the current value of the differential input circuit 61 (transistor 85 in the differential input circuit 61) to a low current value is output to the bias circuit 501. The bias circuit 501 then controls the current value in the differential input circuit 61 to decrease. Therefore, power reduction can be achieved when capturing an image with high illumination.

[0169] Furthermore, when the determination unit 401 determines that a low-light image is being captured, a determination value for controlling the current value of the differential input circuit 61 (transistor 85 in the differential input circuit 61) is output to the bias circuit 501, and the bias circuit 501 is controlled to increase the current value in the differential input circuit 61. This reduces noise when capturing low-light images.

[0170] <Second Construction for Controlling Current in Differential Input Circuits>

[0171] Figure 13 A second construction example of the ADC 42 and its surrounding cells is shown, in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 13 Only the differential input circuit 61 in ADC 42 is shown. DAC 25 is connected to the gate of transistor 81 and is used to control the reference signal REF provided to transistor 81 for differential input circuit 61.

[0172] As described above, DAC 25 generates a reference signal (reference voltage signal) REF and provides it to each pixel 21. The reference signal REF is a slope signal in which the level (voltage) decreases monotonically over time.

[0173] The determination result of the determination unit 401 is provided to the DAC 25. The DAC 25 includes a resistor 551 and a current source 552. In the DAC 25, for example, the current source 552 includes multiple current sources, and the current value of the current source 552 is controlled by controlling the switching on and off of the multiple current sources respectively.

[0174] DAC 25 is configured such that ground (GND) is the reference potential, and the waveform of the DAC (the waveform of the reference signal REF) is determined by the IR voltage drop of the current flowing through resistor 551. It is generally known that current shot noise increases and the noise of DAC 25 deteriorates at higher currents. Considering the voltage range of FD 125 ( Figure 4 For example, in situations where the semaphore is small, such as... Figure 14 As shown, the current in the DAC waveform decreases uniformly.

[0175] exist Figure 14 In the diagram, the solid line represents the waveform of the reference signal REF during the normal time period, and the dashed line represents the waveform of the reference signal REF when the current decreases uniformly. Therefore, by giving the reference signal REF an offset, the noise generated in DAC 25 can be reduced.

[0176] Although it is represented as DC here, it can, for example, be changed along with the offset based on the gain (gradient of the slope). Furthermore, as... Figure 14 As shown by the dashed line, since the DC value of the initial voltage of FD125 can also be reduced, the dark current of FD125 can be suppressed, and the shot noise caused by the dark current of FD125 can also be suppressed. Therefore, random noise can be further reduced.

[0177] That is, in the case of a low-brightness signal (when the signal level is low), control is performed to reduce dark current shot noise by decreasing the current value and setting the initial voltage of the pixel's FD 125 to a low level. On the other hand, in the case of a high-brightness signal (when the signal level is high), control is performed to increase the current and increase the voltage of the FD 125, thereby enabling a high-brightness signal.

[0178] At this point, although dark current shot noise may increase, it is not noticeable due to the high brightness. Furthermore, because a single DAC 25 is used for all pixels, it does not consume as much power as the differential input circuit 61. Therefore, reducing the current of the differential input circuit 61 results in lower power consumption. For example, with 10 Mpixels, the above effect can be achieved at a magnification of 10 M.

[0179] <Third construction for controlling the current of differential input circuits>

[0180] Figure 12 The first configuration shown is for controlling the current of the differential input circuit. Figure 13 The second configuration shown for controlling the current of the differential input circuit can be combined. Figure 15 An example of the construction of the ADC42 and its surrounding units is shown, in which a first construction and a second construction are combined.

[0181] exist Figure 15 In the illustrated ADC 42, a bias circuit 501 is connected to the gate of transistor 85, which controls the current flowing through transistor 85 in the differential input circuit 61. Furthermore, a DAC 25 is connected to the gate of transistor 81, which controls the reference signal REF supplied to transistor 81 in the differential input circuit 61.

[0182] The determination result of the determination unit 401 is provided to the bias circuit 501 and DAC 25. The control performed by the bias circuit 501 and DAC 25 is similar to that described above.

[0183] That is, when the determination unit 401 determines that the signal value is a low-brightness signal (low signal level) that should be noise-resistant, the bias circuit 501 feeds back the current value to the analog circuit (e.g., ADC 42), and the operating direction of the bias circuit 501 is to reduce noise. In the case of the differential input circuit 61, control is performed to increase the current value of the current Icm flowing in the differential input circuit 61, and control is performed to reduce the thermal noise generated by the circuit.

[0184] Conversely, DAC 25 performs control by reducing dark current shot noise by decreasing the current value and setting the initial voltage of the pixel's FD125 to low.

[0185] When the illuminance is high, the bias circuit 501 performs control to reduce the current Icm in the differential input circuit 61. At this time, although noise is increased, the power consumption of the differential input circuit 61 is reduced. Conversely, the DAC 25 performs control to increase the current and the voltage of the FD 125, thereby enabling the acquisition of a signal with high brightness.

[0186] Even with the above-described configuration, the current flowing through the differential input circuit 61 can be controlled, and noise can be controlled. Furthermore, by controlling the current flowing through the multiple transistors in the differential input circuit 61 individually, noise can be controlled more appropriately.

[0187] <Fourth construction for controlling the current of differential input circuits>

[0188] As described above, noise can be suppressed according to the first to third configurations of the differential input circuit. For example, as by Figure 14 As shown by the dashed line and the accompanying description, according to this technology, since the DC value of the initial voltage of FD 125 can also be reduced, the dark current of FD 125 can be suppressed, and shot noise caused by the dark current of FD 125 can also be suppressed. Therefore, random noise can be further reduced.

[0189] That is, in the case of a low-brightness signal (when the signal level is low), control is performed to reduce dark current shot noise by decreasing the current value and setting the initial voltage of the pixel's FD 125 to a low value. On the other hand, in the case of a high-brightness signal (when the signal level is high), control is performed to increase the current and increase the voltage of the FD 125, thereby enabling the acquisition of a high-brightness signal.

[0190] By the way, if Figure 16 As shown, at time t11, when the initial voltage of FD 125 is set to a low voltage (high potential), that is, when the reset voltage V used to reset the charge of FD 125 is set... rst When set to low voltage (high potential), even if the transmission gate is opened at time t12 (TG in the figure), the remaining charge in FD 125 will not flow back to the PD 121 side.

[0191] However, as Figure 17 As shown, at time t21, when the initial voltage of FD 125 is set to a high voltage (low potential), that is, when the reset voltage Vrst used to reset the charge of FD 125 is set to a high voltage (low potential), when the transfer gate (TG in the figure) is opened at time t22, the remaining charge in FD 125 may flow back to the PD 121 side.

[0192] As described above, according to the first to third configurations of the differential input circuit, control is performed such that the initial voltage of the pixel's FD125 is set low, thereby reducing dark current shot noise. When the above control is performed, a reference... Figure 17 In the aforementioned situation, the remaining charge in FD 125 may flow back to the PD 121 side.

[0193] Therefore, a description of a fourth configuration for controlling the current of the differential input circuit, which performs control to reduce dark current shot noise and prevent residual charge in FD 125 from flowing back to the PD 121 side, will be given.

[0194] In the fourth configuration for controlling the current of the differential input circuit, in order to suppress the dark current of FD 125, the initial voltage of FD 125 is reduced, and in order to create a situation in which transmission can be carried out without generating backflow charge, control is performed to temporarily increase the voltage of FD 125 during transmission (control for temporarily reducing the potential).

[0195] Figure 18 An example of the construction of the ADC 42 and its surrounding cells is shown (fourth construction) in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 18 The differential input circuit 61 and pixel circuit 41 in ADC 42 are shown.

[0196] Bias circuit 531 is connected to the gate of transistor 85, and bias circuit 531 is used to control the current Icm flowing through transistor 85 of differential input circuit 61. Bias circuit 531 has the following configuration: wherein, in the configuration of bias circuit 501 ( Figure 12 Switches 541 and 542 were added to the device.

[0197] That is, the bias circuit 531 is configured to receive a determination result from the determination unit 401. Furthermore, the bias circuit 531 includes a current source 512 and a plurality of transistors 511. The bias circuit 531 is configured such that the current value of the connected differential input circuit 61 can be changed by altering the number of transistors used among the plurality of transistors constituting the transistors 511.

[0198] In addition, the bias circuit 531 includes switches 541 and 542. When one of switches 541 and 542 is open, the other switch is controlled to be closed.

[0199] Specifically, when the transmission gate TX is turned on, switch 541 is turned off and switch 542 is turned on. Furthermore, at any other time besides when the transmission gate TX is turned on, switch 541 is turned on and switch 542 is turned off.

[0200] The moment when switch 541 is turned off and switch 542 is turned on can be the same as the moment when the transmission gate TX is turned on, or it can be the moment immediately before the transmission gate TX is turned on.

[0201] Through the above control, when the transmission gate TX is turned on and begins to transmit charge from FD 125, switch 541 is opened and switch 542 is closed, so that the gate of transistor 85 is in a grounded state. When the gate of transistor 85 is in a grounded state, the potential of the drain of transistor 85 is raised.

[0202] Since the drain of transistor 85 is connected to the source side of transistor 82, the source potential of transistor 82 is in a raised state.

[0203] The transistor 82 in the differential input circuit 61 acts as an amplifying transistor. When the parasitic capacitance of the amplifying transistor is parasitic capacitance 551, the potential of parasitic capacitance 551 of the amplifying transistor increases when the source side of transistor 85 becomes high.

[0204] Since FD 125 is connected to the amplifying transistor (transistor 82), the potential of FD 125 will eventually rise as the potential of parasitic capacitance 551 rises.

[0205] As described above, when the transfer gate TX is turned on and begins to transfer charge from FD 125, the voltage of FD 125 can be increased by turning off switch 541 and closing switch 542.

[0206] Even in Figure 17 At time t21, as shown, by boosting the voltage of FD 125, it is also possible to temporarily provide... Figure 16 The state at time t11 is shown, and it is able to prevent the remaining charge in FD 125 from flowing back to the PD 121 side.

[0207] Furthermore, by opening switch 541 and closing switch 542, the voltage of FD 125 is temporarily increased. Then, closing switch 541 and opening switch 542 provides a state in which the bias circuit 531 provides the input bias current Vb to transistor 85. Therefore, as described above, it is possible to switch to a state that suppresses the dark current of FD 125 and suppresses shot noise caused by the dark current of FD 125.

[0208] Reference Figure 19 Timing diagram explanation Figure 18 The operation of pixel 21 shown. Figure 19 The timing diagram shown is created by adding a control pulse bias and the voltage value of FD 125. Figure 5 The timing diagram shown is obtained from the timing diagram in which the control pulse bias is used to control whether an input bias current Vb is provided from the bias circuit 531. Therefore, regarding the reference... Figure 5 The descriptions of the content illustrated in the timing diagram have been omitted.

[0209] The control pulse bias is used to control the opening / closing of switches 541 and 542. Here, it is assumed that when the control pulse bias is off, switch 541 is open and switch 542 is closed. Therefore, when the control pulse bias is off, the bias circuit 531 is grounded and the bias current Vb is not supplied to transistor 85.

[0210] Furthermore, when the control pulse bias is on, switch 541 is closed and switch 542 is open. Therefore, when the control pulse bias is on, the bias circuit 531 is in the state where transistor 511 is connected, and the bias current Vb is supplied to transistor 85.

[0211] Therefore, when the control pulse bias switches from on to off, the value of the input bias current Vb from the bias circuit 53 switches from a predetermined current value (e.g., current Ipixbias) to zero (ground).

[0212] At time t7, the transmission transistor 123 of pixel circuit 41 is turned on by transmitting the Hi signal TX, and the charge generated by photodiode 121 is transferred to FD 125. At time t6, before time t7, switch 541 is turned off and switch 542 is turned off by providing a control pulse bias to switch 541 and switch 542.

[0213] Therefore, at time t7, the value Vb of the input bias current from the bias circuit 53 switches from a predetermined current value (e.g., current Ipixbias) to zero (ground).

[0214] At time t6, when the value of the input bias current Vb from the bias circuit 53 is zero, the voltage value of FD125 gradually increases.

[0215] Note that, for example, the moment when the control pulse bias is turned off (the moment when the input bias current Vb from bias circuit 531 is set to zero, i.e., the moment when control switches 541 and 542 are opened / closed) is set before the moment when the transmission signal TX changes to Hi. However, the moment when the transmission signal TX changes to Hi and the moment when the control pulse bias is turned off can be substantially the same (time t7).

[0216] At the point when the transmitted signal TX returns to low (almost simultaneously with or after the transmitted signal TX returns to low), the value of the input bias current Vb from the bias circuit 53 returns to a predetermined current value (e.g., current Ipixbias). That is, in this case, when the control pulse bias is re-conducted, switch 541 is closed and switch 542 is opened.

[0217] When the input bias current Vb from the bias circuit 53 is supplied to the differential input circuit 61, the voltage of FD125 drops.

[0218] In this way, by temporarily increasing the voltage of FD 125 at the start of the transfer, it is possible to prevent the remaining charge in FD 125 from flowing back to the PD 121 side. Furthermore, when the voltage of FD 125 is temporarily increased and then returned to its original state, and charge transfer of FD 125 is performed after the voltage has returned to its original state, transfer that suppresses the generation of dark current in FD 125 can be performed.

[0219] Note that, although Figure 18 The bias circuit 531 shown includes switches 541 and 542 as an example, but the bias circuit 531 may include a single switch. In other words, the bias circuit 531 can be provided for performing the above-described control as long as it includes a switch that is connected to the ground side at the start of transmission and connected to the transistor 511 at other times, and such a configuration is also within the scope of this technology.

[0220] <Fifth construction for controlling the current of differential input circuits>

[0221] Figure 20 An example of the construction of the ADC 42 and its surrounding units is shown (fifth construction) in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 20 The differential input circuit 61 and pixel circuit 41 in ADC 42 are shown.

[0222] exist Figure 20 In the construction shown, with Figure 18 Similarly, bias circuit 571 is connected to the gate of transistor 85, and this bias circuit 571 is used to control the current Icm flowing through transistor 85 of differential input circuit 61. This bias circuit 571 has the following configuration: wherein, in the configuration of bias circuit 531 ( Figure 18 A transistor 581 and a variable current source 582 that constitute a source follower circuit are added to the circuit, and a transistor 583 for adjusting the operating point of the voltage is added.

[0223] Similar to transistor 511, the added transistors 581 and 583 each include multiple transistors.

[0224] For example, in Figure 18In the bias circuit 531 shown, the driving capability of the bias circuit 531 is determined by the transistor connected to the photodiode 121 constituting the pixel 21.

[0225] As the number of pixels connected to the circuit increases, that is, when pixel array unit 22 ( Figure 1 When the number of pixels 21 in the array increases, the number of bias circuits 531 connected to pixels 21 also increases.

[0226] When the number of pixels 21 is increased in this way, it may be difficult to activate the bias circuit 531 within a specified time and difficult to make current flow to all pixels 21 in the pixel array unit 22 (it is difficult to make current flow within a limited ADC time).

[0227] Therefore, adopting such Figure 20 The bias circuit 571 shown is constructed such that it can be activated within a specified time even when the number of pixels 21 increases.

[0228] Figure 20 The bias circuit 571 shown includes a source follower circuit with a transistor 581. This source follower circuit acts as a buffer, and the voltage buffered in the buffer is used to supply the transistor 85. Therefore, by using the buffered voltage, the bias circuit 571 can be activated for a specified time.

[0229] according to Figure 19 The timing diagram shown is used for... Figure 20 The operation of pixel 21, including bias circuitry 571, is shown. (As already referenced...) Figure 19 The timing diagram shown provides an explanation, so its explanation is omitted here.

[0230] Reference Figure 21 and 22 This section illustrates an example of the layout of the bias circuit 571.

[0231] Figure 21 This is a diagram showing an example of the arrangement of the bias circuit 571 relative to the pixel array unit 22. Here, the bias circuit 571 will be described separately for the switching circuit 571a and the bias circuit 571b.

[0232] Switching circuit 571a is a circuit including switch 541 and switch 542, and biasing circuit 571b is a circuit including transistor 511, current source 512, transistor 581, variable current source 582 and transistor 583.

[0233] exist Figure 21In the arrangement example shown, the bias circuit 571 is disposed on one of the four sides of the pixel array unit 22, the switch circuit 571a is disposed on the pixel array unit 22, and the pixel array unit 22 (each pixel 21) is arranged to be connected to the bias circuit 571b through the switch circuit 571a.

[0234] exist Figure 22 In the arrangement example shown, bias circuits 571-1 to 571-4 are respectively disposed on each of the four sides of the pixel array unit 22. Figure 21 As in the example arrangement shown, with regard to the bias circuit 571 provided on each side of the pixel array unit 22, the switching circuits 571a-1 to 571a-4 are provided on the pixel array unit 22 side, and the pixel array unit 22 (each pixel 21) is arranged to be connected to the bias circuits 571b-1 to 571b-4 across the switching circuits 571a-1 to 571a-4.

[0235] exist Figure 21 In the arrangement example shown, the bias circuit 571 is illustrated as being disposed on one of the four sides of the pixel array unit 22, while Figure 22 In the arrangement example shown, the bias circuit 571 is illustrated as being disposed on each of the four sides of the pixel array unit 22. Although not shown, the bias circuit 571 can also be arranged on two of the four sides of the pixel array unit 22, or the bias circuit 571 can also be arranged on three of the four sides of the pixel array unit 22.

[0236] Which of the four sides of the pixel array unit 22 is provided with the bias circuit 571 is a design item that can be appropriately changed according to layout constraints.

[0237] As in Figure 22 In the arrangement example shown, when the bias circuit 571 is arranged on the four sides of the pixel array unit 22, the bias circuit 571 is formed as a transistor with the same characteristics around the pixel array unit 22 and is capable of providing bias current (voltage) from the periphery. With such an arrangement, as in... Figure 21 Compared to the arrangement example shown where the bias circuit 571 is placed on one side of the pixel array unit 22, the characteristic differences between sensors (characteristic differences between pixels 21) can be reduced.

[0238] exist Figure 21 and 22 In the arrangement example shown, the bias circuit 571 has been illustrated as an example. However, Figure 21 or Figure 22 The layout example shown can also be applied to Figure 18The bias circuit 531 shown is shown.

[0239] <Sixth construction for controlling the current of differential input circuits>

[0240] Figure 23 An example of the construction of the ADC 42 and its surrounding cells is shown (sixth construction) in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 23 The differential input circuit 61 and pixel circuit 41 in ADC 42 are shown.

[0241] Figure 23 The pixel circuit 41 shown is constructed as follows: a wiring 611 is provided near FD 125, and FD 125 and wiring 611 are coupled to a configuration for temporarily increasing the voltage of FD 125 at the start of transmission.

[0242] Bias circuit (e.g., Figure 12 The bias circuit 501 shown is connected to the differential input circuit 61 and provides bias current Vb based on the determination result of the determination unit 401.

[0243] Wiring 611 is a metallic wiring, and wiring 611 is configured to apply voltage at the start of transmission. For example, a voltage source can be configured to be connected to wiring 611, and the voltage source can be controlled by the determination unit 401 so that a voltage with a predetermined voltage value is applied to wiring 611 during transmission.

[0244] When a voltage is applied to wiring 611, the voltage across coupled FD 125 increases. When a voltage is applied to wiring 611, the potential of parasitic capacitance 612 increases, and the potential of FD 125 also increases.

[0245] Reference Figure 24 Timing diagram explanation Figure 23 The operation of pixel 21 is shown. Although Figure 24 The timing diagram shown is Figure 19 The timing diagrams shown are similar, but the control pulses (control pulse bias) used to apply voltage to wiring 611 are different. References omitted. Figure 19 The timing diagram shown illustrates a portion of the description.

[0246] At time t7, the transmission transistor 123 of pixel circuit 41 is turned on by transmitting the Hi signal TX, and the charge generated by photodiode 121 is transferred to FD 125. At time t6, prior to time t7, in order to apply voltage to wiring 611, an ON control pulse bias is output to a voltage source (not shown). Therefore, voltage is applied to wiring 611, and the voltage value of FD 125 increases.

[0247] Note that this is illustrated by the following example: the timing of the control pulse bias being turned on is set before the transmission signal TX changes to Hi. However, the timing of the transmission signal TX changing to Hi and the timing of the control pulse bias being turned on can be substantially the same (time t7).

[0248] At the point when the transmitted signal TX returns to low (almost simultaneously with or after the transmitted signal TX returns to low), the control pulse bias is turned off, and the voltage application to wiring 611 ends. When no voltage is applied to wiring 611, the voltage of FD 125 decreases.

[0249] In this way, when the voltage of FD 125 is temporarily increased at the start of the transfer, it is possible to prevent the remaining charge in FD 125 from flowing back to the PD 121 side. Furthermore, when the voltage of FD 125 is temporarily increased and then returned to its original state, and charge transfer of FD 125 is performed after the voltage has returned to its original state, transfer for suppressing the generation of dark current in FD 125 can be performed.

[0250] <The Seventh Construction for Controlling the Current of Differential Input Circuits>

[0251] Figure 25 An example of the construction of the ADC 42 and its surrounding cells is shown (seventh construction) in which the current flowing through the transistor elements in the ADC 42 is controlled according to the determination result of the determination unit 401. Figure 25 The differential input circuit 61 and pixel circuit 41 in ADC 42 are shown.

[0252] exist Figure 25 In the configuration of the differential input circuit 61 shown, transistor 631 is disposed on the drain side of transistor 85 as a means to temporarily increase the voltage of FD 125 at the start of transmission. Transistor 631 acts as a switch and is configured to connect or disconnect (disconnect) transistor 85 in the differential input circuit 61.

[0253] That is, when transistor 631 is in the ON state as a switch, transistor 85 is in the state of being connected in the differential input circuit 61, so the bias current Vb is in the state of being supplied from the bias circuit 501 to transistor 85 and to the source side of transistor 81 or transistor 82.

[0254] On the other hand, when transistor 631 is in the off state as a switch, transistor 85 is in the isolated state in the differential input circuit 61, and the bias current Vb is supplied from the bias circuit 501 to transistor 85 but not to the source side of transistor 81 or transistor 82.

[0255] Furthermore, here, transistor 631 is a transistor including an NMOS transistor. When the control pulse bias is turned on, a voltage is applied to the gate of transistor 631, and transistor 631 is in the on state. When the control pulse bias is turned off, a voltage is not applied to the gate of transistor 631, and transistor 631 is in the off state.

[0256] When transistor 631 includes a PMOS transistor, the above operation is reversed. As for the operation of transistor 631, when the control pulse bias is turned on, a voltage is applied to the gate of transistor 631, and transistor 631 is in the off state; and when the control pulse bias is turned off, a voltage is not applied to the gate of transistor 631, and transistor 631 is in the on state.

[0257] As an alternative to transistor 631, it can include a switch for turning on and off. Note that, considering the formation of the transistor in pixel 21, the advantage of forming it as a transistor rather than a switch is that it can be manufactured using a process similar to that used to form other transistors.

[0258] according to Figure 19 The timing diagram shown is used for execution. Figure 25 The operation of pixel 21, including transistor 631, is shown. (Note: Reference has been made.) Figure 19 The timing diagram shown is explained below, therefore repeated explanations are omitted.

[0259] At time t7, when the transmission transistor 123 of pixel circuit 41 is turned on by the transmission signal TX via Hi, and the charge generated by photodiode 121 begins to be transferred to FD 125 (before the start), the control pulse bias is turned off, no voltage is applied to the gate of transistor 631, transistor 631 is in the off state, the potential of parasitic capacitance 551 increases, and therefore, the voltage of FD 125 increases.

[0260] Subsequently, at the point when the transmission signal TX returns to low (almost simultaneously with or after the transmission signal TX returns to low), when the control pulse bias is re-energized, a voltage is applied to the gate of transistor 631, transistor 631 is in the energized state, the potential of parasitic capacitance 551 decreases, and as a result, the voltage of FD 125 decreases.

[0261] In this way, when the voltage of FD 125 is temporarily increased at the start of the transfer, it is possible to prevent the remaining charge in FD 125 from flowing back to the PD 121 side. Furthermore, after the voltage of FD 125 is increased, charge is transferred from FD 125, and after the transfer, the voltage returns to the original voltage, thereby enabling the transfer to suppress the generation of dark current in FD 125.

[0262] Note that the first through seventh structures can be used individually or in combination to control the current of the differential input circuit.

[0263] <On the application of control>

[0264] As described above, noise in the ADC 42 is controlled based on the determination result of the determination unit 401. (Refer to...) Figure 26 Explain the output time and application time of the judgment result of the judgment unit 401.

[0265] Pixel 21 begins exposure at the scheduled time. (See reference) Figure 5 The driving of pixel 21, as described, always keeps the discharge transistor 122 in a turned-off state. However, as... Figure 5 As shown by the dashed line, at the desired time, the discharge signal OFG is set to Hi, and the discharge transistor 122 is temporarily turned on and then turned off, thereby setting an arbitrary exposure period. For example, the start of exposure can be determined by the falling pulse of OFG ( Figure 5 )Regulation.

[0266] Exposure time is the time from the start of exposure to the fall of the transmission signal TX. Figure 5 With one ADC42 per pixel, the ratio is 1:1. However, when the FD 125 is shared by multiple pixels and uses a single ADC 42, the exposure time can be set separately (pixel sharing will be explained later).

[0267] During the exposure period, a reset (RST) period is set to initialize FD 125 and compare circuit 51. Figure 2 The system automatically zeroes the circuit and prepares for processing in ADC 42. Then, it initializes the positive feedback circuit (PSB) 63 and sets the initial voltage of DAC 25.

[0268] Following the reset period, the P-phase acquisition period (hereinafter referred to as P-phase, P-phase acquisition period, etc.) is the A / D conversion period for the pixel's reset level. The voltage of DAC 25 gradually decreases, and data is written to latch memory cell 72 ( Figure 2When the signal input from pixel circuit 41 to differential input circuit 61 has the same value (same voltage) as the signal from DAC 25, the output of comparator circuit 51 is inverted, and the write data is written to latch memory unit 72.

[0269] Note that here, the case with positive feedback circuit 63 is used as an example to illustrate the circuit used to accelerate the reaction, but any other circuit can be used as long as the circuit can achieve a similar function (store latched data within a predetermined time).

[0270] During the P-phase output period, the ADC 42 outputs the data acquired during the P-phase acquisition period.

[0271] After the P-phase output period, a D-phase acquisition period (hereinafter referred to as D-phase, D-phase acquisition period, etc.) is set. This D-phase acquisition period is the A / D conversion period for the pixel signal level. During the D-phase acquisition period, the transmission transistor 123 ( Figure 4 The circuit is switched on, and the signal from photodiode 121 is transmitted to FD 125. The voltage of DAC 25 gradually decreases, and the time code from time code transmission unit 23 is provided to latch control circuit 71. Figure 2 ).

[0272] When the signal input from pixel circuit 41 to differential input circuit 61 has the same value (same voltage) as the signal of DAC 25, the output of comparator circuit 51 is inverted, and the time code at this time is written to latch memory unit 72.

[0273] By reducing the signal (slope) from DAC 25 to GND level (the voltage that turns off the pixel current), the power consumed by ADC 42 in pixel 21 is set to zero, and a standby state is set.

[0274] On the other hand, during the D-phase output period, the ADC 42 outputs the data acquired during the D-phase acquisition period.

[0275] The processing unit (not shown) for processing signals from ADC 42 performs CDS processing on P-phase and D-phase data, thereby removing fixed pattern noise, FD 125 reset noise, and circuit reset noise.

[0276] At this point, the remaining noise consists of thermal noise, 1 / f noise, and random telegraph signal (RTS) noise, all determined by the current flowing through the analog circuit during operation. To control these noises, they can be reduced by controlling the current value in the output signal level control circuit (ADC 42) as described above.

[0277] Therefore, as a time when noise is controlled based on the output signal level, for example, there exists such... Figure 26 The time indicated. Note that here, noise control performed by the bias circuit 501 is illustrated as an example.

[0278] The signals of all pixels can be read to calculate the average value of these signals, and the amount of current flowing through a predetermined transistor in the ADC 42 can be calculated from the average value. Furthermore, a portion of the D-phase output can be read to determine its brightness value, and the current value (bias value) for the next frame can be calculated.

[0279] exist Figure 26 In the D-phase output period, the determination unit 401 calculates the current value Icm, and after the start of the exposure of the next frame and before the reset period, the calculated current value Icm is applied to the analog circuit, such as the differential input circuit 61 in the ADC 42.

[0280] Note that the current value Icm can be constructed to be calculated during the P-phase output period and can be applied to the current value Icm calculated during the D-phase acquisition period in the same frame. However, in this case, data with different current values ​​Icm applied in the P-phase and D-phase within the same frame will be used, and noise may not be properly eliminated in the CDS of the P-phase data and the D-phase data.

[0281] Therefore, as described above, the current value Icm is calculated during the D-phase output period, and the calculated current value Icm is applied after the start of exposure in the next frame and before the reset period (i.e., during the P-phase acquisition period and D-phase acquisition period in the next frame).

[0282] Note that the current value Icm can be calculated during the P-phase output period, and the calculated current value Icm can be configured for application during the P-phase acquisition period and D-phase acquisition period of the next frame.

[0283] The calculation of the current value Icm will be explained. Here, the case with a maximum output value of 14 bits (from 0 to 16383) will be used as an example. If the output after 8 consecutive CDS frames is less than 4096, the image to be processed (the captured image) is determined to be dark, and the current value Icm is increased to improve noise on the low-light side.

[0284] On the other hand, if the output after 8 frames of CDS has a value greater than 4096, it is considered that there are many high illumination signals, and it is determined that a bright image with shot noise dominating the image can be obtained, and the drive is set to reduce the current value Icm.

[0285] By providing hysteresis in this way, a mechanism can be provided to prevent the screen from flickering near a threshold of 4096. Note that although 8 frames were used as an example here, the number of frames can certainly be any number other than 8.

[0286] <Shared pixel structure>

[0287] In the above embodiment, the comparator circuit 51 is configured such that an ADC 42 is arranged in one pixel 21, but the comparator circuit 51 can be configured such that multiple pixels 21 share one ADC 42.

[0288] Figure 27 This is a circuit diagram illustrating an example of the construction of a comparator circuit 51 in the case of pixel sharing where an ADC 42 is shared by multiple pixels 21. Figure 27 An example of the construction of a comparator circuit 51 is shown in the case where an ADC 42 is shared by four pixels 21 (pixel 21A, pixel 21B, pixel 21C and pixel 21D).

[0289] exist Figure 27 In the above, the construction of the differential input circuit 61, voltage conversion circuit 62, and positive feedback circuit 63 constituting the comparator circuit 51 is similar to that of the other circuits. Figure 2 The structure shown is similar.

[0290] exist Figure 27 In this configuration, four pixels 21A to 21D are equipped with pixel circuits 41A to 41D, and each of the pixel circuits 41A to 41D is equipped with a photodiode 121q, a discharge transistor 122q, and a transmission transistor 123q. On the other hand, the reset transistor 124' and FD 125' are shared by the four pixels 21A to 21D.

[0291] Note that in Figure 27 Although in China, Figure 2 The circuit configuration shown is the circuit configuration of comparator circuit 51, but other circuit configurations can also be used.

[0292] In this way, Figure 12 , 13 The configuration shown in 15 can be applied to shared pixels, in which multiple pixels 21 share a single ADC 42 to control the current in the ADC 42 (the noise of the ADC 42).

[0293] For example, in Figure 27 The differential input circuit 61 shown is constructed in the case of a pixel structure where four pixels share a pixel configuration, and in... Figure 12 The differential input circuit 61 shown is constructed identically to the differential input circuit 61 in the case of a non-pixel-shared pixel configuration. Therefore, for example, with... Figure 12 The situation shown is similar, and it is possible to Figure 27 The pixel configuration shown, which shares four pixels, includes a bias circuit 501, and the bias circuit 501 can be configured to be connected to the gate of the transistor 85 in the differential input circuit 61.

[0294] Using this construction, as in the reference Figure 12 In the aforementioned case, the current flowing through the transistor 85 can be controlled based on the determination of the determination unit 401 (e.g., the determination of whether the brightness is high or low), and the noise generated in the differential input circuit 61 (including the comparator circuit 51 of the differential input circuit 61) can be controlled.

[0295] In addition, with Figure 13 The situation shown is similar, in Figure 27 The four-pixel shared pixel configuration shown includes a DAC 25, which can be configured to be connected to the gate of the transistor 81 in the differential input circuit 61.

[0296] Using this construction, as in the reference Figure 13 In the aforementioned case, the reference signal REF provided to the transistor 81 can be controlled based on the determination of the determination unit 401 (e.g., the determination of whether the brightness is high or low), and the noise generated in the differential input circuit 61 (including the comparison circuit 51 of the differential input circuit 61) can be controlled.

[0297] In addition, with Figure 15 The situation shown is similar, and it is possible to Figure 27 The four-pixel shared pixel configuration shown includes a bias circuit 501 and a DAC 25. The bias circuit 501 can be connected to the gate of the transistor 85 in the differential input circuit 61, and the DAC 25 can be configured to be connected to the gate of the transistor 81 in the differential input circuit 61.

[0298] Using this construction, as in the reference Figure 15 In the aforementioned case, the current flowing through the transistor 85 can be controlled based on the determination of the determination unit 401 (e.g., the determination of whether the brightness is high or low), and the reference signal REF provided to the transistor 81 can be controlled, and the noise generated in the differential input circuit 61 (including the comparison circuit 51 of the differential input circuit 61) can be controlled.

[0299] <On the timing of applying control in shared pixels>

[0300] Reference Figure 28 Explain the output time and application time of the determination result of the determination unit 401 in the shared pixel.

[0301] In a shared pixel, the processing and reference performed by each pixel circuit 41 Figure 26The situation described is similar. That is, each pixel circuit 41 is configured with a reset period, a P-phase acquisition period, a P-phase output period, a D-phase acquisition period, and a D-phase output period after the start of exposure, and performs corresponding processing in each period.

[0302] Here, the case where exposure begins by turning on the discharge transistor 122 (OFG) will be used as an example. In each pixel circuit 41, the exposure period is from the fall of the discharge transistor 122 disposed in the pixel circuit 41 to the fall of the transfer transistor 123.

[0303] By controlling four pixels individually, four global shutter images offset by one pixel in spatial resolution can be obtained. High dynamic range (HDR) video recording can be achieved by controlling the exposure time of these four images individually (without the same exposure time).

[0304] For example, when the exposure time of pixel circuit 41A is Ta, the exposure time of pixel circuit 41B is Tb, the exposure time of pixel circuit 41C is Tc, and the exposure time of pixel circuit 41D is Td, and Ta:Tb:Tc:Td = 1:4:16:64, the dynamic range can be increased by 64 times according to the exposure time ratio.

[0305] Even if the image is saturated at 64x exposure, it can prevent whiteout when it is not saturated at 1x exposure.

[0306] When such a drive is executed, if the image is generally dark and unsaturated at the shortest exposure time Ta, for example, when it is a value below 64 LSB (1 bit), the output after CDS may be below 4096 when acquired with exposure time Td. In this case, for example, as in the reference... Figure 26 In the case described, the exposure time Td (which has the longest exposure time) is read after 8 consecutive frames. After that, the current Icm in the differential input circuit 61 or the current provided to the reference signal Ref (generated by DAC 25) of the differential input circuit 61 is controlled, thereby suppressing the generation of noise.

[0307] Furthermore, when setting accuracy cannot be obtained by using only exposure time Ta due to shot noise and other factors, control can be implemented to combine the signals of exposure time Tb and Tc. In this way, it can be determined whether, for example, the average value at exposure time Tb exceeds 256, the average value at exposure time Tc exceeds 1024, and the result can be applied to exposure time Td after a specific frame.

[0308] Furthermore, the exposure time Td of a predetermined frame can be used for calculation, and the calculated settings can be applied to the exposure times Ta, Tb, Tc, and Td of the next frame after that predetermined frame. Based on this control, power consumption can be optimized by applying only a long exposure Td, during which a dark image that minimizes noise effects is output when shooting with HDR.

[0309] Note that the example given here is the case of four outputs in the order of P phase and D phase. However, the above technique can be applied in a similar manner to the sequential reading of the opposite D phase and P phase, the combined reading of P phase and D phase, or two readings, 16 readings, etc., instead of four readings.

[0310] Note that this explanation uses four-pixel sharing as an example, but this technology can also be applied to other applications such as two-pixel sharing.

[0311] <Multi-substrate structure>

[0312] In the description up to this point, the camera device 1 has been described as being formed on a single semiconductor substrate 11, but the camera device 1 can be constructed by creating circuits on multiple semiconductor substrates 11.

[0313] Figure 29 This is a conceptual diagram of a camera device 1 constructed by stacking two semiconductor substrates 11 (upper substrate 11A and lower substrate 11C).

[0314] A pixel circuit 41, including a photodiode 121, is formed on the upper substrate 11A. The lower substrate 11C is provided with at least a data storage unit 52 for storing time codes and a time code transmission unit 23. The upper substrate 11A and the lower substrate 11C are joined by a metal bonding method such as Cu-Cu.

[0315] Figure 30 An example of a circuit structure formed on an upper substrate 11A and a lower substrate 11C is shown. On the upper substrate 11A, transistors 81, 82, and 85 of the pixel circuit 41 and the differential input circuit 61 of the ADC 42 are formed. On the lower substrate 11C, the circuitry of the ADC 42, excluding transistors 81, 82, and 85, and a timecode transmission unit 23 are formed.

[0316] The upper substrate 11A can be a pixel wafer made solely of NMOS; the lower substrate 11C can be a logic wafer on which circuitry preceding the PMOS included in the differential input circuit 61 is formed. Constructed in this way, in response to the slow response of the PMOS in the differential input circuit 61, when the NOR threshold of the subsequent stage is exceeded, the feedback (positive feedback) to the PMOS on the constant voltage side reacts rapidly.

[0317] Therefore, the time for current to pass through is minimized, while the externally supplied digital signal (Gray code) can be accurately latched and stored. The latched data is output to an external processing unit and used for processing such as CDS.

[0318] <Multi-substrate structure 2>

[0319] Figure 29 and 30 This is an example of constructing the camera device 1 using two semiconductor substrates 11, but the camera device 1 can also be constructed using three semiconductor substrates 11.

[0320] Figure 31 A conceptual diagram is shown showing an imaging device 1 constructed by stacking three semiconductor substrates 11 (upper substrate 11A, middle substrate 11B and lower substrate 11C).

[0321] At least a portion of a pixel circuit 41, including a photodiode 121, and a comparator circuit 51 are formed on the upper substrate 11A. The lower substrate 11C is provided with at least a data storage unit 52 for storing time codes and a time code transmission unit 23. The remaining circuitry of the comparator circuit 51, not provided on the upper substrate 11A, is formed on the intermediate substrate 11B. The upper substrate 11A and the intermediate substrate 11B, as well as the intermediate substrate 11B and the lower substrate 11C, are bonded by, for example, a metal bonding such as Cu-Cu.

[0322] Figure 32 An example of the circuit arrangement of each semiconductor substrate 11 is shown in the case where the camera device 1 includes three semiconductor substrates 11.

[0323] exist Figure 32 In the example, the circuit set on the upper substrate 11A and Figure 30 The circuit of the upper substrate 11A is the same as that shown. The remaining circuit of the comparison circuit 51 is provided on the middle substrate 11B, and the data storage unit 52 and the time code transmission unit 23 are provided on the lower substrate 11C.

[0324] Figures 29 to 32In the example shown, the determination unit 401, the bias circuit 501, and the DAC 25 can be formed on the lower substrate 11C. Alternatively, a substrate that will be further laminated on the lower substrate 11C can be provided, and the determination unit 401, the bias circuit 501, and the DAC 25 can be formed on this substrate.

[0325] Furthermore, the camera device 1 may have a stacked structure, and the ADC 42 may be configured to be connected to each pixel. For example, a photoelectric conversion element (photodiode 121) may be included in the first layer, the conversion unit (ADC 42) may be connected to each photoelectric conversion element, and the conversion unit may be configured to be formed in a second layer below the first layer.

[0326] Furthermore, there may be a structure containing multiple image sensors (camera device 1) with two or more layers, and each of the multiple image sensors may be a camera device 1 used to detect different types of light (e.g., radiation, infrared light, or ambient light).

[0327] <Other Structures>

[0328] This technology is not limited to reference. Figure 10 The scope of application of the above-described constructions can also be applied, for example, to the constructions shown below.

[0329] Figure 33 This is a diagram illustrating another configuration of the ADC 42 and its peripheral circuitry using this technology. According to... Figure 10 The comparison of the structures shown Figure 33 The configuration shown is such that a source follower 702 and a CDS 704 are added between the pixel circuit 41 and the ADC 42 (between the pixel circuit 41 and the adder unit 303). Additionally, an adder unit 701 for controlling noise in the source follower 702 and an adder unit 703 for controlling noise in the CDS 704 are added.

[0330] The decision unit 401 controls the noise levels of the source follower 702, CDS 704, and ADC 42 based on the output of ADC 42. The decision unit 401 controls the noise level of at least one of the source follower 702, CDS 704, and ADC 42.

[0331] Figure 33 The following scenario illustrates that the determination result of determination unit 401 is provided to adder units 701, 703, and 303; however, for example, the determination result can be configured to be provided only to adder unit 701 of source follower 702. Furthermore, the determination result of determination unit 401 can be provided only to CDS 704 or ADC 42.

[0332] In addition, such as Figure 33 As shown, the determination result of determination unit 401 can be provided to addition unit 701, addition unit 703 and addition unit 303 respectively, and the noise level of source follower 702, CDS 704 and ADC 42 can be controlled respectively. At this time, the same determination result can be provided, or different determination results suitable for each can be provided.

[0333] exist Figure 33 In the illustrated configuration, for example, controlling the current of the current source of the source follower 702 reduces noise and power consumption. Furthermore, for example, controlling the current of the analog elements constituting the CDS 704 reduces noise and power consumption. Additionally, controlling the current in the ADC 42 as described above reduces noise and power consumption.

[0334] Figure 34 This is a diagram illustrating another configuration of the ADC 42 and its peripheral circuitry using this technology. According to... Figure 10 The comparison of the structures shown Figure 34 The configuration shown is such that a source follower 702 is added between pixel circuit 41 and ADC 42 (between pixel circuit 41 and adder unit 303). Additionally, an adder unit 701 is added to control noise in the source follower 702.

[0335] Figure 34 The illustrated configuration demonstrates the application of this technique to a ramp-type array ADC. In this configuration, only one of the source follower 702 and ADC 42 can be configured to control the noise level. Furthermore, the noise levels of the source follower 702 and ADC 42 can be controlled separately.

[0336] While controlling the noise levels of the source follower 702 and the ADC 42, the same decision result or a different decision result can be provided regarding the decision result from the decision unit 401.

[0337] exist Figure 34 In the illustrated configuration, for example, the current of the current source of the source follower 702 is controlled, thus reducing noise and power consumption. Furthermore, when the current in the ADC 42 is controlled as described above, noise and power consumption are also reduced.

[0338] Figure 35 This is a diagram illustrating another configuration of the ADC 42 and its peripheral circuitry using this technology. According to... Figure 10 The comparison of the structures shown Figure 35The configuration shown is such that a source follower 702 is added between pixel circuit 41 and ADC 42 (between pixel circuit 41 and adder unit 303). Additionally, an adder unit 701 is added to control noise in the source follower 702. Furthermore, a decision unit 611 is added to control ADC 42 based on the output of the source follower 702.

[0339] Figure 35 The illustrated configuration demonstrates the application of this technique to an adaptive gain multi-slope ADC. In this configuration, only one of the source follower 702 and ADC 42 can be configured to control the noise level. Furthermore, the noise levels of the source follower 702 and ADC 42 can be controlled separately.

[0340] While controlling the noise levels of the source follower 702 and the ADC 42, the determination result of the determination unit 401 can provide the same determination result or different determination results.

[0341] exist Figure 35 In the illustrated configuration, for example, controlling the current of the current source of the source follower 702 reduces noise and power consumption. Furthermore, controlling the current in the ADC 42 as described above also reduces noise and power consumption.

[0342] Figure 36 This is a diagram illustrating another configuration of the ADC 42 and its peripheral circuitry using this technology. According to... Figure 10 The comparison of the structures shown Figure 36 The configuration shown is such that a source follower 702 and a gain amplifier 722 are added between pixel circuit 41 and ADC 42 (between pixel circuit 41 and adder unit 303). Additionally, adder unit 701 for controlling noise in source follower 702 and adder unit 721 for controlling noise in gain amplifier 722 are also added.

[0343] The decision unit 401 controls the noise levels of the source follower 702, the gain amplifier 722, and the ADC 42 based on the output of the ADC 42. The decision unit 401 controls the noise level of at least one of the source follower 702, the gain amplifier 722, and the ADC 42.

[0344] The decision unit 401 can provide the same or different decision results to the source follower 702, the gain amplifier 722 and the ADC 42.

[0345] exist Figure 36In the illustrated configuration, for example, controlling the current of the current source of the source follower 702 reduces noise and power consumption. Furthermore, for example, controlling the current of the analog elements constituting the gain amplifier 722 reduces noise and power consumption. Additionally, controlling the current in the ADC 42 as described above reduces noise and power consumption.

[0346] This technology can be applied to any of the above-mentioned structures, and by applying this technology, the current consumed by analog circuits such as source followers, gain amplifiers, CDS or ADCs can be adaptively and variably adjusted according to the output signal after AD conversion, so as to achieve low power under high illumination and low noise under low illumination.

[0347] In addition, refer to Figures 29 to 32 The described layered structure can be applied to any of the above constructions.

[0348] <Examples of Electronic Device Applications>

[0349] This invention is not limited to applications in camera devices. That is, it can generally be applied to electronic devices that use camera devices in a camera unit (photoelectric conversion unit), such as: camera devices like digital cameras or camcorders; portable terminal devices with camera functionality; or copiers that use a camera device as an image reading unit. The camera device can be in the form of a chip, or it can be in the form of a module with camera functionality, in which the camera unit and signal processing unit or optical system are packaged together.

[0350] Figure 37 This is a block diagram illustrating an example of the construction of a camera device as an electronic device according to the present invention.

[0351] Figure 37 The imaging device 800 includes: an optical unit 801 having a lens group, etc.; an imaging device (image-capturing device) 802 employing the structure of the imaging device 1 described above; and a digital signal processor (DSP) circuit 803, which is a camera signal processing circuit. Furthermore, the imaging device 800 also includes a frame memory 804, a display unit 805, a recording unit 806, an operation unit 807, and a power supply unit 808. The DSP circuit 803, frame memory 804, display unit 805, recording unit 806, operation unit 807, and power supply unit 808 are interconnected via a bus 809.

[0352] The optical unit 801 receives incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 802. The imaging device 802 converts the amount of incident light from which the optical unit 801 forms the image on the imaging surface into an electrical signal pixel by pixel, and outputs the electrical signal as a pixel signal.

[0353] The display unit 805 includes, for example, a panel-type display device (e.g., a liquid crystal panel or an organic electroluminescence (EL) panel), and displays moving or still images captured by the imaging device 802. The recording unit 806 records the moving or still images captured by the imaging device 802 onto a recording medium such as a hard disk or semiconductor memory.

[0354] The operation unit 807 issues operation commands for various functions of the camera device 800 under the user's operation. The power supply unit 808 appropriately supplies various power sources to the DSP circuit 803, frame memory 804, display unit 805, recording unit 806, and operation unit 807 as operating power sources.

[0355] The camera device 1 with the above-described structure can be used as camera device 802.

[0356] This invention is applicable not only to camera devices, but also to all semiconductor devices having other semiconductor integrated circuits.

[0357] The embodiments of the present invention are not limited to the foregoing embodiments, but various changes can be made without departing from the spirit of the present invention.

[0358] Although the circuit structures of the above embodiments have been described as circuit structures using electrons as charges, the present invention can also be a circuit structure using holes as charges. Furthermore, in each of the above circuit structures, it is possible to implement a circuit structure that switches the polarity of transistors (NMOS transistors and PMOS transistors). In this case, the control signal input to the transistor is a signal that inverts Hi and Low.

[0359] In each of the above embodiments, although the reference signal REF has been described as a slope signal in which the level (voltage) decreases monotonically with time, the reference signal REF can also be a slope signal in which the level (voltage) increases monotonically with time.

[0360] Furthermore, it is possible to combine all or part of the foregoing embodiments. It is also possible to provide forms in which other embodiments not described in the above embodiments are appropriately combined.

[0361] <Application Examples of In Vivo Information Acquisition Systems>

[0362] The technology according to the present invention (the technology) is applicable to various products. For example, the technology according to the present invention can be applied to endoscopic surgical systems.

[0363] Figure 38 This is a block diagram illustrating an example of a schematic construction of a patient in vivo information acquisition system using a capsule endoscope, the technology of which (the present technology) can be applied to the in vivo information acquisition system.

[0364] The in vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200.

[0365] During the examination, the patient swallows a capsule endoscope 10100. The capsule endoscope 10100 has camera and wireless communication functions. It moves inside organs such as the stomach and intestines by peristalsis until it is naturally expelled by the patient. It sequentially takes images of the inside of the organs (hereinafter also referred to as in vivo images) at predetermined intervals and sequentially wirelessly transmits information about the in vivo images to an external control device 10200 outside the body.

[0366] The external control device 10200 provides overall control over the operation of the in vivo information acquisition system 10001. Furthermore, the external control device 10200 receives information about in vivo images transmitted from the capsule endoscope 10100, and based on the received information about the in vivo images, generates image data for displaying the in vivo images on a display device (not shown).

[0367] In the in vivo information acquisition system 10001, in this way, in vivo images obtained by photographing the patient's physical condition can be acquired at any time during the period from when the capsule endoscope 10100 is swallowed to when it is expelled.

[0368] The construction and function of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

[0369] The capsule endoscope 10100 includes a capsule-shaped housing 10101. The housing 10101 houses a light source unit 10111, a camera unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116, and a control unit 10117.

[0370] The light source unit 10111 includes a light source such as a light-emitting diode (LED), and the light source unit 10111 uses light to illuminate the imaging area of ​​the imaging unit 10112.

[0371] The imaging unit 10112 includes an image sensor and an optical system consisting of multiple lenses disposed in front of the image sensor. Reflected light (hereinafter referred to as observation light) that illuminates the body tissue to be observed is collected by the optical system and incident on the image sensor. In the imaging unit 10112, the observation light incident on the image sensor undergoes photoelectric conversion to generate an image signal corresponding to the observation light. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

[0372] The image processing unit 10113 is composed of a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various types of signal processing on the image signals generated by the camera unit 10112. The image processing unit 10113 provides the processed image signals as raw data to the wireless communication unit 10114.

[0373] The wireless communication unit 10114 performs predetermined processing, such as modulation processing, on the image signal that has been processed by the image processing unit 10113, and transmits the image signal to the external control device 10200 via the antenna 10114A. Furthermore, the wireless communication unit 10114 receives control signals related to the drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signals received from the external control device 10200 to the control unit 10117.

[0374] The power supply unit 10115 includes an antenna coil for receiving power, a power regeneration circuit for regenerating power from the current generated in the antenna coil, and a boost circuit. Power is generated in the power supply unit 10115 using a principle known as contactless charging.

[0375] The power supply unit 10116 is composed of a secondary battery and stores the power generated by the power supply unit 10115. Figure 38 To avoid complicating the accompanying drawings, illustrations such as arrows indicating the objects from which power is supplied from the power supply unit 10116 are omitted. However, the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117, and can be used to drive these units.

[0376] The control unit 10117 includes a processor such as a CPU and controls the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power supply unit 10115 according to control signals sent from the external control device 10200.

[0377] The external control device 10200 comprises a processor such as a CPU or GPU, a microcomputer, or a control board in which a processor and storage elements (e.g., memory) are installed. The external control device 10200 controls the operation of the capsule endoscope 10100 by sending control signals to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the illumination conditions of the observed target in the light source unit 10111 can be changed via the control signals from the external control device 10200. Furthermore, the imaging conditions (e.g., the frame rate or exposure value in the imaging unit 10112) can be changed via the control signals from the external control device 10200. Additionally, the processing content in the image processing unit 10113 and the conditions for transmitting image signals in the wireless communication unit 10114 can be changed via the control signals from the external control device 10200 (e.g., the transmission interval or the number of images transmitted).

[0378] Furthermore, the external control device 10200 performs various types of image processing on the image signals transmitted from the capsule endoscope 10100 to generate image data for displaying the captured intraoperative images on a display device. For example, various signal processing can be performed, such as imaging processing (de-mosaic processing), high image quality processing (band enhancement processing, super-resolution processing, noise reduction (NR) processing, and / or jitter correction processing, etc.), and / or magnification processing (electronic zoom processing). The external control device 10200 controls the drive of the display device, thereby displaying the captured intraoperative images based on the generated image data. Alternatively, the external control device 10200 can cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print out the generated image data.

[0379] Examples of in vivo information acquisition systems to which the technology according to the present invention is applicable have been described. In the above-described configuration, the technology according to the present invention can be applied to, for example, any of the light source unit 10111 to the control unit 10117. Specifically, including... Figure 3 The imaging device 1, such as the ADC 42 shown, can be applied to the imaging unit 10112.

[0380] <Examples of the Application of Endoscopic Surgical Systems>

[0381] The technology according to the present invention (the technology) is applicable to various products. For example, the technology according to the present invention can be applied to endoscopic surgical systems.

[0382] Figure 39 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system capable of applying the technology (the technology) according to the present invention.

[0383] Figure 39 The illustration shows a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy delivery device 11112; a support arm device 11120 for supporting the endoscope 11100; and a trolley 11200 equipped with various devices for endoscopic surgery.

[0384] Endoscope 11100 includes: a tube 11101, wherein a region having a predetermined length from its distal end is inserted into a body cavity of a patient 11132; and a camera 11102 connected to the base of the tube 11101. In the example shown, an endoscope 11100 configured as a so-called rigid endoscope including a rigid tube 11101 is illustrated. However, endoscope 11100 can also be configured as a so-called flexible endoscope including a flexible tube.

[0385] An opening for mounting an objective lens is provided at the end of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the end of the endoscope tube 11101 through a light guide extending inside the endoscope tube 11101, and then illuminated towards the object of observation in the body cavity of the patient 11132 through the aforementioned objective lens. Note that the endoscope 11100 can be a forward-viewing endoscope, or an oblique-viewing endoscope, or a side-viewing endoscope.

[0386] The camera 11102 includes an optical system and an imaging element, and reflected light (observation light) from the observed target is converged onto an image sensor via the optical system. The observation light undergoes photoelectric conversion by the image sensor, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is sent as raw data to the camera control unit (CCU) 11201.

[0387] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), and controls the operation of the endoscope 11100 and the display device 11202 as a whole. Furthermore, the CCU 11201 receives image signals from the camera 11102 and performs various image processing operations on the image signals, such as image processing (de-mosaicing), for displaying images based on the image signals.

[0388] Under the control of CCU 11201, display device 11202 displays an image based on an image signal (image processed by CCU 11201).

[0389] For example, the light source device 11203 includes a light source such as a light emitting diode (LED) and provides illumination light to the endoscope 11100 when photographing the surgical site.

[0390] Input device 11204 is the input interface of endoscopic surgery system 11000. Users can input various information items or commands regarding endoscopic surgery system 11000 through input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, and focal length, etc.).

[0391] The treatment tool control device 11205 controls the drive of the energy treatment tool 11112 for cauterizing and cutting tissue, or sealing blood vessels, etc. To ensure the field of vision of the endoscope 11100 and the surgeon's working space, the pneumoperitoneum device 11206 delivers gas into the body cavity through the pneumoperitoneum tube 11111, thereby expanding the body cavity of the patient 11132. The recorder 11207 is a device capable of recording various information items related to the surgery. The printer 11208 is a device capable of printing various information items related to the surgery in various forms such as text, images, or charts.

[0392] Note that, for example, the light source device 11203 that provides illumination to the endoscope 11100 when photographing the surgical site can be composed of a white light source, which may be composed of an LED, a laser light source, or a combination of LEDs and laser light sources. When the white light source includes a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision; therefore, the white balance of the captured image can be adjusted using the light source device 11203. Furthermore, in this case, the lasers from the R, G, and B laser sources illuminate the object of observation in a time-division manner, and the driving of the image sensor of the camera 11102 is controlled synchronously with the illumination sequence; therefore, images corresponding to each of the R, G, and B sources can also be captured in a time-division manner. According to this method, color images can be obtained even without a color filter in the image sensor.

[0393] Furthermore, the drive of the light source device 11203 can be controlled to change the light intensity to be output at predetermined intervals. The drive of the image sensor of the camera 11102 is controlled synchronously with the time of light intensity change, images are acquired in a time-division manner, and these images are synthesized. Therefore, it is possible to produce high dynamic range images without so-called black defects and overexposure.

[0394] Furthermore, the light source device 11203 can be configured to provide light of a predetermined wavelength band corresponding to special light imaging. In special light imaging, for example, by utilizing the wavelength dependence of light absorption in human tissue, a narrower bandwidth of light than the illumination light used in conventional observation (i.e., white light) is applied to perform so-called narrowband imaging of predetermined tissues such as blood vessels in the mucosal surface with high contrast. Alternatively, in special light imaging, fluorescence imaging can be performed, i.e., obtaining an image by fluorescence generated by irradiation with excitation light. In fluorescence imaging, for example, human tissue is irradiated with excitation light and the fluorescence from the human tissue is observed (autofluorescence imaging), or a reagent such as indocyanine green (ICG) is locally injected into human tissue, and the human tissue is irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to provide narrowband light and / or excitation light corresponding to such special light imaging.

[0395] Figure 40 It is shown Figure 39 A block diagram illustrating an example of the functional configuration of the camera 11102 and CCU 11201.

[0396] Camera 11102 includes a lens unit 11401, an image capture unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are connected to each other via a transmission cable 11400.

[0397] Lens unit 11401 is an optical system disposed in the connection portion with lens barrel 11101. Observation light introduced from the end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 includes a combination of multiple lenses (including zoom lenses and focusing lenses).

[0398] The image sensor constituting the camera unit 11402 can be a single sensor (so-called single-plate type) or multiple sensors (so-called multi-plate type). When the camera unit 11402 is configured as a multi-plate type, for example, each image sensor can generate image signals corresponding to R, G, and B respectively, and a color image can be obtained by combining these image signals. Alternatively, the camera unit 11402 may include a pair of image sensors for acquiring right-eye and left-eye image signals respectively corresponding to three-dimensional (3D) display. Performing 3D display allows the surgeon 11131 to more accurately determine the depth of biological tissue in the surgical area. Note that when the camera unit 11402 is configured as a multi-plate type, multiple lens units 11401 can be provided corresponding to each image sensor.

[0399] Furthermore, the camera unit 11402 does not necessarily have to be located within the camera 11102. For example, the camera unit 11402 can be located inside the lens barrel 11101 and immediately behind the objective lens.

[0400] The drive unit 11403 includes an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and focusing lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0401] The communication unit 11404 includes communication means for sending various information items to and receiving various information items from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the camera unit 11402 as raw data to the CCU 11201 via the transmission cable 11400.

[0402] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and provides these control signals to the camera control unit 11405. For example, the control signals include information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0403] Note that imaging conditions such as frame rate, exposure value, magnification, and focus, as described above, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, so-called automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions are provided in the endoscope 11100.

[0404] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0405] The communication unit 11411 includes communication means for sending various information items to and receiving various information items from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via the transmission cable 11400.

[0406] Furthermore, the communication unit 11411 sends control signals for controlling the drive of the camera 11102 to the camera 11102. The image signals and control signals described above can be transmitted via electrical communication or optical communication, etc.

[0407] The image processor 11412 performs various image processing operations on the image signal, which is raw data sent from the camera 11102.

[0408] The control unit 11413 performs various controls related to imaging the surgical site, etc., through the endoscope 11100, and displays the images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0409] Furthermore, based on the image signal processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site, etc. At this time, the control unit 11413 can identify various objects in the captured image by utilizing various image recognition technologies. For example, the control unit 11413 detects the shape or color of the edges of objects included in the captured image, and thus can identify surgical tools such as forceps, specific biological sites, bleeding, and haze when using the energy treatment tool 11112. When the captured image is displayed on the display device 11202, the control unit 11413 can use the recognition results to display various surgical assistance information items to be superimposed on the image of the surgical site. The surgical assistance information is superimposed and presented to the surgeon 11131, thereby reducing the burden on the surgeon 11131 and enabling the surgeon 11131 to perform surgery reliably.

[0410] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable thereof.

[0411] Here, in the example shown, communication is performed in a wired manner using transmission cable 11400. However, communication between camera 11102 and CCU 11201 can also be performed wirelessly.

[0412] Examples of endoscopic surgical systems in which the technology according to the present invention can be applied have been described. In the above-described configuration, the technology according to the present invention can be applied to endoscope 11100, camera 11102 (image processing unit 11402 of camera 11102), and CCU 11201 (image processing unit 11412 of CCU 11201), etc. Specifically, including Figure 3 The imaging device 1 of the ADC42 shown can be applied to the imaging unit 10402.

[0413] Note that although an endoscopic surgical system has been described here as an example, the technology according to the present invention can also be applied to, for example, microscopic surgical systems.

[0414] <Examples of applications of moving objects>

[0415] The technology according to the present invention (the technology) is applicable to a variety of products. For example, the technology according to the present invention can be implemented as a device mounted on any type of mobile body, such as: automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, and robots, etc.

[0416] Figure 41This is a block diagram illustrating a schematic example of the construction of a vehicle control system, which is an example of a mobile body control system capable of applying the technology according to the present invention.

[0417] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 41 In the example shown, the vehicle control system 12000 includes: a driveline control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0418] The driveline control unit 12010 controls the operation of equipment related to the vehicle's driveline according to various programs. For example, the driveline control unit 12010 functions as a control device for the following equipment: drive force generating equipment, such as an internal combustion engine or drive motor, for generating the vehicle's drive force; drive force transmission mechanism for transmitting the drive force to the wheels; steering mechanism for adjusting the vehicle's steering angle; and braking equipment for generating the vehicle's braking force.

[0419] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for devices such as: keyless entry systems; smart key systems; power windows; or various lights such as headlights, reversing lights, brake lights, hazard lights, or fog lights. In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from a portable device that replaces the key. The body system control unit 12020 accepts these radio wave or signal inputs and controls the vehicle's door locks, power windows, or lights, etc.

[0420] The exterior information detection unit 12030 detects information related to the exterior of the vehicle, including the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like pedestrians, vehicles, obstacles, traffic signs, or text on the road surface, or detecting distances.

[0421] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output this electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0422] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for capturing images of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or it can determine whether the driver is dozing off.

[0423] Based on information about the exterior and interior of the vehicle acquired by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking system, and can output control commands to the drive line control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing advanced driver assistance system (ADAS) functions, including: collision avoidance or mitigation, distance-based following, cruise control, collision warning, or lane departure warning, etc.

[0424] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism, or braking system based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing cooperative control for achieving autonomous driving and the like, which does not depend on the driver's operation.

[0425] Furthermore, based on the external information of the vehicle obtained by the external information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights according to the position of the preceding vehicle or oncoming vehicle detected by the external information detection unit 12030, so as to switch the high beams to the low beams, thereby performing cooperative control for anti-glare purposes.

[0426] The audio and image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of visually or audibly notifying passengers in the vehicle or outside the vehicle of information. Figure 41In the example, audio speaker 12061, display unit 12062, and instrument panel 12063 are illustrated as output devices. For example, display unit 12062 may include at least one of an in-vehicle display or a head-up display.

[0427] Figure 42 This is a diagram showing an example of the mounting location of the camera unit 12031.

[0428] exist Figure 42 In the middle, camera units 12101, 12102, 12103, 12104 and 12105 are set as camera unit 12031.

[0429] For example, camera units 12101, 12102, 12103, 12104, and 12105 are located on the front nose, rearview mirrors, rear bumper, rear door, and the upper part of the windshield inside the passenger compartment of vehicle 12100. Camera unit 12101 attached to the front nose and camera unit 12105 attached to the upper part of the windshield inside the passenger compartment primarily acquire images of the front area of ​​vehicle 12100. Camera units 12102 and 12103 attached to the rearview mirrors primarily acquire images of the side areas of vehicle 12100. Camera unit 12104 attached to the rear bumper or rear door primarily acquires images of the rear area of ​​vehicle 12100. Camera unit 12105 attached to the upper part of the windshield inside the passenger compartment is mainly used to detect vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0430] Notice, Figure 42 Examples of the camera ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the camera range of camera unit 12101 attached to the front nose. Camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 attached to the rearview mirrors, respectively. Camera range 12114 represents the camera range of camera unit 12104 attached to the rear bumper or rear door. For example, overlaying the image data captured by camera units 12101 to 12104 will provide a top-down view of the vehicle 12100.

[0431] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple image sensors, or may be an image sensor having pixels for phase difference detection.

[0432] For example, by determining the distance to each three-dimensional object within the camera range 12111-12114 and the change of that distance over time (relative speed to vehicle 12100) based on distance information obtained from camera units 12101-12104, specifically, microcomputer 12051 can extract the closest three-dimensional object traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., greater than or equal to 0 km / h) in the lane of vehicle 12100 as the preceding vehicle. Furthermore, microcomputer 12051 can preset the vehicle distance to be maintained with the preceding vehicle and can perform automatic braking control (including follow-stop control) and automatic acceleration control (including follow-start control), etc. In this way, cooperative control for achieving autonomous driving, etc., that does not rely on driver operation, can be performed.

[0433] For example, while classifying data based on distance information obtained from camera units 12101-12104 into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, the microcomputer 12051 can extract three-dimensional object data of the aforementioned three-dimensional objects and use this data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around vehicle 12100 into obstacles that are visually recognizable to the driver of vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk to represent the degree of danger of colliding with each obstacle, and when the collision risk is higher than or equal to a set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through audio speaker 12061 and display unit 12062, or execute forced deceleration or evasive steering through drive line control unit 12010 to perform driving assistance for collision avoidance.

[0434] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. For example, this pedestrian identification is performed by: extracting feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object and identifying whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and identifies the pedestrian, the audio and image output unit 12052 controls the display unit 12062 to overlay a rectangular outline for emphasis on the identified pedestrian. Furthermore, the audio and image output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0435] Thus far, an example of a vehicle control system to which the technology according to the present invention is applicable has been described. In the above-described configuration, the technology according to the present invention can be applied, for example, to camera unit 12031. Specifically, it includes... Figure 3 The imaging device 1 of the ADC 42 shown can be applied to the imaging unit 12031.

[0436] Note that in this specification, "system" refers to an entire device consisting of multiple devices.

[0437] Note that the effects described in this specification are illustrative and not limiting, and may provide other effects.

[0438] Note that the embodiments of this technology are not limited to the foregoing embodiments, but various changes can be made without departing from the spirit of this technology.

[0439] Note that this technique can be constructed as follows. (1)

[0441] A camera device, comprising:

[0442] Photoelectric conversion element;

[0443] A conversion unit is used to convert signals from the photoelectric conversion element into digital signals;

[0444] A bias circuit is provided to provide a bias current, which controls the current flowing through the analog circuitry in the conversion unit; and

[0445] The control unit is configured to control the bias circuit based on the output signal from the conversion unit, wherein,

[0446] When the transfer of charge from the photoelectric conversion element begins, the control unit increases the voltage at a predetermined location in the analog circuit. (2)

[0448] According to the camera device of (1), the conversion unit uses a slope signal whose level decreases monotonically with time to convert the signal from the photoelectric conversion element into the digital signal. (3)

[0450] According to the camera device described in (1) or (2), when the level of the output signal is high, the control unit performs control to reduce the current flowing through the analog circuit. (4)

[0452] The camera device according to any one of (1) to (3), wherein, when the level of the output signal is low, the control unit performs control for increasing the current flowing through the analog circuit. (5)

[0454] The camera device according to any one of (1) to (4), wherein the voltage at the predetermined position of the analog circuit is the voltage of the floating diffusion layer. (6)

[0456] The camera device according to any one of (1) to (5), wherein

[0457] The bias circuit includes a switch, and

[0458] The control unit controls the switch such that when the charge from the photoelectric conversion element begins to be transferred, the bias current from the bias circuit is not provided to the analog circuit. (7)

[0460] According to the camera device described in (6), the switch is connected to the ground side when the charge from the photoelectric conversion element is started to be transmitted. (8)

[0462] According to the camera device described in (6), the bias circuit includes a source follower circuit. (9)

[0464] The camera device according to any one of (1) to (5) further includes:

[0465] Wiring for applying voltage to the predetermined location of the analog circuit, wherein,

[0466] When the charge from the photoelectric conversion element begins to be transferred, a voltage is applied to the wiring. (10)

[0468] The camera device according to any one of (1) to (5) further includes:

[0469] A transistor is used to connect or disconnect the portion receiving the supply from the bias circuit from the predetermined position of the analog circuit, wherein...

[0470] When the transfer of charge from the photoelectric conversion element begins, the transistor enters the off state. (11)

[0472] An electronic device, comprising:

[0473] The camera device includes:

[0474] Photoelectric conversion element;

[0475] A conversion unit is used to convert signals from the photoelectric conversion element into digital signals;

[0476] A bias circuit is provided to provide a bias current, which controls the current flowing through the analog circuitry in the conversion unit; and

[0477] The control unit is configured to control the bias circuit based on the output signal from the conversion unit, wherein,

[0478] When the transfer of charge from the photoelectric conversion element begins, the control unit increases the voltage at a predetermined location in the analog circuit.

[0479] List of reference numerals

[0480] 1 camera device

[0481] 21 pixels

[0482] 22-pixel array unit

[0483] 23 Timecode Transmission Unit

[0484] 25DAC

[0485] 26 Timecode Generation Units

[0486] 28 Output Units

[0487] 41-pixel circuit

[0488] 42ADC

[0489] 51 Comparator Circuit

[0490] 52 Data storage units

[0491] 61 Differential Input Circuit

[0492] 62 Voltage Conversion Circuit

[0493] 63 Positive Feedback Circuit

[0494] 71 Latch Control Circuit

[0495] 72 latch memory units

[0496] 81–87, 91 transistors

[0497] 101–105, 111–113 transistors

[0498] 401 Decision Unit

[0499] 501 Bias Circuit

[0500] 511 transistor

[0501] 512 Current Source

[0502] 531 Bias Circuit

[0503] 541, 542 switches

[0504] 551 Parasitic Capacitance

[0505] 552 Current Source

[0506] 571 Bias Circuit

[0507] 581 transistor

[0508] 582 Variable Current Source

[0509] 583 transistors

[0510] 611 wiring

[0511] 612 Parasitic Capacitance

[0512] 631 transistor

[0513] 701 Adder Unit

[0514] 702 Source Follower

[0515] 703 Adder Unit

[0516] 721 Addition Unit

[0517] 722 Gain Amplifier

Claims

1. A light detection device, comprising: A first substrate, comprising: Multiple pixels, said multiple pixels being connected to a floating diffusion layer; and A first portion of the differential input circuit, the first portion being shared by the plurality of pixels; and A second substrate, which is stacked on the first substrate, wherein the second substrate includes: The second portion of the differential input circuit is connected to the first portion of the differential input circuit; A feedback circuit, which is connected to the second portion of the differential input circuit; and Data storage unit, which is connected to the feedback circuit; and Wiring, wherein the voltage of the floating diffusion layer is increased by providing voltage to the wiring.

2. The optical detection device according to claim 1, wherein, The first part of the differential input circuit includes a first input and a second input. The first input is connected to the plurality of pixels through the floating diffusion layer, and The second input is connected to a digital-to-analog converter used to control the voltage of the reference signal.

3. The optical detection device according to claim 2, wherein, The reference signal is a slope signal, and The voltage of the reference signal decreases monotonically over time.

4. The optical detection device according to claim 3, further comprising: The comparator circuit includes the differential input circuit and the feedback circuit, wherein the comparator circuit is configured as follows: The first signal received at the first input is compared with the reference signal received at the second input; and The comparison result between the voltage of the first signal and the voltage of the reference signal is output as an output signal.

5. The light detecting device according to claim 4, wherein The feedback circuit is configured to increase the switching speed of the output signal.

6. The optical detection device according to claim 5, wherein... The data storage unit includes a latched storage unit, and The latch memory unit is configured to store a time code based on the output signal.

7. The light detecting device of claim 6, further comprising: A timecode transmission unit is configured to provide the timecode, wherein the timecode transmission unit extends in the column direction of the plurality of pixels.

8. The light detecting device according to claim 7, wherein The time code is Gray code.

9. The light detecting device according to claim 8, wherein The first substrate and the second substrate are electrically connected by a metal bonding process.

10. The light detecting device according to claim 9, wherein The first portion and the second portion of the differential input circuit are electrically connected via the metal junction.

11. A light detection device, comprising: A first substrate, comprising: Multiple pixels; and A first portion of a differential input circuit, the first portion being shared by the plurality of pixels; a second substrate, which is stacked on the first substrate, wherein the second substrate includes: The second portion of the differential input circuit is connected to the first portion of the differential input circuit; A feedback circuit, which is connected to the second portion of the differential input circuit; and The data storage unit is connected to the feedback circuit. The first portion and the second portion of the differential input circuit are electrically connected via a metal connection; and Wiring The floating diffusion layer is connected to the plurality of pixels, and The voltage of the floating diffusion layer is increased by providing voltage to the wiring.

12. The optical detection device according to claim 11, wherein, The first part of the differential input circuit includes a first input and a second input. The first input is connected to the plurality of pixels through the floating diffusion layer, and The second input is connected to a digital-to-analog converter used to control the voltage of the reference signal.

13. The optical detection device according to claim 12, wherein, The reference signal is a slope signal, and The voltage of the reference signal decreases monotonically over time.

14. The optical detection device according to claim 13, further comprising: The comparator circuit includes the differential input circuit and the feedback circuit, wherein the comparator circuit is configured as follows: The first signal received at the first input is compared with the reference signal received at the second input; and The comparison result between the voltage of the first signal and the voltage of the reference signal is output as an output signal.

15. The light detecting device of claim 14, wherein, The feedback circuit is configured to increase the switching speed of the output signal.

16. The optical detection device according to claim 15, wherein... The data storage unit includes a latched storage unit, and The latch memory unit is configured to store a time code based on the output signal.

17. The light detection device according to claim 16, further comprising: A timecode transmission unit is configured to provide the timecode, wherein the timecode transmission unit extends in the column direction of the plurality of pixels.

18. The optical detection device according to claim 17, wherein, The time code is Gray code.

19. The optical detection device according to claim 18, wherein, The first substrate and the second substrate are electrically connected by the metal bonding.

20. A light detection device, comprising: A first substrate, comprising: Multiple pixels, including the first pixel; and A first portion of a differential input circuit, the first portion being connected to the first pixel; a second substrate, stacked on the first substrate, wherein the second substrate includes: The second portion of the differential input circuit is connected to the first portion of the differential input circuit; A feedback circuit, which is connected to the second portion of the differential input circuit; and The data storage unit is connected to the feedback circuit. The first portion and the second portion of the differential input circuit are electrically connected via a metal connection; and Wiring The floating diffusion layer is connected to the plurality of pixels, and The voltage of the floating diffusion layer is increased by providing voltage to the wiring.

21. The optical detection device according to claim 20, wherein, The first part of the differential input circuit includes a first input and a second input. The first input is connected to the first pixel through the floating diffusion layer, and The second input is connected to a digital-to-analog converter used to control the voltage of the reference signal.

22. The optical detection device according to claim 21, wherein, The reference signal is a slope signal, and The voltage of the reference signal decreases monotonically over time.

23. The optical detection device according to claim 22, further comprising: The comparator circuit includes the differential input circuit and the feedback circuit, wherein the comparator circuit is configured as follows: The first signal received at the first input is compared with the reference signal received at the second input; and The comparison result between the voltage of the first signal and the voltage of the reference signal is output as an output signal.

24. The optical detection device according to claim 23, wherein, The feedback circuit is configured to increase the switching speed of the output signal.

25. The optical detection device according to claim 24, wherein... The data storage unit includes a latched storage unit, and The latch memory unit is configured to store a time code based on the output signal.

26. The optical detection device according to claim 25, further comprising: A timecode transmission unit is configured to provide the timecode, wherein the timecode transmission unit extends in the column direction of the plurality of pixels.

27. The optical detection device according to claim 26, wherein, The time code is Gray code.

28. The optical detection device according to claim 27, wherein, The first substrate and the second substrate are electrically connected by the metal bonding.

Images