Error correction circuits, error correction methods and communication devices
By combining high-correction-capability first-stage error correction and simple error detection processing in a communication system, and utilizing correction bit likelihood calculation and high-likelihood row detection, the problem of increased circuit size and power consumption is solved, achieving a highly efficient error correction effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NTT ELECTORNICS CORP
- Filing Date
- 2021-10-01
- Publication Date
- 2026-05-26
Smart Images
Figure CN116349136B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to error correction circuits, error correction methods, and communication devices that can improve transmission characteristics. Background Technology
[0002] In coherent optical communication, digital signal processing is used to compensate for distortions and frequency / phase fluctuations generated during transmission to improve transmission characteristics. To further improve transmission characteristics, in addition to compensation, error correction circuitry is provided between the transmitter and receiver to reduce data errors in the transmission. This is typically achieved by performing error-correcting coding on the data at the transmitter and performing error correction based on the coding at the receiver.
[0003] Error correction methods, such as Hamming coding, BCH coding, Reed-Solomon coding, and convolutional coding / Viterbi decoding, are generally known. Especially in recent communication devices, due to the advanced computing power of CPUs, extensive and complex processing has become possible, and high-performance error correction methods such as LDPC (Low-Density Parity-Check Code) are used. In recent years, as in Patent Documents 1 and 2, data is arranged in n rows × m columns, and error correction processing is performed on the data in both row and column directions to improve correction capabilities.
[0004] Error correction processing includes hard decision-making, which performs correction based on the result of decoding to "1" or "0", and soft decision-making, which performs correction based on the coordinates of the received signal in the complex plane (before decoding to "1" or "0"). Compared to the former method, the latter method enhances correction capability but increases circuitry and processing scale as well as power consumption.
[0005] Related technical documents
[0006] Patent documents
[0007] Patent Document 1: Japanese Patent Application Publication No. 2006-074656
[0008] Patent Document 2: Japanese Patent Application Publication No. 2006-295510 Summary of the Invention
[0009] The problem to be solved by the present invention
[0010] As mentioned above, communications requiring high transmission performance necessitate high-performance error correction methods based on soft decision. This leads to increased circuit size and power consumption. Data errors arise relatively randomly relative to thermal noise, but sometimes occur continuously relative to polarization fluctuations (burst errors). To address burst errors, it is necessary to extend the coding unit (code length) or the unit of error dispersion (interleaving length). This also increases circuit size and power consumption.
[0011] The present invention was made to overcome the above-mentioned defects, and its purpose is to provide an error correction circuit, error correction method and communication device that can improve transmission characteristics while suppressing circuit size.
[0012] Problem Solving Methods
[0013] To address the aforementioned problems, according to the present invention, an error correction circuit is provided, comprising: a first error correction processing circuit configured to perform error correction processing on array data that has undergone a first encoding in the row direction at the transmitting side; an error detection processing circuit configured to perform error detection processing on array data that has undergone a second encoding in the column direction at the transmitting side to detect at least one bit error; a correction bit likelihood calculation circuit configured to calculate the sum of the likelihoods of correction bits for each row, wherein the correction bits are bits corrected by the first error correction processing circuit, and the likelihood is an indicator representing the determinism of the bit; a high likelihood row detection circuit configured to detect rows of array data in descending order of the sum of the likelihoods of correction bits for each row output from the correction bit likelihood calculation circuit; and a second error correction processing circuit configured to correct the bits at the intersection of the column where the error was detected and the row detected by the high likelihood row detection circuit when the error detection processing circuit detects at least one bit error.
[0014] To address the aforementioned problems, according to the present invention, an error correction circuit is provided, comprising: a first error correction processing circuit configured to perform error correction processing on array data that has undergone a first encoding in the row direction at the transmitting side; an error detection processing circuit configured to perform error detection processing on array data that has undergone a second encoding in the column direction at the transmitting side to detect at least one bit error; a correction bit likelihood calculation circuit configured to calculate the sum of the likelihoods of correction bits for each row, wherein the correction bits are bits corrected by the first error correction processing circuit, and the likelihood is an indicator representing the determinism of the bit; and a second error correction processing circuit configured to perform error correction in the order of rows with larger sums of the likelihoods of the correction bits when the error detection processing circuit detects at least one bit error.
[0015] To address the aforementioned problems, according to the present invention, an error correction method is provided that is executed in an error correction circuit, the error correction circuit comprising: a first error correction processing circuit, an error detection processing circuit, a second error correction processing circuit, and a correction bit likelihood calculation circuit. The method includes the following steps: causing the first error correction processing circuit to perform error correction processing on array data that has already undergone first encoding in the row direction at the transmitting side; causing the error detection processing circuit to perform error detection processing on at least one bit of array data that has already undergone second encoding in the column direction at the transmitting side; causing the correction bit likelihood calculation circuit to calculate a likelihood as an indicator of the determinism of a bit and to calculate the sum of the calculated likelihoods of the correction bits for each row of the array data, wherein the correction bits are bits corrected by the first error correction processing circuit; and causing the second error correction processing circuit to correct bits in order of the rows with the larger sum of the likelihoods of the correction bits when the error detection processing circuit detects an error of at least one bit.
[0016] Invention Effects
[0017] According to the present invention, an error correction circuit, error correction method, and communication device can be provided that can improve transmission characteristics while suppressing circuit size. Attached Figure Description
[0018] Figure 1 An example of the arrangement of a communication device including an error correction circuit according to an embodiment of the present invention is shown;
[0019] Figure 2A This is a view used to illustrate the encoding operation on the transmitting side according to an embodiment of the present invention;
[0020] Figure 2B This is a view used to illustrate the encoding operation on the transmitting side according to an embodiment of the present invention;
[0021] Figure 2C This is a view used to illustrate the encoding operation on the transmitting side according to an embodiment of the present invention;
[0022] Figure 2D This is a view used to illustrate the encoding operation on the transmitting side according to an embodiment of the present invention;
[0023] Figure 3A This is a block diagram illustrating an example arrangement of an error correction circuit according to an embodiment of the present invention;
[0024] Figure 3B This is a view used to illustrate the error correction operation of the error correction circuit on the receiving side according to an embodiment of the present invention;
[0025] Figure 4 This is a view used to illustrate the operation of the first error correction processing circuit according to an embodiment of the present invention;
[0026] Figure 5 This is a diagram used to illustrate the corrected bit likelihood according to an embodiment of the present invention;
[0027] Figure 6A This is a view used to illustrate the operation of the second error correction processing circuit according to an embodiment of the present invention;
[0028] Figure 6B This is a view used to illustrate the operation of the second error correction processing circuit according to an embodiment of the present invention; and
[0029] Figure 7 This is a flowchart illustrating the operation of the error correction method according to an embodiment of the present invention. Detailed Implementation
[0030] Embodiments of the present invention will now be described with reference to the accompanying drawings. The present invention can be practiced in many different embodiments and should not be limited to the embodiments described below.
[0031] Overview of the Invention
[0032] According to the present invention, a first error correction process is performed on array data that has already been encoded in the row direction (first encoding) at the transmitting side, and a second error correction process is performed on array data that has already been encoded in the column direction (second encoding) at the transmitting side, in the column direction. In the second error correction process, a correction bit likelihood is calculated with respect to the bits corrected in the row direction by the first error correction process, and the bits at the intersection of the column where the detected error and the row with a large correction bit likelihood are corrected are corrected. The correction bit likelihood is an indicator of the determinism (reliability) of the bits in the received signal, and is used to estimate rows containing bits that could not be corrected or were highly likely to have been incorrectly corrected in the first error correction process. In this embodiment, "large likelihood (sum)" means that the bits could not be corrected or were highly likely to have been incorrectly corrected. Note that "large likelihood (sum)" and "high likelihood (sum)" are synonymous. Likelihood can be reliability information.
[0033] According to the present invention, by combining a first error correction circuit with high correction capability and a second error correction circuit using simple error detection, an error correction circuit capable of improving transmission characteristics while reducing circuit size can be constructed.
[0034] On the transmitting side, the transmitted data are arranged in parallel. First error correction coding with high correction capability (soft-decision error correction such as LDPC) is performed on the data in the row direction, and coding for simple error detection (coding for detecting single or multiple errors, such as CRC checksum) is performed on the data in the column direction. Note that the first error correction can employ circuitry that is reduced in size by relatively shortening the code length.
[0035] On the receiving side, array data similar to that on the transmitting side is constructed, and a first error correction process is performed on the data in the row direction. Regarding the error-correcting bits in the first error correction process, a predetermined number of rows are detected in descending order of the sum of likelihoods, which serves as an indicator of the determinism of the bits. For example, the likelihood can be calculated based on the absolute value of the difference between the coordinates of the received signal before error correction in the complex plane and the coordinates of the closest constellation set on the transmitting side. In this case, since the coordinate difference is small in the complex plane, the likelihood is considered high, and a predetermined number of rows are detected in ascending order of the sum of the absolute values of the coordinate differences. By detecting a predetermined number of rows in descending order of likelihood, rows that could not be corrected or were highly likely to be incorrectly corrected during the first error correction process on the data in the row direction due to significant influences such as noise can be estimated.
[0036] On the receiving side, error detection is performed on the data in the column direction after the first error correction process. When an error is detected in the data in the column direction, a second error correction process is performed on the bits intersecting the column where the error was detected, in descending order of likelihood of the detected rows.
[0037] According to the present invention, by combining a first error correction with high correction capability and a second error correction using simple error detection, an error correction circuit capable of improving transmission characteristics while reducing circuit size can be constructed. The circuit size is reduced by shortening the code length in the first error correction, and the resulting degradation in correction capability can be compensated by a simpler second error correction.
[0038] Communication devices including error correction circuits
[0039] Figure 1 An example of the arrangement of a communication device including an error correction circuit according to an embodiment of the present invention is shown. Figure 1 An example of applying the error correction circuit 20 according to an embodiment of the present invention to a communication device of the coherent optical communication type is shown. Note that the application target of the present invention is not limited to communication devices of the coherent optical communication type, and the present invention is applicable to all other communication devices including wireless communication.
[0040] exist Figure 1 In a coherent optical communication device, the transmitting side includes a transmitting signal processing circuit 100 and a transmitting optical module 300, while the receiving side includes a receiving optical module 400 and a receiving signal processing circuit 200. The transmitting signal processing circuit 100 may include an error correction coding circuit 10. The receiving signal processing circuit 200 may include an A / D conversion circuit 30, a dispersion compensation circuit 40, a polarization dispersion compensation circuit 50, and an error correction circuit 20. The transmitting and receiving sides are connected via an optical fiber 500.
[0041] The error correction coding circuit 10 in the transmitting signal processing circuit 100 performs error correction coding on the transmitted data. The transmitting optical module 300 generates an optical signal based on the error-corrected transmitted data. In typical coherent optical communication, the horizontally polarized optical signal X and the vertically polarized optical signal Y are multiplexed and transmitted. The transmitted data is divided into horizontally polarized optical signal data (XI and XQ) and vertically polarized optical signal data (YI and YQ).
[0042] XI and XQ represent coordinates, namely the horizontal and orthogonal components of the horizontally polarized light signal data on the complex plane. YI and YQ represent coordinates, namely the horizontal and orthogonal components of the vertically polarized light signal data on the complex plane. The transmitted data is mapped to the coordinates of the carrier wave (signal LD: laser diode) on the complex plane and transmitted to the receiving side via optical fiber 500.
[0043] The receiving optical module 400 generates received data from the received optical signal. The receiving optical module 400 can output horizontally polarized light signal data (XI and XQ) and vertically polarized light signal data (YI and YQ). In the receiving signal processing circuit 200, the data (XI, XQ, YI, and YQ) are converted into digital signals by the A / D conversion circuit 30, and these signals are provided to various compensation circuits. The dispersion compensation circuit 40 compensates for the dispersion of the provided signals, the polarization dispersion compensation circuit 50 compensates for the polarization dispersion of these signals, and the error correction circuit 20 performs data error correction processing.
[0044] In the coherent optical communication device described above, data is transmitted using both horizontally and vertically polarized light signals, but it can also be transmitted using only one polarization signal. Even in this case, the error correction circuit 20 according to an embodiment of the present invention can be used.
[0045] Communication devices capable of using the error correction circuit 20 according to embodiments of the present invention are not limited to the coherent optical communication devices described above. The error correction circuit 20 according to embodiments of the present invention can also be used in other communication devices including wireless communication. Needless to say, such communication devices also fall within the scope of the present invention. Note that in wireless communication, often only one polarization signal is used.
[0046] Encoding operation on the sending side
[0047] Figures 2A to 2D This is a view used to illustrate the encoding operation on the transmitting side according to an embodiment of the present invention. Note, for example... Figures 2A to 2D The bit numbers shown are merely examples, and the invention is not limited to these values. Figure 2A An example of an array that transmits data is shown. Figure 2B This illustrates when optical signal data (XI, XQ, YI, and YQ) are applied... Figure 2AHere is a configuration example for line 1 in the example. Figure 2C It shows when Figure 2B The configuration examples in [the document] have been rearranged into [the following format] Figure 2A Here is a configuration example for a single line in the code. Figure 2D This illustrates when optical signal data (XI, XQ, YI, and YQ) are applied... Figure 2A Configuration example for the entire array.
[0048] In this embodiment, for example, soft-decision LDPC can be used as the first error correction method. In this case, the circuit size can be reduced by shortening the code length (information bits + redundant bits). As the error correction code for error detection, CRC (Cyclic Redundancy Check), Hamming code, BCH code, Reed-Solomon code, etc. can be used. CRC can be constructed from a circuit much smaller than that of soft-decision LDPC.
[0049] In error detection methods such as CRC, single or multiple errors can be detected. Even in error detection, either soft-decision or hard-decision methods can be used. Generally, soft-decision methods offer higher error correction capabilities than hard-decision methods. However, using hard-decision methods allows for further reduction in circuit size.
[0050] exist Figure 2A In the configuration example, the information bits are arranged in a row-wise order of 608 bits per row, with 98 rows in the column direction. In the error correction coding on the transmitting side, firstly, two error detection redundancy bits are added to the 98 information bits in the column direction, forming 100 column-wise bits per column. Then, 288 error correction redundancy bits are added to the 608 bits in the row direction (information bits (rows 1 to 98)) and error detection redundancy bits (rows 99 and 100), forming 896 row-wise bits. This completes the coding of 100 rows.
[0051] In the above example, the configuration in which rows and columns are interchanged naturally falls within the scope of this invention. Although not shown, it is also possible to first construct 896 row direction bits by adding 288 error-correcting redundancy bits to 608 information bits (rows 1 to 98) in the row direction, and then construct 100 column direction bits by adding 2 error-detection redundancy bits to 98 information bits (columns 1 to 608) and error-correcting redundancy bits (columns 609 to 896) in the column direction.
[0052] Applied to XI / XQ / YI / YQ
[0053] Next, we will refer to Figures 2B to 2D Explanation when Figure 2A The array data in the configuration is applied to horizontally polarized light signal data (XI and XQ) and vertically polarized light signal data (YI and YQ).
[0054] Figure 2B An example configuration of the XI, XQ, YI, and YQ data strings is shown. Each data string consists of four minimum frames (XI-1 to XI-4, XQ-1 to XQ-4, YI-1 to YI-4, or YQ-1 to YQ-4), and each minimum frame consists of 38 information bits and 18 redundant bits. The redundant bits can be generated using LDPC encoding with a short code length.
[0055] Then, as Figure 2C As shown, Figure 2B The data string is integrated into the information bits and redundant bits in the order XI / XQ / YI / YQ. As a result, Figure 2A A single data string in a row can be constructed from XI information bits × 4 + XQ information bits × 4 + YI information bits × 4 + YQ information bits × 4 and XI redundant bits × 4 + XQ redundant bits × 4 + YI redundant bits × 4 + YQ redundant bits × 4. After constructing the data strings for the 98 rows, the XI, XQ, YI, and YQ data strings are rearranged as follows: Figure 2D The data array shown.
[0056] As described above, for 608 columns, error detection redundancy bits are added in the column direction to the XI, XQ, YI, and YQ information bits initially arranged in 608×98, and then for 100 rows, error correction redundancy bits are added in the row direction. When adding error correction redundancy bits, error correction coding is performed on the XI, XQ, YI, and YQ data for each short code length (38 information bits + 18 redundancy bits) of the minimum frame. Note that the error correction circuit 20 can be shared by performing coding on the error detection redundancy bits of the two rows (rows 99 and 100) for each minimum frame in a manner similar to XI, XQ, YI, and YQ.
[0057] Layout of error correction circuit
[0058] Figure 3A This is a block diagram illustrating an example arrangement of an error correction circuit according to an embodiment of the present invention. The error correction circuit 20 on the receiving side includes: a first error correction processing circuit 21, which includes a data array circuit 22 and an error correction processing circuit (per row) 23; an error detection processing circuit 26; a second error correction processing circuit 27; a correction bit likelihood calculation circuit 24; and a high likelihood row detection circuit 25.
[0059] The first error correction processing circuit 21 from Figure 1 The polarization dispersion compensation circuit 50 shown receives signals XI, XQ, YI, and YQ. For example... Figure 3BAs shown, the data array circuit 22 arranges the data in a manner similar to the data array constructed on the transmitting side. That is, each row constitutes 16 frames of XI×4+XQ×4+YI×4+YQ×4. Each frame has 38 information bits and 18 redundant bits, resulting in a short code length of 56 bits. The configuration of one row is similar to... Figure 2C The configuration is the same on the sending side.
[0060] Operation of the first error correction processing circuit
[0061] Figure 4 This is a view illustrating the operation of a first error correction processing circuit according to an embodiment of the present invention. The first error correction processing circuit 21 includes 16 error correction circuits, each for a code length of 56 bits. Error correction for one row of the data array is performed at a time by the 16 error correction circuits.
[0062] In this configuration example, LDPC is used as the first error correction method, but due to the short code length, the circuit size can be greatly reduced. Even with 16 circuits, the first error correction processing circuit can be constructed with a circuit size much smaller than the circuit that would otherwise require 16 circuits to process the data string (608 information bits + 288 redundant bits) at a time.
[0063] In high-performance error correction such as LDPC, the circuit size increases with code length. Therefore, the first error correction process is constructed by using multiple short-code-length circuits, such as... Figure 4 As shown, the circuit size can be reduced to approximately 1 / 100th or less. Although Figure 4 The code length in this example is 869 bits, but the code length can be appropriately set depending on the state of the transmission line used and the circuit size of the communication device. Ideally, the code length in this embodiment is, for example, 1000 bits or less.
[0064] The first error correction processing circuit 21 with the above arrangement sequentially performs error correction processing on 98 rows of information bits and two rows of error detection redundancy bits, and finally outputs 608 bits × 100 rows of data.
[0065] Operation of the error detection circuit
[0066] Then, the error detection processing circuit 26 performs column-wise error detection processing on the 608-bit × 98-row data output from the first error correction processing circuit. In this embodiment, CRC is used as the error detection method, and one or more bits of error detection are performed for each column. The error detection processing circuit 26 outputs information about the columns in which errors were detected (the columns in which errors were detected and the number of bits in each column in which errors were detected).
[0067] Hard-decision methods can be used as CRC error correction / detection methods and can reduce circuit size compared to high-performance error correction methods using soft-decision methods (e.g., LDPC). They can also detect multiple error bits. Furthermore, BCH codes, Hamming codes, Reed-Solomon codes, etc., with smaller circuit sizes than those used in soft-decision-based methods such as LDPC, can also be used for error detection.
[0068] Operation of the correction bit likelihood calculation circuit
[0069] The correction bit likelihood calculation circuit 24 calculates the likelihood of the correction bits for each row based on the correction bit information from the first error correction processing circuit 21. Likelihood is an indicator of the determinism of the bits before correction. Figure 5 This is a graph used to illustrate the likelihood of the correction bits. Note that... Figure 5 The likelihood of horizontally polarized light signal data (XI and XQ) is shown, but this also applies to vertically polarized light signal data (YI and YQ).
[0070] The data input to the first error correction processing circuit 21 is coordinate data on the complex plane, such that the correction processing targets are (XI and XQ) and (YI and YQ), because the first error correction method is a soft-decision method. In the first error correction of the soft-decision method, the deviation from the ideal coordinate point set on the transmitting side is considered in the decision.
[0071] For bits corrected in the first error correction process, the likelihood is represented by the absolute value of the difference between the coordinates (XIr, XQr) and (YIr, YQr) of the received signal before error correction and the coordinates (XIt, XQt) and (YIt, YQt) of the constellation set on the transmitting side within the identification area of the received signal. In the following text, the coordinates (XIt, XQt) and (YIt, YQt) will be referred to as the "ideal constellation" or "ideal coordinate point." The coordinates of the ideal constellation are the ideal coordinates within the identification area, where the data can be determined as the error-corrected data, and are equivalent to the mapped coordinates at the time of transmission. In the case of horizontally polarized light signal data, the likelihood can be represented in the complex plane based on the absolute value of (XIr-XIt)+j(XQr-XQt)=(A1 / A0)exp(jφ), where A1 is the amplitude of the received signal before error correction, A0 is the amplitude of the ideal constellation, and φ is the phase difference between these signals. The likelihood can be represented similarly for vertically polarized light signal data. During error correction, when it is determined that the received signal is incorrect, the received signal is corrected to the ideal signal point in another identification area.
[0072] Likelihood is measured by the amount of deviation from the ideal coordinate point caused by noise, etc. When the deviation is small, the "determinism (reliability)" of the data is estimated to be high. "Determinism" is the reproducibility of the ideal coordinate point on the transmitting side. Likelihood values and the difference (deviation) in the coordinates are negatively correlated. In the following description, high likelihood means small difference (deviation) in the coordinates. Since the first error correction processing circuit 21 corrects some bits, the likelihood (correction bit likelihood) is calculated, with each likelihood for all corrected bits. Furthermore, the sum of the likelihoods of the corrected bits is calculated and output for each row of the data array.
[0073] In the above description, the difference in coordinates (deviation) is used as an indicator of likelihood; however, the calculation of likelihood is not limited to the calculation of the difference in coordinates described above. For example, likelihood can also be calculated based solely on signal strength or solely on phase difference. Likelihood, used as an indicator of determinism, can generally be calculated using various methods, and even in this invention, another indicator can be used, as long as that indicator represents determinism. In this invention, indicators other than coordinate difference can also be used as likelihood, and this, of course, falls within the scope of this invention. The likelihood in this invention even includes the log-likelihood ratio (LLR) obtained by calculating the logarithm of the likelihood ratio.
[0074] Operation of high likelihood line detection circuit
[0075] Based on the sum of the likelihoods of the correction bits from each row of the correction bit likelihood calculation circuit 24, the high likelihood row detection circuit 25 detects rows in descending order of the sum.
[0076] Typically, bit errors occur when interference, such as noise, is applied to a bit string and exceeds the recognition range for each bit. In this case, if the number of errors falls within a correctable range, the bit errors are corrected. However, if large noise or similar interference is applied and the number of errors exceeds the correctable range, uncorrectable bit errors occur. If even greater noise or similar interference is applied, bits that were not originally errors may be incorrectly corrected. In such cases, for data strings in very poor transmission conditions, it can be estimated whether there are still incorrectly corrected or uncorrected bits.
[0077] The inventors' empirical observations and theoretical tests reveal that data strings in very poor transmission conditions are estimated to have a large likelihood of the aforementioned corrected bits (small differences in coordinates). It also becomes apparent that the probability of the presence of incorrectly corrected or uncorrected bits is estimated to be higher in the order of rows with the largest sum of the likelihoods of the corrected bits. Initially, the probability of incorrect correction is estimated to be lower when the likelihood is large. Nevertheless, rows in which many bits are corrected are estimated to be rows with very poor transmission conditions. According to the invention, as a second error correction process, incorrectly detected bits are corrected in the order of rows with larger likelihoods to perform additional error correction on bits incorrectly corrected or uncorrected in the first error correction process, thereby compensating for the first error correction process. Note that, as stated above, the likelihood is not limited to the aforementioned differences in coordinates, and another metric can be used, as long as that metric represents determinism.
[0078] Operation of the second error correction processing circuit
[0079] Figure 6A and 6B This is a view illustrating the operation of the second error correction processing circuit 27 according to an embodiment of the present invention. The second error correction processing circuit 27 performs additional error correction based on the columns in which errors are detected, the number of erroneous bits detected in each column sent from the error detection processing circuit 26, and the order of the rows detected by the high-likelihood row detection circuit 25. More specifically, the second error correction processing circuit 27 performs correction by counting the number of bits detected in the order of rows with the largest sum of likelihoods, i.e., bit reversal for each bit where the columns detected by the error detection processing circuit 26 and the rows selected by the high-likelihood row detection circuit 25 intersect.
[0080] exist Figure 6A In this context, assuming that as a result of the error correction processing circuit 21 performing error correction processing on the corresponding first to 100th rows, the high likelihood row detection circuit 25 detects the third row (R3) as the first detected row and the 50th row (R50) as the second detected row. Rn represents the nth row.
[0081] Then, assuming that the error detection processing circuit 26 detects a 1-bit error in column 150 (C150) and a 2-bit error in column 300 (C300), this is taken as the result of performing error detection processing on the corresponding first to 608 columns. Cn represents the nth column.
[0082] In this case, the bit at the intersection of column 150 (C150) and row 3 (R3) and the two bits at the intersection of column 300 (C300) and row 3 (R3) and row 50 (R50) are corrected. The case where the error detection processing circuit 26 can detect three or more bits of error also falls within the scope of this invention. In this case, a second error correction process is performed based on the number of detected error bits.
[0083] like Figure 6B As shown, the information bits corrected by the second error correction processing circuit 27 are output as XI / XQ / YI / YQ data on 608 columns × 98 rows. By using the second error correction, which is much simpler to detect than the first error correction, the second error correction processing circuit 27 can easily correct bits that were incorrectly corrected or uncorrected in the first error correction.
[0084] According to this embodiment, the first error correction process can be compensated by performing additional error correction on bits that are estimated to be incorrectly corrected or not yet corrected in the first error correction. The combination of the first error correction with high correction capability and the second error correction using simple error detection enables an error correction circuit that improves transmission characteristics while reducing circuit size. When performing dual error correction, as with conventional concatenated coding, even in the second error correction process, the coordinates of the received signal are used as likelihood information to perform complex error correction calculations. Conversely, according to the present invention, likelihood is used to estimate rows in poor transmission states, and error detection calculations can be performed using simple hard-decision processing. Since likelihood is used to detect poor rows, overall error correction capability at the level of soft-decision processing can be obtained. Therefore, equivalent error correction capability can be achieved with a smaller circuit size. The circuit size can be further reduced by significantly shortening the code length in the first error correction.
[0085] Operation of error correction methods
[0086] Figure 7 This is a flowchart illustrating the operation of an error correction method according to an embodiment of the present invention. The error correction method according to this embodiment is executed in an error correction circuit 20 including a first error correction processing circuit, an error detection processing circuit, a second error correction processing circuit, a correction bit likelihood calculation circuit, and a high likelihood row detection circuit.
[0087] When the received signal XI / XQ / YI / YQ is input to the first error correction processing circuit 21 (step S1), the data array circuit 22 arranges the data in a manner similar to the data array formed on the transmitting side (step S2).
[0088] The error correction processing circuit (per row) 23 performs the first error correction processing (step S3) on the array data obtained by the data array circuit 22 in the row direction.
[0089] The correction bit likelihood calculation circuit 24 calculates the likelihood of the bit corrected by the first error correction processing circuit based on the absolute value of the difference between the coordinates of the received signal of each bit in the complex plane before correction and the coordinates of the ideal constellation set by the transmitting side in the complex plane, and outputs the total value of the calculated correction bit likelihood (step S4). The high likelihood row detection circuit 25 detects rows of array data in descending order of the total value of the correction bit likelihood of each row from the correction bit likelihood calculation circuit 24 (step S5).
[0090] For the bit corrected by the first error correction processing circuit 21, the error detection processing circuit 26 performs error detection processing on at least one bit in the column direction of the array data encoded on the transmitting side in the column direction (step S6).
[0091] If one or more bit errors are detected in the error detection processing circuit 26, the second error correction processing circuit 27 corrects the bits at the intersections of the column where the detected error occurs and the row output from the correction bit likelihood calculation circuit, in the order of the rows with the largest sum of the likelihoods of the correction bits (step S7). The sum of likelihoods represents the total value (likelihood) of the deterministic values of each correction bit in a row before correction.
[0092] The second error correction processing circuit 27 outputs correction information bits as XI / XQ / YI / YQ data (step S8).
[0093] Other embodiments
[0094] In the above description, the high-likelihood row detection circuit 25 detects rows in descending order of the sum of the likelihoods of the correction bits from each row of the correction bit likelihood calculation circuit 24. However, a similar arrangement can be implemented without the high-likelihood row detection circuit. In this case, when the column with the error detected and the number of bits with the error detected in each column are input from the error detection processing circuit 26, the second error correction processing circuit 27 can perform correction in descending order of the sum of the likelihoods of the correction bits from each row output from the correction bit likelihood calculation circuit 24.
[0095] Since the sum of the likelihoods of the correction bits used in the second error correction processing circuit 27 is represented by the total value of the absolute values of the differences between the received signals on the coordinate plane, the data range becomes wider, and sometimes a large amount of storage and circuit size are required. In this case, the necessary circuit size can be reduced by standardizing the total value of the likelihoods of the correction bits. For example, let x be the likelihood of the correction bits, use y = (ax) / b (where a and b are predetermined values) to transform the total value, and the transformed y can be standardized to take values from 0 to 1. In this equation, a and b can be appropriately set according to the possible values of the total value of the likelihoods of the correction bits x.
[0096] By standardizing the total likelihood of the correction bits, the data width can be limited to the standardized range, and the circuit size of memory and other devices used to store the total likelihood value can be reduced. When performing the second error correction process, the overall circuit size of the error correction circuit can be further reduced by using the standardized value y instead of the rows detected by the high-likelihood row detection circuit 25. Note that since the standardized value y also represents likelihood, even the second error correction process can be considered a soft-decision process, and the correction capability is improved compared to hard-decision processing.
[0097] Industrial applicability
[0098] This invention can be used as an error correction circuit and communication device in optical communication and the like.
[0099] Explanation of reference numerals and symbols in the attached drawings
[0100] 100 Transmit signal processing circuit, 200 Receive signal processing circuit, 300 Transmit optical module, 400 Receive optical module, 10 Error correction coding circuit, 20 Error correction circuit, 21 First error correction processing circuit, 22 Data array circuit, 23 Error correction processing circuit (per row), 24 Correction bit likelihood calculation circuit, 25 High likelihood row detection circuit, 26 Error detection processing circuit, 27 Second error correction processing circuit, 30 A / D conversion circuit, 40 Dispersion compensation circuit, 50 Polarization dispersion compensation circuit.
Claims
1. An error correction circuit, comprising: The first error correction processing circuit is configured to perform error correction processing on array data that has already undergone a first encoding in the row direction at the transmitting side in the row direction; An error detection processing circuit is configured to perform error detection processing on the array data that has already undergone a second encoding in the column direction on the transmitting side, in order to detect at least one bit error and output the column in which the error was detected and the number of error bits detected in each column; A correction bit likelihood calculation circuit is configured to calculate the sum of likelihoods for each row, the likelihood being an index representing the certainty of the bit prior to correction by the first error correction processing circuit. A high-likelihood row detection circuit is configured to detect rows of the array data in descending order of the sum of the likelihoods of the correction bits of each row output from the correction bit likelihood calculation circuit. as well as The second error correction processing circuit is configured to, when the error detection processing circuit detects at least one bit error, correct the bits at the following positions by bit reversal: the bits at the intersection of the column where the error was detected and the rows selected by the high likelihood row detection circuit in descending order of the sum of the likelihoods of the correction bits, the number of which is equal to the number of detected error bits.
2. An error correction circuit, comprising: The first error correction processing circuit is configured to perform error correction processing on array data that has already undergone a first encoding in the row direction at the transmitting side in the row direction; An error detection processing circuit is configured to perform error detection processing on the array data that has already undergone a second encoding in the column direction on the transmitting side, in order to detect at least one bit error and output the column in which the error was detected and the number of error bits detected in each column; A correction bit likelihood calculation circuit is configured to calculate the sum of likelihoods for each row, the likelihood being an index representing the certainty of the bit prior to correction by the first error correction processing circuit. as well as The second error correction processing circuit is configured to correct the bits at the following positions by bit reversal when the error detection processing circuit detects at least one bit error: the bits at the intersection of the column where the error was detected and the row corresponding to the number of detected error bits in descending order of the sum of the likelihoods of the correction bits.
3. The error correction circuit according to claim 1 or 2, wherein, The likelihood of the correction bit is calculated based on the absolute value of the difference between the coordinates of the received signal in the complex plane before error correction and the coordinates of the constellation set in the complex plane on the transmitting side within the identification area of the received signal.
4. The error correction circuit according to claim 1 or 2, wherein, The sum of the absolute values of the likelihoods of the correction bits is standardized.
5. The error correction circuit according to claim 1 or 2, wherein, The first error correction processing circuit performs error correction through soft decision, and the error detection processing circuit performs error detection through hard decision.
6. The error correction circuit according to claim 1 or 2, wherein, The array data is formed from horizontally polarized light signal data and vertically polarized light signal data of a coherent optical communication method.
7. The error correction circuit according to claim 1 or 2, wherein, The first error correction processing circuit has a code length of no more than 1000 bits.
8. An error correction method executed in an error correction circuit, the error correction circuit comprising: The error correction method comprises a first error correction processing circuit, an error detection processing circuit, a second error correction processing circuit, and a correction bit likelihood calculation circuit, and includes the following steps: The first error correction processing circuit performs error correction processing on the array data that has already undergone the first encoding in the row direction on the transmitting side in the row direction; The error detection processing circuit performs at least one bit of error detection processing on the array data that has already undergone the second encoding in the column direction on the transmitting side, in order to detect at least one bit of error, and outputs the column in which the error was detected and the number of error bits detected in each column; The correction bit likelihood calculation circuit calculates the likelihood of the correction bit, which is an index representing the certainty of the bit before correction by the first error correction processing circuit, and outputs the sum of the calculated likelihoods of the correction bits for each row of the array data, the correction bits being corrected by the first error correction processing circuit; and When the error detection processing circuit detects at least one bit error, the second error correction processing circuit corrects the bits at the following positions by bit reversal: the bits at the intersection of the column where the error was detected and the row in descending order of the sum of the likelihoods of the correction bits, the number of which is equal to the number of error bits detected.
9. A communication device comprising the error correction circuit according to claim 1 or 2.