Dual-channel dynamic load automated testing system, method, apparatus, and medium

Abstract

This application discloses a dual-channel dynamic load automated testing system, method, equipment, and medium. The first dynamic test circuit includes a first current adjustment module and a second current adjustment module; the connection point between the first and second current adjustment modules is a first detection point. The second dynamic test circuit includes a third and a fourth current adjustment module; the connection point between the third and fourth current adjustment modules is a second detection point. By adjusting the resistance values ​​of the first and second dynamic test circuits, the source voltage of the field-effect transistor is controlled, thereby controlling the load current changes at the first detection point and the second monitoring point. This application achieves that the currents flowing to the two chip detection points are different and change simultaneously, while also accommodating large current load changes, and simplifies the testing process, improving efficiency.

Description

Technical Field

[0001] This invention relates to the field of dynamic chip testing, and in particular to a dual-channel dynamic load automated testing system, method, computer equipment, and storage medium. Background Technology

[0002] With the rapid development of server performance, server diversity and structure have become more complex, and server motherboards have become more intricately composed. Therefore, motherboard testing has become increasingly complex, and the accuracy requirements for load testing have become increasingly stringent. In this increasingly rigorous and complex testing process, improving testing accuracy and achieving highly efficient automated testing has become an inevitable trend. During dynamic stability testing of power supply performance, it is necessary to subject the digital and analog power supplies at the chip to dynamic load changes while simultaneously measuring the voltage of the digital and analog power supplies at the chip to assess whether the chip voltage meets the chip requirements.

[0003] To assess the voltage stability of the output voltage under varying load conditions, the load current is typically changed artificially, and the output voltage is measured to see if it meets certain standards. Current solutions generally use an electronic load, which is soldered to the output of the power supply under test via two cables. The electronic load is set with dynamic load test conditions, then subjected to load, while the waveform of the output voltage is monitored. However, current solutions are cumbersome and inefficient. Electronic loads are bulky and cannot handle load changes with large current rates, nor can they simultaneously change the current flowing to both detection points. Summary of the Invention

[0004] This invention proposes a dual-channel dynamic load automated testing system, method, computer equipment, and storage medium, which can solve the technical problems of cumbersome and inefficient dynamic stability testing of power supply performance, large electronic load size which cannot meet the load changes with large current change rates, and the inability to achieve simultaneous changes in current flowing to two detection points.

[0005] To achieve the above objectives, the present invention provides a dual-channel dynamic load automated testing system, comprising:

[0006] The first dynamic test circuit includes a first current adjustment module and a second current adjustment module; the connection point between the first current adjustment module and the second current adjustment module is the first detection point; the first current adjustment module receives a half-wave voltage and its resistance value is adjustable, and the second current adjustment module receives a stable voltage and its resistance value is adjustable.

[0007] The second dynamic test circuit includes a third current adjustment module and a fourth current adjustment module; the connection point between the third current adjustment module and the fourth current adjustment module is the second detection point; the third current adjustment module receives the half-wave voltage and its resistance value is adjustable, and the fourth current adjustment module receives a stable voltage and its resistance value is adjustable.

[0008] The first and second detection points are connected to the chip under test. The load on the chip under test at the first and second detection points is controlled by adjusting the resistance values ​​of the second and fourth current adjustment modules and by adjusting the resistance values ​​of the first and third current adjustment modules.

[0009] Furthermore, the automated test system for channel dynamic load also includes a first oscilloscope and a second oscilloscope;

[0010] The first oscilloscope is connected to the first detection point and is used to detect the voltage value of the chip under test under the load corresponding to the first detection point; the second oscilloscope is connected to the second detection point and is used to detect the voltage value of the chip under test under the load corresponding to the second detection point. The chip under test is determined to be qualified based on the deviation between the detected voltage value of the first detection point and the detected voltage value of the second detection point and the set voltage of the first detection point and the second detection point.

[0011] Furthermore, the first current regulation module includes a first sliding resistor, a first field-effect transistor, and a first sampling resistor;

[0012] The half-wave voltage is input to one end of the lower terminal of the first sliding resistor, and the other end of the lower terminal of the first sliding resistor is grounded; the other end of the lower terminal of the first sliding resistor is connected to the source of the first field-effect transistor through the first sampling resistor, the drain of the first field-effect transistor is connected to the first detection point, and the gate of the first field-effect transistor is connected to the upper terminal of the first sliding resistor.

[0013] By adjusting the position of the swivel of the first sliding resistor, the voltage value of the first field-effect transistor can be adjusted so that the first detection point connected to it receives the first current.

[0014] Furthermore, the second current regulation module includes a second sliding resistor, a second field-effect transistor, and a second sampling resistor;

[0015] The stable voltage is input to one end of the lower terminal of the second sliding resistor, and the other end of the lower terminal of the second sliding resistor is grounded; the other end of the lower terminal of the second sliding resistor is connected to the source of the second field-effect transistor through the second sampling resistor, the drain of the second field-effect transistor is connected to the first detection point, and the gate of the second field-effect transistor is connected to the upper terminal of the second sliding resistor.

[0016] By adjusting the position of the slid plate of the second sliding resistor, the voltage value of the second field-effect transistor can be adjusted so that the first detection point connected to it receives a second current; the current at the first detection point is equal to the sum of the first current and the second current.

[0017] Furthermore, the third current regulation module includes a third sliding resistor, a third field-effect transistor, and a third sampling resistor;

[0018] The half-wave voltage is input to one end of the lower terminal of the third sliding resistor, and the other end of the lower terminal of the third sliding resistor is grounded; the other end of the lower terminal of the third sliding resistor is connected to the source of the third field-effect transistor through the third sampling resistor, the drain of the third field-effect transistor is connected to the second detection point, and the gate of the third field-effect transistor is connected to the upper terminal of the third sliding resistor.

[0019] By adjusting the position of the swivel of the third sliding resistor, the voltage value of the third field-effect transistor can be adjusted so that the second detection point connected to it can obtain a third current.

[0020] Furthermore, the fourth current regulation module includes a fourth sliding resistor, a fourth field-effect transistor, and a fourth sampling resistor;

[0021] The stable voltage is input to one end of the lower terminal of the fourth sliding resistor, and the other end of the lower terminal of the fourth sliding resistor is grounded; the other end of the lower terminal of the fourth sliding resistor is connected to the source of the fourth field-effect transistor through the fourth sampling resistor, the drain of the fourth field-effect transistor is connected to the second detection point, and the gate of the fourth field-effect transistor is connected to the upper terminal of the fourth sliding resistor.

[0022] By adjusting the position of the slid plate of the fourth sliding resistor, the voltage value of the fourth field-effect transistor can be adjusted so that the second detection point connected to it obtains a fourth current; the current at the second detection point is equal to the sum of the third current and the fourth current.

[0023] Furthermore, the dual-channel dynamic load automated testing system also includes a voltage protector;

[0024] The voltage protector includes a first voltage protector, a second voltage protector, a third voltage protector, and a fourth voltage protector;

[0025] The first voltage protector includes a first comparator and a first channel switch. The positive input terminal of the first comparator is input with the voltage across the first sampling resistor, the negative input terminal of the first comparator is input with a first reference voltage, and the output terminal of the first comparator is connected to the first channel switch. The first channel switch is connected in series between the gate of the first field-effect transistor and the upper terminal of the sliding resistor.

[0026] The second voltage protector includes a second comparator and a second channel switch. The positive input terminal of the second comparator is input with the voltage across the second sampling resistor, the negative input terminal of the second comparator is input with a second reference voltage, and the output terminal of the second comparator is connected to the second channel switch. The second channel switch is connected in series between the gate of the second field-effect transistor and the upper terminal of the sliding resistor.

[0027] The third voltage protector includes a third comparator and a third channel switch. The positive input terminal of the third comparator is input to the voltage across the third sampling resistor, the negative input terminal of the third comparator is input to the third reference voltage, and the output terminal of the third comparator is connected to the third channel switch. The third channel switch is connected in series between the gate of the third field-effect transistor and the upper terminal of the sliding resistor.

[0028] The fourth voltage protector includes a fourth comparator and a fourth channel switch. The positive input terminal of the fourth comparator receives the voltage across the fourth sampling resistor, the negative input terminal of the fourth comparator receives the fourth reference voltage, and the output terminal of the fourth comparator is connected to the fourth channel switch. The fourth channel switch is connected in series between the gate of the fourth field-effect transistor and the upper terminal of the sliding resistor.

[0029] On the other hand, a dual-channel dynamic load automated testing method is provided, the method comprising:

[0030] Connect the chip to be tested to both the first detection point and the second detection point simultaneously;

[0031] The resistance values ​​of the first current adjustment module and the second current adjustment module are adjusted to control the current load of the chip under test at the first detection point; the resistance values ​​of the third current adjustment module and the fourth current adjustment module are adjusted to control the current load of the chip under test at the second detection point.

[0032] Detect the voltage value of the chip under test under the load corresponding to the first detection point and the second detection point;

[0033] The test chip is deemed qualified based on the deviation between the voltage values ​​at the first and second detection points and the set voltage values ​​at the first and second detection points.

[0034] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0035] Connect the chip to be tested to both the first detection point and the second detection point simultaneously;

[0036] The resistance values ​​of the first current adjustment module and the second current adjustment module are adjusted to control the current load of the chip under test at the first detection point; the resistance values ​​of the third current adjustment module and the fourth current adjustment module are adjusted to control the current load of the chip under test at the second detection point.

[0037] Detect the voltage value of the chip under test under the load corresponding to the first detection point and the second detection point;

[0038] The test chip is deemed qualified based on the deviation between the voltage values ​​at the first and second detection points and the set voltage values ​​at the first and second detection points.

[0039] In another aspect, a computer-readable storage medium is provided, the computer-readable storage medium storing a program that, when executed by a processor, causes the processor to perform the following steps:

[0040] Connect the chip to be tested to both the first detection point and the second detection point simultaneously;

[0041] The resistance values ​​of the first current adjustment module and the second current adjustment module are adjusted to control the current load of the chip under test at the first detection point; the resistance values ​​of the third current adjustment module and the fourth current adjustment module are adjusted to control the current load of the chip under test at the second detection point.

[0042] Detect the voltage value of the chip under test under the load corresponding to the first detection point and the second detection point;

[0043] The test chip is deemed qualified based on the deviation between the voltage values ​​at the first and second detection points and the set voltage values ​​at the first and second detection points.

[0044] The dual-channel dynamic load automated testing system proposed in this application has the following advantages:

[0045] With the above settings, the current flowing to the sampling resistor changes with the voltage of the field-effect transistor during chip performance testing. Furthermore, the different voltage divisions of different field-effect transistors result in different currents flowing to the sampling resistor. Since the same half-wave voltage connects two detection points, the currents flowing to the two detection points change simultaneously. Therefore, this application achieves different and simultaneous currents flowing to the two chip detection points, which can accommodate large current load changes. Simultaneously, it simplifies the testing process and improves efficiency. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a circuit diagram of the dual-channel dynamic load automated testing system provided in the embodiments of this application;

[0048] Figure 2 This is a circuit diagram of the comparator in the dual-channel dynamic load automated testing system provided in this application embodiment;

[0049] Figure 3 This is an oscilloscope sampling diagram of the dual-channel dynamic load automated testing system provided in this application embodiment;

[0050] Figure 4 This is a flowchart of the dual-channel dynamic load automated testing method provided in the embodiments of this application;

[0051] Figure 5 This is a module distribution diagram of the dual-channel dynamic load automated testing system provided in the embodiments of this application.

[0052] The attached diagram includes: 1. First dynamic test circuit; 2. Second dynamic test circuit; 11. First current adjustment module; 12. Second current adjustment module; 21. Third current adjustment module; 22. Fourth current adjustment module; I1. First current; I2. Second current; I3. Third current; I4. Fourth current; V1. First detection point; V2. Second detection point; Q1. First field-effect transistor; Q2. Second field-effect transistor; Q3. Third field-effect transistor; Q4. Fourth field-effect transistor; SW1. First channel switch; SW2. Second channel switch; SW3. Third channel switch; SW4. Fourth channel switch; R1. First sliding resistor; R2. Second sliding resistor; R3. Third sliding resistor; R4. Fourth sliding resistor; Rs1. First sampling resistor; Rs2. First sampling resistor; Rs3. First sampling resistor; Rs4, first sampling resistor; Ss, half-wave voltage; Vs, stable voltage; Vref1, first reference voltage; Vref2, second reference voltage; Vref3, third reference voltage; Vref4, fourth reference voltage; Vsen1, first sampling voltage; Vsen2, second sampling voltage; Vsen3, third sampling voltage; Vsen4, fourth sampling voltage. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] Example 1

[0055] like Figure 1As shown, the server power safety protection system provided in this application includes: a first dynamic test circuit 1, comprising a first current adjustment module 11 and a second current adjustment module 12; the connection point between the first current adjustment module 11 and the second current adjustment module 12 is a first detection point V1; the first current adjustment module 11 receives a half-wave voltage Ss and its resistance value is adjustable, and the second current adjustment module 12 receives a stable voltage Vs and its resistance value is adjustable; a second dynamic test circuit 2, comprising a third current adjustment module 21 and a fourth current adjustment module 22; the third current adjustment module 21 and the fourth current adjustment module 22... The connection point 2 is the second detection point V2; the third current adjustment module 21 inputs the half-wave voltage Ss and its resistance value is adjustable, and the fourth current adjustment module 22 inputs a stable voltage Vs and its resistance value is adjustable; wherein, the first detection point V1 and the second detection point V2 are used to connect to the chip under test, and the load of the chip under test at the first detection point V1 and the second detection point V2 is controlled by adjusting the resistance values ​​of the second current adjustment module 12 and the fourth current adjustment module 22 and by adjusting the resistance values ​​of the first current adjustment module 11 and the third current adjustment module 21.

[0056] With the above settings, the current flowing to the sampling resistor changes with the voltage of the field-effect transistor during chip performance testing. Furthermore, the different voltage divisions of different field-effect transistors result in different currents flowing to the sampling resistor. Since the same half-wave voltage Ss connects two detection points, the currents flowing to the two detection points change simultaneously. Therefore, this application achieves different and simultaneous currents flowing to the two chip detection points, while also accommodating large current load variations. The simple test load also reduces the impact of parasitic inductance on the test load current. Simultaneously, the testing process is simplified, improving efficiency.

[0057] like Figure 1 As shown, in this embodiment, the dual-channel dynamic load automated testing system includes:

[0058] The first dynamic test circuit 1 includes a first current adjustment module 11 and a second current adjustment module 12; the connection point between the first current adjustment module 11 and the second current adjustment module 12 is the first detection point V1; the first current adjustment module 11 is input with a half-wave voltage Ss and its resistance value is adjustable, and the second current adjustment module 12 is input with a stable voltage Vs and its resistance value is adjustable.

[0059] The first dynamic test circuit 1 includes a first current adjustment module 11 and a second current adjustment module 12. The connection point of the first current adjustment module 11 and the second current adjustment module 12 is the first detection point V1. The first current adjustment module 11 is used to provide a first current I1 to the first detection point V1. The first current I1 is a half-wave current. By adjusting the slider of the sliding resistor in the first current adjustment module 11, the magnitude of the first current I1 flowing into the first detection point V1 can be changed. The second current adjustment module 12 is used to provide a second current I2 to the first detection point V1. The second current I2 is a stable current. By adjusting the slider of the sliding resistor in the second current adjustment module 12, the magnitude of the second current I2 flowing into the first detection point V1 can be changed. The current value flowing into the first detection point V1 is the sum of the first current I1 and the second current I2.

[0060] The second dynamic test circuit 2 is provided with a third current adjustment module 21 and a fourth current adjustment module 22; the connection point of the third current adjustment module 21 and the fourth current adjustment module 22 is the second detection point V2; the third current adjustment module 21 inputs the half-wave voltage Ss and its resistance value can be adjusted, and the fourth current adjustment module 22 inputs a stable voltage Vs and its resistance value can be adjusted.

[0061] The second dynamic test circuit 2 includes a third current adjustment module 21 and a fourth current adjustment module 22. The connection point of the third current adjustment module 21 and the fourth current adjustment module 22 is the second detection point V2. The third current adjustment module 21 is used to provide a third current I3 to the second detection point V2. The third current I3 is a half-wave current. By adjusting the slider of the sliding resistor in the third current adjustment module 21, the magnitude of the third current I3 flowing into the second detection point V2 can be changed. The fourth current adjustment module 22 is used to provide a fourth current I4 to the second detection point V2. The fourth current I4 is a stable current. By adjusting the slider of the sliding resistor in the fourth current adjustment module 22, the magnitude of the fourth current I4 flowing into the second detection point V2 can be changed. The current value flowing into the second detection point V2 is the sum of the third current I3 and the fourth current I4.

[0062] The first detection point V1 and the second detection point V2 are used to connect to the chip under test. The load of the chip under test at the first detection point V1 and the second detection point V2 is controlled by adjusting the resistance values ​​of the second current adjustment module 12 and the fourth current adjustment module 22, and by adjusting the resistance values ​​of the first current adjustment module 11 and the third current adjustment module 21.

[0063] The first detection point V1 and the second detection point V2 are connected to the chip under test. The current flowing through the first detection point V1 and the second detection point V2 will flow through the chip under test connected to the first detection point V1 and the second detection point V2. The current flowing through these points will be considered as the load current of the chip under test, and the magnitude and rate of change of the load current will be regarded as the change of the load of the chip under test. By moving the sliding resistor of the first current adjustment module 11, the value of the first current I1 flowing through the first test point can be changed. By moving the sliding resistor of the second current adjustment module 12, the value of the second current I1 flowing through the first test point can be changed. The value of I2, by changing the values ​​of the first current I1 and the second current I2, alters the load current at the first test point, thus changing the load on the chip under test. Moving the sliding resistor of the third current adjustment module 21 changes the value of the third current I3 flowing through the first test point. Moving the sliding resistor of the fourth current adjustment module 22 changes the value of the fourth current I4 flowing through the first test point. Changing the values ​​of the third current I3 and the fourth current I4 alters the load current at the second test point, thus changing the load on the chip under test. By changing the load on the chip under test, dynamic load testing can be performed.

[0064] Example 2

[0065] This embodiment 2 includes the features of the above embodiments, such as Figure 1 As shown, this embodiment provides a dual-channel dynamic load automated testing system, which includes a first oscilloscope and a second oscilloscope.

[0066] The first oscilloscope is connected to the first detection point V1 and is used to detect the voltage value of the chip under test under the load corresponding to the first detection point V1; the second oscilloscope is connected to the second detection point V2 and is used to detect the voltage value of the chip under test under the load corresponding to the second detection point V2. The chip under test is determined to be qualified based on the deviation between the detected voltage value of the first detection point V1 and the detected voltage value of the second detection point V2 and the set voltage of the first detection point V1 and the second detection point V2.

[0067] Understandably, in this embodiment of the invention, a first oscilloscope is connected to a first detection point V1. The first oscilloscope is used to detect the voltage value across the first detection point V1 when a load current flows through it during chip testing, and displays the voltage value across the first detection point V1 through an oscilloscope voltage waveform curve. A second oscilloscope is connected to a second detection point V2. The second oscilloscope is used to detect the voltage value across the second detection point V2 when a load current flows through it during chip testing, and displays the voltage value across the second detection point V2 through an oscilloscope voltage waveform curve.

[0068] If the deviations between the detected voltage value of the first detection point V1 and its set voltage value, and between the detected voltage value of the second detection point V2 and its set voltage value, are within 5%, the chip under test is deemed qualified. If the deviations between the detected voltage value of the first detection point V1 and its set voltage value are not within 5%, and between the detected voltage value of the second detection point V2 and its set voltage value are both within 5%, the chip under test is deemed unqualified. If the deviations between the detected voltage value of the first detection point V1 and its set voltage value are both within 5%, and between the detected voltage value of the second detection point V2 and its set voltage value, the chip under test is deemed unqualified. If the deviations between the detected voltage value of the first detection point V1 and its set voltage value, and between the detected voltage value of the second detection point V2 and its set voltage value are both not within 5%, the chip under test is deemed unqualified.

[0069] like Figure 1 As shown, this embodiment provides a dual-channel dynamic load automated testing system. The first current adjustment module 11 includes a first sliding resistor R1, a first field-effect transistor Q1, and a first sampling resistor Rs1. One end of the lower terminal of the first sliding resistor R1 is input with the half-wave voltage Ss, and the other end of the lower terminal of the first sliding resistor R1 is grounded. The other end of the lower terminal of the first sliding resistor R1 is connected to the source of the first field-effect transistor Q1 through the first sampling resistor Rs1. The drain of the first field-effect transistor Q1 is connected to the first detection point V1, and the gate of the first field-effect transistor Q1 is connected to the upper terminal of the first sliding resistor R1. By adjusting the swivel position of the first sliding resistor R1, the voltage value of the first field-effect transistor Q1 can be adjusted so that the first detection point V1 connected to it obtains a first current I1.

[0070] It is understood that, in this embodiment of the invention, the first current adjustment module 11 includes a first sliding resistor R1, a first field-effect transistor Q1, and a first sampling resistor Rs1. The first current adjustment module 11 is input with a half-wave voltage Ss. The half-wave power supply is connected to one end of the lower terminal of the first sliding rheostat. The other end of the lower terminal of the first sliding resistor R1 is grounded to protect the first current adjustment module 11. The upper terminal of the first sliding resistor R1 is connected to the gate of the first field-effect transistor Q1. The voltage value of the first field-effect transistor Q1 can be changed by moving the slider of the first sliding resistor R1. According to the output characteristics of the first field-effect transistor Q1, the drain outputs a first current I1 of different magnitudes for different voltage values. The drain of the first field-effect transistor Q1 is connected to the first detection point V1. Therefore, the first current I1 flows through the first detection point V1 as the load current.

[0071] like Figure 1 As shown, this embodiment provides a dual-channel dynamic load automated testing system. The second current adjustment module 12 includes a second sliding resistor R2, a second field-effect transistor Q2, and a second sampling resistor Rs2. One end of the lower terminal of the second sliding resistor R2 is input with the stable voltage Vs, and the other end of the lower terminal of the second sliding resistor R2 is grounded. The other end of the lower terminal of the second sliding resistor R2 is connected to the source of the second field-effect transistor Q2 through the second sampling resistor Rs2. The drain of the second field-effect transistor Q2 is connected to the first detection point V1, and the gate of the second field-effect transistor Q2 is connected to the upper terminal of the second sliding resistor R2. By adjusting the swivel position of the second sliding resistor R2, the voltage value of the second field-effect transistor Q2 can be adjusted so that the first detection point V1 connected to it obtains a second current I2. The current at the first detection point V1 is equal to the sum of the first current I1 and the second current I2.

[0072] It is understood that, in this embodiment of the invention, the second current regulation module 12 includes a second sliding resistor R2, a second field-effect transistor Q2, and a second sampling resistor Rs2. The second current regulation module 12 is input with a stable voltage Vs. The stable power supply is connected to one end of the lower terminal of the second sliding resistor. The other end of the lower terminal of the second sliding resistor R2 is grounded to protect the second current regulation module 12. The upper terminal of the second sliding resistor R2 is connected to the gate of the second field-effect transistor Q2. By moving the slider of the second sliding resistor R2, the voltage value of the second field-effect transistor Q2 can be changed. According to the output characteristics of the second field-effect transistor Q2, different voltage values ​​result in different drain output currents I2. The drain of the second field-effect transistor Q2 is connected to the first detection point V1. Therefore, the second current I2 flows through the first detection point V1 as the load current. The load current at the first detection point V1 is the sum of I1 and the second current I2.

[0073] like Figure 1As shown, this embodiment provides a dual-channel dynamic load automated testing system. The third current adjustment module 21 includes a third sliding resistor R3, a third field-effect transistor Q3, and a third sampling resistor Rs3. The lower terminal of the third sliding resistor R3 is connected to one end of the half-wave voltage Ss, and the other end of the lower terminal of the third sliding resistor R3 is grounded. The other end of the lower terminal of the third sliding resistor R3 is connected to the source of the third field-effect transistor Q3 through the third sampling resistor Rs3. The drain of the third field-effect transistor Q3 is connected to the second detection point V2, and the gate of the third field-effect transistor Q3 is connected to the upper terminal of the third sliding resistor R3. By adjusting the swivel position of the third sliding resistor R3, the voltage value of the third field-effect transistor Q3 can be adjusted so that the second detection point V2 connected to it obtains a third current I3.

[0074] It is understood that in this embodiment of the invention, the third current adjustment module 21 includes a third sliding resistor R3, a third field-effect transistor Q3, and a third sampling resistor Rs3. The third current adjustment module 21 is input with a half-wave voltage Ss. The half-wave voltage Ss input by the first current adjustment module 11 and the half-wave voltage Ss input by the third current adjustment module 21 are the same half-wave voltage Ss. The half-wave power supply is connected to one end of the lower terminal of the third sliding resistor. The other end of the lower terminal of the third sliding resistor R3 is grounded to protect the third current adjustment module 21. The upper terminal of the third sliding resistor R3 is connected to the gate of the third field-effect transistor Q3. The voltage value of the third field-effect transistor Q3 can be changed by moving the slider of the third sliding resistor R3. According to the output characteristics of the third field-effect transistor Q3, the drain outputs a third current I3 of different magnitudes for different voltage values. The drain of the third field-effect transistor Q3 is connected to the second detection point V2. Therefore, the third current I3 flows through the second detection point V2 as the load current.

[0075] like Figure 1 As shown, this embodiment provides a dual-channel dynamic load automated testing system. The fourth current adjustment module 22 includes a fourth sliding resistor R4, a fourth field-effect transistor Q4, and a fourth sampling resistor Rs4. One end of the lower terminal of the fourth sliding resistor R4 is input with the stable voltage Vs, and the other end of the lower terminal of the fourth sliding resistor R4 is grounded. The other end of the lower terminal of the fourth sliding resistor R4 is connected to the source of the fourth field-effect transistor Q4 through the fourth sampling resistor Rs4. The drain of the fourth field-effect transistor Q4 is connected to the second detection point V2, and the gate of the fourth field-effect transistor Q4 is connected to the upper terminal of the fourth sliding resistor R4. By adjusting the swivel position of the fourth sliding resistor R4, the voltage value of the fourth field-effect transistor Q4 can be adjusted so that the second detection point V2 connected to it obtains a fourth current I4. The current at the second detection point V2 is equal to the sum of the third current I3 and the fourth current I4.

[0076] It is understood that, in this embodiment of the invention, the fourth current regulation module 22 includes a fourth sliding resistor R4, a fourth field-effect transistor Q4, and a fourth sampling resistor Rs4. The fourth current regulation module 22 is input with a stable voltage Vs. The stable power supply is connected to one end of the lower terminal of the fourth sliding resistor. The other end of the lower terminal of the fourth sliding resistor R4 is grounded to protect the fourth current regulation module 22. The upper terminal of the fourth sliding resistor R4 is connected to the gate of the fourth field-effect transistor Q4. By moving the slider of the fourth sliding resistor R4, the voltage value of the fourth field-effect transistor Q4 can be changed. According to the output characteristics of the fourth field-effect transistor Q4, different voltage values ​​result in different drain output currents I4. The drain of the fourth field-effect transistor Q4 is connected to the second detection point V2. Therefore, the fourth current I4 flows through the second detection point V2 as a load current. The load current at the second detection point V2 is the sum of the third current I3 and the fourth current I4.

[0077] like Figure 2 , 3 As shown, this embodiment provides a dual-channel dynamic load automated testing system, which further includes a voltage protector; the voltage protector includes a first voltage protector, a second voltage protector, a third voltage protector, and a fourth voltage protector.

[0078] The first voltage protector includes a first comparator and a first channel switch SW1. The positive input terminal of the first comparator is input with the voltage across the first sampling resistor Rs1, the negative input terminal of the first comparator is input with a first reference voltage, and the output terminal of the first comparator is connected to the first channel switch SW1. The first channel switch SW1 is connected in series between the gate of the first field-effect transistor Q1 and the upper terminal of the sliding resistor.

[0079] The second voltage protector includes a second comparator and a second channel switch SW2. The positive input terminal of the second comparator is input with the voltage across the second sampling resistor Rs2, and the negative input terminal of the second comparator is input with a second reference voltage. The output terminal of the second comparator is connected to the second channel switch SW2. The second channel switch SW2 is connected in series between the gate of the second field-effect transistor Q2 and the upper terminal of the sliding resistor.

[0080] The third voltage protector includes a third comparator and a third channel switch SW3. The positive input terminal of the third comparator is input with the voltage across the third sampling resistor Rs3, and the negative input terminal of the third comparator is input with the third reference voltage. The output terminal of the third comparator is connected to the third channel switch SW3. The third channel switch SW3 is connected in series between the gate of the third field-effect transistor Q3 and the upper terminal of the sliding resistor.

[0081] The fourth voltage protector includes a fourth comparator and a fourth channel switch SW4. The positive input terminal of the fourth comparator is input with the voltage across the fourth sampling resistor Rs4, and the negative input terminal of the fourth comparator is input with the fourth reference voltage. The output terminal of the fourth comparator is connected to the fourth channel switch SW4, which is connected in series between the gate of the fourth field-effect transistor Q4 and the upper terminal of the sliding resistor.

[0082] It is understood that, in this embodiment of the invention, the dual-channel dynamic load automated testing system further includes a voltage protector; the voltage protector includes a first voltage protector, a second voltage protector, a third voltage protector, and a fourth voltage protector. The first voltage protector includes a first comparator and a first channel switch SW1. The positive input terminal of the first comparator receives the voltage across the first sampling resistor Rs1, the negative input terminal receives a first reference voltage, and the output terminal of the first comparator is connected to the first channel switch SW1. The first channel switch SW1 is connected in series between the gate of the first field-effect transistor Q1 and the upper terminal of the sliding resistor. When the voltage at the positive input terminal of the first comparator is greater than the voltage at the negative input terminal, the first comparator sends a high-level signal s1 to the first channel switch SW1, turning off the first channel switch SW1 and protecting the first field-effect transistor Q1 from breakdown. At this time, the first field-effect transistor Q1 no longer has voltage, and its drain no longer outputs current.

[0083] The second voltage protector includes a second comparator and a second channel switch SW2. The positive input terminal of the second comparator receives the voltage across the second sampling resistor Rs2, and the negative input terminal receives the second reference voltage. The output terminal of the second comparator is connected to the second channel switch SW2, which is connected in series between the gate of the second field-effect transistor Q2 and the upper terminal of the sliding resistor. When the voltage at the positive input terminal of the second comparator is greater than the voltage at the negative input terminal, the second comparator sends a high-level signal s2 to the second channel switch SW2, turning off the second channel switch SW2 and protecting the second field-effect transistor Q2 from breakdown. At this time, the second field-effect transistor Q2 no longer has voltage, and its drain no longer outputs current.

[0084] The third voltage protector includes a third comparator and a third channel switch SW3. The positive input terminal of the third comparator receives the voltage across the third sampling resistor Rs3, and the negative input terminal receives the third reference voltage. The output terminal of the third comparator is connected to the third channel switch SW3, which is connected in series between the gate of the third field-effect transistor Q3 and the upper terminal of the sliding resistor. When the voltage at the positive input terminal of the third comparator is greater than the voltage at the negative input terminal, the third comparator sends a high-level signal s3 to the third channel switch SW3, turning off the third channel switch SW3 and protecting the third field-effect transistor Q3 from breakdown. At this time, the third field-effect transistor Q3 no longer has voltage, and its drain no longer outputs current.

[0085] The fourth voltage protector includes a fourth comparator and a fourth channel switch SW4. The positive input of the fourth comparator is the voltage across the fourth sampling resistor Rs4, and the negative input is the fourth reference voltage. The output of the fourth comparator is connected to the fourth channel switch SW4, which is connected in series between the gate of the fourth field-effect transistor Q4 and the upper terminal of the sliding resistor. When the voltage at the positive input of the fourth comparator is greater than the voltage at the negative input, the fourth comparator sends a high-level signal s4 to the fourth channel switch SW4, turning off the fourth channel switch SW4 and protecting the fourth field-effect transistor Q4 from breakdown. At this time, the fourth field-effect transistor Q4 no longer has voltage, and its drain no longer outputs current.

[0086] Specific limitations regarding the dual-channel dynamic load automated testing system can be found in the method limitations section above, and will not be repeated here. Each module in the aforementioned dual-channel dynamic load automated testing system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0087] Example 3

[0088] like Figure 4 As shown in one embodiment, a method for applying a dual-channel dynamic load automated testing system is provided, including the following steps S1-S4:

[0089] S1: Connect the chip to be tested to both the first detection point V1 and the second detection point V2.

[0090] In this embodiment of the invention, when the first detection point V1 and the second detection point V2 are connected to the chip under test, the current of the first detection point V1 and the second detection point V2 will pass through the chip under test. By detecting the voltage across the first detection point V1 and the second detection point V2, the impact of load changes on the chip under test can be determined, thereby determining whether the chip under test is qualified.

[0091] S2: Adjust the resistance values ​​of the first current adjustment module 11 and the second current adjustment module 12 to control the current load of the chip under test at the first detection point V1; adjust the resistance values ​​of the third current adjustment module 21 and the fourth current adjustment module 22 to control the current load of the chip under test at the second detection point V2.

[0092] In this embodiment of the invention, the resistance value of the first current adjustment module 11 controls the source voltage of the first field-effect transistor Q1, and the source voltage of the first field-effect transistor Q1 controls the drain output of the first field-effect transistor Q1 to output different I1, so different first currents I1 flow through the first detection point V1. The resistance value of the second current adjustment module 12 controls the source voltage of the second field-effect transistor Q2, and the source voltage of the second field-effect transistor Q2 controls the drain output of the second field-effect transistor Q2 to output different second currents I2, so different second currents I2 flow through the first detection point V1. The sum of the first current I1 and the second current I2 is the load of the first detection point V1. When the first current I1 and the second current I2 change, the load of the first detection point V1 changes. The resistance value of the third current adjustment module 21 controls the source voltage of the third field-effect transistor Q3. The source voltage of the third field-effect transistor Q3 controls the drain output of the third field-effect transistor Q3 to output different third currents I3. Different third currents I3 flow through the second detection point V2. The resistance value of the fourth current adjustment module 22 controls the source voltage of the fourth field-effect transistor Q4. The source voltage of the fourth field-effect transistor Q4 controls the drain output of the fourth field-effect transistor Q4 to output different fourth currents I4. Different fourth currents I4 flow through the second detection point V2. The sum of the third current I3 and the fourth current I4 is the load of the second detection point V2. When the third current I3 and the fourth current I4 change, the load of the second detection point V2 changes.

[0093] S3: Detect the voltage value of the chip under test under the load corresponding to the first detection point V1 and the second detection point V2.

[0094] In this embodiment of the invention, a first oscilloscope is connected to both ends of a first detection point V1 to detect the voltage across the first detection point V1 under load. When the first current I1 and the second current I2 flow through the first detection point V1, a load is generated on the chip under test, and the voltage value across the first detection point V1 is the voltage value of the detection point of the chip under test in the circuit.

[0095] The second oscilloscope is connected to both ends of the second detection point V2 and is used to detect the voltage across the second detection point V2 under load. When the third current I3 and the fourth current I4 flow through the second detection point V2, a load is generated on the chip under test, and the voltage value across the second detection point V2 is the voltage value of the detection point of the chip under test in the circuit.

[0096] S4: Determine whether the chip under test is qualified based on the deviation between the voltage values ​​of the first detection point V1 and the second detection point V2 and the set voltage values ​​of the first detection point V1 and the second detection point V2.

[0097] In this embodiment of the invention, if the deviation between the detected voltage value of the first detection point V1 and the set voltage value of the first detection point V1, and the deviation between the detected voltage value of the second detection point V2 and the set voltage value of the second detection point V2, the chip under test is determined to be qualified; if the deviation between the detected voltage value of the first detection point V1 and the set voltage value of the first detection point V1 is not within 5%, and the deviation between the detected voltage value of the second detection point V2 and the set voltage value of the second detection point V2 is within 5%, the chip under test is determined to be unqualified; if the deviation between the detected voltage value of the first detection point V1 and the set voltage value of the first detection point V1, and the deviation between the detected voltage value of the second detection point V2 and the set voltage value of the second detection point V2 is not within 5%, the chip under test is determined to be unqualified; if the deviations between the detected voltage value of the first detection point V1 and the set voltage value of the first detection point V1, and the deviation between the detected voltage value of the second detection point V2 and the set voltage value of the second detection point V2 are both not within 5%, the chip under test is determined to be unqualified.

[0098] The above-mentioned method for applying a dual-channel dynamic load automated testing system, combined with the aforementioned technical features, achieves a beneficial effect by solving the technical problems raised in the background art.

[0099] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order requirement for the execution of these steps; they can be executed in other orders. Furthermore, Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0100] Example 4

[0101] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a method for recognizing hot-swappable hard drives.

[0102] The computer device can be a terminal. It includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When executed by the processor, the computer program implements a method for recognizing hot-swappable hard drives. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0103] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0104] Connect the chip to be tested to both the first detection point V1 and the second detection point V2 simultaneously.

[0105] The resistance values ​​of the first current adjustment module 11 and the second current adjustment module 12 are adjusted to control the current load of the chip under test at the first detection point V1; the resistance values ​​of the third current adjustment module 21 and the fourth current adjustment module 22 are adjusted to control the current load of the chip under test at the second detection point V2.

[0106] Detect the voltage value of the chip under test under the load corresponding to the first detection point V1 and the second detection point V2;

[0107] The test chip is deemed qualified based on the deviation between the voltage values ​​of the first detection point V1 and the second detection point V2 and the set voltage values ​​of the first detection point V1 and the second detection point V2.

[0108] Example 5

[0109] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps:

[0110] Connect the chip to be tested to both the first detection point V1 and the second detection point V2 simultaneously.

[0111] The resistance values ​​of the first current adjustment module 11 and the second current adjustment module 12 are adjusted to control the current load of the chip under test at the first detection point V1; the resistance values ​​of the third current adjustment module 21 and the fourth current adjustment module 22 are adjusted to control the current load of the chip under test at the second detection point V2.

[0112] Detect the voltage value of the chip under test under the load corresponding to the first detection point V1 and the second detection point V2;

[0113] The test chip is deemed qualified based on the deviation between the voltage values ​​of the first detection point V1 and the second detection point V2 and the set voltage values ​​of the first detection point V1 and the second detection point V2.

[0114] The dual-channel dynamic load automated testing system proposed in this application adjusts the resistance values ​​of the second and fourth sliding resistors by inputting stable voltages to the second and fourth current adjustment modules, thereby enabling the second and fourth current adjustment modules to obtain a second current and a fourth current, respectively. It also adjusts the resistance value of the first sliding resistor by inputting a half-wave voltage to the first current adjustment module, enabling the first current adjustment module to obtain a first current. Furthermore, it adjusts the resistance value of the third sliding resistor by inputting a half-wave voltage to the third current adjustment module, enabling the third current adjustment module to obtain a third current. The first and third currents are different values, while the half-wave voltages of the first and third current adjustment modules are the same. The sum of the first and second currents represents the load across the first detection point, and the sum of the third and fourth currents represents the load across the second detection point. By comparing the monitored voltage values ​​at the first and second detection points of the chip under test with the set voltage values ​​at the first and second detection points of the chip under test, the system determines whether the power supply under test is qualified.

[0115] With the above settings, the current flowing to the sampling resistor changes with the voltage of the field-effect transistor during chip performance testing. Furthermore, the different voltage divisions of different field-effect transistors result in different currents flowing to the sampling resistor. Since the same half-wave voltage connects two detection points, the currents flowing to the two detection points change simultaneously. Therefore, this application achieves different and simultaneous currents flowing to the two chip detection points, while also accommodating large current load variations. The simple test load also reduces the impact of parasitic inductance on the test load current. Simultaneously, the testing process is simplified, improving efficiency.

[0116] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A dual channel dynamic load automated test system, characterized by, include: The first dynamic test circuit includes a first current regulation module and a second current regulation module. The connection point between the first current adjustment module and the second current adjustment module is the first detection point; the first current adjustment module receives a half-wave voltage and its resistance value is adjustable, and the second current adjustment module receives a stable voltage and its resistance value is adjustable. The second dynamic test circuit is equipped with a third current adjustment module and a fourth current adjustment module; The connection point between the third current adjustment module and the fourth current adjustment module is the second detection point; the third current adjustment module receives the half-wave voltage and its resistance value is adjustable, and the fourth current adjustment module receives a stable voltage and its resistance value is adjustable. The first and second detection points are both connected to the chip under test. The load on the chip under test at the first and second detection points is controlled by adjusting the resistance values ​​of the second and fourth current adjustment modules and by adjusting the resistance values ​​of the first and third current adjustment modules.

2. The dual lane dynamic load automated test system of claim 1, wherein, The automated test system for dynamic load of the channel also includes a first oscilloscope and a second oscilloscope; The first oscilloscope is connected to the first detection point and is used to detect the voltage value of the chip under test under the load corresponding to the first detection point. The second oscilloscope is connected to the second detection point and is used to detect the voltage value of the chip under test under the load corresponding to the second detection point. The chip under test is determined to be qualified based on the deviation between the detected voltage value of the first detection point and the detected voltage value of the second detection point and the set voltage of the first detection point and the second detection point.

3. The dual lane dynamic load automated test system of claim 1, wherein, The first current regulation module includes a first sliding resistor, a first field-effect transistor, and a first sampling resistor; The half-wave voltage is input to one end of the lower terminal of the first sliding resistor, and the other end of the lower terminal of the first sliding resistor is grounded; the other end of the lower terminal of the first sliding resistor is connected to the source of the first field-effect transistor through the first sampling resistor, the drain of the first field-effect transistor is connected to the first detection point, and the gate of the first field-effect transistor is connected to the upper terminal of the first sliding resistor. By adjusting the position of the swivel of the first sliding resistor, the voltage value of the first field-effect transistor can be adjusted so that the first detection point connected to it receives the first current.

4. The dual lane dynamic load automated test system of claim 3, wherein, The second current regulation module includes a second sliding resistor, a second field-effect transistor, and a second sampling resistor; The stable voltage is input to one end of the lower terminal of the second sliding resistor, and the other end of the lower terminal of the second sliding resistor is grounded; the other end of the lower terminal of the second sliding resistor is connected to the source of the second field-effect transistor through the second sampling resistor, the drain of the second field-effect transistor is connected to the first detection point, and the gate of the second field-effect transistor is connected to the upper terminal of the second sliding resistor. By adjusting the position of the slid plate of the second sliding resistor, the voltage value of the second field-effect transistor can be adjusted so that the first detection point connected to it receives a second current; the current at the first detection point is equal to the sum of the first current and the second current.

5. The dual lane dynamic load automated test system of claim 4, wherein, The third current regulation module includes a third sliding resistor, a third field-effect transistor, and a third sampling resistor; The half-wave voltage is input to one end of the lower terminal of the third sliding resistor, and the other end of the lower terminal of the third sliding resistor is grounded; the other end of the lower terminal of the third sliding resistor is connected to the source of the third field-effect transistor through the third sampling resistor, the drain of the third field-effect transistor is connected to the second detection point, and the gate of the third field-effect transistor is connected to the upper terminal of the third sliding resistor. By adjusting the position of the swivel of the third sliding resistor, the voltage value of the third field-effect transistor can be adjusted so that the second detection point connected to it can obtain a third current.

6. The dual lane dynamic load automated test system of claim 5, wherein, The fourth current regulation module includes a fourth sliding resistor, a fourth field-effect transistor, and a fourth sampling resistor; The stable voltage is input to one end of the lower terminal of the fourth sliding resistor, and the other end of the lower terminal of the fourth sliding resistor is grounded; the other end of the lower terminal of the fourth sliding resistor is connected to the source of the fourth field-effect transistor through the fourth sampling resistor, the drain of the fourth field-effect transistor is connected to the second detection point, and the gate of the fourth field-effect transistor is connected to the upper terminal of the fourth sliding resistor. By adjusting the position of the slid plate of the fourth sliding resistor, the voltage value of the fourth field-effect transistor can be adjusted so that the second detection point connected to it obtains a fourth current; the current at the second detection point is equal to the sum of the third current and the fourth current.

7. The dual lane dynamic load automated test system of claim 6, wherein, The dual-channel dynamic load automated testing system also includes a voltage protector; The voltage protector includes a first voltage protector, a second voltage protector, a third voltage protector, and a fourth voltage protector; The first voltage protector includes a first comparator and a first channel switch. The positive input terminal of the first comparator is input with the voltage across the first sampling resistor, the negative input terminal of the first comparator is input with a first reference voltage, and the output terminal of the first comparator is connected to the first channel switch. The first channel switch is connected in series between the gate of the first field-effect transistor and the upper terminal of the sliding resistor. The second voltage protector includes a second comparator and a second channel switch. The positive input terminal of the second comparator is input with the voltage across the second sampling resistor, the negative input terminal of the second comparator is input with a second reference voltage, and the output terminal of the second comparator is connected to the second channel switch. The second channel switch is connected in series between the gate of the second field-effect transistor and the upper terminal of the sliding resistor. The third voltage protector includes a third comparator and a third channel switch. The positive input terminal of the third comparator is input to the voltage across the third sampling resistor, the negative input terminal of the third comparator is input to the third reference voltage, and the output terminal of the third comparator is connected to the third channel switch. The third channel switch is connected in series between the gate of the third field-effect transistor and the upper terminal of the sliding resistor. The fourth voltage protector includes a fourth comparator and a fourth channel switch. The positive input terminal of the fourth comparator receives the voltage across the fourth sampling resistor, the negative input terminal of the fourth comparator receives the fourth reference voltage, and the output terminal of the fourth comparator is connected to the fourth channel switch. The fourth channel switch is connected in series between the gate of the fourth field-effect transistor and the upper terminal of the sliding resistor.

8. A dual channel dynamic load automated testing method using the dual channel dynamic load automated testing system as claimed in any one of claims 1 to 7, characterized in that, The method includes: Connect the chip to be tested to both the first detection point and the second detection point simultaneously; The resistance values ​​of the first current adjustment module and the second current adjustment module are adjusted to control the current load of the chip under test at the first detection point; the resistance values ​​of the third current adjustment module and the fourth current adjustment module are adjusted to control the current load of the chip under test at the second detection point. Detect the voltage value of the chip under test under the load corresponding to the first detection point and the second detection point; The test chip is deemed qualified based on the deviation between the voltage values ​​at the first and second detection points and the set voltage values ​​at the first and second detection points.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 8.

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