Chip quality anomaly analysis method and system fusing timing resistance value data

Abstract

This invention discloses a chip quality anomaly analysis method and system that integrates timing resistance data, relating to the field of integrated circuit manufacturing and testing technology. The method includes: obtaining circuit component manufacturing parameters, predicting resistance, and obtaining circuit component resistance values; building a graph neural network based on chip circuit component design data, training a digital chip with circuit component resistance values ​​and test input timing signals as node inputs, and generating a predicted output timing signal; comparing the predicted output timing signal and the test output timing signal to obtain a signal timing deviation coefficient; and returning a chip quality anomaly signal to the chip manufacturing end when the signal timing deviation coefficient is greater than or equal to a deviation coefficient threshold. This invention performs virtualized quality prediction before chip physical manufacturing, reducing material waste caused by traditional testing and forming a closed loop from testing to process optimization, thereby improving the quality control capability and process regulation efficiency of the manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing and testing technology, and specifically to a method and system for analyzing chip quality anomalies by integrating timing resistance data. Background Technology

[0002] In the field of integrated circuit manufacturing, ensuring the functionality and performance reliability of chips is of paramount importance. Accurate characterization of the resistance parameters of circuit elements and in-depth analysis of their impact on timing signal transmission have become key technical means for evaluating chip quality.

[0003] Current technologies typically involve applying input signals to a chip after its physical fabrication and acquiring its output timing waveforms using specialized testing equipment. The characteristic patterns in the timing resistance data are then analyzed to determine if the chip exhibits quality anomalies caused by process variations, material defects, or poor contact. However, this type of testing scheme, reliant on already manufactured chips, has inherent flaws. This method is essentially a post-hoc intervention experiment; once the test results are unsatisfactory, the invested wafer materials, manufacturing process costs, and packaging resources become irreversible losses. This quality assessment model not only leads to significant material waste and increased production costs but also, due to the severe lag in problem detection, makes it difficult to provide timely and effective process adjustment feedback to the manufacturing front end. Even though some improved solutions attempt to introduce anomaly detection algorithms for real-time analysis of test curves to provide early warnings, their analysis is still limited to the measured data of already produced chips, failing to change the fact that quality assessment lags behind physical manufacturing. Therefore, it cannot reduce material waste at the source or perform proactive process optimization. Summary of the Invention

[0004] This invention addresses the technical problems in existing technologies, such as lagging chip quality inspection, reliance on physical chip finished product testing leading to severe material loss, and inability to achieve timely feedback from the front end of the process. It provides a chip quality anomaly analysis method and system that integrates timing resistance data.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: In a first aspect, the present invention provides a chip quality anomaly analysis method that integrates timing resistance data, including: Obtain the manufacturing parameters of the circuit components, predict the resistance, and obtain the resistance value of the circuit components; Based on the design data of chip circuit components, a graph neural network is built with components as nodes and circuit connection positions as edges. The resistance values ​​of the circuit components and the test input timing signals are used as node inputs to train the digital chip and generate predictive output timing signals. By comparing the predicted output timing signal and the test output timing signal, the signal timing deviation coefficient is obtained; When the timing deviation coefficient of the signal is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end.

[0006] Secondly, the present invention provides a chip quality anomaly analysis system that integrates timing resistance data, including: The parameter acquisition and prediction module is used to obtain the manufacturing parameters of circuit components, predict the resistance, and obtain the resistance value of the circuit components. The graph network construction and training module is used to build a graph neural network based on chip circuit element design data, with elements as nodes and circuit connection positions as edges. The digital chip is trained using the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals. The timing deviation analysis module is used to compare the predicted output timing signal and the test output timing signal to obtain the signal timing deviation coefficient; The quality judgment and feedback module is used to return a chip quality abnormality signal to the chip manufacturing end when the timing deviation coefficient of the signal is greater than or equal to the deviation coefficient threshold.

[0007] The beneficial effects of this invention are: Compared to existing technologies, this invention first shifts the quality assessment node from the completion of physical chip fabrication to the manufacturing parameter input stage. By predicting the resistance values ​​of circuit components and combining them with circuit design data to construct an executable simulation digital chip model, virtual quality prediction is achieved before material input. Secondly, by using graph neural networks to model the internal circuit connections and timing signal propagation of the chip, the impact of resistance parameter fluctuations on the final output timing signal can be accurately simulated, revealing potential functional anomalies caused by process deviations. Thirdly, by quantifying the timing deviation coefficient between the predicted output timing signal and the standard signal, an objective and accurate digital assessment of chip quality can be achieved, providing a clear and reliable basis for quality judgment. Finally, when the prediction results indicate quality risks, anomaly signals can be promptly fed back to the manufacturing end, forming a rapid closed loop from design and parameter prediction to manufacturing process adjustment. This not only reduces material waste and production costs caused by traditional physical testing but also realizes a shift from passive testing to proactive prediction, and from back-end intervention to front-end optimization, improving the yield control level and process monitoring capabilities of chip manufacturing. Attached Figure Description

[0008] Figure 1 A flowchart illustrating the chip quality anomaly analysis method that integrates timing resistance data provided by this invention; Figure 2 This is a schematic diagram of the chip quality anomaly analysis system that integrates timing resistance data provided by the present invention.

[0009] In the attached diagram, the components represented by each number are as follows: Parameter acquisition and prediction module 11, graph network construction and training module 12, time series deviation analysis module 13, quality judgment and feedback module 14. Detailed Implementation

[0010] Example 1, as Figure 1 As shown, this embodiment of the invention provides a chip quality anomaly analysis method that integrates timing resistance data, including: S10: Obtain the manufacturing parameters of the circuit components, predict the resistance, and obtain the resistance value of the circuit components; First, the manufacturing parameters of the circuit element are obtained, and resistance is predicted to obtain the resistance value of the circuit element. In the integrated circuit manufacturing process, the electrical characteristics of the circuit element are determined by its fabrication process. The specific parameters of each process, such as the energy and dose of ion implantation, the thickness and uniformity of thin film deposition, and the precision and sidewall morphology of etching, all affect the final material properties and geometry of the element, thus directly affecting its resistance value. Therefore, manufacturing parameters are the technological root of the element's resistance characteristics.

[0011] Resistance prediction based on circuit component manufacturing parameters aims to estimate the component's resistance characteristics in advance, given process parameters, before physical chip manufacturing, and to assess the potential impact of process fluctuations on circuit performance. This prediction process transforms abstract process descriptions into concrete electrical parameters, enabling the identification of problematic points with abnormal resistance discovered during backend testing at the frontend process parameter review stage. This allows for early warning and screening of process parameter combinations that may lead to product performance defects before the physical manufacturing of wafer materials. Through this resistance prediction, the risk of batch material loss due to improper parameter settings can be reduced, unreasonable manufacturing settings can be identified and adjusted early, and trial production waste can be minimized.

[0012] Specifically, this involves obtaining the manufacturing parameters of circuit components, predicting resistance, and obtaining the resistance values ​​of the circuit components, including: From the manufacturing parameters of the circuit element, extract the circuit element model and manufacturing process data, and collect historical manufacturing data of multiple sets of circuit elements of the same model and the same process. Each set of historical manufacturing data of the multiple sets of circuit elements includes historical manufacturing parameters of the circuit element and recorded resistance value of the circuit element. Traverse the historical manufacturing data of the multiple sets of circuit elements, and filter the set of circuit element resistance values ​​in which the similarity between the historical manufacturing parameters of the circuit elements and the manufacturing parameters of the circuit elements is greater than or equal to the manufacturing parameter similarity threshold. Calculate the set of values ​​of the resistance values ​​recorded by the circuit element, and set them as the resistance values ​​of the circuit element.

[0013] First, the circuit element model and manufacturing process data are extracted from the circuit element manufacturing parameters. Specifically, the circuit element model is a unique identifier for a specific circuit element, used to characterize the standard category and specifications of the circuit element in the design and process specifications; the manufacturing process data is a description of the process flow of the manufacturing process of the circuit element of that model, specifically characterizing a series of processing steps required for the circuit element of that model from start to finish. Each step is usually identified by the specific processing equipment model that performs the step. For example, the process sequence can be represented as "equipment model A → equipment model B → equipment model C".

[0014] Subsequently, based on the extracted circuit component model and manufacturing process data, multiple sets of historical manufacturing data for circuit components of the same model and following the same process were collected. Each set of historical manufacturing data for circuit components completely includes two parts: the first is the historical manufacturing parameters of the circuit component, that is, a complete set of process parameters actually used in the production of the historical component; the second is the corresponding recorded resistance value of the circuit component obtained through actual measurement after manufacturing.

[0015] Next, the collected historical manufacturing data of multiple circuit components are traversed. For each set of historical manufacturing data, the historical manufacturing parameters of the circuit components included are compared and calculated one by one with the manufacturing parameters of the circuit component to be predicted, resulting in a quantified manufacturing parameter similarity. Specifically, this manufacturing parameter similarity measures the overall closeness between the historical manufacturing parameter set and the current manufacturing parameter set. The higher the manufacturing parameter similarity, the closer the manufacturing conditions corresponding to this set of historical manufacturing data are to the manufacturing conditions set for the current prediction target, and the higher the consistency in resistance characteristics of the circuit components produced by the two may be. The lower the similarity, the greater the difference in manufacturing conditions between the two, and the lower the reference value of its resistance characteristics.

[0016] Specifically, the manufacturing parameter similarity calculation process includes: From the historical manufacturing parameters of the circuit elements, extract the historical manufacturing parameters of the first process node up to the historical manufacturing parameters of the Nth process node; From the manufacturing parameters of the circuit elements, extract the manufacturing parameters of the first process node up to the manufacturing parameters of the Nth process node; By comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained. The similarity of the manufacturing parameters of the Nth process node is obtained by comparing the historical manufacturing parameters of the Nth process node with the manufacturing parameters of the Nth process node. The average value of the manufacturing parameter similarity of the first process node up to the manufacturing parameter similarity of the Nth process node is set as the manufacturing parameter similarity.

[0017] First, from the historical manufacturing parameters of the circuit components used as a reference, the process parameters corresponding to the first process are extracted in sequence according to the order of the manufacturing process. These are the historical manufacturing parameters of the first process node. The historical manufacturing parameters of subsequent process nodes are then extracted until the last node of the entire process flow is extracted, which is the historical manufacturing parameters of the Nth process node.

[0018] At the same time, from the current manufacturing parameters of the circuit components to be predicted, the manufacturing parameters of the first process node up to the Nth process node are extracted in the same process node order to ensure that the historical manufacturing parameters and the current manufacturing parameters are completely aligned in the process structure, which facilitates subsequent point-by-point comparison.

[0019] Furthermore, for the first process node, the historical manufacturing parameters of the first process node are compared with the manufacturing parameters of the first process node, and the similarity of the two parameter sets is comprehensively evaluated.

[0020] Specifically, by comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained, including: The intersection-union comparison (IUCN) of the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node are statistically analyzed to obtain the type parameter similarity. Obtain a predefined set of quantization parameter deviation thresholds that correspond one-to-one with the quantization parameter attribute set; Based on the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node, and using the set of quantitative parameter deviation thresholds as a benchmark, the proportion of quantitative parameter deviations that are less than or equal to the quantitative parameter deviation thresholds is statistically analyzed to obtain the quantitative parameter similarity. Calculate the average of the type parameter similarity and the quantization parameter similarity, and set it as the manufacturing parameter similarity of the first process node.

[0021] First, the historical manufacturing parameters and the type parameters contained within the first process node are processed. Type parameters typically refer to non-numerical descriptive attributes such as the type of materials used, processing methods, and equipment operation modes in the process. An intersection-union ratio (IUGR) is performed on the set of type parameters in the historical and current manufacturing parameters of the first process node. This IUGR calculates the ratio of the number of elements in the intersection to the number of elements in the union of the two sets of type parameters. This ratio directly reflects the degree of consistency in the type composition of the two parameter sets, and its numerical result is defined as the type parameter similarity. Specifically, a higher type parameter similarity indicates that the materials and basic process methods used in the historical and current manufacturing processes at this process node are more consistent.

[0022] Secondly, quantification parameters are processed. Specifically, quantification parameters refer to quantifiable process control variables at each process node, such as processing temperature, duration, applied pressure, gas flow rate, or chemical concentration. A quantification parameter attribute set refers to the collection of all numerical process control variables that need to be monitored and compared at a specific process node and that affect resistance characteristics. First, a pre-configured set of quantification parameter deviation thresholds is established. Each quantification parameter deviation threshold in this set corresponds one-to-one with a specific quantification parameter attribute, used to define the acceptable fluctuation range for that attribute's value. The quantification parameter deviation thresholds are set comprehensively based on the attribute's sensitivity to the final component's resistance value in a specific process, historical process control capability statistics, and the specific product's design specification tolerance requirements.

[0023] Secondly, based on the historical manufacturing parameters and the actual deviation value of each quantified parameter attribute, calculated one by one, based on the historical manufacturing parameter values, the actual deviation value is calculated as the absolute value of the difference between the current manufacturing parameter value and the historical manufacturing parameter value. Then, using a predefined set of quantified parameter deviation thresholds as a benchmark, the number of attributes whose actual quantified parameter deviation is less than or equal to the specified quantified parameter deviation threshold is counted. This number is divided by the total number of quantified parameter attributes, and the resulting ratio is defined as the quantified parameter similarity.

[0024] Specifically, quantitative parameter similarity characterizes the degree of closeness between the current settings and historical records in terms of specific process control values. The greater the quantitative parameter similarity, the closer the current manufacturing parameters are to the settings of historical successful cases in terms of key quantitative control indicators at this process node, and the higher the reproducibility of process conditions. The smaller the quantitative parameter similarity, the greater the difference between the current parameter settings and historical records in multiple quantitative control dimensions, and the lower the consistency of process execution conditions.

[0025] Finally, the type parameter similarity and quantification parameter similarity calculated above are combined to calculate the arithmetic mean of the type parameter similarity and quantification parameter similarity, and this average is set as the manufacturing parameter similarity of the first process node. The manufacturing parameter similarity of the first process node obtained in this way takes into account both the consistency of process type and numerical accuracy, providing an accurate and reliable process-level similarity measure for the calculation of overall manufacturing parameter similarity.

[0026] Furthermore, following the same comparison process described above, the historical manufacturing parameters and current manufacturing parameters are compared sequentially for the second process node, the third process node, and so on up to the last Nth process node, thereby obtaining the manufacturing parameter similarity of the second process node, the manufacturing parameter similarity of the third process node, and so on up to the Nth process node.

[0027] Finally, the node-level similarities calculated for all process nodes are summarized and statistically analyzed. Specifically, the arithmetic mean of the manufacturing parameter similarities from the first process node to the Nth process node is calculated, and this mean is set as the final manufacturing parameter similarity. This calculation process, through hierarchical and refined comparison, ensures that the similarity assessment can comprehensively and meticulously reflect the degree of similarity in manufacturing conditions from individual processes to the overall process.

[0028] Furthermore, by pre-setting a manufacturing parameter similarity threshold, historical manufacturing data of circuit components whose similarity to the current manufacturing parameters reaches or exceeds this threshold is selected. The manufacturing parameter similarity threshold is a predefined numerical limit representing the minimum similarity requirement considered sufficiently valuable in manufacturing parameter comparison. This threshold is typically set based on a combination of historical data quality, process stability requirements, and the need for prediction accuracy. The recorded resistance values ​​of the circuit components in the selected historical manufacturing data are extracted to form a set of recorded resistance values. These resistance values ​​originate from actual outputs under historical manufacturing conditions highly similar to the current manufacturing parameters. Therefore, their statistical characteristics can reliably reflect the possible distribution of circuit component resistance values ​​under the current manufacturing settings, providing a data foundation with a practical process background for subsequent prediction calculations.

[0029] Finally, statistical analysis is performed on the set of recorded resistance values ​​of the circuit elements obtained through the above screening to calculate the central tendency of this set. The central tendency is a statistical measure that characterizes the central location of the overall distribution of multiple resistance values ​​within the set of recorded resistance values; preferably, for example, the median. The calculated central tendency is then set as the resistance value of the circuit element to be predicted. Specifically, this step essentially uses the measured results of similar historical cases to statistically summarize the most representative predicted resistance value, thereby mapping abstract manufacturing parameters to specific and usable electrical characteristic parameters, providing crucial input for subsequent chip-level functional simulation.

[0030] S20: Based on the chip circuit element design data, a graph neural network is built with the elements as nodes and the circuit connection positions as edges. The digital chip is trained with the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate the predicted output timing signals. Furthermore, a virtual model capable of accurately simulating the functional behavior of a chip under the influence of its actual resistance parameters is constructed, namely a digital chip. A digital chip is an abstract representation model based on a graph neural network architecture that uses data-driven methods to represent the physical chip circuit structure and electrical behavior. It is mainly used to simulate and calculate the output timing signals that the chip should produce under a given input timing signal excitation, based on its circuit design data and predicted component resistance values, before the chip is put into physical manufacturing.

[0031] Specifically, the overall functionality of a chip depends on the electrical characteristics of its internal components and their complex interconnections. Among these, the resistance of a component directly determines the transmission delay, signal attenuation, and waveform integrity along each path in the circuit network. Any resistance deviation in any component will be transmitted and accumulated through the circuit connections, potentially causing the chip's output timing signals to deviate from design requirements. While traditional circuit simulation techniques based on physical equations can achieve high-precision simulations, their computational processes are complex and time-consuming, making it difficult to meet the timeliness requirements of rapid quality screening for large-scale combinations of process parameters in manufacturing processes.

[0032] To address the aforementioned challenges, this method employs graph neural networks to construct digital chips. Specifically, the chip circuit element design data is first transformed into graph-structured data, where each circuit element is mapped to a node in the graph, and the circuit connections between elements are mapped to edges connecting nodes. This transformation process fully preserves the topological connection information of the original circuit. Through its message-passing mechanism, the graph neural network can effectively learn and model the propagation and transformation patterns of signals in the complex network defined by nodes and edges.

[0033] During the model training phase, the resistance values ​​of circuit components predicted in previous steps are used as the initial feature vectors of the corresponding nodes and input into the network along with the test input timing signal. By training on multiple sets of historical data, the graph neural network can gradually learn and internalize the complex nonlinear mapping relationship between the component resistance distribution and the overall input-output timing response of the chip under specific circuit topology constraints. After training, the model has the ability to accurately predict the chip's output timing signal based on any given set of input signals and resistance parameters.

[0034] Specifically, this digital chip can generate a predicted output timing signal by calculating and inferring from the input circuit element resistance values ​​and the test input timing signal through its internally trained graph neural network. This predicted output timing signal comprehensively reflects all potential impacts of process fluctuations represented by the circuit element resistance values ​​on the chip's functionality. By performing subsequent refined comparison and quantitative analysis of this predicted output with the ideal standard output signal, the probability and severity of chip functional failure caused by the current manufacturing parameter set can be objectively assessed. This allows for early warning of quality risks before physical manufacturing begins and provides crucial data support and decision-making basis for adjusting and optimizing manufacturing process parameters.

[0035] Specifically, based on chip circuit element design data, a graph neural network is constructed using elements as nodes and circuit connection positions as edges. The digital chip is trained using the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals, including: Based on chip circuit element design data, a graph neural network is built with elements as nodes and circuit connection positions as edges, which is set as the digital chip architecture. Based on the chip model, historical working logs of several circuit elements are collected. Each historical working log of a circuit element includes multiple sets of chip element working data. Each set of chip element working data includes the chip element input timing signal record value and the chip element output timing signal record value. The first element node processor is trained by using the input timing signal record value of the first element as the input of the first element and the output timing signal record value of the first element as the output supervision of the first element. The process continues until the input timing signal of the Mth element is recorded as the input of the Mth element and the output timing signal of the Mth element is recorded as the output of the Mth element, thereby training the Mth element node processor. Using the predicted timing signal output of the upstream element as the input of the adjacent downstream element, the first element node processor up to the Mth element node processor is embedded into the digital chip architecture. The digital chip is trained by using the recorded timing signal input of the first element as input and the recorded timing signal output of the downstream element as supervision.

[0036] Specifically, the process of building and training a digital chip based on chip circuit element design data to generate predictive output timing signals includes four stages: architecture initialization, data preparation, hierarchical training, and system integration.

[0037] First, the architecture is initialized in the first phase. Specifically, based on the chip circuit component design data, each independent functional component in the circuit is abstracted as a node in a graph structure, and the circuit connections between components are abstracted as edges connecting the corresponding nodes. The graph neural network framework built based on the relationship between nodes and edges is defined as the digital chip architecture. This digital chip architecture clarifies the topology of the chip circuit.

[0038] Secondly, the second stage involves data preparation. Specifically, based on the chip model, historical operating logs of several circuit components generated during actual operation or testing of that chip model are collected. Each historical operating log contains multiple sets of chip component operating data. Each set of chip component operating data accurately records the actual waveform of the input timing signal received by a specific component at a specific operating moment, i.e., the recorded value of the chip component input timing signal, and the waveform of the output timing signal generated by the component under that input excitation, i.e., the recorded value of the chip component output timing signal.

[0039] Furthermore, the third stage is hierarchical training, which involves independent pre-training of the processors at each node in the digital chip architecture. Specifically, this step decomposes the complex problem of chip-level behavioral modeling into learning the independent input and output characteristics of each component. First, for the first component node in the digital chip architecture, the recorded values ​​of all chip component input timing signals and chip component output timing signals corresponding to that first component are extracted. Using the recorded values ​​of the first component input timing signals as the input of the first component and the recorded values ​​of the first component output timing signals as the output supervision of the first component, the processor of the first component node is trained to learn to simulate the signal conversion behavior of that individual first component.

[0040] Subsequently, following the same process, the second, third, and so on, up to the last Mth element node in the digital chip architecture, are trained independently using their corresponding historical input / output data to train the second, third, and so on, up to the Mth element node processor. This hierarchical training strategy refines the global problem and helps improve the modeling accuracy of each node processor for the characteristics of the element it represents.

[0041] Finally, the fourth stage of system integration is performed. The pre-trained first-node processors up to the Mth-node processors are embedded and connected according to the circuit connection relationships defined by the digital chip architecture.

[0042] Specifically, using the predicted timing signal output of upstream components as the input of adjacent downstream components, and embedding the processors of the first component node up to the Mth component node into the digital chip architecture, the digital chip is trained using the recorded timing signal input of the first component as input and the recorded timing signal output of the most downstream component as supervision, including: Based on the deviation between the recorded value of the timing signal output by the downstream component and the predicted value of the timing signal output by the downstream component, a main loss function is constructed. Based on the deviation between the predicted value of the output timing signal of the upstream component and the recorded value of the input timing signal of the downstream component, several sub-loss functions are constructed. When the main loss function meets the convergence condition, and more than a preset proportion of the sub-loss functions meet the convergence condition, the digital chip is stored.

[0043] First, a master loss function is constructed. This master loss function is calculated based on the deviation between the predicted output timing signal of the downstream component of the digital chip and the actual recorded output timing signal of the downstream component in the historical work log. The master loss function measures the difference between the overall output of the digital chip and the expected output, and its optimization objective is to make the final output prediction of the digital chip as close as possible to the observed behavior of the actual chip.

[0044] Simultaneously, several sub-loss functions are constructed. Each sub-loss function corresponds to a signal transmission path within the digital chip. Specifically, for each pair of directly connected upstream and downstream components, the deviation between the predicted value of the upstream component's output timing signal generated by the upstream component node processor and the recorded value of the downstream component's input timing signal actually input to that downstream component, as recorded in the historical work log, is calculated. A sub-loss function is constructed based on this deviation. All such deviations together constitute a set of sub-loss functions. The optimization objective of the sub-loss functions is to constrain the signal transmission relationships between the node processors within the digital chip, ensuring they align with the historically observed actual signal flow, thereby ensuring the rationality of internal state transmission and mitigating the accumulation of errors along the signal transmission path.

[0045] The pre-trained first-element node processors up to the Mth-element node processors are embedded and connected according to the circuit connection relationships defined by the digital chip architecture. In this integrated model, the predicted output timing signal values ​​of the upstream element node processors are used as inputs to their adjacent downstream element node processors. Subsequently, end-to-end training is performed using complete chip-level historical data. Specifically, the digital chip is trained using the recorded input timing signal values ​​of the first element as input and the recorded output timing signal values ​​of the last downstream element as supervision.

[0046] During training, the overall connection and integration parameters of the digital chip are optimized, and the embedded node processors are fine-tuned to better simulate the propagation and accumulation effects of signals in the complete circuit network when working collaboratively. Ultimately, this enables the digital chip to generate accurate predicted output timing signals. This step-by-step training method, by first learning local characteristics and then optimizing global collaboration, helps improve the overall accuracy of the model. It is crucial to focus on and correct for potential error accumulation caused by sub-processor coupling during end-to-end training.

[0047] Specifically, the training process iterates continuously, simultaneously optimizing the main loss function and all sub-loss functions. When the main loss function meets the convergence condition, and a predetermined proportion of sub-loss functions also meet the convergence condition, it indicates that the overall output of the digital chip has been sufficiently optimized. The convergence condition for the main loss function is set based on the overall prediction accuracy requirements; for example, the decrease in the main loss function value is less than one ten-thousandth over 10 consecutive training periods. The convergence condition for a predetermined proportion of sub-loss functions meeting the convergence condition (e.g., 80%) is set based on the model's internal consistency requirements. Its convergence condition is that the decrease in the sub-loss function value is less than one thousandth over 5 consecutive training periods, set based on the internal signal transmission error tolerance.

[0048] The digital chip is considered to have completed training only when both of the above conditions are met, and its model parameters and architecture are stored.

[0049] S30: Compare the predicted output timing signal and the test output timing signal to obtain the signal timing deviation coefficient; Furthermore, the predicted output timing signal obtained in the aforementioned steps is compared with the standard test output timing signal. The standard test output timing signal is a set of idealized output waveform data predefined according to the chip design specifications and functional requirements. It represents the correct response that the chip should make to the standard test input timing signal under ideal conditions without any manufacturing deviations. It is usually obtained through high-precision simulation or actual measurement with gold samples.

[0050] The signal timing deviation coefficient is a comprehensive measure of the difference between the predicted output timing signal and the standard test output timing signal. It is a dimensionless quantitative evaluation metric used to characterize the degree to which process fluctuations, reflected by the predicted resistor value, actually cause the chip's functional output to deviate from the ideal state. A larger signal timing deviation coefficient indicates a greater difference between the predicted output and the ideal output, meaning a higher risk of chip functional failure due to current manufacturing parameters.

[0051] S40: When the timing deviation coefficient of the signal is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end.

[0052] Finally, when the calculated signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end.

[0053] Specifically, when the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end, including: When the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, several returned circuit element manufacturing parameters are obtained. When the manufacturing parameters of the returned circuit components are greater than or equal to the quantity threshold, the manufacturing parameters of the returned circuit components are subjected to collective intelligent optimization processing with the signal timing deviation coefficient as the fitness function to obtain recommended manufacturing parameters of the circuit components. The recommended circuit component manufacturing parameters are added to the chip quality anomaly signal and returned to the chip manufacturing end.

[0054] First, when the calculated signal timing deviation coefficient is greater than or equal to a preset deviation coefficient threshold, several returned circuit component manufacturing parameters are obtained. The deviation coefficient threshold is a pre-set numerical limit, determined based on chip product yield requirements, critical timing path tolerances, and process control capabilities. The returned circuit component manufacturing parameters are the set of manufacturing parameters corresponding to all cases triggering quality anomaly warnings within historical inspection cycles, representing a series of process parameter combinations identified as potentially causing chip performance defects. Obtaining these returned circuit component manufacturing parameters essentially involves systematically collecting and archiving historical process deviation data, thereby constructing a statistically significant learning sample library for subsequent data-driven process parameter optimization analysis.

[0055] Secondly, when the number of returned circuit component manufacturing parameters reaches or exceeds a preset threshold, it indicates that a sample base for swarm analysis is available. At this point, an optimization analysis process is initiated: using the signal timing deviation coefficient as a fitness function to measure the quality of parameter combinations, a lower value indicates that the predicted chip performance is closer to the ideal state; and applying a swarm optimization algorithm to the accumulated returned circuit component manufacturing parameters, with the fitness function as the objective. Specifically, this swarm optimization algorithm, such as a genetic algorithm or particle swarm optimization algorithm, treats the accumulated abnormal parameter set as an initial population. By simulating the intelligent behaviors of population evolution or group cooperation in nature, such as selection, crossover, mutation, or particle position updates, iteratively generates new candidate solutions for parameter combinations. In each iteration, the newly generated parameter combinations are rapidly simulated using a pre-trained digital chip model, and their corresponding signal timing deviation coefficient is calculated as a fitness evaluation. This swarm optimization algorithm continuously retains and optimizes parameter combinations that produce lower fitness values, i.e., smaller signal timing deviation coefficients. After multiple rounds of iterative search, a new combination of manufacturing parameters that significantly reduces the fitness function value is finally output within the historical abnormal parameter space. This combination is the recommended manufacturing parameters for circuit components.

[0056] Finally, the recommended circuit component manufacturing parameters obtained from the analysis are packaged together with the basic abnormal alarm information as additional optimization suggestions to form a chip quality abnormality signal, which is returned to the chip manufacturing end. This chip quality abnormality signal can provide manufacturing engineers with a clear direction for process optimization, which helps to quickly locate the root cause of the problem and implement improvements.

[0057] In summary, the embodiments of this application have at least the following technical effects: Compared to existing technologies, this application shifts the chip quality assessment point from the testing stage after physical manufacturing is completed to the manufacturing parameter setting stage. By establishing a predictive model from manufacturing parameters to component resistance values ​​and combining it with circuit design data to construct a digital chip with simulated behavior, it achieves virtualized prediction of chip functional pass rate before material input. First, this invention can identify and warn of quality risks caused by improper process parameter settings in advance, thereby effectively avoiding the material and time losses caused by traditional post-testing. Simultaneously, by accumulating abnormal case data and using a crowdsourcing optimization algorithm to generate process parameter optimization suggestions, this invention forms a closed-loop feedback from quality testing to process optimization, improving the control accuracy and response speed of the manufacturing process. It realizes a transformation from passive testing to proactive prevention, and from single alarms to optimization guidance, providing an efficient and reliable solution for quality control and process optimization in integrated circuit manufacturing.

[0058] Example 2, as Figure 2As shown, based on the same inventive concept as the chip quality anomaly analysis method that integrates timing resistance data provided in Embodiment 1, this embodiment of the invention also provides a chip quality anomaly analysis system that integrates timing resistance data, including: The parameter acquisition and prediction module 11 is used to obtain the manufacturing parameters of the circuit components, perform resistance prediction, and obtain the resistance value of the circuit components. The graph network construction and training module 12 is used to build a graph neural network based on the chip circuit element design data, with the elements as nodes and the circuit connection positions as edges. The digital chip is trained with the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals. Timing deviation analysis module 13 is used to compare the predicted output timing signal and the test output timing signal to obtain the signal timing deviation coefficient; The quality judgment and feedback module 14 is used to return a chip quality abnormality signal to the chip manufacturing end when the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold.

[0059] Specifically, the parameter acquisition and prediction module 11 is used for: Obtain circuit component manufacturing parameters, predict resistance, and obtain circuit component resistance values, including: From the manufacturing parameters of the circuit element, extract the circuit element model and manufacturing process data, and collect historical manufacturing data of multiple sets of circuit elements of the same model and the same process. Each set of historical manufacturing data of the multiple sets of circuit elements includes historical manufacturing parameters of the circuit element and recorded resistance value of the circuit element. Traverse the historical manufacturing data of the multiple sets of circuit elements, and filter the set of circuit element resistance values ​​in which the similarity between the historical manufacturing parameters of the circuit elements and the manufacturing parameters of the circuit elements is greater than or equal to the manufacturing parameter similarity threshold. Calculate the set of values ​​of the resistance values ​​recorded by the circuit element, and set them as the resistance values ​​of the circuit element.

[0060] Specifically, the manufacturing parameter similarity calculation process includes: From the historical manufacturing parameters of the circuit elements, extract the historical manufacturing parameters of the first process node up to the historical manufacturing parameters of the Nth process node; From the manufacturing parameters of the circuit elements, extract the manufacturing parameters of the first process node up to the manufacturing parameters of the Nth process node; By comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained. The similarity of the manufacturing parameters of the Nth process node is obtained by comparing the historical manufacturing parameters of the Nth process node with the manufacturing parameters of the Nth process node. The average value of the manufacturing parameter similarity of the first process node up to the manufacturing parameter similarity of the Nth process node is set as the manufacturing parameter similarity.

[0061] Specifically, by comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained, including: The intersection-union comparison (IUCN) of the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node are statistically analyzed to obtain the type parameter similarity. Obtain a predefined set of quantization parameter deviation thresholds that correspond one-to-one with the quantization parameter attribute set; Based on the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node, and using the set of quantitative parameter deviation thresholds as a benchmark, the proportion of quantitative parameter deviations that are less than or equal to the quantitative parameter deviation thresholds is statistically analyzed to obtain the quantitative parameter similarity. Calculate the average of the type parameter similarity and the quantization parameter similarity, and set it as the manufacturing parameter similarity of the first process node.

[0062] Specifically, the graph network construction and training module 12 is used for: Based on chip circuit element design data, a graph neural network is constructed with elements as nodes and circuit connection positions as edges. The digital chip is trained using the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals, including: Based on chip circuit element design data, a graph neural network is built with elements as nodes and circuit connection positions as edges, which is set as the digital chip architecture. Based on the chip model, historical working logs of several circuit elements are collected. Each historical working log of a circuit element includes multiple sets of chip element working data. Each set of chip element working data includes the chip element input timing signal record value and the chip element output timing signal record value. The first element node processor is trained by using the input timing signal record value of the first element as the input of the first element and the output timing signal record value of the first element as the output supervision of the first element. The process continues until the input timing signal of the Mth element is recorded as the input of the Mth element and the output timing signal of the Mth element is recorded as the output of the Mth element, thereby training the Mth element node processor. Using the predicted timing signal output of the upstream element as the input of the adjacent downstream element, the first element node processor up to the Mth element node processor is embedded into the digital chip architecture. The digital chip is trained by using the recorded timing signal input of the first element as input and the recorded timing signal output of the downstream element as supervision.

[0063] Specifically, using the predicted timing signal output of upstream components as the input of adjacent downstream components, and embedding the processors of the first component node up to the Mth component node into the digital chip architecture, the digital chip is trained using the recorded timing signal input of the first component as input and the recorded timing signal output of the most downstream component as supervision, including: Based on the deviation between the recorded value of the timing signal output by the downstream component and the predicted value of the timing signal output by the downstream component, a main loss function is constructed. Based on the deviation between the predicted value of the output timing signal of the upstream component and the recorded value of the input timing signal of the downstream component, several sub-loss functions are constructed. When the main loss function meets the convergence condition, and more than a preset proportion of the sub-loss functions meet the convergence condition, the digital chip is stored.

[0064] Specifically, the timing deviation analysis module 13 is used for: By comparing the predicted output timing signal and the test output timing signal, the signal timing deviation coefficient is obtained.

[0065] Specifically, the quality judgment and feedback module 14 is used for: When the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end, including: When the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, several returned circuit element manufacturing parameters are obtained. When the manufacturing parameters of the returned circuit components are greater than or equal to the quantity threshold, the manufacturing parameters of the returned circuit components are subjected to collective intelligent optimization processing with the signal timing deviation coefficient as the fitness function to obtain recommended manufacturing parameters of the circuit components. The recommended circuit component manufacturing parameters are added to the chip quality anomaly signal and returned to the chip manufacturing end.

Claims

1. A chip quality anomaly analysis method integrating timing resistance data, characterized in that, include: Obtain the manufacturing parameters of the circuit components, predict the resistance, and obtain the resistance value of the circuit components; Based on the design data of chip circuit components, a graph neural network is built with components as nodes and circuit connection positions as edges. The resistance values ​​of the circuit components and the test input timing signals are used as node inputs to train the digital chip and generate predictive output timing signals. By comparing the predicted output timing signal and the test output timing signal, the signal timing deviation coefficient is obtained; When the timing deviation coefficient of the signal is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end.

2. The method as described in claim 1, characterized in that, Obtain circuit component manufacturing parameters, predict resistance, and obtain circuit component resistance values, including: From the manufacturing parameters of the circuit element, extract the circuit element model and manufacturing process data, and collect historical manufacturing data of multiple sets of circuit elements of the same model and the same process. Each set of historical manufacturing data of the multiple sets of circuit elements includes historical manufacturing parameters of the circuit element and recorded resistance value of the circuit element. Traverse the historical manufacturing data of the multiple sets of circuit elements, and filter the set of circuit element resistance values ​​in which the similarity between the historical manufacturing parameters of the circuit elements and the manufacturing parameters of the circuit elements is greater than or equal to the manufacturing parameter similarity threshold. Calculate the set of values ​​of the resistance values ​​recorded by the circuit element, and set them as the resistance values ​​of the circuit element.

3. The method as described in claim 2, characterized in that, The manufacturing parameter similarity calculation process includes: From the historical manufacturing parameters of the circuit elements, extract the historical manufacturing parameters of the first process node up to the historical manufacturing parameters of the Nth process node; From the manufacturing parameters of the circuit elements, extract the manufacturing parameters of the first process node up to the manufacturing parameters of the Nth process node; By comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained. The similarity of the manufacturing parameters of the Nth process node is obtained by comparing the historical manufacturing parameters of the Nth process node with the manufacturing parameters of the Nth process node. The average value of the manufacturing parameter similarity of the first process node up to the manufacturing parameter similarity of the Nth process node is set as the manufacturing parameter similarity.

4. The method as described in claim 3, characterized in that, By comparing the historical manufacturing parameters of the first process node with the manufacturing parameters of the first process node, the similarity of the manufacturing parameters of the first process node is obtained, including: The intersection-union comparison (IUCN) of the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node are statistically analyzed to obtain the type parameter similarity. Obtain a predefined set of quantization parameter deviation thresholds that correspond one-to-one with the quantization parameter attribute set; Based on the historical manufacturing parameters of the first process node and the manufacturing parameters of the first process node, and using the set of quantitative parameter deviation thresholds as a benchmark, the proportion of quantitative parameter deviations that are less than or equal to the quantitative parameter deviation thresholds is statistically analyzed to obtain the quantitative parameter similarity. Calculate the average of the type parameter similarity and the quantization parameter similarity, and set it as the manufacturing parameter similarity of the first process node.

5. The method as described in claim 1, characterized in that, Based on chip circuit element design data, a graph neural network is constructed with elements as nodes and circuit connection positions as edges. The digital chip is trained using the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals, including: Based on chip circuit element design data, a graph neural network is built with elements as nodes and circuit connection positions as edges, which is set as the digital chip architecture. Based on the chip model, historical working logs of several circuit elements are collected. Each historical working log of a circuit element includes multiple sets of chip element working data. Each set of chip element working data includes the chip element input timing signal record value and the chip element output timing signal record value. The first element node processor is trained by using the input timing signal record value of the first element as the input of the first element and the output timing signal record value of the first element as the output supervision of the first element. The process continues until the input timing signal of the Mth element is recorded as the input of the Mth element and the output timing signal of the Mth element is recorded as the output of the Mth element, thereby training the Mth element node processor. Using the predicted timing signal output of the upstream element as the input of the adjacent downstream element, the first element node processor up to the Mth element node processor is embedded into the digital chip architecture. The digital chip is trained by using the recorded timing signal input of the first element as input and the recorded timing signal output of the downstream element as supervision.

6. The method as described in claim 5, characterized in that, Using the predicted timing signal output of upstream components as the input of adjacent downstream components, and embedding the first component node processor up to the Mth component node processor into the digital chip architecture, the digital chip is trained using the recorded timing signal input of the first component as input and the recorded timing signal output of the most downstream component as supervision. This includes: Based on the deviation between the recorded value of the timing signal output by the downstream component and the predicted value of the timing signal output by the downstream component, a main loss function is constructed. Based on the deviation between the predicted value of the output timing signal of the upstream component and the recorded value of the input timing signal of the downstream component, several sub-loss functions are constructed. When the main loss function meets the convergence condition, and more than a preset proportion of the sub-loss functions meet the convergence condition, the digital chip is stored.

7. The method as described in claim 1, characterized in that, When the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, a chip quality abnormality signal is returned to the chip manufacturing end, including: When the signal timing deviation coefficient is greater than or equal to the deviation coefficient threshold, several returned circuit element manufacturing parameters are obtained. When the manufacturing parameters of the returned circuit components are greater than or equal to the quantity threshold, the manufacturing parameters of the returned circuit components are subjected to collective intelligent optimization processing with the signal timing deviation coefficient as the fitness function to obtain recommended manufacturing parameters of the circuit components. The recommended circuit component manufacturing parameters are added to the chip quality anomaly signal and returned to the chip manufacturing end.

8. A chip quality anomaly analysis system integrating timing resistance data, characterized in that, A chip quality anomaly analysis method for performing the fused timing resistance data as described in any one of claims 1-7, comprising: The parameter acquisition and prediction module is used to obtain the manufacturing parameters of circuit components, predict the resistance, and obtain the resistance value of the circuit components. The graph network construction and training module is used to build a graph neural network based on chip circuit element design data, with elements as nodes and circuit connection positions as edges. The digital chip is trained using the resistance values ​​of the circuit elements and the test input timing signals as node inputs to generate predicted output timing signals. The timing deviation analysis module is used to compare the predicted output timing signal and the test output timing signal to obtain the signal timing deviation coefficient; The quality judgment and feedback module is used to return a chip quality abnormality signal to the chip manufacturing end when the timing deviation coefficient of the signal is greater than or equal to the deviation coefficient threshold.

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