A reference circuit with high PSRR and its control method

Abstract

A high PSRR reference circuit and its control method are disclosed. The circuit includes an external power input terminal VIN, a circuit output terminal Vbg, a control terminal, a bias module, a multiplexer, a low dropout linear regulator LDO, and a reference module. During a predetermined power-on startup period, the reference module does not generate a reference voltage Vbg, but only outputs a default control signal to the multiplexer. The multiplexer outputs a fixed bias voltage to the LDO, and the LDO outputs an internal power signal VCCA with a first PSRR value. After power-on, the reference module enters the working state and outputs the reference voltage Vbg. Then, the reference module outputs a signal opposite to the default control signal, causing the multiplexer's output signal VR to switch to the reference voltage Vbg. The LDO then outputs the internal power signal VCCA with a second PSRR value. The second PSRR value is higher than the first PSRR value. Therefore, this invention improves the PSRR of the reference voltage Vbg through a self-loop of the reference voltage Vbg and the internal power signal VCCA.

Description

Technical Field

[0001] This invention belongs to the field of power management chip technology, and relates to a reference circuit with high power supply rejection ratio (PSRR) and its control method. Background Technology

[0002] Please see Figure 1 , Figure 1 The diagram shows a traditional bandgap reference circuit. Figure 1 As shown, the circuit may include a startup circuit module, a first-stage reference module, a pre-regulated low-dropout linear regulator, and a second-stage reference module. The startup circuit module outputs a first startup voltage based on the input voltage and an enable signal. The first-stage reference module outputs a first-stage reference voltage and a second startup voltage based on the input voltage, the first startup voltage, the enable signal, and a first voltage signal. The pre-regulated low-dropout linear regulator outputs a second voltage signal based on the input voltage, the first-stage reference voltage, and the enable signal. The second-stage reference module outputs the first voltage signal and the second-stage reference voltage based on the second voltage signal, the second startup voltage, and the enable signal. The accuracy of the first-stage reference voltage is less than the accuracy of the second-stage reference voltage.

[0003] The startup circuit module includes a startup main circuit for generating an initial startup current based on the input voltage and the enable signal to establish the first startup voltage; a clamping circuit for clamping the first startup voltage; and a first enable control unit for controlling the startup circuit module to turn on or off in response to a third voltage signal; wherein the third voltage signal is out of phase with the enable signal.

[0004] The first-level reference module may include a second enable control unit and a third enable control unit, used to control the first-level reference module to turn on or off according to the enable signal; a first start control unit, used to respond to the first start voltage, conduct start current when the first-level reference module is turned on, and control the start current to exit after the circuit stabilizes; a first reference circuit of the current module architecture, used to respond to the control of the second enable control unit, the third enable control unit and the first start control unit, and output a first-level reference voltage based on the input voltage; and a start circuit of the second reference module, used to respond to the control of the second enable control unit, the third enable control unit and the first start control unit, and output a second start voltage based on the input voltage and the first voltage signal.

[0005] The pre-regulated low-dropout linear regulator may include an error amplifier; the enable terminal of the error amplifier receives the enable signal, the power supply terminal receives the input voltage, the negative input terminal is connected to the output terminal through a third resistor, the output terminal outputs the second voltage signal, the negative input terminal is also grounded through a fourth resistor, and the positive input terminal receives the first-stage reference voltage.

[0006] The second-stage reference module may include a second startup control unit, used to respond to the second startup voltage, conduct startup current when the circuit starts up, and control the startup current to exit after the circuit stabilizes; a fourth enable control unit, used to respond to the enable signal, and control the opening and closing of the second-stage reference module; a two-stage operational amplifier circuit, used to respond to the control of the fourth enable control unit and the second startup control unit, and clamp the voltage of the first and second terminals based on the second voltage signal; a compensation unit, used to improve the stability of the two-stage operational amplifier circuit; and a second reference circuit of a voltage module architecture, used to respond to the control of the fourth enable control unit and the second startup control unit, and output the first voltage signal and the second-stage reference voltage based on the second voltage signal.

[0007] The control principle of the above circuit is as follows: After the bandgap reference circuit is started, an initial current is injected into the first-stage reference module through the start-up circuit module, causing the first-stage reference module to get out of the zero state; the first-stage reference module generates a first-stage reference voltage, which serves as the input reference voltage of the pre-regulated low-dropout linear regulator; the first-stage reference module provides a second start-up voltage for the second-stage reference module to get out of the zero state; the pre-regulated low-dropout linear regulator generates a second voltage signal that can suppress power supply noise based on the first-stage reference voltage; the second voltage signal powers the second-stage reference module, causing the second-stage reference module to generate a second-stage reference voltage; wherein, the accuracy of the first-stage reference voltage is less than that of the second-stage reference voltage; that is, the control of the bandgap reference circuit generates an internal power supply through a low-precision reference, and the internal power supply generates a high-precision reference voltage.

[0008] However, the above-mentioned bandgap reference circuit and its control method have the following shortcomings:

[0009] ① The second voltage signal has limited ability to suppress power supply noise, partly due to the accuracy of the first reference voltage;

[0010] ② The entire circuit includes a startup circuit, two-stage reference circuits, and an LDO module. The circuit is numerous and complex, and the layout area is large. Summary of the Invention

[0011] To address the aforementioned technical problems, this invention proposes a high PSRR reference circuit with a technical solution that exhibits high noise suppression capability for power supplies.

[0012] To achieve the above objectives, the technical solution of the present invention is as follows:

[0013] A high PSRR reference circuit includes an external power input terminal VIN, a circuit output terminal Vbg, and a control terminal; it also includes a bias module, a multiplexer, a low dropout linear regulator LDO, and a reference module; wherein,

[0014] The input terminal of the bias module is connected to the external power input terminal VIN, and the output terminal is connected to the input terminal of the multiplexer; it is used to generate a fixed bias voltage lower than the voltage of the external power input terminal VIN.

[0015] The input terminal of the multiplexer receives the fixed bias voltage, the reference voltage Vbg of the reference module, and a control signal; based on the control signal, the multiplexer selects either the bias voltage or the reference voltage Vbg as its input signal, and generates an output signal VR; the output signal VR serves as the input reference voltage of the low dropout linear regulator LDO; wherein, the bias voltage is less than the voltage value of the reference voltage Vbg;

[0016] The low-dropout linear regulator (LDO) is powered by the external power input terminal VIN. Based on the output signal VR, it generates an internal power signal VCCA that is lower than the external power input terminal VIN, which is used to power the reference module. The output signal VR serves as the input reference voltage of the LDO, and the internal power signal VCCA is higher than the reference voltage. The PSRR of the voltage VCCA is positively correlated with the PSRR of the output signal VR.

[0017] The reference module, based on the internal power signal VCCA, outputs the control signal and the reference signal Vbg. During the startup of the reference module, it does not output the reference voltage Vbg, but only outputs the default control signal, making the output signal VR of the multiplexer the bias voltage. When the reference module completes startup, operates, and outputs the reference voltage Vbg, it outputs a signal opposite to the default control signal, making the output signal VR of the multiplexer the reference voltage Vbg. After the reference module starts operating, the state of the signal opposite to the default control signal will not change during normal operation of the reference module.

[0018] Furthermore, the bias module includes a resistor R1 and an NMOS transistor M1. The resistor R1 is connected to the external power input terminal VIN and the drain of the NMOS transistor M1 for current limiting. The gate and drain of the NMOS transistor M1 are connected and are always in the saturation region. The bias voltage is equal to the gate voltage of the NMOS transistor M1.

[0019] Further, the multiplexer includes an inverter, an NMOS transistor M3, and an NMOS transistor M4. The input of the inverter is connected to the control signal and the gate of the NMOS transistor M4, and the output of the inverter is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M3 is connected to the bias voltage, and the source of the NMOS transistor M4 is connected to the reference voltage Vbg. The drains of the NMOS transistors M3 and M4 are connected to output the output signal VR. The gates of the two NMOS transistors are respectively connected to the control signal and the inverted signal of the control signal by the inverter. If the gate of the NMOS transistor M3 is connected to a low-level signal, the NMOS transistor M3 is turned off and the NMOS transistor M4 is turned on; if the gate of the NMOS transistor M4 is connected to a low-level signal, the NMOS transistor M4 is turned off and the NMOS transistor M3 is turned on.

[0020] Furthermore, the multiplexer includes an inverter, a first transmission gate, and a second transmission gate; the input of the inverter is connected to the control signal and the switch of the second transmission gate, the output of the inverter is connected to the switch of the first transmission gate, the input of the first transmission gate is connected to the bias voltage, and the input of the second transmission gate is connected to the reference voltage Vbg; the two transmission gates are respectively connected to the control signal and the signal inverted by the inverter. If the first transmission gate is connected to a low-level signal, the first transmission gate is turned off and the second transmission gate is turned on; if the second transmission gate is connected to a low-level signal, the second transmission gate is turned off and the first transmission gate is turned on.

[0021] To achieve the above objectives, another technical solution of the present invention is as follows:

[0022] A control method for a reference circuit employing the aforementioned high PSRR includes the following steps:

[0023] Step S1: The bias module, multiplexer, and low-dropout linear regulator (LDO) are powered on by connecting to the external power input terminal VIN. The bias module generates a fixed bias voltage lower than the voltage at the external power input terminal VIN. The LDO receives the output signal VR from the multiplexer and outputs the internal power signal VCCA to the reference module. When the reference module does not generate the reference voltage Vbg during a predetermined power-on period, it only outputs the default control signal to the multiplexer. The multiplexer outputs the fixed bias voltage to the LDO, and the LDO outputs the internal power signal VCCA with a first PSRR value.

[0024] Step S2: After the reference module completes power-on startup, enters the working state and outputs the reference voltage Vbg, the reference module outputs a signal opposite to the default control signal, causing the output signal VR of the multiplexer to switch to the reference voltage Vbg. The low dropout linear regulator LDO outputs the internal power supply signal VCCA with a second PSRR value. The PSRR of the internal power supply signal VCCA increases. Since the internal power supply signal VCCA serves as the power supply signal for the reference module, the PSRR of the reference voltage increases. The reference voltage Vbg and the internal power supply signal VCCA form a self-loop, creating a virtuous cycle of the internal power supply VCCA with a high power supply rejection ratio and the reference voltage with a high power supply rejection ratio, thus obtaining a reference voltage with a high power supply rejection ratio. The second PSRR value is higher than the first PSRR value.

[0025] As can be seen from the above technical solution, the high PSRR reference circuit proposed in this invention has the following beneficial effects:

[0026] ① Improve the PSRR of the reference voltage through the self-circulation of the reference voltage and the internal power supply;

[0027] ② Improve the PSRR of the internal power supply, and further improve the PSRR of the reference voltage;

[0028] ③ After starting with the reference voltage, the power consumption is low because there are relatively few circuit modules.

[0029] ④ The number of base modules has been reduced, resulting in a smaller layout area. Attached Figure Description

[0030] Figure 1 The diagram shown is a schematic of a traditional bandgap reference circuit.

[0031] Figure 2 The diagram shown is a schematic of the high PSRR reference circuit of the present invention.

[0032] Figure 3 The diagram shown is a schematic of the bias module in an embodiment of the present invention.

[0033] Figure 4 The diagram shown is a preferred embodiment of the high PSRR reference circuit of the present invention.

[0034] Figure 5 The diagram shown is a schematic diagram of another preferred embodiment of the high PSRR reference circuit of the present invention.

[0035] Figure 6 The diagram shown is a schematic representation of the power supply rejection ratio effect of the present invention. Detailed Implementation

[0036] The following is in conjunction with the appendix Figure 2-6 The specific embodiments of the present invention will be described in further detail below.

[0037] Please refer to Figure 2 , Figure 2 The diagram shown is a schematic representation of the high PSRR reference circuit of the present invention. Figure 2 As shown, the high PSRR reference circuit may include an external power input terminal VIN, a circuit output terminal Vbg, and a control terminal; it may also include a bias module, a multiplexer, a low dropout linear regulator LDO, and a reference module, etc.

[0038] In an embodiment of the present invention, the input terminal of the bias module is connected to the external power input terminal VIN, and the output terminal is connected to the input terminal of the multiplexer; it is used to generate a fixed bias voltage lower than the voltage of the external power input terminal VIN.

[0039] The input of the multiplexer receives the fixed bias voltage, the reference voltage Vbg of the reference module, and a control signal. Based on the control signal, the multiplexer selects either the bias voltage or the reference voltage Vbg as its input signal, and generates an output signal VR. The output signal VR serves as the input reference voltage for the low-dropout linear regulator (LDO). The bias voltage is less than the reference voltage Vbg.

[0040] The reference module, based on the internal power signal VCCA, outputs the control signal and the reference signal Vbg. During the startup phase, the reference module does not output the reference voltage Vbg, but only outputs the default control signal, making the multiplexer's output signal VR the bias voltage. Once the reference module has finished startup, is operating, and outputs the reference voltage Vbg, it outputs a signal opposite to the default control signal, making the multiplexer's output signal VR the reference voltage Vbg. After the reference module begins operating, the state of the signal opposite to the default control signal remains unchanged during normal operation.

[0041] Please refer to Figure 3 , Figure 3 The diagram shows a bias module in an embodiment of the present invention. The bias module includes a resistor R1 and an NMOS transistor M1. The resistor R1 is connected to the external power input terminal VIN and the drain of the NMOS transistor M1 for current limiting. The gate and drain of the NMOS transistor M1 are connected and are always in the saturation region. The bias voltage is equal to the gate voltage of the NMOS transistor M1.

[0042] The low-dropout linear regulator (LDO) is powered by the external power input terminal VIN. Based on the output signal VR, it generates an internal power signal VCCA that is lower than the external power input terminal VIN, which is used to power the reference module. The output signal VR serves as the input reference voltage of the LDO, and the LDO generates a voltage VCCA that is higher than the reference voltage. The PSRR of the voltage VCCA is positively correlated with the PSRR of the output signal VR.

[0043] Please see Figure 4 , Figure 4 The diagram shown is a preferred embodiment of the high PSRR reference circuit of the present invention. Figure 4As shown, the multiplexer in this high PSRR reference circuit may include an inverter, an NMOS transistor M3, and an NMOS transistor M4. The input of the inverter is connected to the control signal and the gate of the NMOS transistor M4. The output of the inverter is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M3 is connected to the bias voltage, and the source of the NMOS transistor M4 is connected to the reference voltage Vbg. The drains of the NMOS transistors M3 and M4 are connected to output the output signal VR. The gates of the two NMOS transistors are respectively connected to the control signal and the inverted signal of the control signal by the inverter. If the gate of the NMOS transistor M3 is connected to a low-level signal, the NMOS transistor M3 is turned off and the NMOS transistor M4 is turned on. If the gate of the NMOS transistor M4 is connected to a low-level signal, the NMOS transistor M4 is turned off and the NMOS transistor M3 is turned on.

[0044] Please see Figure 5 , Figure 5 The diagram shown is a schematic representation of another preferred embodiment of the high PSRR reference circuit of the present invention. Figure 5 As shown, the multiplexer in this high PSRR reference circuit may include an inverter, a first transmission gate, and a second transmission gate. The input of the inverter is connected to the control signal and the switch of the second transmission gate, the output of the inverter is connected to the switch of the first transmission gate, the input of the first transmission gate is connected to the bias voltage, and the input of the second transmission gate is connected to the reference voltage Vbg. The two transmission gates are respectively connected to the control signal and the signal inverted by the inverter. If the first transmission gate is connected to a low-level signal, the first transmission gate is turned off and the second transmission gate is turned on; if the second transmission gate is connected to a low-level signal, the second transmission gate is turned off and the first transmission gate is turned on.

[0045] In an embodiment of the present invention, the control method of the high PSRR reference circuit described above includes the following steps:

[0046] Step S1: The bias module, multiplexer, and low-dropout linear regulator (LDO) are powered on by connecting to the external power input terminal VIN. The bias module generates a fixed bias voltage lower than the voltage at the external power input terminal VIN. The LDO receives the output signal VR from the multiplexer and outputs the internal power signal VCCA to the reference module. When the reference module does not generate the reference voltage Vbg during a predetermined power-on period, it only outputs the default control signal to the multiplexer. The multiplexer outputs the fixed bias voltage to the LDO, and the LDO outputs the internal power signal VCCA with a first PSRR value.

[0047] Step S2: After the reference module completes power-on startup, enters the working state and outputs the reference voltage Vbg, the reference module outputs a signal opposite to the default control signal, causing the output signal VR of the multiplexer to switch to the reference voltage Vbg. The low dropout linear regulator LDO outputs the internal power supply signal VCCA with a second PSRR value. The PSRR of the internal power supply signal VCCA increases. Since the internal power supply signal VCCA serves as the power supply signal for the reference module, the PSRR of the reference voltage increases. The reference voltage Vbg and the internal power supply signal VCCA form a self-loop, creating a virtuous cycle of the internal power supply VCCA with a high power supply rejection ratio and the reference voltage with a high power supply rejection ratio, thus obtaining a reference voltage with a high voltage source rejection ratio. The second PSRR value is higher than the first PSRR value.

[0048] In other words, the control principle of the above circuit is as follows:

[0049] By switching the output signal VR of the multiplexer from a bias voltage to a high PSRR reference voltage Vbg, the internal power supply signal VCCA is positively correlated with the high PSRR reference voltage Vbg, and the high PSRR reference voltage Vbg is positively correlated with the internal power supply signal VCCA. In this way, the high PSRR internal power supply signal and the high PSRR reference voltage Vbg promote each other, forming a virtuous cycle, and ultimately generating a high PSRR reference voltage Vbg.

[0050] Please refer to Figure 6 , Figure 6 The diagram shown is a schematic representation of the power supply rejection ratio in an embodiment of the present invention. Figure 6As shown, the vertical axis represents the PSRR value in dB, and the horizontal axis represents the frequency in Hz. A higher PSRR value indicates a stronger ability to suppress power supply noise. The circuit commonly uses a frequency of 1kHz. In this invention, the PSRR of the reference voltage Vbg is 128 dB at 1kHz, demonstrating a strong ability to suppress external power supply noise.

[0051] In other words, after the reference module is working normally, the reference voltage Vbg and the internal power signal VCCA form a self-loop, forming a virtuous cycle of a high power supply rejection ratio (PSRR) internal power supply and a high PSRR reference voltage, thereby achieving a high voltage rejection ratio reference voltage.

[0052] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

Claims

1. A high PSRR reference circuit, comprising an external power input terminal VIN, a circuit output terminal Vbg, and a control terminal; characterized in that, It also includes a bias module, a multiplexer, a low-dropout linear regulator (LDO), and a reference module; among which, The input terminal of the bias module is connected to the external power input terminal VIN, and the output terminal is connected to the input terminal of the multiplexer; it is used to generate a fixed bias voltage lower than the voltage of the external power input terminal VIN. The input terminal of the multiplexer receives the fixed bias voltage, the reference voltage Vbg of the reference module, and a control signal; based on the control signal, the multiplexer selects either the bias voltage or the reference voltage Vbg as its input signal, and generates an output signal VR; the output signal VR serves as the input reference voltage of the low dropout linear regulator LDO; wherein, the bias voltage is less than the voltage value of the reference voltage Vbg; The low-dropout linear regulator (LDO) is powered by the external power input terminal VIN. Based on the output signal VR, it generates an internal power signal VCCA that is lower than the external power input terminal VIN, which is used to power the reference module. The output signal VR serves as the input reference voltage of the LDO, and the internal power signal VCCA is higher than the reference voltage. The PSRR of the voltage VCCA is positively correlated with the PSRR of the output signal VR. The reference module, based on the internal power signal VCCA, outputs the control signal and the reference voltage Vbg. During the startup of the reference module, it does not output the reference voltage Vbg, but only outputs the default control signal, making the output signal VR of the multiplexer the bias voltage. When the reference module completes startup, operates, and outputs the reference voltage Vbg, it outputs a signal opposite to the default control signal, making the output signal VR of the multiplexer the reference voltage Vbg. Once the reference module is operating, the state of the signal opposite to the default control signal will not change during normal operation.

2. The high PSRR reference circuit according to claim 1; characterized in that, The bias module includes a resistor R1 and an NMOS transistor M1. The resistor R1 is connected to the external power input terminal VIN and the drain of the NMOS transistor M1 for current limiting. The gate and drain of the NMOS transistor M1 are connected and are always in the saturation region. The bias voltage is equal to the gate voltage of the NMOS transistor M1.

3. The high PSRR reference circuit according to claim 1, characterized in that, The multiplexer includes an inverter, an NMOS transistor M3, and an NMOS transistor M4. The input of the inverter is connected to the control signal and the gate of the NMOS transistor M4. The output of the inverter is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M3 is connected to the bias voltage, and the source of the NMOS transistor M4 is connected to the reference voltage Vbg. The drains of the NMOS transistors M3 and M4 are connected to output the output signal VR. The gates of the two NMOS transistors are respectively connected to the control signal and the inverted signal of the control signal by the inverter. If the gate of the NMOS transistor M3 is connected to a low-level signal, the NMOS transistor M3 is turned off and the NMOS transistor M4 is turned on. If the gate of the NMOS transistor M4 is connected to a low-level signal, the NMOS transistor M4 is turned off and the NMOS transistor M3 is turned on.

4. The high PSRR reference circuit according to claim 1, characterized in that, The multiplexer includes an inverter, a first transmission gate, and a second transmission gate; the input of the inverter is connected to the control signal and the switch of the second transmission gate, the output of the inverter is connected to the switch of the first transmission gate, the input of the first transmission gate is connected to the bias voltage, and the input of the second transmission gate is connected to the reference voltage Vbg. The two transmission gates are respectively connected to the control signal and the signal after the control signal is inverted by the inverter. If the first transmission gate is connected to a low-level signal, the first transmission gate is turned off and the second transmission gate is turned on; if the second transmission gate is connected to a low-level signal, the second transmission gate is turned off and the first transmission gate is turned on.

5. A control method for a high PSRR reference circuit as described in any one of claims 1-4, characterized in that, Includes the following steps: Step S1: The bias module, multiplexer, and low dropout linear regulator (LDO) are powered on by connecting to the external power input terminal VIN. The bias module generates a fixed bias voltage lower than the voltage at the external power input terminal VIN. The LDO receives the output signal VR from the multiplexer and outputs the internal power signal VCCA to the reference module. When the reference module does not generate the reference voltage Vbg during a predetermined period of power-on startup, it only outputs the default control signal to the multiplexer. The multiplexer outputs the fixed bias voltage to the low dropout linear regulator LDO. The low dropout linear regulator LDO outputs the internal power signal VCCA with a first PSRR value. Step S2: After the reference module completes power-on startup, enters the working state and outputs the reference voltage Vbg, the reference module outputs a signal opposite to the default control signal, causing the output signal VR of the multiplexer to switch to the reference voltage Vbg. The low dropout linear regulator LDO outputs the internal power supply signal VCCA with a second PSRR value. The PSRR of the internal power supply signal VCCA increases. Since the internal power supply signal VCCA serves as the power supply signal for the reference module, the PSRR of the reference voltage increases. The reference voltage Vbg and the internal power supply signal VCCA form a self-loop, creating a virtuous cycle of the internal power supply VCCA with a high power supply rejection ratio and the reference voltage with a high power supply rejection ratio, thus obtaining a reference voltage with a high power supply rejection ratio. The second PSRR value is higher than the first PSRR value.

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