A deadlock avoidance method for TriBA-cNoC based on synchronous Hamiltonian cycle

Abstract

The present invention relates to a TriBA-cNoC deadlock avoidance method based on a synchronous Hamiltonian cycle, and belongs to the technical field of computer many-core processors. This method solves the technical problem of TriBA-cNoC nodes deadlocking due to shared storage and forwarding buffers and shared physical transmission channels. Based on the topological characteristics of TriBA-cNoC, it can avoid the common versatility limitations of current many-core processors, which are easily caused by the randomness of data transmission directions and communication deadlocks. Usually, only application-oriented static routing can be provided by users, or only some physical channels can be used to form a synchronous ring network. This method avoids the use of handshake signals and does not require the front node to feedback its buffer occupancy status information, thereby reducing the time cost and improving communication performance, laying a foundation for the versatility of TriBA-cNoC and multi- / many-core processors based on this on-chip network.

Description

Technical Field

[0001] The present invention relates to a deadlock avoidance method for a TriBA-cNoC (Triple-core Inter-Chip Network on a Chip) many-core processor based on a synchronous Hamiltonian ring, and belongs to the technical field of computer many-core processors. Background Art

[0002] A many-core processor is a multi-node / core computing system implemented on a single chip. While typical multi-node computing systems can avoid communication deadlocks by using full interconnection, many-core processors are not suitable for this approach due to limited on-chip resources. Consequently, various resource sharing methods are necessary. Consequently, resource sharing in many-core processors based on a network-on-chip (NoC) inevitably leads to communication deadlocks. Only by resolving (avoiding or preventing) this deadlock problem can many-core processors be used effectively.

[0003] Deadlock is a deadlock state. When multiple (two or more) processes (or concurrent hardware modules) in a computing system compete for resources, each process is in a state of waiting for resources to be obtained before moving forward. Without external interference, the system itself cannot exit this state. This is called deadlock in the computing system. The four necessary conditions for deadlock to occur are:

[0004] Mutual exclusion: A resource can only be used by one process at a time;

[0005] Request and hold: When a process is blocked for requesting resources, it holds on to the resources it has obtained;

[0006] Non-deprivable: The resources obtained by the process cannot be forcibly deprived before they are used up;

[0007] Circular waiting: A circular waiting resource relationship is formed between several processes, with each process connected head to tail.

[0008] In many-core processors based on network-on-chip, communication deadlock is inevitable due to the existence of a large number of circular paths and the sharing of store-and-forward buffers. Figure 1 The figure below shows an example of a deadlock caused by a shared buffer. Data is transmitted along the circular path shown by the dotted line. When the store-and-forward buffer of each node on the path is exhausted, each node will face the state of waiting for the node in front to have a free buffer to receive data. A dependency is formed between the node in front and the current node. Because all buffers in the ring are exhausted, this dependency extends to the entire path, resulting in a deadlock.

[0009] If the necessary conditions for deadlock can be eliminated, then the computing system will not deadlock. Therefore, employing certain technical means to eliminate one or more of these necessary conditions in the system, thus preventing the system from deadlocking, is called deadlock prevention. Since the four conditions mentioned above are merely necessary, they are only a possibility for deadlock to occur, not sufficient conditions. That is, deadlock does not necessarily guarantee its actual occurrence. Therefore, at runtime, the system can have these necessary conditions, but by employing some means to prevent the system from entering deadlock, this is called deadlock avoidance.

[0010] Currently, technical means used by those skilled in the art to address deadlock mainly include the following categories:

[0011] 1. Strictly regulate the order in which messages request routing resources to prevent circular dependencies. For example, the classic turn model and the even-odd turn model break circular dependencies by restricting specific turns. However, this approach can lead to high process startup latency and low communication efficiency.

[0012] 2. Add additional cache as an escape path for deadlock avoidance and recovery. For example, typical virtual network partitioning and flat adaptive routing algorithms establish virtual channels based on physical channels to ensure no dependencies. However, this increases costs due to excessive resource usage.

[0013] 3. Use some technology to monitor and control the number of idle buffers in the network to ensure that messages can obtain resources and be forwarded. For example, bubble flow technology can avoid deadlock by controlling the number of buffers. However, the long process blocking time and the need to call additional resources for processing cannot be ignored.

[0014] 4. Using detour routing, each input flit of the router is arranged to a certain output port, thus ensuring that each cycle message can be delivered. However, it is possible that the movement is not on the shortest path from the current node to the destination node. Summary of the Invention

[0015] The present invention aims to overcome the shortcomings of existing technologies and address the technical issue of deadlock in TriBA-cNoC nodes caused by shared storage and forwarding buffers and shared physical transmission channels. Specifically, it aims to eliminate the necessary conditions for deadlock and prevent the computing system from experiencing a deadlock. A TriBA-cNoC deadlock avoidance method based on a synchronous Hamiltonian cycle is creatively proposed. Triplet-Based Architecture (TriBA) is a multicore processor architecture that combines the advantages of advanced multicore architectures such as Tiled, stream processors, and PIM.

[0016] The present invention is based on the topological characteristics of TriBA-cNoC, which is completely different from other existing on-chip networks. By virtue of this characteristic, efficient communication without deadlock can be achieved without negative impact, and thus it is a new deadlock elimination method.

[0017] In order to enable those skilled in the art to more clearly understand the present method, first, the TriBA-cNoC is described.

[0018] The present invention uses the TriBA-cNoC topology TC F For concepts such as construction methods and graph theory definitions, basic groups, vertices, supervertices, and shortest path routing algorithms, please refer to the public literature - "Shi Feng et al. TriBA-Net shortest path routing mechanism based on S3 transformation, Chinese Science: Information Science v.48.01 (2018): 100-114". In this literature, the topology construction method and its graph theory definition contain the encoding / naming method of TriBA-cNoC nodes. The TC in this literature L , which is TC in the present invention F , F and L have the same meaning. The TriBA-cNoC in this paper is the same as the TriBA-Net in the reference. Furthermore, networks and their topology research belong to two different fields, network theory and graph theory, respectively. Conventional practice is to use terminology from these two fields, but the corresponding relationship between them is obvious.

[0019] Because the present invention relates to both fields, unless otherwise specified, the various terms will not be explained and will be used interchangeably. For example, a vertex in graph theory corresponds to a node in network terminology, a supervertex corresponds to a supernode, a subgraph corresponds to a subnet, and so on.

[0020] TriBA-cNoC, a three-core network-on-chip (CNoC) with a topology called TC F , its plane diagram is shown as Figure 2 As shown, also known as the number of nodes 3 F , where F is called the number of levels of the topology (TC F with a clear hierarchical structure).

[0021] TC F The splicing construction method is as follows:

[0022] First, place three identical TC F-1 As three super nodes, named x F ∈{1, 2, 3}. Then, interconnect the three super nodes in pairs, as Figure 2 Medium TC 1 As shown, a new F-layer graph is formed. In this new graph, all three TCF-1 The nodes need to be renamed. The naming rule is: F-1 The node name x F-1 ...add the corresponding supernode name before x1 to form a new name x F x F-1 …x1.

[0023] In the above construction method, the node naming (coding) rule is called IDC-132. F By three super vertex TC F-1 Any subgraph is connected in pairs. There are three subgraphs TC as super nodes f-1 The three super nodes are interconnected in pairs and are denoted as and

[0024] TC F The graph theory definition of is as follows:

[0025] Definition: Graph TC F ={V(TC F ), E(TC F )}, vertex set V(TC F ) and edge set E(TC F ) are:

[0026]

[0027]

[0028] in, is A text string x of length Ff consisting of Chinese characters F …x f+1 , when the semantics are clear, it is written as a f-1 represents a string of (f-1) characters a; is the set of natural numbers; Represents a vertex and Adjacency, that is, there is an edge between two points F is the number of topological levels, and f is the number of subgraph levels. F is an undirected (i.e. bidirectional) graph, so

[0029] TC F It has the following characteristics:

[0030] 1. Cutting-edge

[0031] TCF The three vertices of the apex are called apexes or apex vertices, and the name (code) of apex i is i F .

[0032] 2. Basic Group

[0033] TC F The smallest "triangle" structure formed by the interconnection of three vertices is called a basic group, which is a clique in graph theory.

[0034] 3. Nested Structure

[0035] TC F It shows an obvious nested hierarchical structure, and the TC of the F layer F Contains 3 F The present invention uses both graph theory and network terminology, and does not make a detailed distinction unless necessary.

[0036] 4. Input / Output Ports

[0037] TC F The node contains three bidirectional ports, also known as three input ports and three output ports. The naming convention is shown in the figure. The port connected to basic group node i is numbered i, and the output port and input port are denoted as Pouti and Pini, respectively. For example, a node connected to the output port and input port of node 3 in the basic group are denoted as Pout3 and Pin3, respectively.

[0038] While graph theory describes data transmission using only vertices and edges, in networking terms, transmission is implemented by the internal circuits of nodes, with ports placed on physical channels (equivalent to edges) for transmission. Therefore, information such as port names and numbers is crucial.

[0039] Meanwhile, the present invention also relates to a routing algorithm of a TriBA-cNoC network on chip, wherein the shortest path routing (starting point) algorithm is taken as an example to describe the algorithm.

[0040] 1. Focus routing diagram

[0041] Because the shortest path routing strategy is adopted, the routing calculation is always limited to a certain subnet and has nothing to do with other nodes outside the area. This area is called the focal routing subgraph, or FRG for short. f , f is the subgraph level, As shown in the picture.

[0042] 2. Rotation Transformation

[0043] TriBA-cNoC has obvious rotational symmetry, which can greatly simplify routing calculation and implementation. The present invention defines the corresponding selection transformation group S3. Specifically, is a rotation group S3 whose elements have a definite order:

[0044]

[0045] in, represents the order of the rotation transformation of nodes (including supernodes and tips) on TriBA-cNoC. For example, Indicates that 1 node is rotated and transformed to the position of 1 node, that is, the node itself remains unchanged; It means that node 1 is rotated to the position of node 2, node 2 is rotated to the position of node 1, and the rest are similar.

[0046] 3. Transmission Mode

[0047] In communications, transmission is generally divided into six situations, called transmission modes, which are denoted as TM0 to TM5 and are numbered in binary form. Figure 4 As shown, TM0 corresponds to the routing node and the communication end point, which are located in the lower left and lower right corners of TriBA-cNoC respectively. The routing algorithm is based on TC F of The symmetries are calculated in the equivalent TM0 mode and then back to the original mode by inverse transformation.

[0048] Specifically, the routing node Communication endpoint The data transmission mode between them is as follows:

[0049]

[0050] Among them, the focus routing graph FRG f ; is bitwise OR; "·" is bitwise AND; TM ith is the i-th digit of a binary number. s″ f , s′ f Represents routing nodes The first and second binary digits of the f-th layer code (for example, when the layer code is 2, its binary representation is 10, then s″ f , s′ f are 1 and 0 respectively); t′ f , t″ f Similar to s″ f , s′ f .exist Under the transformation, the current transmission mode routing calculation is the same as the routing result in the equivalent TM0, that is, for the mode TM iCommunication, routing nodes and communication endpoints After the conversion, the data transmission mode between nodes becomes equivalent to TM0. Therefore, using this relationship, it is possible to convert between the current communication mode and the corresponding equivalent TM0 mode.

[0051] 4. Route calculation in TM0 mode

[0052] Under the shortest path routing constraint, the source node, communication destination and alternative paths of FM0 mode are as follows: Figure 6 As shown in the figure, PathA and PathB refer to the adjacent path and the span path, respectively. The core of the routing calculation in this mode is to compare the length of the adjacent path PathA and the span path PathB. The shorter one is the selected routing path.

[0053] On the basis of the above, the present invention proposes a TriBA-cNoC deadlock avoidance method based on a synchronous Hamiltonian ring. First, this method designs a corresponding virtual channel based on the Hamiltonian ring possessed by TriBA-cNoC. The Hamiltonian ring adopted is unique to the TriBA-cNoC topology and cannot be the same as other topologies. Second, this method is based on the Hamiltonian ring and adopts synchronous transmission, which is essentially different from the existing technology. Third, the topological characteristics of the current mainstream multi-core processors lead to the fact that they almost without exception need to be optimized by using application characteristics in applications in order to run efficiently without deadlock, that is, they cannot be universal. The deadlock removal method of the present invention is only applicable to TriBA-cNoC and has nothing to do with the application, so that the processor based on TriBA-cNoC can be further used as a general-purpose processor.

[0054] Beneficial effects

[0055] Compared with the prior art, the present invention has the following advantages:

[0056] 1. The synchronous transmission mechanism adopted by the present invention avoids the use of handshake signals and does not require the front node to feedback its buffer occupancy status information, thereby reducing time costs and improving communication performance;

[0057] 2. Based on the architectural features of TriBA-cNoC, the present invention can avoid the common versatility limitations of current many-core processors. In contemporary mainstream many-core topology architectures (2D-Mesh or its improvements), the randomness of data transmission direction can easily lead to communication deadlocks. Typically, users can only provide application-oriented static routing, or only use some physical channels to form a synchronous ring network (a relatively simple network topology). This lays the foundation for the versatility of TriBA-cNoC and multi- / many-core processors based on this on-chip network.

[0058] It can be seen that this method provides a solution for the use of multi-core / many-core processors based on TriBA-cNoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Deadlock caused by shared buffer;

[0060] Figure 2 Define TC for the topology of TriBA-cNoC and its graph theory F ;

[0061] Figure 3 Focus Routing Graph FRG f ;

[0062] Figure 4 It is the data transmission mode of TriBA-cNoC communication;

[0063] Figure 5 is the encoding of the internal port of the TriBA-cNoC node;

[0064] Figure 6 TM0 mode communication and focus routing graph FRG f Schematic diagram;

[0065] Figure 7 For TC F Schematic diagram of the Hamiltonian path between the tip nodes and its proof (taking the tips Apex-1 and Apex-2 as examples), where For TC F-1 The symmetry point of

[0066] Figure 8 For TC F Schematic diagram of the Hamiltonian cycle;

[0067] Figure 9 For TC 3 The Hamiltonian circulation formed by the three bidirectional virtual Hamiltonian channels; the dotted lines are only used to indicate the grouping of physical transmission channels, rather than the usual virtual connections;

[0068] Figure 10 Schematic diagram of the symmetric points of the Hamiltonian path in TM0 mode communication and the maximum number of layers of edges that the data will pass through, with FRG 4 Take the lower left vertex as an example, where the symmetrical point is the vertex. DETAILED DESCRIPTION

[0069] The method of the present invention is further described in detail below with reference to the accompanying drawings.

[0070] A deadlock avoidance method for TriBA-cNoC based on synchronous Hamiltonian cycles. Communication data is logically grouped based on the network topology. Each group transmits independently, with no data exchange between groups. Even groups with the same data type in different directions do not interact, eliminating contention between groups. Within each unidirectional ring, synchronous transmission is used to avoid buffer contention.

[0071] On the basis of the existing technology, the present invention adopts the following new technical means.

[0072] TriBA-cNoC, a three-core network-on-chip (CNoC) with a topology called TC F .

[0073] Based on TC F Hamiltonian properties refer to Hamiltonian paths and Hamiltonian cycles. F There exists a Hamiltonian path (H-path, such as Figure 7 a), and TC F Contains Hamiltonian cycles (H-cycle, such as Figure 7 shown).

[0074] Specifically, TC F There exists a Hamiltonian path between any two tip nodes, that is, the path starts from a tip node and ends at another tip node, passing through each vertex once and only once.

[0075] TC F Scale F, with tip 1 F and 2 F Take the Hamiltonian path between as an example, the Hamiltonian path is as follows Figure 7 As shown in a.

[0076] Basic steps: F=1, TC 1 ( Figure 7 b). Bidirectional path is the Hamiltonian path.

[0077] Inductive step: F>1, TC F ( Figure 7 b). TC F By three TC F-1 and three interconnected edges between them. Due to the inductive hypothesis, each TC F-1 There are Hamiltonian paths between the tips, so the three TC F-1 The Hamiltonian path and two interconnecting edges ( Figure 7 b) constitutes TC F Hamiltonian path.

[0078] TC FThere exists a Hamiltonian cycle in it, that is, a closed path that passes through every vertex once and only once.

[0079] To more intuitively understand the principle of using the Hamiltonian property of TriBA-cNoC to eliminate deadlock, TC F The Hamiltonian cycle is redrawn as shown in Figure (with TC 3 For example, (e.g., ) Clearly, while data is transmitted randomly in various directions at runtime, it appears to flow along a loop at a macro level. This is why it's called a virtual Hamiltonian circuit, or simply a Hamiltonian circuit, or even a circuit. The term "virtual" refers to the fact that data doesn't move exclusively along Hamiltonian or non-Hamiltonian edges; it can jump between both types of edges.

[0080] As shown in the figure, around the Hamiltonian cycle, the two endpoints connected by non-Hamiltonian edges are like "shortcuts" appearing from time to time on the Hamiltonian cycle. As data is transmitted, it jumps between the Hamiltonian cycle and the shortcut. If we assume that the data on the "shortcut" uses its own independent channel in the Hamiltonian cycle for transmission, then the data transmission on the TriBA-cNoC is "logically" transmitted along F independent logical channels. For example, the three-layer TriBA-cNoC topology TC in the figure 3 Logically divided into three rings.

[0081] If data can be technically guaranteed to be independent along its logical ring on the TriBA-cNoC (that is, data only resides within one logical ring throughout its entire life cycle) and transmitted synchronously, then the data on the ring will never conflict with the data that is always located behind it, thus breaking one of the necessary conditions for deadlock to occur - circular waiting, and thus preventing the occurrence of deadlock.

[0082] In addition, in the figure, the Hamiltonian cycle is located on the outside, and the inner centripetal direction appears in turn to indirectly connect two vertices and connect two TCs. 1 , connect two TC 2 ,... and other non-Hamiltonian edges. The levels of these edges are called 2, 3, 4... respectively; Hamiltonian edges are the first-level edges.

[0083] Hamiltonian path midpoint

[0084] In this invention, communication data is transmitted using its own "logically" independent channels. Technically, this is achieved by time-sharing the physical channel, but using exclusive storage and forwarding buffers corresponding to each data type. The determination of the buffer type used by the communication data must be made based on the Hamiltonian path structure and direction at the same time as the routing calculation. To this end, the following solution is adopted:

[0085] Any TC F The tip nodes are all midpoints of the Hamiltonian path between the other two tip nodes, that is, the distances from the tip to the other two tip nodes along the Hamiltonian path (Hamiltonian distance for short) are the same.

[0086] TC F Scale F, with tip 3 F To the other two tips 1 F and 2 F The Hamiltonian distance is taken as an example to prove the correctness of the scheme.

[0087] Basic steps: F = 1, that is, TC 1 The Hamiltonian distance from tip 3 to both tips 1 and 2 is 1.

[0088] Inductive steps: F>1, TC F It consists of three vertices and their interconnected edges (three in total). Due to the inductive hypothesis, the tip 3 F-1 To the TC F-1 The Hamiltonian distances of the other two vertices are equal (both ), these two vertices to 1 F and 2 F The Hamiltonian distance is 3 f-1 -1, i.e. tip 3 F to 1 F and 2 F The Hamiltonian distances are

[0089] Symmetry axis / point of subgraph:

[0090] TC F Each subgraph of has its own symmetry axis, which varies with TC F The shape of the Hamiltonian path changes. In the present invention, the symmetry axis of the subgraph is marked as follows:

[0091] Subgraph In the plane diagram (as shown in the figure), the two tips i f and j f Hamiltonian path (TC F The Hamiltonian path part) midpoint (or symmetric point) tip k f , the vertex or its symmetry axis is recorded as in, It's TC f Name (a text string of length Ff), And i≠j≠k.

[0092] For example, It is TC named 213 4 Subgraph whose axis of symmetry / vertex is tip 2 4 Or vertex 2132222.

[0093] The structure of the subgraph symmetry axis:

[0094] A subgraph with a specific symmetry axis is composed of three subgraphs with a specific symmetry axis at a lower level, as follows:

[0095] The axis of symmetry is Image The symmetry axes are and TC f-1 Subgraphs and interconnected edges, where It's TC f name, And i≠j≠k.

[0096] TC f f, with the axis of symmetry Take this as an example to prove the correctness of the scheme:

[0097] Basic steps: When f=1( Figure 7 TC in a 1 ), if the TC of the three vertices 1 The name is Then its symmetry point is That is, the vertex This is the same as the actual situation. When f=2( Figure 7 TC in a 2 ), if its axis of symmetry is At this time, its three TC 1 The symmetry axes of the subgraphs are as described in the theorem. and That is, the vertex and Same as the actual situation.

[0098] Inductive steps: When f>2, TC f By three TC f-1 And three interconnected single sides, if TC f Symmetrical point Obviously considering the three TC f-1 The endpoint of the Hamiltonian path segment is located at TC f TC in the lower left corner f-1 The symmetry point of Right now TC located directly above f-1 The axis of symmetry must be Right now TC at the bottom right f-1 The symmetry point of Right now

[0099] For example, TC 4 Axis of symmetry After you can open one level, the next level has three TCs 3 The symmetric points of the subgraph are and Each subgraph where the symmetry axis is located can be further expanded, for example TC 3 TC after the subgraph continues to expand 2 The symmetry axes of the subgraphs are and …….

[0100] The method of the present invention, the routing core calculation is performed in the equivalent TM0 mode, along with the focus routing graph FRG f The shape of the Hamiltonian cycle (part) is different for different locations, so the routing core calculation must also determine the current FRG after obtaining the forwarding port. f The present invention includes the following steps: f Symmetrical point / axis, calculation of TM0 mode FRG f The symmetry axis (Axis) and the process of determining the buffer type used by the data are as follows:

[0101] Among them, FRG f The symmetry point / axis determination process is as follows:

[0102] FRG f Name x F …x f+1 As input, set the axis of symmetry to x F , x F is the initial symmetry point.

[0103] Create a loop variable i, and execute "if x i-1 Different from Axis, let Axis be the non-x in the set {1, 2, 3} i-1 Finally, the obtained symmetrical point / axis is output as the final result (you can also press Output in the form of ( ) where the source node is located. f Given by the pipeline of the origin routing algorithm.

[0104] Specifically, as shown in Algorithm 1:

[0105]

[0106] *F in the algorithm is finite, so the algorithm can be implemented in hardware

[0107] Calculate TM0 mode FRG f The symmetry axis is as follows:

[0108] With source node s=s F ...s1, target node t = t F ...t1 and the current communication mode TM (F is the maximum level of the processor's TriBA-cNoC) are input, and the symmetry axis Axis is output, determining the TM0 mode FRG f axis of symmetry.

[0109] The principle is as follows:

[0110] First, when s F =1 and t F =2 or s F =2 and t F =1, then Axis=3; when s F =1 and t F =3 or s F =3 and t F =1, then Axis must be 2; when s F =2 and t F =3 or s F =3 and t F = 2, then Axis must be 1. This gives us the initial value of the axis of symmetry.

[0111] Secondly, to decompose the composition of the Hamiltonian path layer by layer, it is necessary to repeatedly apply the above-mentioned subgraph symmetry axis structure process, and perform symmetry axis structure decomposition and analysis on the subgraphs at each level in a loop body with a loop variable i (decreases by 1 each loop) from F-1 to 1.

[0112] Specifically, as shown in Algorithm 2.

[0113]

[0114] *All variables in the algorithm are finite, so all inter-process parallelism can be implemented in hardware

[0115] Determining the data buffer type in TM0 mode communication (overall framework of the deadlock elimination method)

[0116] As previously mentioned (see Reference 1), the core work of routing calculation is performed in the equivalent TM0 mode of the current communication. Therefore, in this mode, it is necessary to determine the buffer type required for communication data while performing routing calculation. This calculation is called "Determination of Data Buffer Type in TM0 Mode Communication" (Algorithm 3). Its specific calculation task is to calculate the maximum number of all edge levels that the communication will pass through in the entire process from the source node to the destination under various circumstances, and use this as the buffer type of the corresponding data (that is, the logical Hamiltonian cycle to which it belongs).

[0117] This calculation is based on the focus routing graph FRG f , symmetric point Axis, current communication mode TM, source node s=s F...f+1 ...s1, target node t=t F... f +1 ...t1 is the input, and the two cases of selecting Path B or Path A for route calculation are as follows:

[0118] When the route selects PathB: If f = F, then output f and end. This is because the topological characteristics indicate that the data must pass through the edge.

[0119] If f≠F, output f+1 and end. This is because, according to the topological characteristics, the symmetric point is x F..f+1 1 f When the data is transmitted, it must pass through the edge The symmetric point is x F..f+1 2 f When the data is transmitted, it must pass through the edge

[0120] When Path A is selected, there are three possibilities: when the symmetric point is 1, it is located at the lower left; when the symmetric point is 2, it is located at the lower right; and when the symmetric point is 3, it is located directly above. For each possibility, the maximum number of edges that will be passed through during subsequent communication data transmission can be determined based on the topological characteristics.

[0121] Finally, the highest edge level calculated is the data buffer type, that is, the logical Hamiltonian cycle number.

[0122] The above process is shown in Algorithm 3.

[0123]

[0124]

[0125] * All processes and sub-processes are parallel

[0126] In addition, in the method of the present invention, the buffer type is numbered according to the logical level of the Hamiltonian cycle, with level 1 corresponding to the Hamiltonian edge and levels 2 to F corresponding to the non-Hamiltonian edge. When determining the data buffer type, it should be determined at the data creation (communication source node), which requires the pipeline implementation of the starting point routing algorithm, which will provide a series of relevant information (such as the current transmission mode TM, the current FRG f and its symmetric points, etc.) are used to calculate the buffer type. In the equivalent TM0 mode, the source and target nodes are x F …x f+1 1s f-1 ...s1 and x F …x f+1 2t f-1 ...a name of the form t1.

[0127] Figure 9 Shows drawing TC in the style of a torus 3 The Hamiltonian cycle graph of . Figure 9 The data transmission path in the network is divided into three logical rings, including the first-level Hamiltonian edge that directly connects all nodes, the indirect connection between two nodes (e.g. The second layer of non-Hamiltonian edges and the edges connecting the two TCs 1 (For example The third-layer cross-group edge (e.g., etc.) technically ensures that data in the network is independently and synchronously transmitted in three logical rings (it only stays in one logical ring during its entire life cycle). This ensures that data in a ring will never conflict with data that is always behind it, breaking one of the necessary conditions for deadlock—cyclic waiting—and thus preventing deadlock from occurring.

[0128] Figure 10 Demonstrated the use of FRG 4 Take the example to determine the specific implementation process of the data buffer type in TM0 mode communication. Figure 10 In TM0 mode, FRG 4 , symmetric point x F …x51 4 , source node x F..f+1 1s3s2s1, communication endpoint x F..f+1 2t3t2t1 is the input information, and the route selected is Path A. The process of determining the highest level (i.e., buffer type) of the edge that the current communication data will pass through in future transmission is as follows:

[0129] 1. When s3=3 or t3=2, the source node is named x F..f+1 13s2s1, communication endpoint x F..f+1 When 22t2t1, the communication must pass through the fourth layer of non-Hamiltonian edges or That is, the buffer type is four;

[0130] 2. When s3=1 or t3=3, the source node is named x F..f+1 11s2s1, communication endpoint x F..f+1 At 23t2t1, the communication must pass through the third layer of non-Hamiltonian edges or That is, the buffer type is three;

[0131] 3. When s2=1 or t2=3, the source node is named x F..f+1 121s1(s3=2 means that the source node is located in each scale FRG including V2 f Subgraph, the same below), communication end point x F..f+1 At 213t1, communication must pass through the third layer of non-Hamiltonian edges or That is, the buffer type is three;

[0132] 4. When s2=3 or t2=2, the source node is named x F..f+1 123s1, communication endpoint x F..f+1 At 212t1, communication must pass through the second layer of non-Hamiltonian edges or That is, the buffer type is two;

[0133] 5. When s1=3 or t1=2, the source node is named x F..f+1 1223, communication end point x F..f+1 When 2112, the communication must pass through the second layer of non-Hamiltonian edges or That is, the buffer type is two;

[0134] 6. In other cases, the edges passing through Hamiltonian are the first layer, that is, the buffer type is one.

[0135] Example 1

[0136] TC F In the TriBA-cNoC implementation, each bidirectional edge uses two channels with opposite transmission directions, which are used in a time-sharing manner for each packet. This virtual channel is used to implement the bidirectional Hamiltonian cycle in layers 1 through F of the method described in this invention. This is a relatively low-cost implementation method that can be adopted by most processor applications.

[0137] Example 2

[0138] The groups to be transmitted are the same as those in Example 2, except that each group is transmitted using a bidirectional Hamiltonian cycle consisting of an exclusive physical channel. Although the implementation cost is relatively high, the performance is greatly improved.

[0139] Example 3

[0140] The transmitted packets are the same as those in Example 2, and bidirectional transmission is implemented for some packets using virtual channels, similar to Example 1. The remaining packets are transmitted using an exclusive bidirectional Hamiltonian cycle similar to Example 3. This approach achieves a balance between cost and performance.

[0141] In specific applications, grouping can be implemented using time-division multiplexing physical channels or dedicated physical channels, or a combination of the two, so the implementation is flexible. The above examples illustrate the specific application features of the present method. It should be noted that the above examples are only used to illustrate the present invention and are not intended to limit the present invention.

Claims

1. A deadlock avoidance method for TriBA-cNoC many-core processors based on synchronous Hamiltonian cycles, characterized by: The corresponding virtual channel is designed based on the Hamiltonian cycle of TriBA-cNoC, where TriBA-cNoC represents the three-core inter-chip network and the topology is named TC. F Communication data is logically grouped based on the network topology. Each group transmits independently, and there is no data interaction between groups. Even groups with the same type of data in different directions do not interact with each other, and there is no competition between groups. Synchronous transmission is used within each unidirectional ring. First, identify the focus routing graph FRG f Symmetrical point / axis, the method is as follows: FRG f Name x F …x f+1 As input, let the symmetry point / axis Axis be x F , x F As the initial symmetric point; establish a loop variable i, and execute "if x i-1 Different from Axis, let Axis be the non-x in the set {1,2,3} i-1 and other values ​​of non-Axis, F is the topology TC F The number of levels, f is the number of levels of the subgraph; the obtained symmetric point / axis Axis is output as the final result; Then, calculate the TM0 mode FRG f The symmetry point / axis Axis determines the type of buffer that will be used for communication data as follows: Calculate the maximum number of all edge levels that the communication will pass through in the entire process from the source node to the end point in various cases, and use this as the buffer type of the corresponding data, that is, the logical Hamiltonian cycle to which it belongs; the calculation is based on the focus routing graph FRG f , symmetry point / axis Axis, current communication mode TM, source node s=s F…f+1 ...s1, target node t=t F…f+1 ...t1 is the input, which corresponds to the two cases where PathB or PathA is selected for route calculation. PathA and PathB refer to the adjacent path and the spanning path, respectively: When Path B is selected as the route: if f = F, then output f and end; if f ≠ F, then output f + 1 and end; when Path A is selected as the route: when the symmetric point is 1, it is located at the lower left; when the symmetric point is 2, it is located at the lower right; when the symmetric point is 3, it is located at the top; for each possibility, the maximum level of edges that will be passed through in the subsequent communication data transmission process can be determined based on the topological characteristics; The highest edge level calculated is the data buffer type, i.e., the logical Hamiltonian cycle number, which determines which logical Hamiltonian cycle it belongs to and selects the corresponding virtual channel for communication. The buffer type is numbered according to the logical level of the Hamiltonian cycle flow, with level 1 corresponding to Hamiltonian edges and levels 2 to F corresponding to non-Hamiltonian edges. When determining the data buffer type, it should be determined at the data creation point and combined with the pipeline implementation of the starting point routing algorithm. Finally, the above method is applied to the TriBA-cNoC many-core processor to avoid deadlock.

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