Light emitting display device

Abstract

A light emitting display apparatus includes a gate driver including stages disposed in a substrate, and a plurality of gate lines connected to the stages. Each of the stages includes a shift register and two buffers connected to the shift register, a first-1 buffer of the two buffers constituting an n-th stage is disposed in an n-th horizontal section, a first shift register constituting the n-th stage is disposed in an n+2-th horizontal section, where n is an odd number, a second-2 buffer of the two buffers constituting an n+1-th stage and a second shift register constituting the n+1-th stage are disposed in an n+3-th horizontal section, a second-1 buffer is disposed in an n+1-th horizontal section, the n-th, n+1-th, n+2-th and n+3-th horizontal sections are areas including pixels arranged along 4n-3-th and 4n-2-th gate lines, 4n-1-th and 4n-th gate lines, 4n+1-th and 4n+2-th gate lines, 4n+3-th and 4n+4-th gate lines, respectively. Accordingly, the number of transistors included in one stage and the number of signal lines connected to one stage can be reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194754, filed on December 31, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a light-emitting display device. Background Technology

[0004] Based on the gate-in-panel (GIP) type, gate drivers can be directly set in the non-display area of ​​the light-emitting display panel that constitutes the light-emitting display device.

[0005] Recently, in order to achieve high resolution and increase user immersion, the width of the non-display area has been gradually reduced, and light-emitting display devices that do not include the non-display area have been proposed. However, there are limitations in reducing the area of ​​the transistors included in the gate driver.

[0006] Therefore, a light-emitting display panel has been proposed that incorporates transistors constituting gate drivers in the display area. In this case, the signal lines constituting the gate drivers are arranged along the gate lines.

[0007] However, as the resolution of the light-emitting display panel increases, the area for setting signal lines gradually decreases.

[0008] Therefore, a method is needed to reduce the number of signal lines along the gate line. Summary of the Invention

[0009] Therefore, this disclosure aims to provide a light-emitting display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One aspect of this disclosure aims to provide a light-emitting display device in which one of two buffers constituting a stage and a shift register constituting the stage are provided in the nth level portion, and the other buffer is provided in the n+2th level portion.

[0011] Additional advantages and features of this disclosure will be set forth in part in the description which follows, and some of these advantages and features will become apparent from the study of the narrator or may be appreciated by practice of the disclosure. These objects and other advantages of the invention are realized and obtained through the written description, claims, and the structures specifically pointed out in the accompanying drawings.

[0012] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a light-emitting display device is provided, comprising: a gate driver including a stage disposed in a substrate; and a plurality of gate lines connected to the stage. Each of the stages includes a shift register and two buffers connected to the shift register. A first-1 buffer (of the two buffers constituting the nth stage) and a first shift register constituting the nth stage are provided in the nth level portion, and a first-2 buffer (of the two buffers) is provided in the n+2 level portion, where n is an odd number. A second-2 buffer (of the two buffers constituting the n+1 stage) and a second shift register constituting the n+1 stage are provided in the n+3 level portion, and a second-1 buffer (of the two buffers) is provided in the n+1 level portion. The nth level portion is a region including pixels arranged along the 4n-3 and 4n-2 gate lines, the n+1 level portion is a region including pixels arranged along the 4n-1 and 4n gate lines, the n+2 level portion is a region including pixels arranged along the 4n+1 and 4n+2 gate lines, and the n+3 level portion is a region including pixels arranged along the 4n+3 and 4n+4 gate lines. Furthermore, a light-emitting display device is also provided, comprising: a gate driver, the gate driver including a stage disposed in a substrate; a plurality of gate lines connected to the stage; data lines intersecting the plurality of gate lines; and pixels arranged along the data lines and the gate lines, wherein the nth stage is configured to output a 4n-3th gate pulse, a 4n-1th gate pulse, a 4n+1th gate pulse, and a 4n+3th gate pulse, where n is an odd number, and wherein the n+1th stage is configured to output a 4n-2th gate pulse, a 4nth gate pulse, a 4n+2th gate pulse, and a 4n+4th gate pulse. Furthermore, the 4n-3rd gate pulse, the 4n-1st gate pulse, the 4n-2nd gate pulse, the 4nth gate pulse, the 4n+1st gate pulse, the 4n+3rd gate pulse, the 4n+2nd gate pulse, and the 4n+4th gate pulse are respectively output to the sequentially arranged 4n-3rd gate line, the 4n-2nd gate line, the 4n-1st gate line, the 4nth gate line, the 4n+1st gate line, the 4n+2nd gate line, the 4n+3rd gate line, and the 4n+4th gate line, so that the pixels arranged along the same data line are driven in a zigzag pattern.

[0013] It should be understood that the foregoing general description of this disclosure and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings, which provide a further understanding of this disclosure and are incorporated in and form part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0015] Figure 1 This is an example diagram illustrating the construction of a light-emitting display device according to the present disclosure;

[0016] Figure 2 This is an example diagram illustrating the structure of pixels applied to a light-emitting display device according to this disclosure;

[0017] Figure 3 This is an example diagram illustrating the structure of a gate driver applied to a light-emitting display device according to the present disclosure;

[0018] Figure 4 It is a schematic map solution Figure 3 Example diagrams of the structure of each level shown;

[0019] Figure 5 It is a diagram Figure 4 An example diagram of the structure of each of the first signal output unit and the second signal output unit shown;

[0020] Figure 6 The detailed diagrams are above for reference. Figures 3 to 5 Example diagram of the described level;

[0021] Figure 7 This is an example diagram illustrating the structure of a light-emitting display panel applied to a light-emitting display device according to the present disclosure;

[0022] Figure 8 This is an example diagram illustrating the arrangement structure of the stages applied to a light-emitting display device according to this disclosure;

[0023] Figure 9 The diagram is set in Figure 8 An example diagram of the signal lines in the horizontal section shown;

[0024] Figure 10 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure;

[0025] Figure 11 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure;

[0026] Figure 12 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure;

[0027] Figure 13 It is used to describe Figure 5 The waveform diagram of the driving method of the stage shown;

[0028] Figure 14 It is a diagram Figure 4 An example diagram of the structure of each of the first signal output unit and the second signal output unit shown; and

[0029] Figure 15 It is used to describe Figure 14 The waveform diagram of the driving method of the stage is shown. Detailed Implementation

[0030] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, which illustrate examples of these embodiments. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0031] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0032] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details illustrated. Similar reference numerals denote similar elements throughout. In the following description, detailed descriptions of related known technologies will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure. When the terms "comprising," "having," and "including" are used in the description in this application, additional parts may be added unless "only" is used. Singular terms may include plural forms unless otherwise stated.

[0033] When interpreting a feature, the feature is interpreted as containing a range of errors or tolerances, even though such range of errors or tolerances is not explicitly described.

[0034] When describing positional relationships, for example, when the positional relationship between two parts is described as such as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts unless more restrictive terms such as "only" or "directly" are used.

[0035] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly,” “immediately,” or “directly” are used.

[0036] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to distinguish the corresponding element from other elements, and the basis, order, or number of the corresponding elements shall not be limited by these terms. An element is “connected,” “bonded,” or “adhered” to another element or layer, not only directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer in the case of “setting” or “inserting” one or more intermediate elements or layers between these elements or layers, unless otherwise specified.

[0038] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0039] When adding reference numerals to elements in each figure, the same reference numerals may denote the same element even if it is shown in other figures. Furthermore, for ease of description, the scale of each element shown in the figures differs from the actual scale; therefore, it is not limited to the scale described in the figures.

[0040] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is an example diagram illustrating the construction of a light-emitting display device according to the present disclosure. Figure 2 This is an example diagram illustrating the structure of pixels applied to a light-emitting display device according to the present disclosure.

[0042] The light-emitting display device according to this disclosure can constitute various electronic devices. Electronic devices may include, for example, smartphones, tablet PCs, televisions (TVs), and monitors.

[0043] like Figure 1As shown, the light-emitting display device according to this disclosure may include: a light-emitting display panel 100, which includes a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a gate driver 200, which provides gate signals to a plurality of gate lines GL1 to GLg disposed in the display area 120 of the light-emitting display panel 100; a data driver 300, which provides data voltages to a plurality of data lines DL1 to DLd disposed in the light-emitting display panel 100; a controller 400, which controls the driving of the gate driver 200 and the data driver 300; and a power supply, which supplies power to the controller, the gate driver, the data driver, and the light-emitting display panel. Specifically, in the light-emitting display device according to this disclosure, stages included in the gate driver 200 may be disposed in the display area 120, and gate lines GL1 to GLg connected to the stages may be disposed in the light-emitting display panel 100.

[0044] First, the light-emitting display panel 100 may include a display area 120 and a non-display area 130.

[0045] Multiple pixels 110 of the displayed image can be set in the display area 120, and the non-display area 130 can surround the display area 120.

[0046] In this disclosure, since the stages included in the gate driver 200 are located in the display area 120, the width of the non-display area 130 can be minimized.

[0047] In particular, the non-display area 130 can be omitted in this disclosure. That is, the display area 120 can be disposed on the entire surface of the front surface of the light-emitting display panel 100. In this case, as described above, since the gate driver 200 connected to the gate line is disposed in the display area, the non-display area of ​​the gate driver 200 can be omitted. Furthermore, for example, the end of the data line connected to the data driver 300 can be connected to... Figure 1 The upper end of the light-emitting display panel 100 shown extends to both the upper end and the rear surface of the light-emitting display panel, and can be connected to the data driver 300 located on the rear surface of the light-emitting display panel. Therefore, it is not necessary to provide a non-display area for the gate driver 200 and the data driver 300, nor to provide pads for connecting gate lines and data lines to the gate driver 200 and the data driver 300, on the front surface of the light-emitting display panel 100. Therefore, the non-display area 130 can be omitted in this disclosure.

[0048] However, this disclosure is not limited thereto. Therefore, a non-display area 130 for arranging various lines may be provided outside the display area 120.

[0049] Gate lines GL1 to GLg, data lines DL1 to DLd, and pixels 110 can be configured in the display area 120. Therefore, the display area 120 can display an image. Here, g and d can each be natural numbers.

[0050] like Figure 2 As shown, the pixels 110 included in the light-emitting display panel 100 may include a pixel driving circuit PDC and a light-emitting unit. The pixel driving circuit PDC includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. The light-emitting unit includes a light-emitting device ED.

[0051] The first terminal of the driving transistor Tdr can be connected to the high-voltage power line PLA through which the high voltage EVDD is provided, and the second terminal of the driving transistor Tdr can be connected to the light-emitting device ED.

[0052] The first terminal of the switching transistor Tsw1 can be connected to the data line DL, the second terminal of the switching transistor Tsw1 can be connected to the gate of the driving transistor Tdr, and the gate of the switching transistor Tsw1 can be connected to the gate line GL.

[0053] It can provide a data voltage Vdata to the data line DL and a gate signal GS to the gate line GL.

[0054] The sensing transistor Tsw2 can be configured to measure the threshold voltage or mobility of the driving transistor. The first terminal of the sensing transistor Tsw2 can be connected to the second terminal of the driving transistor Tdr and the light-emitting device ED. The second terminal of the sensing transistor Tsw2 can be connected to the reference voltage line RL through which the reference voltage Vref is provided. The gate of the sensing transistor Tsw2 can be connected to the sensing control line SCL through which the sensing control signal SS is provided.

[0055] The structure of the pixels 110 included in the light-emitting display panel 100 is not limited to... Figure 2 The structure shown is such that the structure of pixel 110 can be changed into various shapes.

[0056] An insulating layer and various electrodes constituting the pixel 110 can be disposed on a substrate such as a glass substrate or a film (hereinafter referred to as the substrate). In other words, the light-emitting display panel 100 may include a substrate, a plurality of insulating layers disposed on the substrate, and a plurality of electrodes disposed on the substrate.

[0057] The data driver 300 can be disposed on a chip-on-film (COF) attached to the light-emitting display panel 100. In this case, the data driver 300 can be connected to data lines DL1 to DLd included in the light-emitting display panel 100 and to the controller 400 included in the motherboard.

[0058] The data driver 300 can be directly integrated into the light-emitting display panel 100 and then connected to the controller 400 included in the motherboard. In this case, the data driver 300 can be constructed using transistors included in the light-emitting display panel 100.

[0059] The data driver 300 can be implemented as an integrated circuit (IC) together with the controller 400. In this case, the IC can be mounted on the COF or directly integrated into the light-emitting display panel 100.

[0060] Furthermore, as described above, the data driver 300 can be connected to the upper end of the light-emitting display panel 100 via a data line extending from the rear surface of the light-emitting display panel 100 to the rear surface of the light-emitting display panel 100 via a side connected to the upper end of the light-emitting display panel 100.

[0061] The controller 400 can re-align the input video data transmitted from the external system using a timing synchronization signal transmitted from the external system, and can generate a data control signal DCS to be provided to the data driver 300 and a gate control signal GCS to be provided to the gate driver 200.

[0062] For this purpose, the controller 400 may include: a data aligner that realigns input video data to generate image data Data and provides the image data Data to the data driver 300; a control signal generator that generates a gate control signal GCS and a data control signal DCS using a timing synchronization signal; an input unit that receives the timing synchronization signal and input video data transmitted from an external system and transmits the input video data and the timing synchronization signal to the data aligner and the control signal generator, respectively; and an output unit that provides the image data Data generated by the data aligner and the data control signal DCS generated by the control signal generator to the data driver 300, and provides the gate control signal GCS generated by the control signal generator to the gate driver 200.

[0063] An external system can perform the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a TV, the external system can receive various audio, video, and text information through a communication network and can transmit the received video information to the controller 400. In this case, the image information may include the input video information.

[0064] The power supply can generate various types of electricity and can provide the generated electricity to the controller 400, gate driver 200, data driver 300 and light-emitting display panel 100.

[0065] Gate driver 200 can provide gate pulses to gate lines GL1 to Glg. When the gate pulse generated by gate driver 200 is provided to the gate of switching transistor Tsw1 included in pixel 110, switching transistor Tsw1 can be turned on. When switching transistor Tsw1 is turned on, data voltage supplied through data lines can be provided to pixel 110. When a gate cutoff signal generated by gate driver 200 is provided to switching transistor Tsw1, switching transistor Tsw1 can be turned off. When switching transistor Tsw1 is turned off, data voltage is no longer provided to pixel 110. The gate signal GS provided to gate line GL can include gate pulses and gate cutoff signals.

[0066] The gate driver 200 may include multiple stages, and these stages may be connected to gate lines GL1 to GLg.

[0067] These stages can be included in the substrate constituting the light-emitting display panel 100, specifically in the display area 120.

[0068] The construction and function of the gate driver 200 will be described below with reference to the accompanying drawings.

[0069] Figure 3 This is an example diagram illustrating the structure of a gate driver applied to a light-emitting display device according to this disclosure. Figure 3 In this case, n can be an odd number less than g.

[0070] Gate driver 200 may include Stage 1 through Stage g / 4. Each of Stages 1 through g / 4 can output four gate pulses. In the following description, "gate pulse" may be used as a simple expression when describing all gate pulses, when the order of gate pulses is not required, or when a gate driver that limits the output gate pulses is not required. "Stage" may be used as a simple expression when a general name for all stages is required or when the order of stages is not required. "Gate cut-off signal" may be used as a simple expression when a general name for all gate cut-off signals is required or when the order of gate cut-off signals is not required.

[0071] Stage 1 can connect to the first gate line GL1, the second gate line GL2, the fifth gate line GL5 and the sixth gate line GL6, and Stage 2 can connect to the third gate line GL3, the fourth gate line CL4, the seventh gate line GL7 and the eighth gate line GL8.

[0072] In this configuration, the first gate pulse GP1 output from the first stage can be output to the first gate line GL1, the second gate pulse GP2 output from the second stage can be output to the third gate line GL3, the third gate pulse GP3 output from the first stage can be output to the second gate line GL2, the fourth gate pulse GP4 output from the second stage can be output to the fourth gate line GL4, the fifth gate pulse GP5 output from the first stage can be output to the fifth gate line GL5, the sixth gate pulse GP6 output from the second stage can be output to the seventh gate line GL7, the seventh gate pulse GP7 output from the first stage can be output to the sixth gate line GL6, and the eighth gate pulse GP8 output from the second stage can be output to the eighth gate line GL8.

[0073] Here, GL1 to GL8 can be the arrangement order of the gate lines, and GP1 to GP8 can be the output order of the gate pulses. That is, in this disclosure, the gate lines can be arranged in the order of the first gate line GL1 to the eighth gate line GL8, and the gate pulses can be output in the order of the first gate line GL1, the third gate line GL3, the second gate line GL2, the fourth gate line GL4, the fifth gate line GL5, the seventh gate line GL7, the sixth gate line GL6, and the eighth gate line GL8. Hereinafter, this order can be referred to as zigzag.

[0074] The gate pulses can be output in the order described above, with each pulse consisting of two stages and eight gate lines.

[0075] Figure 4 It is a schematic map solution Figure 3 The example diagrams for each level shown are, specifically, schematic diagrams illustrating the nth and (n+1)th levels. Here, n can be an odd number less than g. Figure 5 It is a diagram Figure 4 An example diagram of the structure of each of the first signal output unit and the second signal output unit shown.

[0076] Each stage may include multiple transistors, and the gate control signal GCS can be provided to each stage separately. Each stage can generate gate pulses using various signals and voltages, and the gate pulses can be sequentially provided to gate lines GL1 to GLg.

[0077] For this purpose, each stage may include a shift register and two buffers connected to the shift register.

[0078] For example, such as Figure 4 As shown, the nth stage n (where n is an odd number) may include a first shift register 210a and a first signal output unit 220a. The first signal output unit 220a outputs gate pulses GP4n-3, GP4n-1, GP4n+1 and GP4n+3 based on the control signal generated by the first shift register 210. The first signal output unit 220a may include a first-1 buffer 220a_1 and a first-2 buffer 220a_2.

[0079] like Figure 4 As shown, the (n+1)th stage n+1 may include a second shift register 210b and a second signal output unit 220b. The second signal output unit 220b outputs gate pulses GP4n-2, GP4n, GP4n+2 and GP4n+4 based on the control signal generated by the second shift register 210b. The second signal output unit 220b may include a second-first buffer 220b_1 and a second-second buffer 220b_2.

[0080] First, the first shift register 210a may include multiple transistors. To describe the basic structure and function of the first shift register 210a applied in this disclosure, Figure 4 The diagram illustrates the first shift register 210a, which includes two transistors, Tst and Trs, and an inverter, IN. In other words, Figure 4 An example of the first shift register 210a applied to this disclosure is illustrated in the schematic diagram.

[0081] In the first shift register 210a, the start transistor Tst can be turned on by the start signal Vst, and the high voltage VD can be transmitted to the first-1 buffer 220a_1 and the first-2 buffer 220a_2 through the Q node Q. Therefore, the gate pulse can be output from the first-1 buffer 220a_1 and the first-2 buffer 220a_2. The high voltage VD after passing through the start transistor Tst can be converted to a voltage lower than the high voltage by the inverter IN, and can be transmitted to the Qb node Qb.

[0082] When the start transistor Tst is off and the reset transistor Trs is turned on by the reset signal Rest, a low voltage GVSS can be provided to node Q through the reset transistor Trs. The low voltage GVSS can be converted to a voltage higher than the low voltage GVSS by the inverter IN and can be transmitted to node Qb. Therefore, the gate cutoff signal can be output to buffers 1-1 220a_1 and 1-2 220a_2.

[0083] The inverter IN can be configured in various ways, including at least one transistor, to perform the above-described functions. That is, the first shift register 210a can be configured in various ways, including at least three transistors, to perform the above-described functions.

[0084] Second, the second shift register 210b can be formed with the same structure as the first shift register 210a. Therefore, the second shift register 210b can also be formed with various structures including at least three transistors to perform the above-described functions.

[0085] Third, such as Figure 5 As shown, the first-1 buffer 220a_1 may include: a first pull-up transistor Pu1 and a first pull-down transistor for outputting gate pulse and gate cutoff signals to the 4n-3 gate line GL4n-3; and a second pull-up transistor Pu2 and a second pull-down transistor for outputting gate pulse and gate cutoff signals to the 4n-2 gate line GL4n-2. The first pull-up transistor Pu1 and the second pull-up transistor Pu2 may be connected to the Q node Q of the first shift register 210a, and the first pull-down transistor and the second pull-down transistor may be connected to the Qb node Qb of the first shift register 210a.

[0086] Fourth, such as Figure 5 As shown, the first-second buffer 220a_2 may include: a third pull-up transistor Pu3 and a third pull-down transistor for outputting the gate pulse and gate cutoff signal to the 4n+1 gate line GL4n+1; and a fourth pull-up transistor Pu4 and a fourth pull-down transistor for outputting the gate pulse and gate cutoff signal to the 4n+2 gate line GL4n+2. The third pull-up transistor Pu3 and the fourth pull-up transistor Pu4 may be connected to the Q node Q of the first shift register 210a, and the third pull-down transistor and the fourth pull-down transistor may be connected to the Qb node Qb of the first shift register 210a.

[0087] Based on the arrangement of each of the first-1 buffer 220a_1 and the first-2 buffer 220a_2, the first-1 buffer 220a_1 may include a switching transistor TA7c for simultaneously providing the signal applied to the Q node Q to the first pull-up transistors Pu1 to Pu4, and the switching clock CRCLK1 may be provided to the switching transistor TA7c. In this case, to stably perform the operation of the switching transistor TA7c and the first pull-up transistors Pu1 to Pu4, capacitors may be connected to each of the switching transistor TA7c and the first pull-up transistors Pu1 to Pu4.

[0088] Fifth, such as Figure 5As shown, the 2-1 buffer 220b_1 may include: a fifth pull-up transistor Pu5 and a fifth pull-down transistor for outputting the gate pulse and gate cutoff signal to the 4n-1 gate line GL4n-1; and a sixth pull-up transistor Pu6 and a sixth pull-down transistor for outputting the gate pulse and gate cutoff signal to the fourth gate line GL4n. The fifth pull-up transistor Pu5 and the sixth pull-up transistor Pu6 may be connected to the Q node Q of the second shift register 210b, and the fifth pull-down transistor and the sixth pull-down transistor may be connected to the Qb node Qb of the second shift register 210b.

[0089] Sixth, such as Figure 5 As shown, the second-2 buffer 220b_2 may include: a seventh pull-up transistor Pu7 and a seventh pull-down transistor for outputting the gate pulse and gate cutoff signal to the 4n+3 gate line GL4n+3; and an eighth pull-up transistor Pu8 and an eighth pull-down transistor for outputting the gate pulse and gate cutoff signal to the 4n+4 gate line GL4n+4. The seventh pull-up transistor Pu7 and the eighth pull-up transistor Pu8 may be connected to the Q node Q of the second shift register 210b, and the seventh pull-down transistor and the eighth pull-down transistor may be connected to the Qb node Qb of the second shift register 210b.

[0090] Based on the arrangement of each of the 2-1 buffer 220b_1 and the 2-2 buffer 220b_2, a switching transistor T7c can be included in the 2-1 buffer 220b_1 for simultaneously providing the signal applied to the Q node Q to the fifth pull-up transistors Pu5 to the eighth pull-up transistors Pu8, and a switching clock CRCLK1 can be provided to the switching transistor T7c. In this case, to stably perform the operation of the switching transistor T7c and the fifth pull-up transistors Pu5 to the eighth pull-up transistors Pu8, a capacitor can be connected to each of the switching transistor T7c and the fifth pull-up transistors Pu5 to the eighth pull-up transistors Pu8.

[0091] In other words, the first-1 buffer 220a_1 and the second-1 buffer 220b_1 can alternately output gate pulses, and the first-2 buffer 220a_2 and the second-2 buffer 220b_2 can alternately output gate pulses.

[0092] In this case, based on the first gate clock SCCLK1 to the eighth gate clock SCCLK8 provided to the nth and n+1th stages, the 4n-3rd gate pulse GP4n-3 to the 4n+4th gate pulse GP4n+4 can be output sequentially, and the 4n-3rd gate pulse GP4n-3 to the 4n+4th gate pulse GP4n+4 can be provided to the 4n-3rd gate line GL4n-3, the 4n-1st gate line GL4n-1, the 4n-2nd gate line GL4n-2, the 4nth gate line CL4n, the 4n+1st gate line GL4n+1, the 4n+3rd gate line GL4n+3, the 4n+2nd gate line GL4n+2, and the 4n+4th gate line GL4n+4.

[0093] Therefore, as Figure 5 As shown by the dashed arrow A in the diagram, pixels arranged along the data line DL can be driven in a zigzag pattern.

[0094] In other words, according to this disclosure, after providing a data voltage to the first red pixel R1, a data voltage can be provided to the second red pixel R2, and after providing a data voltage to the first white pixel W1, a data voltage can be provided to the second white pixel W2.

[0095] Therefore, according to this disclosure, data toggling can be reduced by half. When data toggling is reduced, the problem of heat generation in the IC constituting the data driver can be resolved. Therefore, the quality of the display device according to this disclosure can be improved.

[0096] Figure 6 The detailed diagrams are above for reference. Figures 3 to 5 An example diagram illustrating the hierarchy is provided. The detailed structure of the hierarchy is not a feature of this disclosure and is therefore omitted. Figure 6 A detailed description of the structure and function of each transistor shown is provided, and reference will be made to... Figure 6 Describe the basic structure and functions of the description level. The following text will refer to... Figure 6 The following description describes level n, and the description below can be applied to level n+1.

[0097] For example, in constituting Figure 6 In the first shift register 210a of the nth stage shown, when the start transistor Tst is turned on by the start signal Vst, a high voltage VD can be provided to the first-1 buffer 220a_1 and the first-2 buffer 220a_2 through the Q node Q. The switching transistor T7c and capacitor Ca located at the front end of the first-1 buffer 220a_1 and the second buffer 220a_2 can perform the function of stably providing the high voltage VD provided to the Q node Q to the first-1 buffer 220a_1 and the first-2 buffer 220a_2.

[0098] In this configuration, by sequentially inputting the first gate clock SCCLK1, the third gate clock SCCLK3, the fifth gate clock SCCLK5, and the seventh gate clock SCCLK7, the first pull-up transistor Tu1 to the fourth pull-up transistor Tu4 can be sequentially turned on, and the 4n-3 gate pulse GP4n-3, the 4n-1 gate pulse GP4n-1, the 4n+1 gate pulse GP4n+1, and the 4n+3 gate pulse GL4n+3 can be sequentially output to the 4n-3 gate line GL4n-3, the 4n-1 gate line GL4n-1, the 4n+1 gate line GL4n+1, and the 4n+3 gate line GL4n+3.

[0099] Furthermore, when the start transistor Tst is turned off and the reset transistor Trs is turned on by the reset signal Rest, a low voltage GVSS can be provided to the Q node Q through the reset transistor Trs. In this case, because the first pull-up transistors Tu1 to the fourth pull-up transistors Tu4 are turned off by the low voltage GVSS, the first-1 buffer 220a_1 and the first-2 buffer 220a_2 no longer need to output gate pulses.

[0100] In this configuration, the low voltage GVSS can be converted to a voltage higher than the low voltage GVSS by the circuit constituting the inverter In, and can be provided to the Qb node Qb. Therefore, the gate cutoff signal can be output through the first pull-down transistors Td1 to Td4 included in the first-1 buffer 220a_1 and the first-2 buffer 220a_2. Figure 6 In this configuration, a voltage higher than the low voltage GVSS can be alternately provided to the Qb node Qb and the Qb_e node Qb_e. That is, the gate cutoff signal can be continuously output to the gate line for all periods within a frame cycle except for the timing of the output gate pulse. In this case, when the gate cutoff signal is output to a gate line through a single pull-down transistor, that single pull-down transistor may degrade within a short period. To address this issue, such as... Figure 6 As shown, two pull-down transistors can be placed in a single gate line, and a voltage higher than the low voltage GVSS can be alternately supplied to the Qb node Qb and the Qb_e node Qb_e. For example, in the first frame, the first pull-down transistor Td1 can be turned on, and the gate cutoff signal can be output to the 4n-3 gate line GL4n-3 through the first pull-down transistor Td1. In the second frame, the 1-1 pull-down transistor Td1a can be turned on, and the gate cutoff signal can be output to the 4n-3 gate line GL4n-3 through the 1-1 pull-down transistor Td1a. Furthermore, the 2-1 transistors Td2a to Td4a and the second pull-down transistors Td2 to Td4 can be turned on alternately.

[0101] As shown above (refer to the reference) Figure 4 As described, Figure 6 The first shift register 210a shown may include a start transistor Tst, a reset transistor Trs, and various transistors that constitute the inverter IN.

[0102] In this case, the second shift register 210b, the second-first buffer 220b_1, and the second-second buffer 220b_2 constituting the n+1 stage can be configured in the same form as the first shift register 210a, the first-first buffer 220a_1, and the first-second buffer 220a_2 constituting the nth stage.

[0103] Figure 7 This is an example diagram illustrating the structure of a light-emitting display panel applied to a light-emitting display device according to this disclosure. Figure 8 This is an example diagram illustrating the arrangement structure of the stages applied to a light-emitting display device according to this disclosure. Figure 9 The diagram is set in Figure 8 An example diagram of the signal lines in the horizontal section shown. Figure 10 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure. In the following description, descriptions of the above references will be omitted or briefly summarized. Figures 1 to 6 The details described are the same or similar.

[0104] The light-emitting display device according to this disclosure may include a gate driver 300, which includes stages 1 to g / 4 in a substrate 101 and gate lines GL1 to GLg connected to stages 1 to g / 4.

[0105] As shown above (refer to the reference) Figures 3 to 6 Each of the described stages, from Stage 1 to Stage g / 4, may include a shift register and two buffers connected to that shift register.

[0106] First, the first-1 buffer 220a_1 and the first shift register 210a of the two buffers constituting the nth stage n can be set in the nth level part Hn, and the first-2 buffer 220a_2 of the two buffers can be set in the n+2 level part Hn+2 (where n is an odd number).

[0107] In addition, the second-2 buffer 220b_2, which constitutes the second-1st stage (Stage n+1), and the second shift register 210b, which constitutes the second-1st stage (Stage n+1), can be set in the (n+3)th level portion Hn+3, and the second-1 buffer 220b_1, which constitutes the second-1st stage (Stage n+1), can be set in the (n+1)th level portion Hn+1.

[0108] The nth horizontal portion Hn can be a region including pixels arranged along the (4n-3)th and (4n-2)th gate lines, the (n+1)th horizontal portion Hn+1 can be a region including pixels arranged along the (4n-1)th and (4n)th gate lines, the (n+2)th horizontal portion Hn+2 can be a region including pixels arranged along the (4n+1)th and (4n+2)th gate lines, and the (n+3)th horizontal portion Hn+3 can be a region including pixels arranged along the (4n+3)th and (4n+4)th gate lines.

[0109] For example, when n is 1, such as Figure 7 and Figure 8 As shown, the first buffer 220a_1, which constitutes the first stage 1, and the first shift register 210a, which constitutes the first stage 1, can be set in the first level section H1, and the first buffer 220a_2, which constitutes the first stage 1, can be set in the third level section H3.

[0110] Furthermore, the second-2 buffer 220b_2, which constitutes the second Stage 2, and the second shift register 210b, which constitutes the second Stage 2, can be set in the fourth level section H4, and the second-1 buffer 220b_1, which constitutes the second stage 2, can be set in the second level section H2.

[0111] The first horizontal portion H1 may be a region including pixels arranged along the first gate line GL1 and the second gate line GL2, the second horizontal portion H2 may be a region including pixels arranged along the third gate line GL3 and the fourth gate line GL4, the third horizontal portion H3 may be a region including pixels arranged along the fifth gate line GL5 and the sixth gate line GL6, and the fourth horizontal portion H4 may be a region including pixels arranged along the seventh gate line GL7 and the eighth gate line GL8.

[0112] In other words, in this disclosure, each horizontal section may include a branch circuit unit BC, and the branch circuit unit BC includes at least one transistor constituting a stage. For example... Figure 7 As shown, branch circuit units BC can be disposed between pixels 110. In particular, branch circuit units BC can be disposed between unit pixels 110a arranged along two adjacent gate lines.

[0113] For example, such as Figure 7 As shown, when a unit pixel 110a includes a red pixel R, a blue pixel B, a white pixel W, and a green pixel G, the four pixels 110 can be arranged along two adjacent gate lines (e.g., GL1 and GL2). In particular, the red pixel R and the blue pixel B can be arranged adjacent to each other along one gate line (e.g., GL1), the white pixel W and the green pixel G can be arranged adjacent to each other along another gate line (e.g., GL2), and the red pixel R, the blue pixel B, the white pixel W, and the green pixel G can also be arranged adjacent to each other.

[0114] In this case, the unit pixel 110a and the branch circuit unit BC can be arranged alternately along two adjacent gate lines (e.g., GL1 and GL2).

[0115] However, when the number of unit pixels 110a is greater than the number of transistors disposed in a horizontal portion H, transistors may not be disposed in the branch circuit unit BC. That is, a branch circuit unit BC that does not contain transistors may exist. In the following text, the branch circuit unit BC that does not contain transistors may simply be referred to as a virtual branch circuit.

[0116] To provide additional description, Figure 6 The first shift register 210a shown may include thirty transistors, nine transistors may be set in the first-1 buffer 220a_1, and six transistors may be set in the first-2 buffer 220a_2.

[0117] In this configuration, the first shift register 210a and the first-1 buffer 220a_1 may include thirty-nine transistors. Therefore, the horizontal portion in which the first shift register 210a and the first-1 buffer 220a_1 are located may include thirty-nine first branch circuit units BC1, and the horizontal portion in which the first-2 buffer 220a_2 is located may include six first branch circuit units BC1.

[0118] Therefore, the horizontal portion in which the second shift register 210b and the second-2 buffer 220b_2 are located may include thirty-nine second branch circuit units BC2, and the horizontal portion in which the second-1 buffer 220b_1 is located may include six second branch circuit units BC2.

[0119] The first-1 buffer 220a_1 constituting the nth stage n can be connected to the 4n-3 gate line GL4n-3 and the 4n-2 gate line GL4n-2, and the first-2 buffer 220a_2 constituting the nth stage n can be connected to the 4n+1 gate line GL4n+1 and the 4n+2 gate line GL4n+2.

[0120] For example, when n is 1, such as Figures 3 to 8 As shown, the first-1 buffer 220a_1 constituting the first stage 1 can be connected to the first gate line GL1 and the second gate line GL2, and the first-2 buffer 220a_2 constituting the first stage 1 can be connected to the fifth gate line GL5 and the sixth gate line CL6.

[0121] The 2-2 buffer 220b_2 constituting Stage n+1 can be connected to the 4n+3 gate line GL4n+3 and the 4n+4 gate line GL4n+4, and the 2-1 buffer 220b_1 constituting Stage n+1 can be connected to the 4n-1 gate line GL4n-1 and the 4n gate line GL4n.

[0122] For example, such as Figures 3 to 8 As shown, when n is 1, the 2-2 buffer 220b_2 constituting the second stage 2 can be connected to the seventh gate line GL7 and the eighth gate line GL8, and the 2-1 buffer 220b_1 constituting the second stage 2 can be connected to the third gate line GL3 and the fourth gate line GL4.

[0123] At least one nth signal line 203 connected to the first-1 buffer 220a_1 and the first shift register 210a, and three n+1th signal lines 204 connected to the second-1 buffer 220b_1, can be set in the nth signal line portion SLn between the nth horizontal portion Hn and the (n+1)th horizontal portion Hn+1.

[0124] At least one of the three nth signal lines 203 can extend to the n+2 signal line portion SLn+2 between the n+2 horizontal portion Hn+2 and the n+3 horizontal portion Hn+3.

[0125] The three (n+1)th signal lines 204 can be extended to the (n+2)th signal line portion SLn+2.

[0126] At least one of the (n+1)th signal lines can be further configured in the (n+2)th signal line section SLn+2 to be connected to the (2-2)th buffer 220b_2 and the second shift register 210b.

[0127] For example, when n is 1, such as Figures 7 to 9 As shown, at least one first signal line 203 connected to the first-1 buffer 220a_1 and the first shift register 210a, and three second signal lines 204 connected to the second-1 buffer 220b_1 can be provided in the first signal line portion SL1 between the first horizontal portion H1 and the second horizontal portion H2.

[0128] At least one of the three first signal lines 203 in the nth signal line 203 can extend to the third signal line portion SL3 between the third horizontal portion H3 and the fourth horizontal portion H4.

[0129] The three second signal lines 204 can extend to the third signal line section SL3.

[0130] At least one second signal line 204 may be further configured to be connected to the second-2 buffer 220b_2 and the second shift register 210b.

[0131] Here, the nth signal line 203 or the first signal line 203 can represent the line included in the nth stage n, and the (n+1)th signal line 204 or the second signal line 204 can represent the line included in the (n+1)th stage n+1.

[0132] For example, in the level implementation applied to the content of this disclosure as follows Figure 6 In the case shown, such as Figure 9 As shown, the nth horizontal section Hn may include seven nth signal lines 203 and three (n+1)th signal lines 204.

[0133] The seven nth signal lines 203 may include lines LQ, LQb, LQb_e, and L4 to L7, which are connected to nodes Q, Qb, Qb_e, and Qb_e. Figure 6 The nth stage n shown includes the fourth node N4 to the seventh node N7.

[0134] The three (n+1)th signal lines 204 may include lines LQ, LQb, and LQb_e, which are connected to the Q nodes Q, Qb nodes Qb, and Qb_e nodes Qb_e included in the (n+1)th stage.

[0135] like Figures 7 to 9As shown, for the purpose of providing additional description, seven first signal lines 203 connected to the first-1 buffer 220a_1 and the first shift register 210a, and three second signal lines 204 connected to the second-1 buffer 220b_1 may be provided in the first signal line portion SL1 between the first horizontal portion H1 and the second horizontal portion H2.

[0136] However, the number of first signal lines 203 and the number of second signal lines 204 can be varied according to the structure of the stage.

[0137] The line LQ connected to the Q node included in the nth level, the line LQb connected to the Qb node, and the line LQb_e connected to the Qb_e node can be connected together to the first-1 buffer 220a_1 and the first-2 buffer 220a_2.

[0138] In addition, the line LQ connected to the Q node included in the (n+1)th stage, the line LQb connected to the Qb node, and the line LQb_e connected to the Qb_e node can be connected together to the 2-1 buffer 220b_1 and the 2-2 buffer 220b_2.

[0139] Therefore, the three nth signal lines 203 included in the (n+2)th signal line section SLn+2 can be connected to the first-second buffer 220a_2, and the three n+1th signal lines 204 included in the (n+2)th signal line section SLn+2 can be connected to the second-second buffer 220b_2 and the second shift register 210b.

[0140] For example, in Figure 9 In the first-1 buffer 220a_1, the three lines connected to the first-1 buffer 220a_1 (i.e., line LQ connected to the Q node, line LQb connected to the Qb node, and line LQb_e connected to the Qb_e node) can be extended to the third signal line section SL3 and can be connected to the first-2 buffer 220a_2.

[0141] In addition, Figure 9 In the middle, the three lines connected to the second-1 buffer 220b_1 (i.e., line LQ connected to the Q node, line LQb connected to the Qb node, and line LQb_e connected to the Qb_e node) can extend to the third signal line section SL3 and can be connected to the second-1 buffer 220b_1 and the second shift register 210b.

[0142] In this case, the third signal line section SL3 may include three nth signal lines 203 extending from the first signal line section SL1, three n+1th signal lines 204 extending from the first signal line section SL1, and four n+1th signal lines connected to the second-1st buffer 220b_1 and the second shift register 210b.

[0143] Therefore, each of the first signal line portion SL1 and the third signal line portion SL3 may include ten signal lines.

[0144] In other words, Figure 6 In the nth stage n shown, the first shift register 210a, the first-1 buffer 220a_1 and the first-2 buffer 220a_2 can be connected by seven signal lines, and the first-1 buffer 220a_1 and the first-2 buffer 220a_2 can be connected by three signal lines.

[0145] Therefore, in Stage n+1, which is implemented with the same structure as Stage n, the second shift register 210b, the second-1 buffer 220b_1 and the second-2 buffer 220b_2 can be connected by seven signal lines, and the second-1 buffer 220b_1 and the second-2 buffer 220b_2 can be connected by three signal lines.

[0146] When the structure of each of the nth and (n+1)th stages changes, the number of signal lines included in each signal line section can change.

[0147] In this case, signal lines may not be provided at the upper end of the first horizontal portion H1, the second signal line portion between the second horizontal portion H2 and the third horizontal portion H3, and the fourth signal line portion between the fourth horizontal portion H4 and the fifth horizontal portion H5.

[0148] However, the width of the upper end of the first horizontal portion H1, the width of each horizontal portion, and the width of the lower end of the g / 2 horizontal portion Hg / 2 can be formed equally. Therefore, all areas of the light-emitting display panel can be formed with the same structure.

[0149] also, Figure 9 The metal wire ML shown may be provided Figure 6 The lines shown are the high voltage VD, GVDD_o and GVDD_e, the low voltage GVSS, and the clock lines CRCLK1, SCCLK1, SCCLK3, SCCLK5, and SCCLK7. Figure 9 Among the metal lines ML shown, there may be virtual metal lines that do not provide any signal.

[0150] As described above, the three nth signal lines 203 and the three (n+1)th signal lines 204 should extend to the same signal line portion SL.

[0151] In this case, the ends of one side of the three nth signal lines 203 included in the nth signal line portion SLn and the ends of one side of the three n+1th signal lines 204 included in the (n+1)th signal line portion SLn+1 can be... Figure 7 and Figure 8 The same region shown extends to the (n+2)th signal line portion SLn+2.

[0152] For further explanation, one end of one side of the three nth signal lines 203 included in the nth signal line portion SLn can extend to the (n+2)th signal line portion SLn+2 through a first region where the gate lines included in the (n+1)th horizontal portion Hn+1 and the (n+2)th horizontal portion Hn+2 are disposed, and one end of one side of the three (n+1)th signal lines 204 included in the nth signal line portion SLn can extend to the (n+2)th signal line portion SLn+2 through the first region. Here, the first region can be either the left end or the right end of the light-emitting display panel.

[0153] In other words, Figure 7 and Figure 8 In the light-emitting display panel shown, the ends of one side of the three nth signal lines 203 included in the nth signal line portion SLn and the ends of one side of the three n+1 signal lines 204 included in the n+1 signal line portion SLn+1 can extend from the left end of the light-emitting display panel to the n+2 signal line portion SLn+2.

[0154] However, the ends of one side of the three nth signal lines 203 included in the nth signal line portion SLn and the ends of one side of the three n+1th signal lines 204 included in the (n+1)th signal line portion SLn+1 can extend from the right end of the light-emitting display panel to the (n+2)th signal line portion SLn+2.

[0155] Finally, the ends of one side of the three nth signal lines 203 included in the nth signal line portion SLn and the ends of one side of the three n+1 signal lines 204 included in the n+1 signal line portion SLn+1 can extend to the n+2 signal line portion SLn+2 through different regions.

[0156] For further explanation, one end of one side of the three nth signal lines 203 included in the nth signal line portion SLn can extend to the (n+2)th signal line portion SLn+2 through a first region where the end of the gate line included in the (n+1)th horizontal portion Hn+1 and the (n+2)th horizontal portion Hn+2 is disposed, and the end of one side of the three nth signal lines 203 included in the nth signal line portion SLn can extend to the (n+2)th signal line portion SLn+2 through a second region where the end of the gate line included in the (n+1)th horizontal portion Hn+1 and the (n+2)th horizontal portion Hn+2 is disposed, on the other side. Here, the first region and the second region can represent opposing regions facing each other. For example, in Figure 7 In the first region, the gate line GL is located between the left end of the gate line GL and the end of the light-emitting display panel, and the second region is located between the right end of the gate line GL and the end of the light-emitting display panel.

[0157] In other words, Figure 10 In the light-emitting display panel shown, the ends of one side of the three nth signal lines 203 included in the nth signal line portion SLn can extend from the left end of the light-emitting display panel to the (n+2)th signal line portion SLn+2, and the ends of one side of the three (n+1)th signal lines 204 included in the (n+1)th signal line portion SLn+1 can extend from the right end of the light-emitting display panel to the (n+2)th signal line portion SLn+2.

[0158] Figure 11 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure. In the following description, descriptions related to the above references will be omitted or briefly described. Figures 1 to 10 The details described are the same or similar.

[0159] When the width of the light-emitting display panel increases, the length of the gate lines can increase, thus reducing the gate pulse transmission speed. In this case, the magnitude and phase of the gate pulse can be changed depending on the position of the gate lines.

[0160] To address this issue, as detailed in this disclosure, such as Figure 11 As shown, levels can be set in each of the left and right areas of the luminous display panel.

[0161] In this case, the substrate 101 constituting the light-emitting display panel can be divided into a left region and a right region based on the boundary corresponding to the direction perpendicular to the gate line. That is, the substrate 101 can be divided into a left region and a right region based on the boundary line BL passing through the center of the substrate 101.

[0162] First, you can set the reference above in the left area. Figures 1 to 10The nth stage (Stage n) and the (n+1)th stage (Stage n+1) are described.

[0163] In the right-hand region, we can set the nth right-hand stage n_R corresponding to the nth stage n and the (n+1)th right-hand stage n+1_R corresponding to the (n+1)th stage n+1. The nth right-hand stage n_R and the (n+1)th right-hand stage n+1_R can be implemented with the same structure as the nth stage n and the (n+1)th stage n+1.

[0164] For example, such as Figure 11 As shown, a first stage 1 and a second stage 2 can be set in the left area, and a first right stage 1_R and a second right stage 2_R corresponding to the first stage 1 can be set in the right area. A first right-side branch circuit unit BC1_R can be included in the first right-side stage 1_R, and a second right-side branch circuit unit BC2_R can be included in the second right-side stage 2_R.

[0165] In the (n+2)th level Hn+2, the third-to-second buffer R220a_2 and the third shift register R210a of the two buffers constituting the nth right stage Stage n_R can be set. In the (n+2)th level Hn, the third-to-first buffer R220a_1 of the two buffers can be set. In the (n+1)th level Hn+1, the fourth-to-first buffer R220b_1 and the third shift register R210b of the two buffers constituting the n+1 right stage Stage+1_R can be set. In the (n+3)th level Hn+3, the fourth-to-second buffer R220b_2 of the two buffers can be set.

[0166] As described above, the number of transistors included in the first shift register 210a and the second shift register 210b can be greater than the number of transistors included in the first-1 buffer 220a_1, the first-2 buffer 220a_2, the second-1 buffer 220b_1, and the second-2 buffer 220b_2.

[0167] Therefore, when two shift registers are located in the same horizontal section, the transistors included in the two shift registers may not be located in the horizontal section.

[0168] Therefore, a shift register and two buffers can be set up in a horizontal section.

[0169] In this configuration, buffer 3-2 R220a_2 can be connected to gate lines 4n+1 and 4n+2, and buffer 3-1 R220a_1 can be connected to gate lines 4n-3 and 4n-2. Buffer 4-1 R220b_1 can be connected to gate lines 4n-1 and 4n, and buffer 4-2 R220b_2 can be connected to gate lines 4n+3 and 4n+4.

[0170] Therefore, buffer 220a_1 (first-first) and buffer R220a_1 (third-first) can output the same gate pulse, buffer 220a_2 (first-second) and buffer R220a_2 (third-second) can output the same gate pulse, buffer 220b_1 (second-first) and buffer R220b_1 (fourth-first) can output the same gate pulse, and buffer 220b_2 (second-second) and buffer R220b_2 (fourth-second) can output the same gate pulse.

[0171] In other words, the first shift register 210a can be implemented with the same structure as the third shift register R210a, the second shift register 210b can be implemented with the same structure as the fourth shift register R210b, the first-1 buffer 220a_1 and the third-1 buffer R220a_1 can be implemented with the same structure, the first-2 buffer 220a_2 and the third-2 buffer R220a_2 can be implemented with the same structure, the second-1 buffer 220b_1 and the fourth-1 buffer R220b_1 can be implemented with the same structure, and the second-2 buffer 220b_1 and the fourth-2 buffer R220b_2 can be implemented with the same structure.

[0172] The gate lines GL4n-3 and GL4n-2 included in the nth horizontal portion Hn, and the gate lines GL4n+1 and GL4n+2 included in the n+2th horizontal portion Hn+2, can be connected to the nth stage n and the nth right stage n_R. For example, in Figure 11 In this configuration, the first stage 1 and the first right stage 1_R can be connected to the same gate line.

[0173] Furthermore, the 4n-1 gate line GL4n-1 and the 4th gate line GL4n included in the (n+1)th horizontal portion Hn+1, and the 4n+3 gate line GL4n+3 and the 4n+4 gate line GL4n+4 included in the (n+3)th horizontal portion Hn+3, can be connected to the (n+1)th stage n+1 and the (n+1)th right stage stage n+1_R. For example, in Figure 11 In this configuration, the second stage Stage 2 and the second right stage Stage2_R can be connected to the same gate line.

[0174] In other words, Stage n and Stage n_R (the rightmost stage of the nth stage) can be connected to the same gate line, and Stage n+1 and Stage n+1_R (the rightmost stage of the n+1 stage) can be connected to the same gate line.

[0175] Finally, as Figure 11 As shown, three nth signal lines 203 connecting the first-1 buffer 220a_1 to the first-2 buffer 220a_2 and three (n+1)th signal lines 204 connecting the second-1 buffer 220b_1 to the second-2 buffer 220b_2 can be provided in the first region (e.g., through different signal line portions at the left end of the light-emitting display panel).

[0176] In this case, such as Figure 11 As shown, three nth right signal lines 203a connecting the 3-1st buffer R220a_1 to the 3-2nd buffer R220a_2 and three (n+1)th right signal lines 204a connecting the 4-1st buffer R220b_1 to the 4-2nd buffer R220b_2 can be provided in a second region opposite to the first region (e.g., different signal line portions passing through the right end of the light-emitting display panel).

[0177] When signal lines 203, 203a, 204 and 204a overlap with the gate line, noise can be applied to the gate line, causing abnormal operation of each switching transistor Tsw1. Therefore, signal lines 203, 203a, 204 and 204a can be positioned in a location that does not overlap with the gate line.

[0178] Figure 12 This is another example diagram illustrating the arrangement of stages applied to a light-emitting display device according to this disclosure. Except that the gate lines are separated from each other with reference to the boundary line BL, Figure 12 The light-emitting display panel shown can have the same characteristics as... Figure 11 The structure is the same as that of the light-emitting display panel shown. Therefore, in the following text, only the description will be used. Figure 12 and Figure 11 Different characteristics.

[0179] First, right gate lines GL4-3a to GL4n+4a, corresponding to the gate lines GL4n-3 to GL4n+4, which are disposed in the left region of the substrate, can be provided in the right region of the substrate.

[0180] In this case, the 4n-3 gate line GL4n-3 to the 4n+4 gate line GL4n+4 can be separated from the 4n-3 right gate line GL4-3a to the 4n+4 right gate line GL4n+4a.

[0181] Gate lines GL4n-3 (4n-3), GL4n-2 (4n-2), GL4n+1 (4n+1), and GL4n+2 (4n+2) can be connected to stage n, and right gate lines GL4n-3a (4n-3), GL4n-2a (4n-2), GL4n+1a (4n+1), and GL4n+2a (4n+2) can be connected to stage n_R (n-right stage).

[0182] Gate lines GL4n-1 (4n-1), GL4n (4n), GL4n+3 (4n+3), and GL4n+4 (4n+4) can be connected to Stage n+1 (n+1), and right gate lines GL4n-1a (4n-1), GL4na (4n-3), GL4n+3a (4n+3), and GL4n+4a (4n+4) can be connected to Stage n+1 (n+1) ...

[0183] Finally, as Figure 12 As shown, three nth signal lines 203 connecting the first-1 buffer 220a_1 to the first-2 buffer 220a_2 can be provided in a first region (e.g., through different signal line portions at the left end of the light-emitting display panel), and three (n+1)th signal lines 204 connecting the second-1 buffer 220b_1 to the second-2 buffer 220b_2 can be provided in a third region opposite to the first region (e.g., through different signal line portions of the region adjacent to the left side of the boundary line BL).

[0184] In other words, Figure 12 In the light-emitting display panel shown, because the gate lines are separated from each other with reference to the boundary line BL, even when the (n+1)th signal line 204 is arranged near the boundary line BL, the (n+1)th signal line 204 will not overlap with the gate line. Therefore, no problems will occur caused by the (n+1)th signal line 204 and the gate line overlapping.

[0185] In this case, such as Figure 12As shown, three nth signal lines 203a connecting the third buffer R220a_1 to the third buffer R220a_2 can be provided in a second region opposite to the first region (e.g., different signal line portions passing through the right end of the light-emitting display panel), and three (n+1)th right signal lines 204a connecting the fourth-first buffer R220b_1 to the fourth-second buffer R220b_2 can be provided in a fourth region opposite to the second region (e.g., different signal line portions passing through the region adjacent to the right side of the boundary line BL).

[0186] However, the nth signal line 203 and the nth right signal line 203a can be set on the left and right sides of the boundary line BL, and the (n+1)th signal line 204 and the (n+1)th right signal line 204a can be set on the left and right sides of the light-emitting display panel.

[0187] Figure 13 It is used to describe Figure 5 The waveform diagram of the driving method of the stage shown in the figure. Figure 14 It is a diagram Figure 4 An example diagram of the structure of each of the first signal output unit and the second signal output unit shown is provided. Figure 15 It is used to describe Figure 14 The waveform diagram of the driving method of the stage is shown.

[0188] As described above, the gate pulses can be sequentially output to gate lines 4n-3, 4n-1, 4n-2, 4n, 4n+1, 4n+3, 4n+2, and 4n+4, and this output pattern can be represented as a zigzag. Gate pulses GP1 to GP8 can be generated based on the gate clocks SCCLK1 to SCCLK8 described below. That is, the first gate clock SCCLK1 to the eighth gate clock SCCLK8 provided to buffers 1-1, 1-2, and 2-2 can be the first gate pulse GP1 to the eighth gate pulse GP8.

[0189] Therefore, such as Figure 5 and Figure 13 As shown, the first gate clock SCCLK1 and the third gate clock SCCLK3 can be provided to the first-1 buffer 220a_1, the fifth gate clock SCCLK5 and the seventh gate clock SCCLK7 can be provided to the first-2 buffer 220a_2, the second gate clock SCCLK2 and the fourth gate clock SCCLK4 can be provided to the second-1 buffer 220b_1, and the sixth gate clock SCCLK6 and the eighth gate clock SCCLK8 can be provided to the second-2 buffer 220b_2.

[0190] In this case, the first Q-node signal Q1 applied to the Q-node Q of the nth stage n can fall together with the fall of the first gate clock SCCLK1, the third gate clock SCCLK3, the fifth gate clock SCCLK5 and the seventh gate clock SCCLK7, and can rise together with the rise of the first gate clock SCCLK1, the third gate clock SCCLK3, the fifth gate clock SCCLK5 and the seventh gate clock SCCLK7.

[0191] Furthermore, the second Q-node signal Q2 applied to the Q-node Q of Stage n+1 can fall together with the fall of the second gate clock SCCLK2, the fourth gate clock SCCLK4, the sixth gate clock SCCLK6, and the eighth gate clock SCCLK8, and can rise together with the rise of the second gate clock SCCLK2, the fourth gate clock SCCLK4, the sixth gate clock SCCLK6, and the eighth gate clock SCCLK8.

[0192] In other words, such as Figure 13 As shown, when the gate clocks do not overlap, the conditions for all gate clocks rising can be the same as the conditions for all gate clocks falling.

[0193] Therefore, the waveforms of all gate pulses generated based on the gate clock can remain in the same form.

[0194] However, as the resolution of light-emitting display devices increases, gate pulses should be supplied to more gate lines simultaneously, so the interval between gate clocks can be reduced.

[0195] Therefore, gate clocks can be overlapped.

[0196] In this scenario, because the effect of the first gate clock's decline is offset by the effect of the third gate clock's rise, and the effect of the third gate clock's decline is offset by the effect of the fifth gate clock's rise, the first Q-node signal Q1 applied to the Q-node Q of Stage n can remain at the same level as the first gate clock while providing the first, third, and fifth gate clocks. Therefore, the first, third, and fifth gate clocks can be output in the same manner.

[0197] However, since there is no rising signal at the falling time of the seventh gate clock, the first Q-node signal Q1 can fall. Therefore, the conditions for outputting the seventh gate pulse at the seventh gate clock can be different from the conditions for outputting the first, second, and fifth gate pulses based on the first, third, and fifth gate clocks.

[0198] Therefore, the waveform of the seventh gate pulse based on the seventh gate clock can be different from the waveforms of the first gate pulse, the second gate pulse, and the fifth gate pulse.

[0199] The same phenomenon can also occur in the second Q-node signal Q2 applied to the Q-node Q of Stage n+1. Therefore, the waveform of the eighth gate pulse based on the eighth gate clock can be different from the waveforms of the second, fourth, and sixth gate pulses based on the second, fourth, and sixth gate clocks.

[0200] To prevent this problem, such as Figure 14 As shown, the first stabilizing capacitor C1 can be connected to the Q node Q of the nth stage n, and the second stabilizing capacitor C2 can be connected to the Q node Q of the (n+1)th stage n+1.

[0201] In this case, the ninth gate clock SCCLK9 ​​can be provided to the first stabilizing capacitor C1, and the tenth gate clock SCCLK10 can be provided to the second stabilizing capacitor C2.

[0202] For example, the ninth gate clock SCCLK9 ​​can rise when the seventh gate clock SCCLK7 falls, and the tenth gate clock SCCLK10 can rise when the eighth gate clock SCCLK8 falls.

[0203] Therefore, since the effect of the seventh gate clock SCCLK7 falling is canceled out by the effect of the ninth gate clock SCCLK9 ​​rising, the level of the first Q node signal Q1 when the seventh gate clock SCCLK7 falls can be the same as the level of the first Q node signal Q1 when the first gate clock SCCLK1, the third gate clock SCCLK3, and the fifth gate clock SCCLK5 fall.

[0204] Therefore, the waveform of the seventh gate pulse GP7 based on the seventh gate clock SCCLK7 can be the same as the waveforms of the first gate pulse GP1, the third gate pulse GP3, and the fifth gate pulse GP5 based on the first gate clock SCCLK1, the third gate clock SCCLK3, and the fifth gate clock SCCLK5.

[0205] Furthermore, since the effect of the eighth gate clock SCCLK8 falling is canceled out by the effect of the tenth gate clock SCCLK10 rising, the level of the second Q node signal Q2 when the eighth gate clock SCCLK8 falls can be the same as the level of the second Q node signal Q2 when the second gate clock SCCLK2, the fourth gate clock SCCRK4, and the sixth gate clock SCCLK6 fall.

[0206] Therefore, the waveform of the eighth gate pulse GP8 based on the eighth gate clock SCCLK8 can be the same as the waveforms of the second gate pulse GP2, the fourth gate pulse GP4, and the sixth gate pulse GP6 based on the second gate clock SCCLK2, the fourth gate clock SCCLK4, and the sixth gate clock SCCLK6.

[0207] Therefore, gate pulses of the same form can be output to all gate lines.

[0208] Therefore, the quality of light-emitting display devices can be improved.

[0209] According to this disclosure, compared with the light-emitting display panels of related technologies, the number of transistors included in a stage and the number of signal lines connected to a stage can be reduced.

[0210] Therefore, even as the resolution of the light-emitting display panel increases, all signal lines connected to the stage can be included in the display area.

[0211] Furthermore, according to this disclosure, since four gate pulses are output from one stage, the number of stages can be reduced, and therefore, the area where stages are set can be reduced compared to light-emitting display panels of the related art.

[0212] Furthermore, according to this disclosure, data switching can be reduced by half. When data switching is reduced, the problem of overheating in the IC constituting the data driver can be resolved. Therefore, the quality of the display device according to this disclosure can be improved.

[0213] A light-emitting display panel according to embodiments of this disclosure may include: a plurality of data lines DL1, ..., DLd extending in a first direction; g gate lines GL1, ..., GLg extending in a second direction different from the first direction, the g gate lines GL1, ..., GLg being divided into g / 2 adjacent gate line pairs, where g is a multiple of 4; a plurality of sub-pixels, wherein each sub-pixel is disposed at the intersection of a corresponding gate line GL and a corresponding data line DL and is connected to the corresponding gate line GL and the corresponding data line DL; a plurality of horizontal portions H, wherein each horizontal portion H is a region including a sub-pixel connected to one of the adjacent gate line pairs, and includes a plurality of branch circuit units BC; a plurality of signal line portions SL, each signal line portion being a region between two adjacent horizontal portions H; and a gate driver for driving the gate lines, the gate driver including g / 4 stages Stage1, ..., Stage g / 4, wherein the g / 4 stages are divided into n stage pairs (Stage n, Stage n+1), where n is an odd number, and each stage pair (Stage n, Stage n+1) includes the nth stage. n and n+1 Stage n+1; Stage 1 includes: a first shift register 210a, a first-1 buffer 220a_1, and a first-2 buffer 220a_2, wherein the two buffers 220a_1 and 220a_2 are connected to the first shift register 210a; wherein the first shift register 210a and the first-1 buffer 220a_1 and the first-2 buffer 220a_2 each include a plurality of transistors T deposited in the branch circuit unit BC, wherein the first-1 buffer 220a_1 is further connected to a first adjacent gate pair (GL4n- 3, GL4n-2), and the transistor T included in the first shift register 210a and the first-1 buffer 220a_1 is deposited in the branch circuit unit BC included in the first horizontal portion H1 corresponding to the first adjacent gate line pair (GL4n-3, GL4n-2), and is connected by a first signal line 203 arranged in the first signal line portion SL1, which is located between the first horizontal portion H1 and the second horizontal portion H2 corresponding to the second adjacent gate line pair (GL4n-1, GL4n);Furthermore, the first-second buffer 220a_2 is further connected to the third adjacent gate line pair (GL4n+1, GL4n+2), and the transistor T included in the first-second buffer 220a_2 is deposited in the branch circuit unit BC included in the third horizontal portion H3 corresponding to the third adjacent gate line pair (GL4n+1, GL4n+2), and connected via another first signal line 203 arranged in the third signal line portion SL3, the third signal line portion SL3 being located between the third horizontal portion H3 and the fourth horizontal portion H4 corresponding to the fourth adjacent gate line pair (GL4n+3, GL4n+4); wherein each of the other first signal lines 203 includes a corresponding first extension extending through a region at the right or left end of the light-emitting display panel, the first extension being connected to a corresponding first signal line 203 among the first signal lines 203.

[0214] In some embodiments of this disclosure, the second stage 2 includes: a second shift register 210b, a second-1 buffer 220b_1, and a second-2 buffer 220b_2, wherein the two buffers 220b_1 and 220b_2 are connected to the second shift register 210b; wherein the second shift register 210b and the second-1 buffer 220b_1 and the second-2 buffer 220b_2 each include a plurality of transistors T deposited in the branch circuit unit BC, wherein the second-2 buffer 220b_2 is further connected to the fourth phase. The adjacent gate line pairs (GL4n+3, GL4n+4) and the transistor T included in the second shift register 210b and the second-2 buffer 220b_2 are deposited in the branch circuit unit BC included in the fourth horizontal portion H4; and the second-1 buffer 220b_1 is further connected to the second adjacent gate line pairs (GL4n-1, GL4n), and the transistor T included in the second-1 buffer 220b_1 is deposited in the branch circuit unit BC included in the second horizontal portion H2.

[0215] In some embodiments of this disclosure, the transistor T included in the second shift register 210b and the second-2 buffer 220b_2 is connected via a second signal line 204 arranged in the third signal line portion SL3; and the transistor T included in the second-1 buffer 220b_1 is connected via another second signal line 204 arranged in the first signal line portion SL1.

[0216] In some embodiments of this disclosure, each of the additional second signal lines 204 includes a corresponding second extension extending through a region at the right or left end of the light-emitting display panel, the second extension being connected to a corresponding second signal line 204; wherein, preferably, the first extension extends through a region located on the side opposite to the first direction to the region through which the second extension extends.

[0217] In some embodiments of this disclosure, the light-emitting display panel includes: a left display area and a right display area that does not overlap with the left display area and is adjacent to the left display area in the second direction; the gate driver corresponds to the left display area; the first extension extends through a region at the left end of the light-emitting display panel; and a right gate driver, corresponding to the right display area, the right gate driver including g / 4 stages, the g / 4 stages being divided into g / 8 adjacent right stage pairs, wherein each adjacent right stage pair includes a right first stage Stage1_R and... The right second stage Stage2_R; the right first stage Stage1_R includes: a right first shift register R210a, a right first-1 buffer R220a_1, and a right first-2 buffer R220a_2, wherein the two buffers R220a_1 and R220a_2 are connected to the right first shift register R210a; wherein the right first shift register R210a, the right first-1 buffer R220a_1, and the right first-2 buffer R220a_2 each include a plurality of transistors T deposited in the branch circuit unit BC_R corresponding to the right display area.

[0218] In some embodiments of this disclosure, the right first-1 buffer R220a_1 is further connected to the first adjacent gate line pair (GL4n-3, GL4n-2), and the transistor T included in the right first-1 buffer R220a_1 is deposited in the branch circuit unit BC_R included in the first horizontal portion H1; and wherein the right first-2 buffer R220a_2 is further connected to the third adjacent gate line pair (GL4n+1, GL4n+2), and the transistor T included in the right first shift register R210a and the right first-2 buffer R220a_2 is deposited in the branch circuit unit BC_R included in the third horizontal portion H3.

[0219] In some embodiments of this disclosure, the transistors T included in the right first-second buffer R220a_2 and the right first shift register R210a are connected via a right first signal line 203R arranged in the third signal line portion SL3; the transistors T included in the right first-first buffer R220a_1 are connected via a right first signal line 203R arranged in the first signal line portion SL1; wherein each right first signal line 203R includes a corresponding right first extension extending through a region at the right end of the light-emitting display panel, the right first extension being connected to a corresponding right first signal line 203R.

[0220] In some embodiments of this disclosure, the right second stage Stage2_R includes: a right second shift register R210b, a right second-1 buffer R220b_1, and a right second-2 buffer R220b_2, wherein the two buffers R220b_1 and R220b_2 are connected to the right second shift register R210b; wherein the right second shift register R210b and the right second-1 buffer R220b_1 and the right second-2 buffer R220b_2 each include a plurality of transistors T deposited in a branch circuit unit BC_R corresponding to the right display area.

[0221] In some embodiments of this disclosure, the right 2-2 buffer R220b_2 is further connected to the fourth adjacent gate pair (GL4n+3, GL4n+4), and the transistor T included in the right 2-2 buffer R220b_2 is deposited in the branch circuit unit BC_R included in the fourth horizontal portion H4; and wherein the right 2-1 buffer R220b_1 is further connected to the second adjacent gate pair (GL4n-1, GL4n), and the right second shift register R210b and the transistor T included in the right 2-1 buffer R220b_1 are deposited in the branch circuit unit BC_R included in the second horizontal portion H2.

[0222] In some embodiments of this disclosure, the transistors T included in the right second-1 buffer R220b_1 and the right second shift register R210b are connected via a right second signal line 204R arranged in the first signal line portion SL1; the transistors T included in the right second-2 buffer R220b_2 are connected via another right second signal line 204R arranged in the third signal line portion SL3; wherein, preferably, each of the other right second signal lines 204R includes a corresponding right second extension extending through a region at the right end of the light-emitting display panel, the right second extension being connected to a corresponding right second signal line 204R.

[0223] In some embodiments of this disclosure, gate lines GL1, ..., GLg each include a break at the boundary line BL between the left display area and the right display area; wherein, preferably, each of the additional second signal lines 204 includes a corresponding second extension extending through a region in the left display area adjacent to the boundary line BL, the second extension being connected to a corresponding second signal line 204 among the second signal lines 204; and each of the additional right second signal lines 204R includes a corresponding right second extension extending through a region in the right display area adjacent to the boundary line BL, the right second extension being connected to a corresponding right second signal line 204R among the right second signal lines R204.

[0224] In some embodiments of this disclosure, the first-1 buffer 220a_1 includes a first transistor Pu1 connected between the first gate clock (SCCLK1) line and the first gate line GL4n-3 in the first adjacent gate line pair, and includes a second transistor Pu2 connected between the third gate clock (SCCLK3) line and the second gate line GL4n-2 in the first adjacent gate line pair; wherein the first-2 buffer 220a_2 includes a third transistor (Pu3) connected between the fifth gate clock (SCCLK5) line and the fifth gate line GL4n+1 in the third adjacent gate line pair, and includes a fourth transistor Pu4 connected between the seventh gate clock (SCCLK7) line and the sixth gate line GL4n+2 in the third adjacent gate line pair.

[0225] In some embodiments of this disclosure, the first transistor Pu1, the second transistor Pu2, the third transistor Pu3, and the fourth transistor Pu4 include a gate terminal connected to the output signal line Q of the first shift register 210a, the output signal line Q being included in the first signal line 203 and the additional first signal line 203 and coupled to the ninth gate clock (SCCLK9) line via capacitor C1.

[0226] In some embodiments of this disclosure, the second-1 buffer (220b_1) includes a fifth transistor Pu5 connected between the second gate clock (SCCLK2) line and the third gate line GL4n-1 in the second adjacent gate line pair, and includes a sixth transistor Pu6 connected between the fourth gate clock (SCCLK4) line and the fourth gate line GL4n in the second adjacent gate line pair; and wherein the second-2 buffer 220b_2 includes a seventh transistor Pu7 connected between the sixth gate clock (SCCLK6) line and the seventh gate line GL4n+3 in the fourth adjacent gate line pair, and includes an eighth transistor Pu8 connected between the eighth gate clock (SCCLK8) line and the eighth gate line GL4n+4 in the fourth adjacent gate line pair.

[0227] In a driving method for a gate driver of a light-emitting display panel according to an embodiment of the present disclosure, a first stage 1 and a second stage 2 receive a plurality of gate clocks from a controller 400 via corresponding clock lines; wherein the gate clocks include at least eight gate clocks SCCLK1, ..., SCCLK8, and the at least eight gate clocks SCCLK1, ..., SCCLK8 are subsequently supplied on the corresponding clock lines in chronological order from the first to the eighth gate clocks SCCLK1, ..., SCCLK8; wherein the first-1 buffer 220a_1 receives the first gate clock SSCLK1 output to the first gate line GL4n-3 in the first adjacent gate line pair and the third gate clock SCCLK3 output to the second gate line GL4n-2 in the first adjacent gate line pair; the first-2 buffer 220a_2 receives the output to the third adjacent gate line pair... The fifth gate clock SCCLK5 of the fifth gate line GL4n+1 and the seventh gate clock SCCLK7 of the sixth gate line GL4n+2 in the third adjacent gate line pair are output; the second-1 buffer 220b_1 receives the second gate clock SCCLK2 of the third gate line GL4n-1 in the second adjacent gate line pair and the fourth gate clock SCCLK4 of the fourth gate line GL4n in the second adjacent gate line pair; and the second-2 buffer 220b_2 receives the sixth gate clock SSCLK6 of the seventh gate line GL4n+3 in the fourth adjacent gate line pair and the eighth gate clock SCCLK8 of the eighth gate line GL4n+4 in the fourth adjacent gate line pair.

[0228] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be implemented by those skilled in the art through combination or modification of other embodiments. Therefore, any content related to combination and modification should be interpreted as being within the scope of this disclosure.

[0229] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover any modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A light emitting display apparatus comprising: a gate driver including a plurality of stages disposed in a light emitting display panel; and a plurality of gate lines connected to the plurality of stages, wherein each of the plurality of stages includes a shift register and two buffers connected to the shift register, a first-1 buffer of two buffers constituting an n-th stage among the plurality of stages and a first shift register constituting the n-th stage are disposed in an n-th horizontal portion, and a first-2 buffer of the two buffers is disposed in an n+2-th horizontal portion, where n is an odd number, a second-2 buffer of two buffers constituting an n+1-th stage among the plurality of stages and a second shift register constituting the n+1-th stage are disposed in an n+3-th horizontal portion, and a second-1 buffer of the two buffers is disposed in an n+1-th horizontal portion, and the n-th horizontal portion is a region of the light emitting display panel including pixels arranged along a 4n-3-th gate line and a 4n-2-th gate line, the n+1-th horizontal portion is a region of the light emitting display panel including pixels arranged along a 4n-1-th gate line and a 4n-th gate line, the n+2-th horizontal portion is a region of the light emitting display panel including pixels arranged along a 4n+1-th gate line and a 4n+2-th gate line, and the n+3-th horizontal portion is a region of the light emitting display panel including pixels arranged along a 4n+3-th gate line and a 4n+4-th gate line. 2.The light emitting display apparatus of claim 1, wherein the first-1 buffer is connected to the 4n-3-th gate line and the 4n-2-th gate line, and the first-2 buffer is connected to the 4n+1-th gate line and the 4n+2-th gate line. 3.The light emitting display apparatus of claim 1, wherein the second-2 buffer is connected to the 4n+3-th gate line and the 4n+4-th gate line, and the second-1 buffer is connected to the 4n-1-th gate line and the 4n-th gate line. 4.The light emitting display apparatus of claim 1, wherein at least one n-th signal line connected to the first-1 buffer and the first shift register and three n+1-th signal lines connected to the second-1 buffer are disposed in an n-th signal line portion between the n-th horizontal portion and the n+1-th horizontal portion, three of the at least one n-th signal line extend to an n+2-th signal line portion between the n+2-th horizontal portion and the n+3-th horizontal portion, the three n+1-th signal lines extend to the n+2-th signal line portion, and at least one of the n+1-th signal lines connected to the second-2 buffer and the second shift register is further disposed in the n+2-th signal line portion. 5.The light emitting display apparatus of claim 4, wherein the three n-th signal lines disposed in the n+2-th signal line portion are connected to the first-2 buffer, and The three n+1th signal lines provided in the n+2th signal line section are connected to the 2-2th buffer and the second shift register.

6. The light emitting display apparatus of claim 4, wherein the one side end of the three n signal lines provided in the n signal line section and the one side end of the three n+1th signal lines provided in the n signal line section extend to the n+2th signal line section through the same area.

7. The light emitting display apparatus of claim 4, wherein the one side end of the three n signal lines provided in the n signal line section extends to the n+2th signal line section through a first area in which one side ends of gate lines included in the n+1th horizontal section and the n+2th horizontal section are provided, and the one side end of the three n+1th signal lines provided in the n signal line section extends to the n+2th signal line section through the first area.

8. The light emitting display apparatus of claim 4, wherein the one side end of the three n signal lines provided in the n signal line section and the one side end of the three n+1th signal lines provided in the n signal line section extend to the n+2th signal line section through different areas.

9. The light emitting display apparatus of claim 4, wherein the one side end of the three n signal lines provided in the n signal line section extends to the n+2th signal line section through a first area in which one side ends of gate lines included in the n+1th horizontal section and the n+2th horizontal section are provided, and the one side end of the three n+1th signal lines provided in the n signal line section extends to the n+2th signal line section through a second area in which other side ends of the gate lines included in the n+1th horizontal section and the n+2th horizontal section are provided.

10. The light emitting display apparatus of claim 1, wherein a substrate is divided into a left area and a right area with a boundary corresponding to a direction perpendicular to gate lines as a reference, the n stage and the n+1th stage are provided in the left area, and an n right stage corresponding to the n stage and an n+1th right stage corresponding to the n+1th stage are provided in the right area.

11. The light emitting display apparatus of claim 10, wherein a 3-2th buffer of two buffers constituting the n right stage and a third shift register constituting the n right stage are provided in the n+2th horizontal section, and a 3-1th buffer of the two buffers is provided in the n horizontal section, and a 4-1th buffer of two buffers constituting the n+1th right stage and a third shift register constituting the n+1th right stage are provided in the n+1th horizontal section, and a 4-2th buffer of the two buffers is provided in the n+3th horizontal section.

12. The light emitting display apparatus of claim 11, wherein the 3-2 buffer is connected to the 4n+1 gate line and the 4n+2 gate line, and the 3-1 buffer is connected to the 4n-3 gate line and the 4n-2 gate line.

13. The light emitting display apparatus of claim 11, wherein the 4-1 buffer is connected to the 4n-1 gate line and the 4n gate line, and the 4-2 buffer is connected to the 4n+3 gate line and the 4n+4 gate line.

14. The light emitting display apparatus of claim 10, wherein the n stage and the n right stage are connected to the same gate line, and the n+1 stage and the n+1 right stage are connected to the same gate line.

15. The light emitting display apparatus of claim 10, wherein the 4n-3 gate line and the 4n-2 gate line included in the n horizontal portion and the 4n+1 gate line and the 4n+2 gate line included in the n+2 horizontal portion are connected to the n stage and the n right stage, and the 4n-1 gate line and the 4n gate line included in the n+1 horizontal portion and the 4n+3 gate line and the 4n+4 gate line included in the n+3 horizontal portion are connected to the n+1 stage and the n+1 right stage.

16. The light emitting display apparatus of claim 10, wherein 4n-3 right gate lines to 4n+4 right gate lines corresponding to the 4n-3 gate line to the 4n+4 gate line provided in the left side area of the substrate are provided in the right side area of the substrate, and the 4n-3 gate lines to the 4n+4 gate lines are separated from the 4n-3 right gate lines to the 4n+4 right gate lines with the boundary as a reference.

17. The light emitting display apparatus of claim 16, wherein the 4n-3 gate line, the 4n-2 gate line, the 4n+1 gate line and the 4n+2 gate line are connected to the n stage, the 4n-3 right gate line, 4n-2 right gate line, 4n+1 right gate line and 4n+2 right gate line are connected to the n right stage, the 4n-1 gate line, the 4n gate line, the 4n+3 gate line and the 4n+4 gate line are connected to the n+1 stage, and the 4n-1 right gate line, the 4n right gate line, the 4n+3 right gate line and the 4n+4 right gate line are connected to the n+1 right stage.

18. The light emitting display apparatus of claim 1, wherein gate pulses are sequentially output to the 4n-3 gate line, the 4n-1 gate line, the 4n-2 gate line, the 4n gate line, the 4n+1 gate line, the 4n+3 gate line, the 4n+2 gate line and the 4n+4 gate line. ​ ​ ​ ​ ​ ​ 19.The light emitting display apparatus of claim 18, wherein the nth stage is connected to the 4n-3rd gate line, the 4n-2nd gate line, the 4n+1st gate line, and the 4n+2nd gate line, and the (n+1)th stage is connected to the 4n-1st gate line, the 4nth gate line, the 4n+3rd gate line, and the 4n+4th gate line. 20.A light emitting display apparatus comprising: a gate driver including a plurality of stages disposed in a light emitting display panel; a plurality of gate lines connected to the plurality of stages; data lines crossing the plurality of gate lines; and pixels arranged along the data lines and the gate lines, wherein an nth stage among the plurality of stages is configured to output a 4n-3rd gate pulse, a 4n-1st gate pulse, a 4n+1st gate pulse, and a 4n+3rd gate pulse, where n is an odd number, wherein an (n+1)th stage among the plurality of stages is configured to output a 4n-2nd gate pulse, a 4nth gate pulse, a 4n+2nd gate pulse, and a 4n+4th gate pulse, and wherein the 4n-3rd gate pulse, the 4n-1st gate pulse, the 4n-2nd gate pulse, the 4nth gate pulse, the 4n+1st gate pulse, the 4n+3rd gate pulse, the 4n+2nd gate pulse, and the 4n+4th gate pulse are respectively output to 4n-3rd, 4n-2nd, 4n-1st, 4nth, 4n+1st, 4n+2nd, 4n+3rd, and 4n+4th gate lines arranged in sequence, such that the pixels arranged along the same data line are driven in a zigzag form.

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