Shift register unit and driving method therefor, and gate driving circuit and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, and a gate driving circuit and a display apparatus, which belong to the technical field of display. The shift register unit comprises a plurality of control circuits and an output circuit. Under the cooperation of the plurality of control circuits, the potentials of a pull-up node and a pull-down node can be stabilized by flexibly setting a clock signal, thereby ensuring that the output capability of the shift register unit is better. In addition, on the basis that the output circuit respectively outputs, in response to the potentials of the pull-up node and the pull-down node and via different output terminals, a cascade signal to cascaded shift register units in other stages and a driving signal to a pixel, a cascade load can be reduced, thereby preventing a cascade function from being affected by the load, and ensuring that the cascade function is better. In this way, by using the shift register unit, pixels can be driven to reliably emit light, thereby preventing poor display and ensuring a better display effect.

Description

Shift register unit and its driving method, gate driving circuit, display device

[0001] This application claims priority to Chinese Patent Application No. 202411463949.5, filed on October 18, 2024, entitled "Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0003] Gate drive circuits are one of the essential circuits in display devices. They are mainly used to transmit gate drive signals to the pixels in the display device to drive the pixels to emit light.

[0004] Currently, considering the need for narrow bezel designs, gate drive on array (GOA) technology is often used to integrate the gate drive circuit onto the array substrate of the display device. Correspondingly, the gate drive circuit is also called a GOA circuit. Furthermore, a GOA circuit typically includes multiple cascaded shift register units (also called GOA units). These multiple GOA units are connected to multiple rows of pixels to output gate drive signals to the pixels row by row, achieving progressive scanning.

[0005] However, due to structural or connection limitations, the reliability of the current GOA unit's output gate drive signal is poor, which can easily cause display abnormalities and result in poor display performance of the display device. Summary of the Invention

[0006] A shift register unit and its driving method, a gate driving circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] A first control circuit is connected to a first input terminal, a second input terminal, a first control terminal, a second control terminal, a first power supply terminal, a pull-down node, and a pull-up node, respectively. It is used to control the connection and disconnection between the first control terminal and the pull-up node in response to a first input signal provided by the first input terminal, control the connection and disconnection between the second control terminal and the pull-up node in response to a second input signal provided by the second input terminal, and control the connection and disconnection between the first power supply terminal and the pull-up node in response to the potential of the pull-down node.

[0009] The second control circuit is connected to the first control terminal, the second control terminal, the first clock terminal, the second clock terminal, and the intermediate node, respectively, and is used to control the connection and disconnection between the first clock terminal and the intermediate node in response to the first control signal provided by the first control terminal, and to control the connection and disconnection between the second clock terminal and the intermediate node in response to the second control signal provided by the second control terminal.

[0010] The third control circuit is connected to the second power supply terminal, the pull-up node, the intermediate node and the pull-down node respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node.

[0011] The output circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, the shift output terminal, and the drive output terminal, respectively. It is used to control the connection and disconnection of the third clock terminal and the shift output terminal, and the connection and disconnection of the third clock terminal and the drive output terminal, in response to the potential of the pull-up node. It also controls the connection and disconnection of the first power supply terminal and the shift output terminal, and the connection and disconnection of the first power supply terminal and the drive output terminal, in response to the potential of the pull-down node. The shift output terminal is used to connect to other cascaded shift register units, and the drive output terminal is used to connect to pixels in the display panel.

[0012] Optionally, the output circuit includes:

[0013] The first output sub-circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, and the drive output terminal, respectively, and is used to control the connection and disconnection of the third clock terminal and the drive output terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the first power supply terminal and the drive output terminal in response to the potential of the pull-down node.

[0014] The second output sub-circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the third clock terminal and the shift output terminal in response to the potential of the pull-up node, and to control the on / off state of the first power supply terminal and the shift output terminal in response to the potential of the pull-down node.

[0015] Optionally, the first output sub-circuit includes: a first transistor and a second transistor; the second output sub-circuit includes: a third transistor and a fourth transistor;

[0016] The gate of the first transistor is connected to the pull-up node, the first terminal of the first transistor is connected to the third clock terminal, and the second terminal of the first transistor is connected to the drive output terminal.

[0017] The gate of the second transistor is connected to the pull-down node, the first terminal of the second transistor is connected to the first power supply terminal, and the second terminal of the second transistor is connected to the drive output terminal.

[0018] The gate of the third transistor is connected to the pull-up node, the first terminal of the third transistor is connected to the third clock terminal, and the second terminal of the third transistor is connected to the shift output terminal.

[0019] The gate of the fourth transistor is connected to the pull-down node, the first terminal of the fourth transistor is connected to the first power supply terminal, and the second terminal of the fourth transistor is connected to the shift output terminal.

[0020] Optionally, the channel width-to-length ratio of the third transistor is different from that of the first transistor; and / or, the channel width-to-length ratio of the fourth transistor is different from that of the second transistor.

[0021] Optionally, the ratio of the channel width-to-length ratio of the third transistor to that of the first transistor is greater than 80%; the ratio of the channel width-to-length ratio of the fourth transistor to that of the second transistor is greater than 80%.

[0022] Optionally, the first control circuit, the third control circuit, the output circuit, and the second control circuit are arranged sequentially along the first direction and in the direction closer to the drive output terminal;

[0023] Furthermore, the third transistor and the first transistor in the output circuit are arranged sequentially along the second direction, and the fourth transistor and the second transistor are arranged sequentially along the first direction, wherein the first direction intersects the second direction.

[0024] Optionally, the third control circuit includes:

[0025] The first control sub-circuit is connected to the pull-up node, the first power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the first power supply terminal and the pull-down node in response to the potential of the pull-up node.

[0026] The second control sub-circuit is connected to the intermediate node, the second power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the second power supply terminal and the pull-down node in response to the potential of the intermediate node.

[0027] Optionally, the first control sub-circuit includes a fifth transistor; the second control sub-circuit includes a sixth transistor.

[0028] The gate of the fifth transistor is connected to the pull-up node, the first terminal of the fifth transistor is connected to the first power supply terminal, and the second terminal of the fifth transistor is connected to the pull-down node.

[0029] The gate of the sixth transistor is connected to the intermediate node, the first terminal of the sixth transistor is connected to the second power supply terminal, and the second terminal of the sixth transistor is connected to the pull-down node.

[0030] Optionally, the second control circuit includes a seventh transistor and an eighth transistor;

[0031] The gate of the seventh transistor is connected to the first control terminal, the first terminal of the seventh transistor is connected to the first clock terminal, and the second terminal of the seventh transistor is connected to the intermediate node.

[0032] The gate of the eighth transistor is connected to the second control terminal, the first terminal of the eighth transistor is connected to the second clock terminal, and the second terminal of the eighth transistor is connected to the intermediate node.

[0033] Optionally, the first control circuit includes: a ninth transistor, a tenth transistor, and an eleventh transistor;

[0034] The gate of the ninth transistor is connected to the first input terminal, the first electrode of the ninth transistor is connected to the first control terminal, and the second electrode of the ninth transistor is connected to the pull-up node.

[0035] The gate of the tenth transistor is connected to the second input terminal, the first terminal of the tenth transistor is connected to the second control terminal, and the second terminal of the tenth transistor is connected to the pull-up node.

[0036] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the pull-up node.

[0037] Optionally, the pull-up node includes: a first pull-up node and a second pull-up node, the first control circuit, the second control circuit, and the third control circuit are all connected to the first pull-up node, and the output circuit is connected to the second pull-up node; furthermore, the shift register unit further includes:

[0038] The fourth control circuit is connected to the second power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the second power supply signal provided by the second power supply terminal.

[0039] And / or, the shift register unit further includes:

[0040] The first reset circuit is connected to the reset control terminal, the first power supply terminal, and the first pull-up node, respectively, and is used to control the on / off state of the first power supply terminal and the first pull-up node in response to the reset control signal provided by the reset control terminal.

[0041] The second reset circuit is connected to the touch enable terminal, the first power supply terminal and the drive output terminal respectively, and is used to control the on / off state of the first power supply terminal and the drive output terminal in response to the touch enable signal provided by the touch enable terminal.

[0042] A first storage circuit is connected between the second pull-up node and the drive output terminal, and is used to control the potential of the second pull-up node;

[0043] The second storage circuit is connected between the pull-down node and the first power supply terminal, and is used to control the potential of the pull-down node.

[0044] Optionally, the fourth control circuit includes a twelfth transistor; the first reset circuit includes a thirteenth transistor; the second reset circuit includes a fourteenth transistor; the first storage circuit includes a first capacitor; and the second storage circuit includes a second capacitor.

[0045] The gate of the twelfth transistor is connected to the second power supply terminal, the first terminal of the twelfth transistor is connected to the first pull-up node, and the first terminal of the twelfth transistor is connected to the second pull-up node.

[0046] The gate of the thirteenth transistor is connected to the reset control terminal, the first terminal of the thirteenth transistor is connected to the first power supply terminal, and the second terminal of the thirteenth transistor is connected to the first pull-up node.

[0047] The gate of the fourteenth transistor is connected to the touch enable terminal, the first terminal of the fourteenth transistor is connected to the first power supply terminal, and the second terminal of the fourteenth transistor is connected to the drive output terminal.

[0048] One end of the first capacitor is connected to the drive output terminal, and the other end of the first capacitor is connected to the second pull-up node;

[0049] One end of the second capacitor is connected to the first power supply terminal, and the other end of the first capacitor is connected to the pull-down node.

[0050] On the other hand, a method for driving a shift register unit is provided, the method comprising:

[0051] In the first stage, the first control circuit responds to the first input signal provided by the first input terminal and controls the first control terminal to be connected to the pull-up node; the second control circuit responds to the first control signal provided by the first control terminal and controls the first clock terminal to be connected to the intermediate node; the third control circuit responds to the potential of the pull-up node and controls the first power supply terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-up node and controls the third clock terminal to be connected to both the shift output terminal and the drive output terminal.

[0052] In the second stage, the first control circuit responds to the first input signal and controls the first control terminal to be connected to the pull-up node; the second control circuit responds to the first control signal and controls the first clock terminal to be connected to the intermediate node; the third control circuit responds to the potential of the intermediate node and controls the second power supply terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-down node and controls the first power supply terminal to be connected to both the shift output terminal and the drive output terminal.

[0053] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: a plurality of cascaded shift register units as described in the above aspect;

[0054] In this system, the shift output of each shift register unit is connected to the second input of the cascaded previous shift register unit, and the drive output of each shift register unit is connected to the first input of the cascaded subsequent shift register unit.

[0055] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0056] The gate driving circuit is connected to the plurality of pixels through a driving output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0059] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0060] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0061] Figure 4 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

[0062] Figure 5 is a schematic diagram of the circuit structure of a plurality of shift register units provided in an embodiment of this application;

[0063] Figure 6 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0064] Figure 7 is a schematic diagram of the structural layout of multiple shift register units provided in an embodiment of this application;

[0065] Figure 8 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this application;

[0066] Figure 9 is a timing simulation diagram of a shift register unit provided in an embodiment of this application;

[0067] Figure 10 is a timing simulation diagram of another shift register unit provided in an embodiment of this application;

[0068] Figure 11 is a timing simulation diagram of another shift register unit provided in an embodiment of this application;

[0069] Figure 12 is a timing simulation diagram of another shift register unit provided in an embodiment of this application;

[0070] Figure 13 is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0071] Figure 14 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0073] It is understood that the transistors used in the embodiments of this application can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics, such as metal-oxide-semiconductor (MOS) field-effect transistors, also known as MOS transistors. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include either P-type switching transistors or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the whole text.

[0074] In some embodiments, in a cascaded array of multiple shift register units, each shift register unit outputs a driving signal and a cascading signal to the pixel and other cascaded shift register units through a single output terminal, respectively, to drive the pixel to emit light and to drive the other shift register units to operate. That is, each shift register unit simultaneously undertakes the driving function of activating the connected pixels in its own row and the cascading function of other shift register units. Therefore, when the display panel is large, the heavy load connected to this single output terminal can affect the cascading function, preventing the other cascaded shift register units from being fully activated. This can lead to the other shift register units being unable to reliably drive the connected pixels to emit light, resulting in display defects such as screen flickering or split-screen display, and a poor display effect.

[0075] Furthermore, in some embodiments, due to the connection method, a competition relationship may form between the pull-up and pull-down nodes of each shift register unit. For example, the pull-up and pull-down nodes may be charged simultaneously at a certain time, resulting in an unnecessary DC path between the transistor that controls the pull-down node's potential based on the pull-up node's potential and the transistor that controls the pull-up node's potential based on the pull-down node's potential. This will cause the potentials of both the pull-up and pull-down nodes to fail to reach the desired potentials, thus preventing the shift register unit from reliably outputting the desired drive signal and cascaded signal, resulting in poor output capability of the shift register unit and consequently, poor display performance. Therefore, in other embodiments, it is also considered to improve the output capability of the shift register unit by increasing the channel width-to-length ratio of the aforementioned transistors, such as setting the channel width-to-length ratio of the transistor that controls the pull-down node's potential based on the pull-up node's potential and the transistor that controls the pull-up node's potential based on the pull-down node's potential to be 1 / 4. However, increasing the channel width-to-length ratio of the transistors will increase the size of the shift register unit, which is detrimental to the narrow bezel design of the display device. Furthermore, the formation of a DC path will increase the power consumption of the shift register unit, and the transistors are also at risk of being damaged, which will reduce the reliability of the display panel.

[0076] Based on this, the embodiments of this application provide a new shift register unit, which ensures that the output capability of the shift register unit is good, reliably drives the pixels to emit light, and achieves a good display effect, while also facilitating the design of a narrow bezel and ensuring the good working reliability of the display panel.

[0077] Figure 1 is a schematic diagram of a shift register unit provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes: a first control circuit 01, a second control circuit 02, a third control circuit 03, and an output circuit 04.

[0078] The first control circuit 01 is connected to the first input terminal CAS1, the second input terminal CAS2, the first control terminal CN, the second control terminal CNB, the first power supply terminal VGL_G, the pull-down node PD, and the pull-up node PU. The first control circuit 01 is used to control the connection and disconnection of the first control terminal CN and the pull-up node PU in response to the first input signal provided by the first input terminal CAS1; to control the connection and disconnection of the second control terminal CNB and the pull-up node PU in response to the second input signal provided by the second input terminal CAS2; and to control the connection and disconnection of the first power supply terminal VGL_G and the pull-up node PU in response to the potential of the pull-down node PD.

[0079] For example, the first control circuit 01 can control the first control terminal CN to conduct with the pull-up node PU when the potential of the first input signal provided by the first input terminal CAS1 is at the first potential, so that the first control signal provided by the first control terminal CN can be transmitted to the pull-up node PU. Similarly, the first control circuit 01 can control the first control terminal CN to disconnect from the pull-up node PU when the potential of the first input signal provided by the first input terminal CAS1 is at the second potential. Furthermore, the first control circuit 01 can control the first power supply terminal VGL_G to conduct with the pull-up node PU when the potential of the pull-down node PD is at a first potential, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the pull-up node PU. Conversely, it can control the first power supply terminal VGL_G to disconnect from the pull-up node PU when the potential of the pull-down node PD is at a second potential. In other words, the first control circuit 01 can control the potential of the pull-up node PU.

[0080] Optionally, in this embodiment, the first potential can be a higher potential relative to the second potential. That is, the first potential can be a high potential, and the second potential can be a low potential. Of course, in some other embodiments, the first potential can also be a low potential relative to the second potential. Furthermore, for an N-type transistor, the effective potential can be a high potential, and the ineffective potential can be a low potential. For a P-type transistor, the effective potential can be a low potential, and the ineffective potential can be a high potential.

[0081] Optionally, the first input terminal CAS1 can be connected to a cascaded upper-level shift register unit, and the second input terminal CAS2 can be connected to a cascaded lower-level shift register unit to support forward and reverse scan functions. Correspondingly, the first control terminal CN and the second control terminal CNB can be control terminals that support forward and reverse scan functions, respectively. Of course, the first input terminal CAS1 of the first-level shift register unit can be connected to the enable signal terminal STV to operate based on the enable signal provided by the enable signal terminal STV. The forward scan function can refer to sequential scanning from the first row to the last row of the display panel; the reverse scan function can refer to sequential scanning from the last row to the first row of the display panel, where scanning also drives pixel illumination.

[0082] The second control circuit 02 is connected to the first control terminal CN, the second control terminal CNB, the first clock terminal CK1, the second clock terminal CK2, and the intermediate node P0. The second control circuit 02 is used to control the connection and disconnection between the first clock terminal CK1 and the intermediate node P0 in response to the first control signal provided by the first control terminal CN, and to control the connection and disconnection between the second clock terminal CK2 and the intermediate node P0 in response to the second control signal provided by the second control terminal CNB.

[0083] For example, the second control circuit 02 can control the first clock terminal CK1 to conduct with the intermediate node P0 when the potential of the first control signal provided by the first control terminal CN is at the first potential, so that the first clock signal provided by the first clock terminal CK1 can be transmitted to the intermediate node P0. Similarly, when the potential of the first control signal provided by the first control terminal CN is at the second potential, the second control circuit 02 can control the second clock terminal CK2 to conduct with the intermediate node P0 when the potential of the second control signal provided by the second control terminal CNB is at the first potential, so that the second clock signal provided by the second clock terminal CK2 can be transmitted to the intermediate node P0. Likewise, when the potential of the second control signal provided by the second control terminal CNB is at the second potential, the second clock terminal CK2 can control the second clock terminal CK2 to disconnect from the intermediate node P0. In other words, the second control circuit 02 can control the potential of the intermediate node P0.

[0084] As described above, the first control terminal CN and the second control terminal CNB can respectively support forward scan and reverse scan functions. Correspondingly, the second control circuit 02, responding to the first control signal provided by the first control terminal CN and the second control signal provided by the second control terminal CNB, can also control the potential of the intermediate node P0 to support both forward and reverse scan functions. For example, when the potential of the first control signal provided by the first control terminal CN is the first potential and the potential of the second control signal provided by the second control terminal CNB is the second potential, forward scan can be achieved. When the potential of the first control signal provided by the first control terminal CN is the second potential and the potential of the second control signal provided by the second control terminal CNB is the first potential, reverse scan can be achieved.

[0085] The third control circuit 03 is connected to the second power supply terminal VGH_G, the pull-up node PU, the intermediate node P0, and the pull-down node PD, respectively. The third control circuit 03 is used to control the switching between the first power supply terminal VGL_G and the pull-down node PD in response to the potential of the pull-up node PU, and to control the switching between the second power supply terminal VGH_G and the pull-down node PD in response to the potential of the intermediate node P0.

[0086] For example, the third control circuit 03 can control the first power supply terminal VGL_G to conduct with the pull-down node PD when the potential of the pull-up node PU is at the first potential, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the pull-down node PD. It can also control the first power supply terminal VGL_G to disconnect from the pull-down node PD when the potential of the pull-up node PU is at the second potential. Similarly, the third control circuit 03 can control the second power supply terminal VGH_G to conduct with the pull-down node PD when the potential of the intermediate node P0 is at the first potential, so that the second power signal provided by the second power supply terminal VGH_G can be transmitted to the pull-down node PD. It can also control the second power supply terminal VGH_G to disconnect from the pull-down node PD when the potential of the intermediate node P0 is at the second potential. In other words, the third control circuit 03 can control the potential of the pull-down node PD.

[0087] Optionally, the potential of the first power signal provided by the first power supply terminal VGL_G can be low, and the potential of the second power signal provided by the second power supply terminal VGH_G can be high. Here, low potential and high potential are relative terms.

[0088] Understandably, through the cooperation of the first control circuit 01, the second control circuit 02, and the third control circuit 03, the clock signal provided by the clock terminal can be flexibly set to avoid competition between the pull-down node PD and the pull-up node PU. This prevents unnecessary DC paths from forming between the transistor in the first control circuit 01 that controls the potential of the pull-up node PU based on the potential of the pull-down node PD and the transistor in the third control circuit 03 that controls the potential of the pull-up node PD based on the potential of the pull-up node PU. This not only ensures that the potentials of both the pull-up and pull-down nodes can stably reach the desired potentials, ensuring good output capability of the shift register unit, but also reduces the power consumption of the shift register unit and the risk of transistor damage, thus improving the reliability of the display panel. Furthermore, since there are no unnecessary DC paths, it is not necessary to increase the channel width-to-length ratio of the aforementioned transistors to ensure good output capability of the shift register unit, which also facilitates the narrow bezel design of the display device.

[0089] Output circuit 04 is connected to pull-up node PU, pull-down node PD, third clock terminal CK3, first power supply terminal VGL_G, shift output terminal CR, and drive output terminal OUT, respectively. Output circuit 04 is used to control the switching between the third clock terminal CK3 and the shift output terminal CR, and also to control the switching between the third clock terminal CK3 and the drive output terminal OUT, in response to the potential of pull-up node PU; and to control the switching between the first power supply terminal VGL_G and the shift output terminal CR, and also to control the switching between the first power supply terminal VGL_G and the drive output terminal OUT, in response to the potential of pull-down node PD.

[0090] For example, when the pull-up node PU is at the first potential, output circuit 04 can control the third clock terminal CK3 to conduct with the shift output terminal CR and the drive output terminal OUT, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the shift output terminal CR and the drive output terminal OUT. When the pull-up node PU is at the second potential, output circuit 04 can control the third clock terminal CK3 to disconnect from the shift output terminal CR and the drive output terminal OUT. Similarly, when the pull-down node PD is at the first potential, output circuit 04 can control the first power supply terminal VGL_G to conduct with the shift output terminal CR and the drive output terminal OUT, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the shift output terminal CR and the drive output terminal OUT. When the pull-down node PD is at the second potential, output circuit 04 can control the first power supply terminal VGL_G to disconnect from the shift output terminal CR and the drive output terminal OUT. That is, the output circuit 04 can output signals through the drive output terminal OUT and the shift output terminal CR respectively.

[0091] In this embodiment, the shift output terminal CR is used to connect with other cascaded shift register units, and the drive output terminal OUT is used to connect with pixels in the display panel. Correspondingly, the signal output by the shift register unit via the shift output terminal CR can be used as a cascade signal to drive other shift register units. The signal output by the shift register unit via the drive output terminal OUT can be used as a drive signal to drive pixels to emit light. That is, in this embodiment, the cascade signal and the drive signal can be output independently via different output terminals, and the cascading function and the drive function can be executed independently. Thus, compared to the above embodiment where the drive signal and cascade signal are output via the same output terminal (i.e., the shift output terminal CR and the drive output terminal OUT are shared), the load of the pixels originally connected to the cascade output terminal CR can be eliminated, thereby avoiding the cascading function being affected by a large load and ensuring better cascading performance. Furthermore, each shift register unit can reliably drive the connected pixels to emit light, avoiding display defects in the display panel and ensuring better display effects.

[0092] Optionally, other shift register units can be, for example, the next-level shift register unit adjacent to the current shift register unit; that is, adjacent shift register units can be cascaded together through the shift output terminal CR. Furthermore, multi-level shift register units can be connected one-to-one with multiple rows of pixels; that is, each shift register unit can be connected to a corresponding row of pixels through the drive output terminal OUT. Of course, the connection method here is only illustrative. For example, in some other embodiments, odd-numbered shift register units can be cascaded together, and each shift register unit can be connected to multiple rows of pixels.

[0093] Optionally, in conjunction with the foregoing description, the cascaded output terminal CR of each shift register unit can be connected to the first input terminal CAS1 of the cascaded subsequent shift register unit, and can be connected to the second input terminal CAS2 of the cascaded preceding shift register unit, so as to support forward and reverse scan functions through the first input terminal CAS1 and the second input terminal CAS2.

[0094] In summary, this application provides a shift register unit. This shift register unit includes a first control circuit, a second control circuit, a third control circuit, and an output circuit. With the cooperation of the first to third control circuits, the clock signal provided by the clock terminal can be flexibly set to ensure good stability of the potentials of the pull-up and pull-down nodes, thereby ensuring good output capability of the shift register unit. Furthermore, by having the output circuit respond to the potentials of the pull-up and pull-down nodes, outputting cascade signals to other shift register units and driving signals to pixels through different output terminals, the load on the cascade output terminals can be reduced, thus avoiding the cascading function being affected by the load and ensuring good cascading performance. Therefore, using this shift register unit can reliably drive pixels to emit light, avoiding display defects on the display panel and ensuring good display quality.

[0095] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the pull-up node PU may include: a first pull-up node PU1 and a second pull-up node PU2. The first control circuit 01, the second control circuit 02, and the third control circuit 03 may all be connected to the first pull-up node PU1, and the output circuit 04 may be connected to the second pull-up node PU2. Furthermore, the shift register unit may also include: a fourth control circuit 05.

[0096] The fourth control circuit 05 can be connected to the second power supply terminal VGH_G, the first pull-up node PU1, and the second pull-up node PU2, respectively. The fourth control circuit 05 can be used to control the on / off state of the first pull-up node PU1 and the second pull-up node PU2 in response to the second power supply signal provided by the second power supply terminal VGH_G.

[0097] For example, when the potential of the second power signal provided by the second power supply terminal VGH_G is the first potential, the fourth control circuit 05 can control the first pull-up node PU1 and the second pull-up node PU2 to be turned on, so that the signal transmitted to the first pull-up node PU1 can be further transmitted to the second pull-up node PU2.

[0098] It is understandable that by setting the fourth control circuit 05, the first pull-up node PU1 and the second pull-up node PU2 can be isolated, avoiding the problem of voltage backflow from the output circuit 04 causing the potential of the first pull-up node PU1 to be unstable. This also serves to protect the transistor controlling the potential of the first pull-up node PU1, thereby ensuring better output stability of the shift register unit.

[0099] And / or, continuing to refer to Figure 2, it can be seen that in some embodiments, the shift register unit may further include: a first reset circuit 06, a second reset circuit 07, a first storage circuit 08, and a second storage circuit 09.

[0100] The first reset circuit 06 can be connected to the reset control terminal RESET, the first power supply terminal VGL_G, and the first pull-up node PU1, respectively. The first reset circuit 06 can be used to control the on / off state of the first power supply terminal VGL_G and the first pull-up node PU1 in response to the reset control signal provided by the reset control terminal RESET.

[0101] For example, the first reset circuit 06 can control the first power supply terminal VGL_G to conduct with the first pull-up node PU1 when the reset control signal provided by the reset control terminal RESET is at a first potential, allowing the first power signal provided by the first power supply terminal VGL_G to be transmitted to the first pull-up node PU1. Conversely, it can control the first power supply terminal VGL_G to disconnect from the first pull-up node PU1 when the reset control signal provided by the reset control terminal RESET is at a second potential. In other words, the first reset circuit 06 can control the potential of the first pull-up node PU1 to reset it. This reduces signal noise and improves the accuracy of the shift register unit's output signal.

[0102] The second reset circuit 07 can be connected to the touch enable terminal EN_TOUCH, the first power supply terminal VGL_G, and the drive output terminal OUT, respectively. The second reset circuit 07 can be used to control the on / off state of the first power supply terminal VGL_G and the drive output terminal OUT in response to the touch enable signal provided by the touch enable terminal EN_TOUCH.

[0103] For example, the second reset circuit 07 can control the first power supply terminal VGL_G to conduct with the drive output terminal OUT when the potential of the touch enable signal provided by the touch enable terminal EN_TOUCH is at the first potential, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the drive output terminal OUT. Conversely, it can control the first power supply terminal VGL_G to disconnect from the drive output terminal OUT when the potential of the touch enable signal provided by the touch enable terminal EN_TOUCH is at the second potential. That is, the second reset circuit 07 can output a signal (primarily a reset signal) through the drive output terminal OUT to reset the signal output through the drive output terminal OUT. This also reduces signal noise and improves the accuracy of the shift register unit's output signal. The second reset circuit 07 mainly realizes the reset of the output signal of the drive output terminal OUT during touch operation, meaning that the shift register unit can also support touch functionality, meeting various user needs.

[0104] The first storage circuit 08 can be connected between the second pull-up node PU2 and the drive output terminal OUT. The first storage circuit 08 can be used to control the potential of the second pull-up node PU2.

[0105] For example, the first storage circuit 08 can control the potential of the second pull-up node PU2 through coupling to stabilize the potential of the second pull-up node PU2 and achieve the purpose of storing the node potential.

[0106] The second storage circuit 09 can be connected between the pull-down node PD and the first power supply terminal VGL_G. The second storage circuit 09 can be used to control the potential of the pull-down node PD.

[0107] For example, the second storage circuit 09 can control the potential of the pull-down node PD through coupling to stabilize the potential of the pull-down node PD and achieve the purpose of storing the node potential.

[0108] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the output circuit 04 may include: a first output sub-circuit 041 and a second output sub-circuit 042.

[0109] The first output sub-circuit 041 can be connected to the pull-up node PU, the pull-down node PD, the third clock terminal CK3, the first power supply terminal VGL_G, and the drive output terminal OUT, respectively. The first output sub-circuit 041 can control the switching between the third clock terminal CK3 and the drive output terminal OUT in response to the potential of the pull-up node PU, and control the switching between the first power supply terminal VGL_G and the drive output terminal OUT in response to the potential of the pull-down node PD. Optionally, based on the division of the pull-up node PU into a first pull-up node PU1 and a second pull-up node PU2, as shown in Figure 3, the first output sub-circuit 041 can be connected to the second pull-up node PU2.

[0110] For example, the first output sub-circuit 041 can control the third clock terminal CK3 to conduct with the drive output terminal OUT when the potential of the second pull-up node PU2 is at the first potential, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the drive output terminal OUT. Conversely, it can control the third clock terminal CK3 to disconnect from the drive output terminal OUT when the potential of the second pull-up node PU2 is at the second potential. Similarly, the first output sub-circuit 041 can control the first power supply terminal VGL_G to conduct with the drive output terminal OUT when the potential of the pull-down node PD is at the first potential, so that the first power supply signal provided by the first power supply terminal VGL_G can be transmitted to the drive output terminal OUT. Conversely, it can control the first power supply terminal VGL_G to disconnect from the drive output terminal OUT when the potential of the pull-down node PD is at the second potential. In other words, the first output sub-circuit 041 can output a drive signal to the pixel via the drive output terminal OUT to drive the pixel to emit light.

[0111] The second output sub-circuit 042 can be connected to the pull-up node PU, the pull-down node PD, the third clock terminal CK3, the first power supply terminal VGL_G, and the shift output terminal CR, respectively. The second output sub-circuit 042 can control the switching between the third clock terminal CK3 and the shift output terminal CR in response to the potential of the pull-up node PU, and control the switching between the first power supply terminal VGL_G and the shift output terminal CR in response to the potential of the pull-down node PD. Optionally, based on the division of the pull-up node PU into a first pull-up node PU1 and a second pull-up node PU2, as shown in Figure 3, the second output sub-circuit 042 can also be connected to the second pull-up node PU2.

[0112] For example, the second output sub-circuit 042 can control the third clock terminal CK3 to conduct with the shift output terminal CR when the potential of the second pull-up node PU2 is at the first potential, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the shift output terminal CR. Conversely, it can control the third clock terminal CK3 to disconnect from the shift output terminal CR when the potential of the second pull-up node PU2 is at the second potential. Similarly, the second output sub-circuit 042 can control the first power supply terminal VGL_G to conduct with the shift output terminal CR when the potential of the pull-down node PD is at the first potential, so that the first power supply signal provided by the first power supply terminal VGL_G can be transmitted to the shift output terminal CR. Conversely, it can control the first power supply terminal VGL_G to disconnect from the shift output terminal CR when the potential of the pull-down node PD is at the second potential. In other words, the second output sub-circuit 042 can output cascaded signals to other cascaded shift register units via the shift output terminal CR to drive the other shift register units to operate. In this way, by setting different output sub-circuits to independently output drive signals and cascade signals through different output terminals, the cascade function and drive function can be reliably and independently executed.

[0113] Optionally, referring to Figure 3, the third control circuit 03 may include: a first control sub-circuit 031 and a second control sub-circuit 032.

[0114] The first control sub-circuit 031 can be connected to the pull-up node PU, the first power supply terminal VGL_G, and the pull-down node PD, respectively. The first control sub-circuit 031 can be used to control the switching of the first power supply terminal VGL_G and the pull-down node PD in response to the potential of the pull-up node PU. Optionally, based on the division of the pull-up node PU into a first pull-up node PU1 and a second pull-up node PU2, as shown in Figure 3, the first control sub-circuit 031 can be connected to the first pull-up node PU1.

[0115] For example, the first control sub-circuit 031 can control the first power supply terminal VGL_G to conduct with the pull-down node PD when the potential of the first pull-up node PU is at a first potential, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the pull-down node PD. Furthermore, it can control the first power supply terminal VGL_G to disconnect from the pull-down node PD when the potential of the first pull-up node PU is at a second potential. That is, the first control sub-circuit 031 can control the potential of the pull-down node PD based on the potential of the first pull-up node PU.

[0116] The second control sub-circuit 032 can be connected to the intermediate node P0, the second power supply terminal VGH_G, and the pull-down node PD, respectively. The second control sub-circuit 032 can be used to control the on / off state of the second power supply terminal VGH_G and the pull-down node PD in response to the potential of the intermediate node P0.

[0117] For example, the second control sub-circuit 032 can control the second power supply terminal VGH_G to conduct with the pull-down node PD when the potential of the intermediate node P0 is the first potential, so that the second power signal provided by the second power supply terminal VGH_G can be transmitted to the pull-down node PD. Conversely, it can control the second power supply terminal VGH_G to disconnect from the pull-down node PD when the potential of the intermediate node P0 is the second potential. In other words, the second control sub-circuit 032 can control the potential of the pull-down node PD based on the potential of the intermediate node P0.

[0118] It is understandable that, since the potential of the first power signal provided by the first power supply terminal VGL_G is low and the potential of the second power signal provided by the second power supply terminal VGH_G is high, by setting the first control sub-circuit 031 and the second control sub-circuit 032 to respond to the potential of the pull-up node PU respectively, the low-potential first power signal is written to the pull-down node PD, and the high-potential second power signal is written to the pull-down node PD in response to the potential of the intermediate node PU, it is possible to avoid the pull-down node PD of other level shift register units in the higher level being pulled up by the clock signal when the current level shift register unit outputs the drive signal. This avoids the transistor that controls the potential of the pull-down node PD based on the potential of the pull-up node PU (i.e., the transistor included in the first control sub-circuit 031) and the transistor that controls the potential of the pull-up node PU based on the potential of the pull-down node PD (i.e., the transistor included in the first control circuit 01) from forming a competition relationship, thereby achieving the purpose of optimizing the potential of the pull-up node PU and the potential of the pull-down node PU.

[0119] Optionally, Figure 4 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application. As shown in Figure 4, the first output sub-circuit 041 may include: a first transistor T1 and a second transistor T2. The second output sub-circuit 042 may include: a third transistor T3 and a fourth transistor T4.

[0120] The gate of the first transistor T1 can be connected to the pull-up node PU, the first terminal of the first transistor T1 can be connected to the third clock terminal CK3, and the second terminal of the first transistor T1 can be connected to the drive output terminal OUT. Optionally, as described above, the gate of the first transistor T1 can be connected to the second pull-up node PU2 included in the pull-up node PU.

[0121] The gate of the second transistor T2 can be connected to the pull-down node PD, the first terminal of the second transistor T2 can be connected to the first power supply terminal VGL_G, and the second terminal of the second transistor T2 can be connected to the drive output terminal OUT.

[0122] The gate of the third transistor T3 can be connected to the pull-up node PU, the first terminal of the third transistor T3 can be connected to the third clock terminal CK3, and the second terminal of the third transistor T3 can be connected to the shift output terminal CR. Optionally, as described above, the gate of the third transistor T3 can be connected to the second pull-up node PU2 included in the pull-up node PU.

[0123] The gate of the fourth transistor T4 can be connected to the pull-down node PD, the first terminal of the fourth transistor T4 can be connected to the first power supply terminal VGL_G, and the second terminal of the fourth transistor T4 can be connected to the shift output terminal CR.

[0124] Optionally, the channel width-to-length ratio of the third transistor T3 may be different from that of the first transistor T1. And / or, the channel width-to-length ratio of the fourth transistor T4 may be different from that of the second transistor T2.

[0125] Optionally, the ratio of the channel width-to-length ratio of the third transistor T3 to that of the first transistor T1 can be greater than 80%. Similarly, the ratio of the channel width-to-length ratio of the fourth transistor T4 to that of the second transistor T2 can be greater than 80%. For example, the channel width-to-length ratio of the first transistor T1 can be maintained above 20, and the channel width-to-length ratio of the third transistor T3 can be above 80% of that of the first transistor T1. This ensures good driving capability and cascading capability of the shift register unit.

[0126] Optionally, referring to Figure 4, the first control sub-circuit 031 may include a fifth transistor T5. The second control sub-circuit 032 may include a sixth transistor T6.

[0127] The gate of the fifth transistor T5 can be connected to the pull-up node PU, the first terminal of the fifth transistor T5 can be connected to the first power supply terminal VGL_G, and the second terminal of the fifth transistor T5 can be connected to the pull-down node PD. Optionally, as described above, the gate of the fifth transistor T5 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0128] The gate of the sixth transistor T6 can be connected to the intermediate node P0, the first terminal of the sixth transistor T6 can be connected to the second power supply terminal VGH_G, and the second terminal of the sixth transistor T6 can be connected to the pull-down node PD.

[0129] Optionally, referring to Figure 4, the second control circuit 02 may include a seventh transistor T7 and an eighth transistor T8.

[0130] The gate of the seventh transistor T7 can be connected to the first control terminal CN, the first terminal of the seventh transistor T7 can be connected to the first clock terminal CK1, and the second terminal of the seventh transistor T7 can be connected to the intermediate node P0.

[0131] The gate of the eighth transistor T8 can be connected to the second control terminal CNB, the first terminal of the eighth transistor T8 can be connected to the second clock terminal CK2, and the second terminal of the eighth transistor T8 can be connected to the intermediate node P0.

[0132] Optionally, referring to Figure 4, the first control circuit 01 may include: a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11.

[0133] The gate of the ninth transistor T9 can be connected to the first input terminal CAS1, the first terminal of the ninth transistor T9 can be connected to the first control terminal CN, and the second terminal of the ninth transistor T9 can be connected to the pull-up node PU. Optionally, as described above, the second terminal of the ninth transistor T9 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0134] The gate of the tenth transistor T10 can be connected to the second input terminal CAS2, the first terminal of the tenth transistor T10 can be connected to the second control terminal CNB, and the second terminal of the tenth transistor T10 can be connected to the pull-up node PU. Optionally, as described above, the second terminal of the tenth transistor T10 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0135] The gate of the eleventh transistor T11 can be connected to the pull-down node PD, the first terminal of the eleventh transistor T11 can be connected to the first power supply terminal VGL_G, and the second terminal of the eleventh transistor T11 can be connected to the pull-up node PU. Optionally, as described above, the second terminal of the eleventh transistor T11 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0136] Optionally, the fourth control circuit 05 may include a twelfth transistor T12. The first reset circuit 06 may include a thirteenth transistor T13. The second reset circuit 07 may include a fourteenth transistor T14. The first storage circuit 08 may include a first capacitor C1. The second storage circuit 09 may include a second capacitor C2.

[0137] The gate of the twelfth transistor T12 can be connected to the second power supply terminal VGH_G, the first terminal of the twelfth transistor T12 can be connected to the first pull-up node PU1, and the first terminal of the twelfth transistor T12 can be connected to the second pull-up node PU2.

[0138] The gate of the thirteenth transistor T13 can be connected to the reset control terminal RESET, the first terminal of the thirteenth transistor T13 can be connected to the first power supply terminal VGL_G, and the second terminal of the thirteenth transistor T13 can be connected to the first pull-up node PU1.

[0139] The gate of the fourteenth transistor T14 can be connected to the touch enable terminal EN_TOUCH, the first terminal of the fourteenth transistor T14 can be connected to the first power supply terminal VGL_G, and the second terminal of the fourteenth transistor T14 can be connected to the drive output terminal OUT.

[0140] One end of the first capacitor C1 can be connected to the drive output terminal OUT, and the other end of the first capacitor C1 can be connected to the second pull-up node PU2.

[0141] One end of the second capacitor C2 can be connected to the first power supply terminal VGL_G, and the other end of the first capacitor C1 can be connected to the pull-down node PD.

[0142] It is understood that the shift register unit shown in Figure 4 may include 14 transistors and 2 capacitors. Each transistor can be an N-type transistor, such as an NMOS transistor. Furthermore, the NMOS transistor can be made of low-temperature polycrystalline silicon (LTPS). Accordingly, the shift register unit shown in Figure 4 can also be called a novel 14T2C NMOS-type LTPS GOA unit. Of course, the shift register unit is not limited to this structure. Based on the circuit structure shown in Figure 4, the design of the shift register unit provided in this application embodiment is summarized as follows:

[0143] Firstly, in addition to connecting the first transistor T1 and the second transistor T2 to the drive output terminal OUT to output drive signals to the pixels and realize the drive function, a third transistor T3 and a fourth transistor T4 are added to connect to the shift output terminal CR. This allows the shift output terminal CR, distinct from the drive output terminal OUT, to output cascaded signals to the cascaded shift register unit, thus realizing the cascading function. In other words, the drive function and the cascading function are executed separately. Therefore, compared to embodiments that simultaneously output drive signals and cascaded signals through the same output terminal, the load connected to the drive output terminal OUT and the shift output terminal CR can be reduced. This effectively improves display defects such as screen flickering or split-screen display caused by high loading, ensuring a better display effect for the display device.

[0144] Secondly, in some embodiments, there is no sixth transistor T6, and the gate and first terminal of the seventh transistor T7 are both connected to the third clock terminal CK3. Based on this, when the current stage shift register unit outputs a high-level signal (i.e., the third clock signal provided by the third clock terminal CK3 is at a high level), the seventh transistor T7 in the cascaded shift register unit will be turned on, pulling up the potential of the pull-down node PD. Simultaneously, the high-level signal output by the current stage shift register unit will also turn on the ninth transistor T9 in the cascaded shift register unit, pulling up the potential of the first pull-up node PU1. This creates a DC path between the transistor pulling down the potential of the first pull-up node PU1 and the transistor pulling down the potential of the pull-down node PD, resulting in a competition between the potentials of the first pull-up node PU1 and the pull-down node PD. This leads to a poor output capability of the shift register unit. In this embodiment, by adding a sixth transistor T6, connecting the gate of the seventh transistor T7 to the first control terminal CN, and simultaneously connecting the eighth transistor T8 to the second control terminal CNB, the forward and reverse scan functions can be supported while avoiding the aforementioned competition relationship. This optimizes the mutual control capability between the first pull-up node PU1 and the pull-down node PD, thereby ensuring better potential stability of the first pull-up node PU1 and the pull-down node PD, and improving the output capability of the shift register unit. Furthermore, it avoids signal loss caused by the DC path, reduces the operating power consumption of the shift register unit, and improves the anti-aging capability of the shift register unit.

[0145] In some embodiments, to address the poor output capability of the shift register unit caused by the formed DC path, as mentioned above, the output capability of the shift register unit can be improved by setting a larger channel width-to-length ratio of the transistor. However, this setting not only increases the operating power consumption of the shift register unit but also hinders the design of narrow bezels. The embodiments of this application, by avoiding the formation of this DC path through circuit structure and connection relationships, allow for flexible design of the transistor's channel width-to-length ratio according to actual product requirements. This not only reduces the operating power consumption of the shift register unit but also saves bezel space, facilitating narrow bezel designs.

[0146] Taking the cascading of adjacent shift register units as an example, Figure 5 shows a schematic diagram of a structure with multiple cascaded shift register units, based on Figure 4. These multiple cascaded shift register units include the Nth-level shift register unit GOA_N, the (N+1)th-level shift register unit GOA_N+1, the (N+2)th-level shift register unit GOA_N+2, and the (N+3)th-level shift register unit GOA_N+3. Here, N can be an integer greater than 1. The shift register unit shown in Figure 4 can be the Nth-level shift register unit.

[0147] As can be seen from Figures 4 and 5, the shift output terminal CR_N of the Nth stage shift register unit can be connected to the first input terminal CAS1_N+1 of the (N+1)th stage shift register unit. The shift output terminal CR_N+1 of the (N+1)th stage shift register unit can be connected to the second input terminal CAS2_N of the Nth stage shift register unit and the first input terminal CAS1_N+2 of the (N+2)th stage shift register unit, respectively. The shift output terminal CR_N+2 of the (N+2)th stage shift register unit can be connected to the second input terminal CAS2_N+1 of the (N+1)th stage shift register unit and the first input terminal CAS1_N+3 of the (N+3)th stage shift register unit, respectively. The shift output terminal CR_N+3 of the (N+3)th stage shift register unit can be connected to the second input terminal CAS2_N+2 of the (N+2)th stage shift register unit. Accordingly, the first input terminal CAS1_N of the Nth stage shift register unit can be connected to the shift output terminal CR_N-1 of the (N-1)th stage shift register unit; the second input terminal CAS2_N+3 of the N+3rd stage shift register unit can be connected to the shift output terminal CR_N+4 of the N+4th stage shift register unit. The cascading method of other stages of shift register units is similar and will not be described in detail.

[0148] Furthermore, the multiple shift register units shown in Figure 5 share four clock terminals CLK1 to CLK4, representing a shift register unit using a 4-phase clock. However, it is not limited to using a 4-phase clock. For example, an 8-phase clock can be used, sharing eight clock terminals CLK1 to CLK8.

[0149] The Nth stage shift register unit is connected to clock inputs CK1 and CLK2, CK2 and CLK4, and CK3 and CLK1 respectively. The (N+1)th stage shift register unit is connected to clock inputs CK1 and CLK3, CK2 and CLK1 respectively, and CK3 and CLK2 respectively. The (N+2)th stage shift register unit is connected to clock inputs CK1 and CLK4, CK2 and CLK2 respectively, and CK3 and CLK3 respectively. The (N+3)th stage shift register unit is connected to clock inputs CK1 and CLK1, CK2 and CLK3 respectively, and CK3 and CLK4 respectively.

[0150] Optionally, based on Figure 4, Figure 6 shows a schematic layout of one shift register unit. Based on Figure 5, Figure 7 shows a schematic layout of another shift register unit.

[0151] Referring to Figures 6 and 7, it can be seen that the first control circuit 01 (including the ninth transistor T9 and the tenth transistor T10), the third control circuit 03 (including the fifth transistor T5 and the sixth transistor T6), the output circuit 04 (including the first transistor T1 to the fourth transistor T4), and the second control circuit 02 (including the seventh transistor T7 and the eighth transistor T8) can be arranged sequentially along the first direction X1 and along the direction closest to the drive output terminal OUT. Furthermore, the third transistor T3 and the first transistor T1 in the output circuit 04 can be arranged sequentially along the second direction X2, and the fourth transistor T4 and the second transistor T2 can be arranged sequentially along the first direction X1. The first direction X1 intersects the second direction X2. For example, the first direction X1 can be the pixel row direction. The second direction X2 can be the pixel column direction, and the first direction X1 and the second direction X2 can be perpendicular to each other. Furthermore, referring to Figure 6, it can be seen that from the end furthest from the drive output terminal OUT to the end closest to the drive output terminal OUT, that is, from left to right:

[0152] First, the ninth transistor T9 and the tenth transistor T10 included in the first control circuit 01 can be located on the far left and arranged along the second direction X2.

[0153] Next, the second power supply terminal VGH_G, the reset control terminal RESET, and the first power supply terminal VGL_G can be arranged at intervals along the first direction X1 and in the direction closest to the drive output terminal OUT. Furthermore, the thirteenth transistor T13 included in the first reset circuit 06 can be located between the second power supply terminal VGH_G and the reset control terminal RESET, so as to be reliably connected to both the second power supply terminal VGH_G and the reset control terminal RESET, respectively.

[0154] Next, the twelfth transistor T12 included in the fourth control circuit 05 and the fifth transistor T5 included in the third control circuit 03 can be located on the side of the second power supply terminal VGH_G near the drive output terminal OUT and arranged sequentially along the second direction X2. The twelfth transistor T12 establishes the connection between the first pull-up node PU1 and the second pull-up node PU2.

[0155] Next, the eleventh transistor T11 in the first control circuit 01, the fourth transistor T4 and the second transistor T2 in the output circuit 04 can be located on the side of the fifth transistor T5 near the drive output terminal OUT and arranged sequentially in the first direction X1. The sixth transistor T6 in the third control circuit 03 and the second capacitor C2 in the second storage circuit 09 can be located on the upper and lower sides of the second transistor T2, respectively, that is, the sixth transistor T6, the second transistor T2 and the second capacitor C2 can be arranged sequentially along the second direction X2. In addition, the second capacitor C2 can extend along the first direction X1.

[0156] Next, the first capacitor C1 included in the first storage circuit 08 can be located on the side of the second transistor T2 near the drive output terminal OUT, and the first capacitor C1 can extend along the second direction X2. The third transistor T3 and the first transistor T1 included in the output circuit 04 can be located on the side of the first capacitor C1 near the drive output terminal OUT and can be arranged sequentially along the second direction X2.

[0157] Finally, the eighth transistor T8 and the seventh transistor T7 included in the second control circuit 02 can be located on the side of the third transistor T3 near the drive output terminal OUT and can be arranged sequentially along the second direction X2. The second control terminal CNB, the first control terminal CN, multiple clock terminals (e.g., eight clock terminals CLK1 to CLK8) and the touch enable terminal EN_TOUCH can be arranged sequentially along the direction away from the eighth transistor T8 and along the first direction X1.

[0158] It is understood that the layout method adopted in this application embodiment can make full use of space to rationally arrange the various devices, thereby facilitating the design of narrow bezels. Optionally, referring to Figure 6, it can also be seen that the ninth transistor T9 and the tenth transistor T10 can be symmetrically arranged and have the same size. The seventh transistor T7 and the eighth transistor T8 can be symmetrically arranged and have the same size. The size of the fifth transistor T5 can be larger than the size of the sixth transistor T6, and the sizes of the eleventh transistor T11 to the thirteenth transistor T13. The size of the fourth transistor T4 can be smaller than the size of the second transistor T2, and the size of the first transistor T1 can be equal to the size of the third transistor T3. Here, the size can refer to the area of ​​the orthogonal projection on the substrate. In this way, it is also convenient for layout and facilitates the design of narrow bezels.

[0159] Optionally, in the film structure, the shift register unit may include an active layer, an insulating layer, a gate metal layer, and source / drain metal layers stacked sequentially. In some embodiments, adjacent transistors may also share a portion of the film layer to simplify the structure and save costs.

[0160] In summary, this application provides a shift register unit. This shift register unit includes a first control circuit, a second control circuit, a third control circuit, and an output circuit. With the cooperation of the first to third control circuits, the clock signal provided by the clock terminal can be flexibly set to ensure good stability of the potentials of the pull-up and pull-down nodes, thereby ensuring good output capability of the shift register unit. Furthermore, by having the output circuit respond to the potentials of the pull-up and pull-down nodes, outputting cascade signals to other shift register units and driving signals to pixels through different output terminals, the load on the cascade output terminals can be reduced, thus avoiding the cascading function being affected by the load and ensuring good cascading performance. Therefore, using this shift register unit can reliably drive pixels to emit light, avoiding display defects on the display panel and ensuring good display quality.

[0161] This application also provides a method for driving a shift register unit. As shown in Figure 8, the method includes:

[0162] Step 801, First stage: The first control circuit responds to the first input signal provided by the first input terminal and controls the first control terminal to be connected to the pull-up node; the second control circuit responds to the first control signal provided by the first control terminal and controls the first clock terminal to be connected to the intermediate node; the third control circuit responds to the potential of the pull-up node and controls the first power supply terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-up node and controls the third clock terminal to be connected to both the shift output terminal and the drive output terminal.

[0163] Step 802, Second Stage: The first control circuit responds to the first input signal and controls the first control terminal to be connected to the pull-up node; the second control circuit responds to the first control signal and controls the first clock terminal to be connected to the intermediate node; the third control circuit responds to the potential of the intermediate node and controls the second power supply terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-down node and controls the first power supply terminal to be connected to both the shift output terminal and the drive output terminal.

[0164] Optionally, in the structure shown in Figure 5, all transistors in the shift register unit are N-type transistors. Correspondingly, the first potential is high and the second potential is low. The shift register unit shown in Figure 4 is the Nth-stage shift register unit. Taking the cascaded Nth-stage shift register unit and the (N+1)th-stage shift register unit as an example, the driving method of the shift register unit is explained below in conjunction with Figure 9:

[0165] In stage t0, the cascaded signal output from the (N-1)th stage shift register unit via the cascaded output terminal CR_N-1 is at a high potential, meaning the potential of the first input signal provided by the first input terminal CAS1_N can also be high. For the first stage shift register unit where N is 1, the cascaded output terminal CR_N-1 can be replaced with the enable signal terminal STV. That is, the enable signal provided by the enable signal terminal STV can be at a high potential, which, correspondingly, enables the ninth transistor T9 to be turned on for the Nth stage shift register unit. At this time, the potential of the first control signal provided by the first control terminal CN can also be high. Thus, the high-potential first control signal can be transmitted to the first pull-up node PU1 via the turned-on ninth transistor T9, thereby pulling up the potential of the first pull-up node PU1. Furthermore, since the second power supply signal provided by the second power supply terminal VGH_G is at a high potential, the twelfth transistor T12 can be turned on. This allows the high-potential first control signal transmitted to the first pull-up node PU1 to be further transmitted to the second pull-up node PU2. The first capacitor C1 begins charging, turning on both the first transistor T1 and the third transistor T3. Consequently, the third clock signal provided by the third clock terminal CK3 (e.g., CLK1) can be transmitted to the drive output terminal OUT via the turned-on first transistor T1, and to the shift output terminal CR via the turned-on third transistor T3. Since the potential of the third clock signal can be low at this time, the potentials of the drive signal output through the drive output terminal OUT and the cascaded signal output through the shift output terminal CR are both low.

[0166] In stage t1, since the third clock signal provided by the third clock terminal CK3 (i.e., CLK1) is at a high potential for the Nth stage shift register unit, the potentials of the drive signal output through the drive output terminal OUT and the cascade signal output through the shift output terminal CR are both at a high potential. That is, the drive signal of this row can be pulled high to start charging the connected pixels, and a high potential signal can be output to the first input terminal CAS1 of the N+1 stage shift register unit, turning on the ninth transistor T9 in the N+1 stage shift register unit, so that the first capacitor C1 in the N+1 stage shift register unit starts charging and turns on the first transistor T1 and the third transistor T3 in the N+1 stage shift register unit. Since the first clock signal provided by the first clock terminal CK1 (i.e., CLK3) is at a low potential for the (N+1)th stage shift register unit, even if the seventh transistor T7 in the (N+1)th stage shift register unit turns on in response to the high-potential first control signal, the twelfth transistor T12 in the (N+1)th stage shift register unit can be turned off. This prevents the high-potential second power supply signal provided by the second power supply terminal VGH_G from being transmitted to the pull-down node PD of the (N+1)th stage shift register unit. In other words, the potential of the pull-down node PD of the (N+1)th stage shift register unit can be kept low. Compared with the timing diagram of the shift register unit without the sixth transistor T6 shown in Figure 10, it can be seen that the potential of the pull-down node PD of the (N+1)th stage shift register unit will not jump abnormally, thereby improving the DC path.

[0167] It is understandable that in Figure 10, where the shift register unit without the sixth transistor T6 is not configured, when the Nth-stage shift register unit outputs a high-level cascaded signal via the shift output terminal CR, causing the ninth transistor T9 of the (N+1)th-stage shift register unit to turn on and pull up the potential of the first pull-up node PU1, the pull-down node PD of the (N+1)th-stage shift register unit will also be abnormally raised due to the high potential of the first clock signal received by the (N+1)th-stage shift register unit, thereby reducing the output capability of the shift register unit. In this embodiment, by adding the sixth transistor T6, abnormal potential jumps in the pull-down node PD of the (N+1)th-stage shift register unit can be avoided, thus ensuring better output capability of the shift register unit.

[0168] In stages t2, t3, and t4, the potentials of the third clock signals provided by the third clock terminal CK3 (e.g., CLK2) connected to the N+1 stage shift register unit, the potentials of the third clock signals provided by the third clock terminal CK3 (e.g., CLK3) connected to the N+2 stage shift register unit, and the potentials of the third clock signals provided by the third clock terminal CK3 (e.g., CLK4) connected to the N+3 stage shift register unit can be successively high. This allows the N+1 stage shift register unit to the N+3 stage shift register unit to sequentially output high-potential drive signals through the drive output terminal OUT, and output high-potential cascaded signals through the shift output terminal CR, thereby achieving cascaded driving and ensuring normal display.

[0169] In Figure 9, the drive output terminals OUT of the shift register units from level N to level N+3 are labeled as OUT_N, OUT_N+1, OUT_N+2 and OUT_N+3, respectively, and the pull-up node PU and pull-down node PD of the shift register unit of level N+1 are labeled as PU_N+1 and PD_N+1, respectively.

[0170] Optionally, based on the embodiment of cascading two adjacent shift register units, taking the example of shift register units simultaneously outputting cascaded signals and drive signals through one output terminal, Figure 11 schematically shows the signal out output by eight cascaded shift register units through the output terminal OUT. <1> to out <8> And the potential of the pull-up nodes PU of the eight cascaded shift register units. <1> to pu <8> The timing simulation diagram is shown. Also, taking the shift register units outputting cascaded signals and drive signals through the cascaded output terminal CR and the drive output terminal OUT respectively as an example, Figure 12 schematically shows the signal output out of eight cascaded shift register units via the output terminal OUT. <1> to out <8> And the potential of the pull-up nodes PU of the eight cascaded shift register units. <1> to pu <8> The timing simulation diagram.

[0171] Comparing Figures 11 and 12, it can be seen that in the embodiment where cascade signals and drive signals are simultaneously output through a single output terminal, although the first-stage shift register unit can normally output drive signals through the output terminal OUT, the cascade signal output through this terminal is abnormal due to the large cascade load. This causes the potential of the pull-up node PU of the second-stage cascaded shift register unit to be insufficiently pulled up (i.e., too low), which in turn causes the potential of the signal output by the next-stage cascaded shift register unit through the output terminal OUT to be too low. The signals output by the third to eighth-stage shift register units through the output terminal OUT continue to attenuate. Specifically, by the third-stage shift register unit, the potential of its pull-up node PU can no longer be pulled up, so the cascading function is essentially lost from the third-stage shift register unit onwards, causing the display device to malfunction. In the embodiment of this application, because the cascade output terminal CR and the drive output terminal OUT are distinguished to output cascade signals and drive signals respectively, the cascading capability can be improved. Even if the potential of the pull-up node PU of the second-stage shift register unit is slightly attenuated, it can ensure that the potential of the pull-up node PU of each stage shift register unit is relatively stable, so that each stage shift register unit can output normally, thereby enabling the display device to display normally without being affected by loading degradation or transistor characteristic degradation and abnormal display.

[0172] It is understood that since the driving method of the shift register unit has the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the driving method will not be described again here for the sake of brevity.

[0173] This application provides a gate driving circuit. As shown in FIG13, the gate driving circuit includes a plurality of cascaded shift register units (GOAs) as shown in any one of FIG1 to FIG4.

[0174] In this configuration, the shift output terminal CR of each shift register unit GOA can be connected to the second input terminal CAS2 of the cascaded preceding shift register unit GOA, and the drive output terminal of each shift register unit GOA is connected to the first input terminal CAS1 of the cascaded following shift register unit GOA. The cascading method can be referred to Figure 5 and the description in the above embodiments, and will not be repeated here.

[0175] For example, Figure 13 schematically shows the Nth and N+3rd stage shift register units GOA_N to GOA_N+3, and the drive output terminals OUT of the Nth stage shift register units GOA_N to GOA_N+3 are labeled as OUT_N to OUT_N+3 respectively, and the cascaded output terminals CR of the Nth stage shift register units GOA_N to GOA_N+3 are labeled as CR_N to CR_N+3 respectively.

[0176] It is understood that since the gate drive circuit has essentially the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the gate drive circuit will not be described again here for the sake of brevity.

[0177] This application provides a display device. As shown in FIG14, the display device includes: a display panel 100, and a gate driving circuit 000 as shown in FIG13.

[0178] The display panel 000 includes multiple pixels (not shown in Figure 14). Referring to Figure 13, the gate driving circuit 100 is connected to the multiple pixels through the driving output terminal OUT and is used to transmit the gate driving signal GATE to the multiple pixels to drive them to emit light. Of course, it is not limited to outputting the gate driving signal; for example, it can also output the light emission control signal EM to drive the multiple pixels to emit light.

[0179] It is understood that since the display device has essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the display device will not be described again here for the sake of brevity.

[0180] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device or a liquid crystal display (LCD). Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0181] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the scope of this application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0182] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" or "including" encompasses the element or object listed after "comprising" or "including" and its equivalents, and do not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0183] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: A first control circuit is connected to a first input terminal, a second input terminal, a first control terminal, a second control terminal, a first power supply terminal, a pull-down node, and a pull-up node, respectively. It is used to control the connection and disconnection between the first control terminal and the pull-up node in response to a first input signal provided by the first input terminal, control the connection and disconnection between the second control terminal and the pull-up node in response to a second input signal provided by the second input terminal, and control the connection and disconnection between the first power supply terminal and the pull-up node in response to the potential of the pull-down node. The second control circuit is connected to the first control terminal, the second control terminal, the first clock terminal, the second clock terminal, and the intermediate node, respectively, and is used to control the connection and disconnection between the first clock terminal and the intermediate node in response to the first control signal provided by the first control terminal, and to control the connection and disconnection between the second clock terminal and the intermediate node in response to the second control signal provided by the second control terminal. The third control circuit is connected to the second power supply terminal, the pull-up node, the intermediate node and the pull-down node respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node. The output circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, the shift output terminal, and the drive output terminal, respectively. It is used to control the connection and disconnection of the third clock terminal and the shift output terminal, and the connection and disconnection of the third clock terminal and the drive output terminal, in response to the potential of the pull-up node. It also controls the connection and disconnection of the first power supply terminal and the shift output terminal, and the connection and disconnection of the first power supply terminal and the drive output terminal, in response to the potential of the pull-down node. The shift output terminal is used to connect to other cascaded shift register units, and the drive output terminal is used to connect to pixels in the display panel.

2. The shift register cell of claim 1, wherein, The output circuit includes: The first output sub-circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, and the drive output terminal, respectively, and is used to control the connection and disconnection of the third clock terminal and the drive output terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the first power supply terminal and the drive output terminal in response to the potential of the pull-down node. The second output sub-circuit is connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the third clock terminal and the shift output terminal in response to the potential of the pull-up node, and to control the on / off state of the first power supply terminal and the shift output terminal in response to the potential of the pull-down node.

3. The shift register cell of claim 2, wherein, The first output sub-circuit includes: a first transistor and a second transistor; the second output sub-circuit includes: a third transistor and a fourth transistor; The gate of the first transistor is connected to the pull-up node, the first terminal of the first transistor is connected to the third clock terminal, and the second terminal of the first transistor is connected to the drive output terminal. The gate of the second transistor is connected to the pull-down node, the first terminal of the second transistor is connected to the first power supply terminal, and the second terminal of the second transistor is connected to the drive output terminal. The gate of the third transistor is connected to the pull-up node, the first terminal of the third transistor is connected to the third clock terminal, and the second terminal of the third transistor is connected to the shift output terminal. The gate of the fourth transistor is connected to the pull-down node, the first terminal of the fourth transistor is connected to the first power supply terminal, and the second terminal of the fourth transistor is connected to the shift output terminal.

4. The shift register cell of claim 3, wherein, The channel width-to-length ratio of the third transistor is different from that of the first transistor; and / or, the channel width-to-length ratio of the fourth transistor is different from that of the second transistor.

5. The shift register cell of claim 4, wherein, The ratio of the channel width-to-length ratio of the third transistor to that of the first transistor is greater than 80%; the ratio of the channel width-to-length ratio of the fourth transistor to that of the second transistor is greater than 80%.

6. A shift register cell as claimed in any one of claims 3 to 5, wherein, The first control circuit, the third control circuit, the output circuit, and the second control circuit are arranged sequentially along the first direction and in the direction closest to the drive output terminal; Furthermore, the third transistor and the first transistor in the output circuit are arranged sequentially along the second direction, and the fourth transistor and the second transistor are arranged sequentially along the first direction, wherein the first direction intersects the second direction.

7. The shift register cell of any one of claims 1 to 6, wherein, The third control circuit includes: The first control sub-circuit is connected to the pull-up node, the first power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the first power supply terminal and the pull-down node in response to the potential of the pull-up node. The second control sub-circuit is connected to the intermediate node, the second power supply terminal, and the pull-down node respectively, and is used to control the on / off state of the second power supply terminal and the pull-down node in response to the potential of the intermediate node.

8. The shift register cell of claim 7, wherein, The first control sub-circuit includes a fifth transistor; the second control sub-circuit includes a sixth transistor. The gate of the fifth transistor is connected to the pull-up node, the first terminal of the fifth transistor is connected to the first power supply terminal, and the second terminal of the fifth transistor is connected to the pull-down node. The gate of the sixth transistor is connected to the intermediate node, the first terminal of the sixth transistor is connected to the second power supply terminal, and the second terminal of the sixth transistor is connected to the pull-down node.

9. The shift register cell of any of claims 1 to 8, wherein, The second control circuit includes: a seventh transistor and an eighth transistor; The gate of the seventh transistor is connected to the first control terminal, the first terminal of the seventh transistor is connected to the first clock terminal, and the second terminal of the seventh transistor is connected to the intermediate node. The gate of the eighth transistor is connected to the second control terminal, the first terminal of the eighth transistor is connected to the second clock terminal, and the second terminal of the eighth transistor is connected to the intermediate node.

10. The shift register cell of any one of claims 1 to 9, wherein, The first control circuit includes: a ninth transistor, a tenth transistor, and an eleventh transistor; The gate of the ninth transistor is connected to the first input terminal, the first electrode of the ninth transistor is connected to the first control terminal, and the second electrode of the ninth transistor is connected to the pull-up node. The gate of the tenth transistor is connected to the second input terminal, the first terminal of the tenth transistor is connected to the second control terminal, and the second terminal of the tenth transistor is connected to the pull-up node. The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the pull-up node.

11. The shift register cell of any of claims 1 to 10, wherein, The pull-up node includes: a first pull-up node and a second pull-up node; the first control circuit, the second control circuit, and the third control circuit are all connected to the first pull-up node; and the output circuit is connected to the second pull-up node; furthermore, the shift register unit includes: The fourth control circuit is connected to the second power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the second power supply signal provided by the second power supply terminal. And / or, the shift register unit further includes: The first reset circuit is connected to the reset control terminal, the first power supply terminal, and the first pull-up node, respectively, and is used to control the connection and disconnection of the first power supply terminal and the first pull-up node in response to the reset control signal provided by the reset control terminal. The second reset circuit is connected to the touch enable terminal, the first power supply terminal and the drive output terminal respectively, and is used to control the on / off state of the first power supply terminal and the drive output terminal in response to the touch enable signal provided by the touch enable terminal. A first storage circuit is connected between the second pull-up node and the drive output terminal, and is used to control the potential of the second pull-up node; The second storage circuit is connected between the pull-down node and the first power supply terminal, and is used to control the potential of the pull-down node.

12. The shift register cell of claim 11, wherein, The fourth control circuit includes a twelfth transistor; the first reset circuit includes a thirteenth transistor; the second reset circuit includes a fourteenth transistor; the first storage circuit includes a first capacitor; and the second storage circuit includes a second capacitor. The gate of the twelfth transistor is connected to the second power supply terminal, the first terminal of the twelfth transistor is connected to the first pull-up node, and the first terminal of the twelfth transistor is connected to the second pull-up node. The gate of the thirteenth transistor is connected to the reset control terminal, the first terminal of the thirteenth transistor is connected to the first power supply terminal, and the second terminal of the thirteenth transistor is connected to the first pull-up node. The gate of the fourteenth transistor is connected to the touch enable terminal, the first terminal of the fourteenth transistor is connected to the first power supply terminal, and the second terminal of the fourteenth transistor is connected to the drive output terminal. One end of the first capacitor is connected to the drive output terminal, and the other end of the first capacitor is connected to the second pull-up node; One end of the second capacitor is connected to the first power supply terminal, and the other end of the first capacitor is connected to the pull-down node.

13. A method for driving a shift register unit, the method comprising: In the first stage, the first control circuit responds to the first input signal provided by the first input terminal and controls the first control terminal to be connected to the pull-up node. The second control circuit responds to the first control signal provided by the first control terminal and controls the first clock terminal to be connected to the intermediate node; the third control circuit responds to the potential of the pull-up node and controls the first power supply terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node and controls the third clock terminal, shift output terminal, and drive output terminal to all be turned on. In the second stage, the first control circuit responds to the first input signal and controls the first control terminal to be connected to the pull-up node. The second control circuit responds to the first control signal and controls the first clock terminal to be connected to the intermediate node; The third control circuit responds to the potential of the intermediate node and controls the second power supply terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-down node and controls the first power supply terminal to be connected to both the shift output terminal and the drive output terminal.

14. A gate drive circuit, the gate drive circuit comprising: A series of cascaded shift register units as described in any one of claims 1 to 12; In this system, the shift output of each shift register unit is connected to the second input of the cascaded previous shift register unit, and the drive output of each shift register unit is connected to the first input of the cascaded subsequent shift register unit.

15. A display device comprising: The display panel, and the gate driving circuit as described in claim 14; The display panel includes multiple pixels; The gate driving circuit is connected to the plurality of pixels through a driving output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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