Equal-weight arbitration circuit

Abstract

The application provides an equal-weight arbitration circuit, which comprises a priority updating module and a request arbitration module. The priority updating module outputs ID signals corresponding to each request. After the mth request is successfully arbitrated, the priority of the mth request becomes the lowest. For the remaining n-1 requests, if the priority of a request is higher than that of the mth request, the priority of the request remains unchanged; if the priority of a request is lower than that of the mth request, the priority of the request is increased by 1. The request arbitration module receives arbitration request input signals and the ID signals corresponding to each request output by the priority updating module, obtains rearrangement request signals according to the arbitration request input signals and the ID signals corresponding to each request, obtains the position signal of the controllable shift register corresponding to the request with the highest priority by using the rearrangement request signals, and then obtains an arbitration result signal and a shift control signal according to the position signal. The application solves the problem of poor extensibility of the existing arbitration circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an equal-weight arbitration circuit. Background Technology

[0002] In logic circuit design, an arbitration circuit can receive multiple request signals and determine their priority based on their order.

[0003] The commonly used arbitration circuit is the Round Robin arbitration circuit. However, while the Round Robin arbitration circuit has advantages in scalability and the characteristic that circuit delay increases with the number of channels, it is insufficient in implementing equal weights. On the other hand, the circuit structure based on historical values ​​for arbitration has advantages in equal weights, but it is insufficient in scalability and the characteristic that circuit delay increases with the number of channels. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an equal-weight arbitration circuit to solve the problem of insufficient scalability of existing arbitration circuits.

[0005] To achieve the above and other related objectives, the present invention provides an equal-weight arbitration circuit, the circuit comprising: a priority update module and an arbitration request module.

[0006] The priority update module outputs the ID signal corresponding to each request. It includes n controllable shift registers, each of which stores the ID signal corresponding to one request. The ID signal corresponding to each request is one-hot encoded. The priority of the ID signals stored in the n controllable shift registers decreases sequentially, with the ID signal stored in the first controllable shift register having the highest priority and the ID signal stored in the nth controllable shift register having the lowest priority. After the mth request is successfully arbitrated, the priority of the mth request becomes the lowest. For the remaining n-1 requests, if their priority is higher than that of the mth request, their priority remains unchanged; if their priority is lower than that of the mth request, their priority is incremented by 1. When receiving the shift control signal, each controllable shift register shifts the request whose priority needs to be incremented by 1. The nth controllable shift register with the lowest priority receives the arbitration result signal.

[0007] The arbitration request module receives the arbitration request input signal and the ID signals corresponding to each request output by the priority update module. Based on the arbitration request input signal and the ID signals corresponding to each request output by the priority update module, it obtains the rearranged request signal after priority rearrangement. It then uses the rearranged request signal to obtain the position signal of the controllable shift register corresponding to the highest priority request. Finally, it obtains the arbitration result signal and the shift control signal based on the position signal of the controllable shift register corresponding to the highest priority request.

[0008] Wherein, the shift control signal and the arbitration request input signal are both n-bit binary codes, where n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

[0009] Optionally, the n controllable shift registers receive the shift control signal to perform shifting.

[0010] Optionally, when receiving the shift control signal, each of the controllable shift registers may shift requests requiring priority increment by 1 using the following method:

[0011] The n-bit binary code of the shift control signal corresponds one-to-one with the n controllable shift registers. The shift control signal corresponding to the controllable shift register that needs to be shifted is 1, and the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0. Each time the shift is moved to a higher priority direction, the nth controllable shift register with the lowest priority receives the arbitration result signal.

[0012] Optionally, the arbitration result signal is an n-bit one-hot encoded signal.

[0013] Optionally, the method for obtaining the rearranged request signal according to priority based on the arbitration request input signal and the ID signal corresponding to each request includes:

[0014] The arbitration request input signal is ANDed with the ID signals corresponding to each request stored in the n controllable shift registers to obtain n n-bit binary codes;

[0015] Perform an OR operation on n bits of each binary code to obtain an n-bit rearrangement request signal.

[0016] Optionally, the method for obtaining the position signal of the controllable shift register corresponding to the highest priority request using the rearrangement request signal includes:

[0017] Perform a bitwise AND operation between the n-bit rearrangement request signal and its own complement to obtain the position signal of the controllable shift register corresponding to the n-bit highest priority request.

[0018] Optionally, the method for obtaining the arbitration result signal based on the position signal of the controllable shift register corresponding to the highest priority request includes:

[0019] Each bit in the position signal of the controllable shift register corresponding to the highest priority request is expanded into the same n-bit signal, and ANDed with the ID signal corresponding to each request to obtain n n-bit binary codes.

[0020] The arbitration result signal is obtained by performing an OR operation on the n bits of each binary code.

[0021] Optionally, the method for obtaining the shift control signal based on the position signal of the controllable shift register corresponding to the highest priority request includes:

[0022] Perform an OR operation between the position signal of the controllable shift register corresponding to the highest priority request and the result of decrementing itself by 1;

[0023] The result of the OR operation is inverted to obtain the n-bit shift control signal.

[0024] Optionally, the priority update module receives a driving clock signal, and the driving clock signal also drives the generation of the arbitration request input signal.

[0025] As described above, the equal-weighted arbitration circuit of the present invention has a more balanced weight compared to the commonly used Round Robin arbitration circuit, and is easier to expand to multiple channels compared to the commonly used historical value-based arbitration circuit. At the same time, the circuit delay does not increase significantly with the increase of the number of channels. Attached Figure Description

[0026] Figure 1 The diagram shown is an equal-weight arbitration circuit diagram according to the present invention.

[0027] Figure 2 The diagram shown is a circuit diagram of the priority update module of this invention.

[0028] Figure 3 The diagram shown is a circuit diagram of the arbitration request module of this invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] like Figure 1 As shown, this embodiment provides an equal-weight arbitration circuit, which includes a priority update module and an arbitration request module.

[0032] The priority update module outputs the ID signal ID[n:1] corresponding to each request, which includes n controllable shift registers. Each controllable shift register stores the ID signal ID[n:1] corresponding to one request. The ID signal ID[n:1] corresponding to each request is one-hot encoded. The priority of the ID signal ID[n:1] stored in the n controllable shift registers decreases sequentially, with the ID signal ID[n:1] stored in the first controllable shift register having the highest priority. The D signal ID[n:1] has the lowest priority. After the m-th request is successfully arbitrated, the priority of the m-th request becomes the lowest. For the remaining n-1 requests, if their priority is higher than that of the m-th request, their priority remains unchanged. If their priority is lower than that of the m-th request, their priority is increased by 1. When each of the controllable shift registers receives the shift control signal EN[n:1], it shifts the requests whose priority needs to be increased by 1. The n-th controllable shift register with the lowest priority receives the arbitration result signal GRANT[n:1].

[0033] The arbitration request module receives the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request output by the priority update module. Based on the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request output by the priority update module, it obtains the rearranged request signal req_valid[n:1] after priority rearrangement. Using the rearranged request signal req_valid[n:1], it obtains the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request. Then, based on the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request, it obtains the arbitration result signal GRANT[n:1] and the shift control signal EN[n:1].

[0034] Wherein, the shift control signal EN[n:1] and the arbitration request input signal REQ[n:1] are both n-bit binary codes, where n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

[0035] In this embodiment, the leftmost controllable shift register (i.e., the nth controllable shift register) is used to store the request with the lowest priority, and the rightmost controllable shift register (i.e., the first controllable shift register) is used to store the request with the highest priority.

[0036] Specifically, the priority update module receives the driving clock signal CLK, and the driving clock signal CLK also drives the generation of the arbitration request input signal REQ[n:1].

[0037] Specifically, the n controllable shift registers receive the shift control signal EN[n:1] to perform shifting.

[0038] Specifically, when each of the controllable shift registers receives the shift control signal EN[n:1], the method for shifting requests that require priority increment includes: the n-bit binary code of the shift control signal corresponds one-to-one with the n controllable shift registers, and the shift control signal corresponding to the controllable shift register that needs to be shifted is 1, while the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0. Each time the shift is performed in the direction of higher priority, the nth controllable shift register with the lowest priority receives the arbitration result signal.

[0039] In this embodiment, each shift towards the highest priority direction means that the ID signal IDm[n:1] stored in the m-th controllable shift register is moved to the (m-1)-th controllable shift register.

[0040] Specifically, the arbitration result signal GRANT[n:1] is an n-bit one-hot encoded signal.

[0041] Specifically, the method for obtaining the rearranged request signal req_valid[n:1] based on the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request includes: performing a bitwise AND operation on the arbitration request input signal REQ[n:1] with the ID signals ID[n:1] corresponding to each request stored in the n controllable shift registers to obtain n n-bit binary codes; performing an OR operation on the n bits of each binary code to obtain an n-bit rearranged request signal req_valid[n:1].

[0042] Specifically, the method for obtaining the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request using the rearrangement request signal req_valid[n:1] includes: performing an AND operation between the n-bit rearrangement request signal req_valid[n:1] and its own complement to obtain the position signal valid[n:1] of the controllable shift register corresponding to the n-bit highest priority request.

[0043] Specifically, the method for obtaining the arbitration result signal GRANT[n:1] based on the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request includes: expanding each bit in the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request into the same n-bit signal, and performing a bitwise AND operation with the ID signal ID[n:1] corresponding to each request to obtain n n-bit binary codes; performing an OR operation on the n bits of each binary code to obtain the arbitration result signal GRANT[n:1].

[0044] Specifically, the method for obtaining the shift control signal EN[n:1] based on the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request includes: performing an OR operation on the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request and the result of subtracting 1 from itself; and inverting the result of the OR operation to obtain the n-bit shift control signal.

[0045] In this embodiment, it is assumed that there are 3 requests, that is, there are 3 controllable shift registers. REG_ID3[3:1], REG_ID2[3:1] and REG_ID1[3:1] represent the values ​​stored in each of the controllable shift registers, which represent the third request, the second request and the first request, respectively. The first request has the highest priority and the third request has the lowest priority. REG_ID1[3:1] = 3'b001, REG_ID2[3:1] = 3'b010 and REG_ID3[3:1] = 3'b100. When the second and third requests arrive, the arbitration request input signal REQ[n] = 3'b110 is input to the arbitration request module, and the authorization signal GRANT[n] = 3'b010 is output, generating the shift control signal EN[n] = 3'b100, which is then output to the priority update module. Under the drive of the drive clock signal CLK, in the priority update module, REG_ID3[3:1] is updated to 3'b010, REG_ID2[3:1] is updated to 3'b100, and REG_ID1[3:1] remains at its original value of 3'b001.

[0046] The shift request is the request output after the priority update module performs the shift, and is represented as ID3[3:1], ID2[3:1], and ID1[3:1], respectively. For the three signals, ID3[3:1] corresponds to the updated REG_ID3[3:1] with a value of 3'b010, ID2[3:1] is the updated REG_ID2[3:1] with a value of 3'b100, and ID1[3:1] corresponds to the REG_ID1[3:1] with the original value of 3'b00. 1. When the first and third requests occur, the arbitration request input signal REQ[3:1] is 3'b101. ID3[3:1], ID2[3:1], and ID1[3:1] are ANDed with REQ[3:1] respectively to obtain three 3-bit binary codes. Each bit of each 3-bit binary code is ORed to obtain the rearrangement request signal req_valid[3:1], with a value of 3'b011, indicating that the requests corresponding to ID2[3:1] and ID1[3:1] have occurred. The rearrangement request signal req_valid[3:1] is ANDed with its own complement to obtain the confirmation signal valid[3:1], with a value of 3'b001, indicating that the request corresponding to ID1[3:1] has been successfully arbitrated. The confirmation signal valid[3:1] is ANDed with ID3[3:1], ID2[3:1] and ID1[3:1] respectively, and then an OR operation is performed on the result of the AND operation to obtain the one-hot code of the request corresponding to ID1[3:1], that is, the grant signal GRANT[3:1], with a value of 3'b001; at the same time, the confirmation signal valid[3:1] is ORed with the result of itself minus one, and then the result of the OR operation is inverted to obtain the shift control signal EN[3:1], with a value of 3'b110, indicating that REG_ID 3[3:1] and REG_ID2[3:1] in the priority update circuit have been shifted (shifted to the right for storage) under the drive of the clock drive signal CLK, and at the same time, the grant signal GRANT[3:1] is stored in REG_ID3[3:1].

[0047] Specifically, the n controllable shift registers are arranged from left to right, and each represents the requested number of paths.

[0048] Specifically, the priority of each request is stored in each of the controllable shift registers in an n-bit one-hot encoding.

[0049] In summary, the equal-weighted arbitration circuit of this invention has a more balanced weighting compared to the commonly used Round Robin arbitration circuit, and is easier to expand into multiple channels compared to the commonly used historical value-based arbitration circuit. Furthermore, the circuit delay does not increase significantly with the number of channels. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An equal-weight arbitration circuit, characterized in that, The circuit includes: a priority update module and an arbitration request module. The priority update module outputs the ID signal corresponding to each request. It includes n controllable shift registers, each of which stores the ID signal corresponding to one request. The ID signal corresponding to each request is one-hot encoded. The priority of the ID signals stored in the n controllable shift registers decreases sequentially, with the ID signal stored in the first controllable shift register having the highest priority and the ID signal stored in the nth controllable shift register having the lowest priority. After the mth request is successfully arbitrated, the priority of the mth request becomes the lowest. For the remaining n-1 requests, if their priority is higher than that of the mth request, their priority remains unchanged; if their priority is lower than that of the mth request, their priority is incremented by 1. When each controllable shift register receives the shift control signal output by the request arbitration module, it shifts the request whose priority needs to be incremented by 1. The nth controllable shift register with the lowest priority receives the arbitration result signal output by the request arbitration module. The arbitration request module receives the arbitration request input signal and the ID signals corresponding to each request output by the priority update module. Based on the arbitration request input signal and the ID signals corresponding to each request output by the priority update module, it obtains the rearranged request signal after priority rearrangement. It then uses the rearranged request signal to obtain the position signal of the controllable shift register corresponding to the highest priority request. Finally, it obtains the arbitration result signal and the shift control signal based on the position signal of the controllable shift register corresponding to the highest priority request. Wherein, the shift control signal and the arbitration request input signal are both n-bit binary codes, where n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

2. The equal-weight arbitration circuit according to claim 1, characterized in that, The n controllable shift registers receive the shift control signal to perform shifting.

3. The equal-weight arbitration circuit according to claim 2, characterized in that, When each of the controllable shift registers receives the shift control signal, the method for shifting requests that require priority increment includes: The n-bit binary code of the shift control signal corresponds one-to-one with the n controllable shift registers. The shift control signal corresponding to the controllable shift register that needs to be shifted is 1, and the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0. Each time the shift is moved to a higher priority direction, the nth controllable shift register with the lowest priority receives the arbitration result signal.

4. The equal-weight arbitration circuit according to claim 1, characterized in that, The arbitration result signal is an n-bit one-hot encoded signal.

5. The equal-weight arbitration circuit according to claim 1, characterized in that, The method for obtaining the rearranged request signal based on priority according to the arbitration request input signal and the ID signal corresponding to each request includes: The arbitration request input signal is ANDed with the ID signals corresponding to each request stored in the n controllable shift registers to obtain n n-bit binary codes; Perform an OR operation on n bits of each binary code to obtain an n-bit rearrangement request signal.

6. The equal-weight arbitration circuit according to claim 5, characterized in that, The method for obtaining the position signal of the controllable shift register corresponding to the highest priority request using the rearrangement request signal includes: Perform a bitwise AND operation between the n-bit rearrangement request signal and its own complement to obtain the position signal of the controllable shift register corresponding to the n-bit highest priority request.

7. The equal-weight arbitration circuit according to claim 6, characterized in that, The method for obtaining the arbitration result signal based on the position signal of the controllable shift register corresponding to the highest priority request includes: Each bit in the position signal of the controllable shift register corresponding to the highest priority request is expanded into the same n-bit signal, and ANDed with the ID signal corresponding to each request to obtain n n-bit binary codes. The arbitration result signal is obtained by performing an OR operation on the n bits of each binary code.

8. The equal-weight arbitration circuit according to claim 7, characterized in that, The method for obtaining the shift control signal based on the position signal of the controllable shift register corresponding to the highest priority request includes: Perform an OR operation between the position signal of the controllable shift register corresponding to the highest priority request and the result of decrementing itself by 1; The result of the OR operation is inverted to obtain the n-bit shift control signal.

9. The equal-weight arbitration circuit according to claim 1, characterized in that, The priority update module receives a driving clock signal, and the driving clock signal also drives the generation of the arbitration request input signal.

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