Display device and driving method thereof

Abstract

A display device and its driving method are disclosed. The display device includes: a display panel including a plurality of pixels configured to be driven to vary between a first refresh rate and a second refresh rate different from the first refresh rate; a processor configured to output a frequency change command signal representing a switching request between the first refresh rate and the second refresh rate; and a timing controller that controls the time at which the refresh rate of the plurality of pixels varies between the first refresh rate and the second refresh rate according to the time position of the frequency change command signal received from the processor.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0188751, filed on December 27, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device and its driving method. Background Technology

[0004] Variable refresh rate (VRR) is used as one of the various functions required for display devices. VRR is a technology that drives pixels at a certain refresh rate, then increases the refresh rate when high-speed driving is needed, or decreases the refresh rate when reduced power consumption or low-speed driving is needed, thereby operating the pixels. Refresh rate can refer to frame rate or frame frequency.

[0005] When the refresh rate changes based on VRR (e.g., when the refresh rate suddenly increases during low-speed driving), the interface timing associated with the transmission of image signals can be delayed, or the time when the pixel drive voltage to be supplied to the pixel changes can be delayed, resulting in image distortion.

[0006] Therefore, it is necessary to minimize image distortion caused by changes in refresh rate on display devices. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of related technologies, the present invention provides a display device and its driving method, which can minimize image distortion caused by changes in refresh rate.

[0008] To achieve these objectives and other advantages, according to the intent of the invention, as embodied and broadly described herein, a display device includes: a display panel comprising a plurality of pixels driven variably between a first refresh rate and a second refresh rate higher than the first refresh rate; a processor that outputs a frequency change command signal under predetermined specific conditions; and a timing controller that controls the refresh rate change time differently based on the plurality of pixels according to the time position of the frequency change command signal received from the processor.

[0009] In another aspect of the present invention, a driving method for a display device is provided, the display device including a plurality of pixels driven variably between a first refresh rate and a second refresh rate higher than the first refresh rate, the driving method including: outputting a frequency change command signal by using a processor under predetermined specific conditions; and controlling the refresh rate change time differently based on the plurality of pixels by using a timing controller according to the time position of the frequency change command signal received from the processor.

[0010] In one or more embodiments, a display device is provided, comprising: a display panel including a plurality of pixels configured to be driven to vary between a first refresh rate and a second refresh rate different from the first refresh rate; a processor configured to output a frequency change command signal representing a switching request between the first refresh rate and the second refresh rate; and a timing controller that controls the time at which the refresh rate of the plurality of pixels varies between the first refresh rate and the second refresh rate according to the time position of the frequency change command signal received from the processor.

[0011] In one or more embodiments, the plurality of pixels are driven at the first refresh rate during a plurality of skip frames and a first refresh frame that are distinct from each other relative to the first synchronization signal, and the plurality of pixels are driven at the second refresh rate during a plurality of second refresh frames that are distinct from each other relative to the first synchronization signal, wherein first image data is applied to the plurality of pixels during the first refresh frame, and the first image data is maintained in the plurality of pixels during at least one of the plurality of skip frames.

[0012] In one or more embodiments, in response to the timing controller receiving the frequency change command signal during the last hop of the plurality of hops, the timing controller is configured to control the time during which the refresh rate of the plurality of pixels changes between the first refresh rate and the second refresh rate according to the first synchronization signal, wherein, in response to the timing controller receiving the frequency change command signal during a hop preceding the last hop of the plurality of hops, the timing controller is configured to control the time during which the refresh rate of the plurality of pixels changes between the first refresh rate and the second refresh rate according to a second synchronization signal, wherein the first synchronization signal and the second synchronization signal have the same period and different phases.

[0013] In one or more embodiments, in response to the timing controller receiving the frequency change command signal during the last frame skip, the timing controller is configured to: during the last frame skip, based on the first synchronization signal, output a transmission request signal for second image data for refresh driving to the processor, change the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and change the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0014] In one or more embodiments, in response to the timing controller receiving the frequency change command signal during a hop frame preceding the last hop frame, the timing controller differently controls the timing of the refresh rate change between the first refresh rate and the second refresh rate based on whether the frequency change command signal is received during a hop frame preceding the second synchronization signal or during a hop frame following the second synchronization signal.

[0015] In one or more embodiments, in response to receiving the frequency change command signal during a frame skipping period earlier than the second synchronization signal, the timing controller is configured to: during the frame skipping period, based on the second synchronization signal, output a transmission request signal for second image data for refresh driving to the processor, change the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and change the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0016] In one or more embodiments, in response to receiving the frequency change command signal during a frame skipping period following the second synchronization signal, the timing controller is configured to: during another frame skipping period following the first frame skipping period in the plurality of frames, based on the second synchronization signal, output a transmission request signal for second image data for refresh driving to the processor, change the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and change the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0017] In one or more embodiments, the pixel driving voltage is a voltage used to initialize the anode of the light-emitting device constituting each pixel.

[0018] In one or more embodiments, in the refresh frame, the timing controller controls the pixel driving voltage to a second voltage having a first level; in the skip frame, the timing controller controls the pixel driving voltage to a first voltage having a second level lower than the first level.

[0019] In one or more embodiments, when the frequency change command signal is received from the processor in the last skip frame, the timing controller shifts the pixel driving voltage from the second level to the first level for refresh driving of the next refresh frame.

[0020] In one or more embodiments, the timing controller is configured to recognize interrupt information contained in the frequency change command signal, and in response to the interrupt information, perform the refresh rate change operation in a skip frame arranged at the reception time of the frequency change command signal to irregularly change the refresh rate before completing the first refresh rate operation.

[0021] In one or more embodiments, a driving method for a display device is provided, the display device including a plurality of pixels configured to be driven alternately between a first refresh rate and a second refresh rate different from the first refresh rate, the driving method including: outputting a frequency change command signal to a timing controller of the display device via a processor of the display device, the frequency change command signal representing a switching request between the first refresh rate and the second refresh rate; and controlling the refresh rate of the plurality of pixels to vary between the first refresh rate and the second refresh rate at different times according to the time position of the frequency change command signal received from the processor by the timing controller.

[0022] In one or more embodiments, the plurality of pixels are driven at the first refresh rate during a plurality of skip frames and a first refresh frame that are distinct from each other relative to the first synchronization signal, and the plurality of pixels are driven at the second refresh rate during a plurality of second refresh frames that are distinct from each other relative to the first synchronization signal, wherein first image data is applied to the plurality of pixels during the first refresh frame, and the first image data is maintained in the plurality of pixels during at least one of the plurality of skip frames.

[0023] In one or more embodiments, controlling the refresh rate change time differently includes: in response to the timing controller receiving the frequency change command signal during the last hop of the plurality of hops, controlling the refresh rate of the plurality of pixels to change between the first refresh rate and the second refresh rate by the timing controller according to the first synchronization signal, wherein, in response to the timing controller receiving the frequency change command signal during a hop preceding the last hop of the plurality of hops, the timing controller controlling the refresh rate of the plurality of pixels to change between the first refresh rate and the second refresh rate by the timing controller according to the second synchronization signal, wherein the first synchronization signal and the second synchronization signal have the same period and different phases.

[0024] In one or more embodiments, controlling the refresh rate change time according to the first synchronization signal includes: determining, by the timing controller, whether the frequency change command signal is received from the processor during the last frame skip; and during the last frame skip, based on the first synchronization signal, outputting a transmission request signal for second image data for refresh driving to the processor, changing the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and changing the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0025] In one or more embodiments, controlling the refresh rate change time according to the second synchronization signal includes: determining, by the timing controller, whether the frequency change command signal is received during a hop frame earlier than the last hop frame; and, during a hop frame after the second synchronization signal, controlling the refresh rate to change between the first refresh rate and the second refresh rate differently by the timing controller based on whether the frequency change command signal was received during a hop frame before the second synchronization signal or during a hop frame after the second synchronization signal.

[0026] In one or more embodiments, controlling the timing of the refresh rate change differently includes: in response to receiving the frequency change command signal during a frame skip earlier than the second synchronization signal, the timing controller outputs a transmission request signal for second image data for refresh driving to the processor during the frame skip based on the second synchronization signal, changes the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and changes the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0027] In one or more embodiments, controlling the refresh rate change timing differently includes: in response to receiving the frequency change command signal during a frame skip after the second synchronization signal, the timing controller outputs a transmission request signal for second image data for refresh driving to the processor based on the second synchronization signal during another frame skip after the first frame skip in the plurality of frames, changes the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and changes the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

[0028] In one or more embodiments, the pixel driving voltage is a voltage used to initialize the anode of the light-emitting device constituting each pixel.

[0029] In one or more embodiments, in the refresh frame, the pixel driving voltage is controlled to a second voltage having a first level by using the timing controller; in the skip frame, the pixel driving voltage is controlled to a first voltage having a second level lower than the first level by using the timing controller.

[0030] In one or more embodiments, when the frequency change command signal is received from the processor in the last skip frame, the pixel driving voltage is shifted from the second level to the first level by using the timing controller for refresh driving of the next refresh frame.

[0031] In one or more embodiments, controlling the refresh rate change time differently includes: using the timing controller to identify interrupt information contained in the frequency change command signal, and in response to the interrupt information to perform the refresh rate change operation in a skip frame arranged at the reception time of the frequency change command signal, so as to irregularly change the refresh rate before completing the first refresh rate operation. Attached Figure Description

[0032] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0033] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention;

[0034] Figure 2 It is a diagram illustrating an example of the arrangement of pixels included in a display panel;

[0035] Figure 3 This is a diagram illustrating another example of the arrangement of pixels included in a display panel;

[0036] Figure 4 It is a diagram Figure 1 The diagram shows the structure of a driver integrated circuit (IC).

[0037] Figure 5 It is a schematic diagram illustrating the pixel circuitry of each sub-pixel;

[0038] Figure 6 This is a diagram showing the driving timing of the refresh frame;

[0039] Figure 7 This is a diagram showing the driving timing of skip frames;

[0040] Figure 8 This is a diagram showing the timing of driving pixels at a low speed;

[0041] Figure 9 This is a diagram illustrating the timing of the refresh rate changing regularly based on a normal frequency variation command signal in an embodiment of the present invention;

[0042] Figure 10 This is a diagram showing the timing of the irregular changes in refresh rate based on an interrupt-type frequency change command signal in a comparative example of the present invention;

[0043] Figure 11 and 12 It is used to describe in Figure 10 The diagram illustrates the problems that may occur when the refresh rate is changed based on the reception time of an interrupt-type frequency change command signal.

[0044] Figure 13 and 14 This is a diagram illustrating the timing of irregular changes in refresh rate based on an interrupt-type frequency change command signal in an embodiment of the present invention;

[0045] Figure 15 and 16 This is a diagram illustrating another timing sequence in an embodiment of the invention where the refresh rate varies irregularly based on an interrupt-type frequency change command signal;

[0046] Figure 17 This is a diagram illustrating a driving method for a display device according to an embodiment of the present invention. Detailed Implementation

[0047] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the specification, when adding reference numerals for elements in each figure, care should be taken to use similar reference numerals that are already used to refer to similar elements in other figures whenever possible. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the present invention.

[0048] Reference Figures 1 to 4 The display device 1000 according to the present invention can be an electroluminescent display device, but is not limited thereto, and can be applied to various types of display devices. For example, the display device can be implemented as various types such as liquid crystal display (LCD) devices, electrophoretic display devices, electrowetting display devices, and quantum dot display devices. In embodiments of the present invention, for convenience, an electroluminescent display device will be described.

[0049] The display device 1000 according to the present invention may include a display panel 100, a plurality of display panel drivers 120 and 300, and a processor 200.

[0050] Display panel drivers 120 and 300 can apply input image data to pixels P of screen AR to display an image on screen AR. Display panel drivers 120 and 300 may include: a gate driver 120 that provides gate signals to gate lines GL1 and GL2 of display panel 100; a data driver 306 that converts image data into a voltage signal (hereinafter referred to as data voltage) and provides the data voltage to data lines DL1 to DL6 via a data output channel; and a timing controller 303 that controls the operating timing of each of the data driver 306 and the gate driver 120. The data driver 306 and the timing controller 303 may be integrated into a driver integrated circuit (IC) 300.

[0051] The screen AR of the display panel 100 may include: data lines DL1 to DL6; gate lines GL1 and GL2 intersecting the data lines DL1 to DL6; and a pixel array in which pixels P are arranged in a matrix. Pixels P may be arranged in the pixel array in a matrix form defined by the data lines DL1 to DL6 and the gate lines GL1 and GL2. Pixels P may display an image using an applied data voltage.

[0052] Each pixel P may include multiple sub-pixels for implementing color. The sub-pixels may include red sub-pixels (hereinafter referred to as R sub-pixels), green sub-pixels (hereinafter referred to as G sub-pixels), and blue sub-pixels (hereinafter referred to as B sub-pixels). Although not shown, each pixel P may further include white sub-pixels.

[0053] Each sub-pixel may include internal compensation circuitry that senses the electrical characteristics (e.g., threshold voltage) of the driving element to compensate for the gate voltage of the driving element.

[0054] Subpixels can form either an actual color pixel P or a pentile pixel P. In a pentile pixel P, such as... Figure 2 As shown, by using a pixel rendering algorithm, two sub-pixels of different colors can be driven into a single pixel P, thereby achieving a resolution higher than that of pixels with actual colors. The pixel rendering algorithm compensates for insufficient color representation in each sub-pixel by using the colors of light emitted from adjacent sub-pixels.

[0055] In the actual color pixel P, such as Figure 3 As shown, a pixel P can be configured with R, G, and B sub-pixels.

[0056] When the resolution of the pixel array is n*m, the pixel array can include n pixel columns and m pixel rows intersecting the pixel columns. Figure 2 and 3In this context, #1 can represent the pixel row number, and #2 can represent the pixel row number. A pixel column can include pixels P arranged in the Y-axis direction. A pixel row can include pixels P arranged in the X-axis direction. A horizontal period 1H can refer to the time obtained by dividing one frame period by the number of m pixel rows. The gate driver 120 can output gate signals sequentially from the first pixel row to the m-th pixel row, thereby performing a progressive scan of the pixels P row by row. Each sub-pixel of a pixel row can be operated in the order of initialization operation, sensing operation, and data application operation within one horizontal period.

[0057] The pixel array of the display panel 100 can be disposed on a glass substrate, a metal substrate, or a plastic substrate. In a plastic panel, the pixel array can be disposed on a plastic substrate, thereby enabling the display panel 100 to be a flexible panel. The plastic panel may include a pixel array located on an organic film attached to a backplane. A touch sensor array may be disposed on the pixel array.

[0058] The backsheet can be a polyethylene terephthalate (PET) substrate. An organic thin film can be formed on the backsheet. The pixel array and touch sensor array can be disposed on the organic thin film. The backsheet prevents moisture from penetrating into the organic thin film, thus preventing the pixel array from being exposed to moisture. The organic thin film can be a thin polyimide (PI) film substrate. A multilayer buffer layer (not shown) containing insulating material can be formed on the organic thin film. Lines for providing power or signals to the pixel array and touch sensor array can be formed on the organic thin film.

[0059] The gate driver 120 can be mounted on the substrate of the display panel 100 together with the pixel array. The gate driver 120 directly disposed on the substrate of the display panel 100 is known as a gate in panel (GIP) circuit.

[0060] The gate driver 120 can be positioned at one of the left and right bezels of the display panel 100 based on a single feeding scheme, and can provide gate signals to gate lines GL1 and GL2. In the single feeding scheme, Figure 1 One of the two gate drivers 120 in the configuration may not be required.

[0061] The gate driver 120 can be positioned at each of the left and right bezels of the display panel 100 based on a dual-feed mechanism, and can provide gate signals to gate lines GL1 and GL2. In the dual-feed mechanism, the gate signal can be applied simultaneously at both ends of a gate line.

[0062] The gate driver 120 can be driven using a shift register according to the gate timing signal provided from the driver IC 300, and can provide gate signals GATE1 and GATE2 to gate lines GL1 and GL2. The shift register can shift the gate signals GATE1 and GATE2, thereby providing gate signals GATE1 and GATE2 to gate lines GL1 and GL2 sequentially. Gate signals GATE1 and GATE2 may include scan signals and light emission control signals.

[0063] The driver IC 300 can output gate timing signals for controlling the gate driver 120. The driver IC 300 can be connected to data lines DL1 to DL6 via a data output channel and can provide data signals DATA1 to DATA6 to data lines DL1 to DL6.

[0064] like Figure 4 As shown, the driver IC 300 can be connected to the processor 200, the first memory 301, and the display panel 100. The driver IC 300 may include a data calculator 308, a timing controller 303, and a data driver 306. The driver IC 300 may further include a second memory 302, a gamma-compensated voltage generator 305, a power supply 304, and a level shifter 307.

[0065] The data calculator 308 can receive image data DATA from the processor 200 and can improve the image quality by modulating the received image data DATA using a predetermined image quality algorithm. The data calculator 308 may include a data recovery unit that decodes the compressed image data DATA to recover the image data DATA.

[0066] The timing controller 303 provides image data DATA received from the data calculator 308 to the data driver 306. The timing controller 303 generates gate timing signals for controlling the gate driver 120 and source timing signals for controlling the data driver 306, thereby controlling the operating timing of each of the gate driver 120 and the data driver 306. The timing controller 303 also controls the operation of the power supply 304.

[0067] Power supply 304 can generate the power required to drive the pixel array, gate driver 120, and driver IC 300 of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, rectifier, buck converter, and boost converter. Power supply 304 can regulate the input voltage to generate direct current (DC) power such as gamma reference voltage, gate on-state voltage VGL, gate off-state voltage VGH, pixel drive voltage ELVDD, low-level source voltage ELVSS, and initialization voltage Vini.

[0068] A gamma reference voltage can be provided to the gamma compensation voltage generator 305. The gate on-state voltage VGL and gate off-state voltage VGH can be provided to the level shifter 307 and the gate driver 120. Pixel power, such as the pixel drive voltage ELVDD, the low-level source voltage ELVSS, and the initialization voltage Vini, can be collectively provided to the sub-pixel. Each sub-pixel may include pixel circuitry, which includes a light-emitting device EL and a driving element DT.

[0069] The initialization voltage Vini can be the voltage used to initialize the main nodes of the pixel circuit. The gate voltage can be set to "VGH = 8V" and "VGL = -7V", and the pixel power can be set to "ELVDD = 4.6V", "ELVSS = -2V to -3V", and "Vini (or Vref) = -3V to -4V", but the invention is not limited thereto. The data voltage Vdata can be set to "Vdata = 2V to 6V", but is not limited thereto.

[0070] The initialization voltage Vini can be set to a DC voltage that is lower than the data voltage Vdata and higher than the threshold voltage of the light-emitting device EL, thereby controlling the emission of light from the light-emitting device EL and initializing the main nodes of the pixel circuit.

[0071] The power supply 304 can change the low-level source voltage ELVSS according to the brightness value DBV based on the control of the timing controller 303, thereby limiting the maximum brightness of the screen AR implemented via the pixel P.

[0072] Level shifter 307 can receive gate timing signals from timing controller 303 and can shift the voltage level of the gate timing signals. The gate timing signals may include gate timing signals such as a start pulse VST and a shift clock GCLK, and gate voltages such as gate on-voltage VGL and gate off-voltage VGH. The start pulse VST and shift clock GCLK can oscillate between the gate on-voltage VGL and the gate off-voltage VGH.

[0073] Level shifter 307 can shift the low-level voltage of the gate timing signal received from timing controller 303 to the gate on-voltage VGL, and can shift the high-level voltage of the gate timing signal to the gate off-voltage VGH. Level shifter 307 can output and provide the gate timing signal and gate voltages VGH and VGL to gate driver 120 via an output channel.

[0074] The data driver 306 can convert the image data (digital signal) received from the timing controller 303 into a gamma-compensated voltage using a digital-to-analog converter (DAC) to output a data voltage. The data voltage output from the data driver 306 can be provided to the data lines DL1 to DL6 of the pixel array via an output buffer connected to the data channel of the driver IC 300.

[0075] The gamma compensation voltage generator 305 can divide the gamma reference voltage from the power supply 304 using a voltage divider circuit to generate a gray-level-based gamma compensation voltage. The gamma compensation voltage can be an analog voltage set for each gray level of the image data. The gamma compensation voltage output from the gamma compensation voltage generator 305 can be provided to the data driver 306.

[0076] When power is input to the driver IC 300, the second memory 302 can store register settings received from the first memory 301. These register settings can define the waveforms and operating timing of the data driver 306, timing controller 303, gamma-compensated voltage generator 305, and power supply 304, as well as the output voltage level of the power supply 304. The first memory 301 may include flash memory. The second memory 302 may include static random access memory (SRAM).

[0077] The processor 200 can be one of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile system, and wearable system.

[0078] In a mobile system, processor 200 can be implemented as an application processor (AP). In a mobile system, processor 200 can transmit input image data to driver IC 300 via a Mobile Industry Processor Interface (MIPI). Processor 200 can be connected to driver IC 300 via flexible printed circuit (FPC) 310.

[0079] The display device 1000 according to the present invention can use variable refresh rate (VRR) technology. The display device 1000 according to the present invention can drive pixel P at a certain refresh rate, and then increase the refresh rate when high-speed driving is needed, or decrease the refresh rate when low-speed driving or power consumption reduction is needed, thereby operating pixel P in high-speed or low-speed driving mode. Pixel P can be driven such that it can switch between a first refresh rate and a second refresh rate higher than the first refresh rate (e.g., a second refresh rate faster than the first refresh rate). Pixel P can be driven at a low speed at the first refresh rate, or at a high speed at the second refresh rate.

[0080] The processor 200 can output a frequency change command signal to the driver IC 300, indicating a switching request between a first refresh rate and a second refresh rate, under a predetermined specific condition. In one embodiment, the frequency change command signal can be divided into a normal type without interrupt information and an interrupt type including interrupt information. The processor 200 can output a normal type frequency change command signal at the low-speed drive completion time or the high-speed drive completion time, but is not limited thereto. In one embodiment, the predetermined specific condition includes the end of the low-speed drive and the end of the high-speed drive. Thus, the processor 200 outputs a normal type frequency change command signal under the predetermined specific condition of the end of the low-speed drive or the end of the high-speed drive. It is not necessary to predefine the timing of the processor 200 outputting the normal type frequency change command signal.

[0081] The processor 200 can suddenly output an interrupt-type frequency change command signal when high-speed driving is needed, during the middle of low-speed driving. Therefore, the processor 200 can output the interrupt-type frequency change command signal while executing low-speed driving and before it ends, instead of waiting for the low-speed driving to complete. While pixel P is being driven, the processor 200 can irregularly output the interrupt-type frequency change command signal.

[0082] The timing controller 303 of the driver IC 300 can determine whether the frequency change command signal is normal or interrupt-type based on the presence or absence of interrupt information included in the frequency change command signal received from the processor 200. When the frequency change command signal is normal, the timing controller 303 can change the refresh rate used to drive the pixel P from the first refresh rate to the second refresh rate at a predetermined time, regardless of the reception timing of the frequency change command signal, or it can change the refresh rate from the second refresh rate to the first refresh rate.

[0083] When changing the refresh rate according to an interrupt-type frequency change command signal, the timing controller 303 can control the refresh rate change time differently based on the temporal position of the frequency change command signal received from the processor 200, thereby reducing image distortion that may occur when changing the refresh rate. In particular, the timing controller 303 can dualize the standard synchronization signal when changing the refresh rate, and can apply different synchronization signals for normal and interrupt types, thereby preventing or at least reducing interface timing delays associated with image signal transmission or time delays in the change of pixel drive voltage to be supplied to the pixels. (See reference...) Figures 6 to 17 This will be described in detail.

[0084] Figure 5 It is a schematic diagram illustrating the pixel circuit of each sub-pixel.

[0085] Reference Figure 5 The pixel circuit may include first to third circuit units 10, 20, and 30, and first to third connecting portions 12, 23, and 13. One or more components may be omitted or added to the pixel circuit.

[0086] The first circuit unit 10 provides a pixel drive voltage ELVDD to the driving element DT via line 61. The driving element DT can be implemented as a transistor including a gate DRG, a source DRS, and a drain DRD. The second circuit unit 20 can charge a capacitor connected to the gate DRG of the driving element DT and can allow the voltage of the capacitor to be maintained for one frame period. The third circuit unit 30 can provide the current supplied from the pixel drive voltage ELVDD to the anode of the light-emitting device EL via the driving element DT, whereby the current can be converted into light. The cathode of the light-emitting device EL is connected to a low-level source voltage ELVSS via line 62. Each of the first to third circuit units 10, 20, and 30 may include internal compensation circuitry for compensating for the threshold voltage of the driving element DT. The third circuit unit 30 may be connected to a sensing unit for real-time sensing of changes in the threshold voltage or electrical characteristics of the driving element DT.

[0087] The first connection portion 12 can connect to the first circuit unit 10 and the second circuit unit 20. The second connection portion 23 can connect the second circuit unit 20 and the third circuit unit 30. The third connection portion 13 can connect the third circuit unit 30 and the first circuit unit 10. Each of the first connection portion 12, the second connection portion 23 and the third connection portion 13 may include one or more transistors and lines.

[0088] Figure 6 This is a diagram showing the driving timing of the refresh frame. Figure 7 This is a diagram showing the driving timing of frame skipping. Figure 8 This is a diagram showing the timing of driving pixels at a low speed. Figure 6 and 7 The reference mark "DE" in the text indicates the data enable signal.

[0089] Reference Figures 6 to 8Low-speed driving can be a technique that skips pixel application operation and image data transmission in some frames to reduce the refresh rate of image data down to 1Hz. Two or more skip frames S (e.g., S1 to S3) can be arranged between adjacent refresh frames N for low-speed driving. The low-speed driving refresh rate (hereinafter referred to as the first refresh rate) can be implemented by one refresh frame N (e.g., the first refresh frame) and multiple skip frames S, which are distinguished from each other relative to the vertical synchronization signal VSYNC. The high-speed driving refresh rate (hereinafter referred to as the second refresh rate) can be implemented by each refresh frame N (e.g., multiple second refresh frames) that are distinguished from each other relative to the vertical synchronization signal VSYNC. When the second refresh rate is 60Hz, the first refresh rate can be 15Hz or lower, but this is only an implementation method, and the inventive concept is not limited to specific numbers of refresh rates.

[0090] In refresh frame N, new image data can be provided to the pixels of the display panel. The timing controller can transmit a transfer request signal (TE) to the processor at a specific time in each refresh frame N, and can receive new image data from the processor via MIPI for refresh driving in the next refresh frame N. The timing controller can store the received image data in the frame memory, perform image quality compensation operations, and then control the operation of each of the gate driver GDRV and data driver SDRV to apply the image data to the pixels. Figure 7 In this context, HI-Z represents an output state of the circuit. The transmission request signal TE can be a signal used to prevent the tearing effect and can be generated in a predetermined specific timing relative to the vertical synchronization signal VSYNC. The processor can transmit the image data required for the next refresh frame N to the timing controller in response to the transmission request signal TE. In refresh frame N, the timing controller can control the pixel drive voltage VOP to have a first level VL1 (at this time, the pixel drive voltage can be referred to as the first or second voltage). The pixel drive voltage VOP can be a voltage used to initialize the anode of the light-emitting device constituting each pixel.

[0091] In skip frame S, new image data may not be provided to the pixels of the display panel, and the pixels may retain the display state of the previous refresh frame N. That is, previous image data can be retained in multiple pixels during at least one skip frame S. Furthermore, the frame memory can perfectly retain the image data of the previous refresh frame N. In skip frame S, since the pixels are skip-driven and do not update the image, the timing controller can stop (e.g., Hi-Z) the operation of each of the gate driver GDRV and data driver SDRV. In skip frames S1 and S2, except for the last skip frame S3, the timing controller may not transmit the transfer request signal TE to the processor. In the last skip frame S3, the timing controller can transmit the transfer request signal TE to the processor for refresh driving of the next refresh frame N. Unlike refresh frame N, the timing controller can control the pixel drive voltage VOP of skip frame S to have a second level VL2 (in this case, the pixel drive voltage may be referred to as the second or first voltage). The second level VL2 may be lower than the first level VL1.

[0092] In the final skip frame S3, before the timing controller transmits (e.g., outputs) the transmission request signal TE to the processor, the processor may transmit a normal frequency change command signal to the timing controller. In the final skip frame S3, transmission and reception operations between the processor and the timing controller can be performed according to predetermined timing rules.

[0093] In the final frame skipping S3, the timing controller can shift the pixel drive voltage VOP from the second level VL2 to the first level VL1 for the refresh drive of the next refresh frame N, thereby ensuring sufficient voltage settling time.

[0094] Figure 9 This is a diagram illustrating the timing of a refresh rate that varies regularly based on a normal frequency change command signal according to an embodiment of the present invention.

[0095] Reference Figure 9The first refresh rate can be set to 1Hz, and the second refresh rate can be set to 60Hz. The normal-type frequency change command signal CMD can be transmitted to the timing controller via the processor at a predetermined timing (e.g., in frame skipping S58). In this case, the timing controller can perform the frequency change (frame switching) operation after the time allocated to the first refresh frame has elapsed (i.e., after the 1Hz operation is completed). In other words, the timing controller can perform the frequency change operation in frame skipping S59 instead of frame skipping S58. In frame skipping S59, based on the vertical synchronization signal VSYNC, the timing controller can transmit a transmission request signal TE for new image data for the next refresh drive to the processor, can change the pixel drive voltage VOP (VL2 to VL1) to be provided to the pixels based on the refresh drive, and can switch the refresh rate from the first refresh rate to the second refresh rate based on the pixel.

[0096] Since the first refresh rate and the second refresh rate alternate in a predetermined order, the timing controller can stably perform the frequency change operation in S59, which is the last frame skip.

[0097] Figure 10 This is a diagram illustrating the timing of irregular changes in refresh rate based on an interrupt-type frequency change command signal in a comparative example of the present invention. Figure 11 and 12 It is used to describe in Figure 10 The diagram illustrates the problems that may occur when the refresh rate is changed based on the reception time of an interrupt-type frequency change command signal.

[0098] Reference Figure 10 In the middle of performing a low-speed drive based on a first refresh rate, when it is necessary to change to a second refresh rate for a sudden high-speed drive, an interrupt-type frequency change command signal (CMD) can be output. That is, an interrupt-type frequency change command signal (CMD) is output to change the refresh rate before the low-speed drive is complete. For example, in the middle of performing a 1Hz operation, when the processor should suddenly update image data (e.g., by user screen changes or changes via communication), an interrupt-type frequency change command signal (CMD) can be output.

[0099] When the timing controller changes the refresh rate after completing a 1Hz operation based on the interrupt-type frequency change command signal CMD, a time difference of "several frames" or "tens of frames" may occur between the reception time of the command signal CMD and the refresh rate change time. In one embodiment, the refresh rate change time is the time it takes for the refresh rate to change between a first refresh rate and a second refresh rate. To address this issue, the timing controller can identify interrupt information contained in the frequency change command signal CMD and, in response to the interrupt information, perform a refresh rate change operation in the skip frame S7 after receiving the frequency change command signal CMD. This allows the timing controller to irregularly change the refresh rate before completing the 1Hz operation. In this case, the skip frame S7, where the refresh rate change operation is performed, may be the last skip frame, and the first refresh rate may be at 7.5Hz instead of 1Hz. In the figure, "S7→S59" can refer to the fact that even though skip frame S59 is the scheduled last skip frame, skip frame S7 is still the last skip frame based on the interrupt-type frequency change command signal CMD.

[0100] In order to change the frequency of the interrupt, the transmission request signal TE should be transmitted to the processor during the reception time of the frequency change command signal CMD in the frame skipping S7, and the time for shifting the pixel drive voltage VOP should be sufficient.

[0101] Unlike the normal type, the interrupt type frequency change command signal CMD can be received from the processor at random times within a frame. On the other hand, the generation-enabled time of the transmission request signal TE and the change-enabled time of the pixel drive voltage VOP can be predefined at specific times for each frame relative to the vertical synchronization signal VSYNC.

[0102] like Figure 11 As shown, in frame skipping S7, when the reception time tt1 of the interrupt-type frequency change command signal CMD is earlier than the predetermined specific time Ftm, the interrupt-type frequency change can be stably executed.

[0103] On the other hand, such as Figure 12 As shown, in frame skipping S7, when the reception time tt2 of the interrupt-type frequency change command signal CMD is later than the predetermined specific time Ftm, the interrupt-type frequency change will not be executed stably.

[0104] A detailed description is provided here: Since no transmission request signal TE is generated in frame skipping S7 after the reception time tt2 of the frequency change command signal CMD, the next refresh frame can be executed without updating the image data via MIPI. Furthermore, since the time after the reception time tt2 of the frequency change command signal CMD is insufficient, the change of the pixel drive voltage VOP is not performed in frame skipping S7, and the change time of the pixel drive voltage VOP (e.g., the time when the pixel drive voltage VOP changes) can be delayed until the next refresh frame.

[0105] When interrupt-type frequency changes are executed unstably, the interface timing associated with the transmission of image signals can be delayed, and the change time of the pixel drive voltage VOP can be delayed, resulting in image distortion.

[0106] Figure 13 and 14 This is a diagram illustrating the timing of irregular changes in refresh rate based on an interrupt-type frequency change command signal in an embodiment of the present invention. Figure 15 and 16 This is a diagram illustrating another timing sequence in an embodiment of the invention where the refresh rate varies irregularly based on an interrupt-type frequency change command signal.

[0107] Reference Figures 13 to 16 According to an embodiment of the present invention, the timing controller can control the refresh rate change time of the pixel (e.g., the refresh rate change time) differently based on the time position of the frequency change command signal CMD received from the processor, so that even if the frequency change command signal CMD is received irregularly, the frequency can be changed stably, thereby preventing image distortion.

[0108] When the frequency change command signal CMD is received from the processor in the last jump frame S59 among multiple jump frames S1 to S59, the timing controller can control the refresh rate change time based on the vertical synchronization signal VSYNC. Furthermore, when the frequency change command signal CMD is received from the processor in a jump frame preceding the last jump frame S59 (e.g., S7) among multiple jump frames S1 to S59, the timing controller can control the refresh rate change time based on the interrupt synchronization signal ISYNC.

[0109] Therefore, in addition to the vertical synchronization signal VSYNC, the timing controller can further generate an interrupt synchronization signal ISYNC. The vertical synchronization signal VSYNC can define skip frames S1 to S59 and refresh frame N. The vertical synchronization signal VSYNC can define the generation enable time of the transmission request signal TE and the change enable time of the pixel drive voltage VOP in each frame. Based on the reception time of the frequency change command signal CMD in the specific skip frame S7 located before the last skip frame S59, the interrupt synchronization signal ISYNC can provide a standard such that the refresh rate change time is controlled in one of the specific skip frame S7 and the subsequent skip frame S8. For this purpose, the period of the interrupt synchronization signal ISYNC can be the same as the period of the vertical synchronization signal VSYNC, but the phase of the interrupt synchronization signal ISYNC can be different from the phase of the vertical synchronization signal VSYNC. To provide a precise standard, in each frame, the interrupt synchronization signal ISYNC can be synchronized with the generation enable time of the transmission request signal TE.

[0110] When the timing controller receives a normal or interrupt-type frequency change command signal CMD from the processor in the last skip frame S59, it can operate as follows: In the last skip frame S59, based on the vertical synchronization signal VSYNC, the timing controller can transmit a transmission request signal TE for new image data for refresh drive to the processor, can change the pixel drive voltage VOP (VL2 to VL1) to be provided to the pixel based on the refresh drive, and can switch the refresh rate based on the pixel from a first refresh rate (1Hz) to a second refresh rate (60Hz).

[0111] When an interrupt-type frequency change command signal CMD is received from the processor in a specific jump frame S7 (excluding the final jump frame S59), the timing controller can operate as follows: In specific jump frame S7, based on the reception time of the interrupt synchronization signal ISYNC and the frequency change command signal CMD (… Figure 13 and 15 tt3; Figure 14 and 16 The timing controller can control the refresh rate change time differently based on the time sequence relationship between the frequency change command signal CMD and the frame skipping period before or after the interrupt synchronization signal ISYNC. This allows the frequency to be changed stably even if the frequency change command signal CMD is received irregularly, thereby preventing image distortion.

[0112] In a specific frame skipping S7, if the reception time tt3 of the frequency change command signal CMD is earlier than the interrupt synchronization signal ISYNC (e.g., Figure 13 and 15When (as shown), the timing controller can operate as follows. In a specific skip frame S7, based on the interrupt synchronization signal ISYNC, the timing controller can transmit a transmission request signal TE for new image data for refresh driving to the processor, can change the pixel driving voltage VOP (VL2 to VL1) to be provided to the pixel based on the refresh driving, and can switch the refresh rate based on the pixel from a first refresh rate (1Hz) to a second refresh rate (60Hz). Thus, the pixel is driven at the second refresh rate during the second refresh frame (during which new image data or second image data is applied to the pixel after the specific skip frame S7), and the pixel is not driven at the first refresh rate during the remaining skip frames (S8 to S59) scheduled to occur after the specific skip frame S7.

[0113] In a specific frame skipping S7, if the reception time tt4 of the frequency change command signal CMD is later than the interrupt synchronization signal ISYNC (e.g.) Figure 14 and 16 When (as shown), the timing controller can operate as follows. In the next frame S8 (e.g., a subsequent frame) that follows (i.e., adjacent to) a specific frame S7, based on the interrupt synchronization signal ISYNC, the timing controller can transmit a transmission request signal TE for new image data for refresh driving to the processor, can change the pixel drive voltage VOP (VL2 to VL1) to be provided to the pixel based on the refresh drive, and can switch the refresh rate based on the pixel from a first refresh rate (1Hz) to a second refresh rate (60Hz).

[0114] Figure 17 This is a diagram illustrating a driving method for a display device according to an embodiment of the present invention.

[0115] Reference Figure 17 The timing controller can determine whether the frequency change command signal CMD received from the processor contains interrupt information, thereby determining whether the frequency change command signal CMD is normal or interrupt type (steps S171 and S172). The normal type frequency change command signal CMD can be received regularly with a predetermined timing in low-speed drive, but the interrupt type frequency change command signal CMD can be received irregularly with sudden timing in low-speed drive.

[0116] The timing controller can determine whether the reception timing of the interrupt-type frequency change command signal CMD is arranged in the last hop frame contained in a low-speed drive cycle, or in a specific hop frame located before the last hop frame (step S173).

[0117] When a normal frequency change command signal CMD is received during low-speed drive, or when an interrupt-type frequency change command signal CMD is received in the last skip frame during low-speed drive, the timing controller can perform a refresh rate change operation based on the vertical synchronization signal VSYNC. That is, in the last skip frame, based on the vertical synchronization signal VSYNC, the timing controller can transmit a new image data transmission request signal TE for refresh drive to the processor, can change the pixel drive voltage VOP to be provided to the pixel based on refresh drive, and can switch the refresh rate corresponding to the pixel changing from a first refresh rate to a second refresh rate higher than the first refresh rate (steps S174 and S175).

[0118] When an interrupt-type frequency change command signal CMD is received in a specific hop frame preceding the last hop frame, the timing controller can perform a refresh rate change operation based on the interrupt synchronization signal ISYNC. Within that specific hop frame, based on the temporal relationship or sequence between the reception times of the interrupt synchronization signal ISYNC and the frequency change command signal CMD, the timing controller can control the refresh rate change time differently. Therefore, even if the frequency change command signal CMD is received irregularly, the timing controller can still perform the overall operation associated with the transmission request signal TE and the change in the pixel drive voltage VOP to achieve a stable frequency change (steps S176 and S177). (The above has already referred to...) Figures 13 to 16 This was described.

[0119] The embodiments of the present invention can achieve the following effects.

[0120] In embodiments of the present invention, compared to the vertical synchronization signal, interrupt synchronization signals with the same period and different phases can be generated separately, and the refresh rate change time of the pixel can be controlled differently according to the interrupt synchronization signal based on the time position of the frequency change command signal received from the processor. Thus, even if the frequency change command signal is received irregularly, the frequency can be changed stably, thereby preventing image distortion.

[0121] The effects of the present invention are not limited to the examples described above; various other effects may be included in the specification.

[0122] Although the invention has been specifically shown and described with reference to exemplary embodiments, it will be understood that various changes in form and detail may be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels configured to be driven alternately between a first refresh rate and a second refresh rate different from the first refresh rate; A processor configured to output a frequency change command signal, the frequency change command signal representing a switching request between a first refresh rate and a second refresh rate; as well as A timing controller, which controls the timing of refresh rate changes between a first refresh rate and a second refresh rate for the plurality of pixels based on the timing of a frequency change command signal received from the processor. Specifically, in response to the timing controller receiving the frequency change command signal during the last skip frame of a plurality of skip frames, the timing controller is configured to control the time during which the refresh rates of the plurality of pixels change between a first refresh rate and a second refresh rate according to a first synchronization signal. Specifically, in response to the timing controller receiving the frequency change command signal during a hop frame preceding the last hop frame among the plurality of hop frames, the timing controller is configured to control the timing of the refresh rate of the plurality of pixels changing between the first refresh rate and the second refresh rate according to a second synchronization signal. The first synchronization signal and the second synchronization signal have the same period and different phases.

2. The display device of claim 1, wherein the plurality of pixels are driven at the first refresh rate during the plurality of skip frames and the first refresh frame, which are distinct from each other relative to the first synchronization signal, and the plurality of pixels are driven at the second refresh rate during the plurality of second refresh frames, which are distinct from each other relative to the first synchronization signal. The first image data is applied to the plurality of pixels during the first refresh frame, and the first image data is maintained in the plurality of pixels during at least one of the plurality of skip frames.

3. The display device of claim 2, wherein in response to the timing controller receiving the frequency change command signal during the last frame skip, the timing controller is configured to: During the last frame skip, based on the first synchronization signal, a transmission request signal for the second image data for refresh driving is output to the processor, the pixel driving voltage applied to the plurality of pixels is changed from a first voltage to a second voltage greater than the first voltage, and the refresh rate is changed from the first refresh rate to a second refresh rate greater than the first refresh rate.

4. The display device according to claim 2, wherein, In response to the timing controller receiving the frequency change command signal during a hop frame preceding the last hop frame, the timing controller differently controls the timing of the refresh rate change between the first refresh rate and the second refresh rate based on whether the frequency change command signal is received during a hop frame preceding the second synchronization signal or during a hop frame following the second synchronization signal.

5. The display device of claim 4, wherein in response to receiving the frequency change command signal during a frame skip period earlier than the second synchronization signal, the timing controller is configured to: During the frame skipping period, based on the second synchronization signal, a transmission request signal for the second image data for refresh driving is output to the processor, the pixel driving voltage applied to the plurality of pixels is changed from a first voltage to a second voltage greater than the first voltage, and the refresh rate is changed from the first refresh rate to a second refresh rate greater than the first refresh rate.

6. The display device of claim 4, wherein in response to receiving the frequency change command signal during a frame skipping period following the second synchronization signal, the timing controller is configured to: During one of the plurality of skip frames, located after the first skip frame, a transmission request signal for second image data for refresh driving is output to the processor based on the second synchronization signal, the pixel driving voltage applied to the plurality of pixels is changed from a first voltage to a second voltage greater than the first voltage, and the refresh rate is changed from the first refresh rate to a second refresh rate greater than the first refresh rate.

7. The display device according to any one of claims 3, 5 and 6, wherein the pixel driving voltage is a voltage used to initialize the anode of the light-emitting device constituting each pixel.

8. The display device according to claim 7, wherein in the refresh frame, the timing controller controls the pixel driving voltage to a second voltage having a first level; and in the skip frame, the timing controller controls the pixel driving voltage to a first voltage having a second level lower than the first level.

9. The display device of claim 8, wherein when the frequency change command signal is received from the processor in the last skip frame, the timing controller shifts the pixel driving voltage from the second level to the first level for refresh driving of the next refresh frame.

10. The display device of claim 1, wherein the timing controller is configured to recognize interrupt information contained in the frequency change command signal, and in response to the interrupt information, perform the refresh rate change operation in a skip frame arranged at the reception time of the frequency change command signal to irregularly change the refresh rate before completing the first refresh rate operation.

11. A driving method for a display device, the display device comprising a plurality of pixels configured to be driven varying between a first refresh rate and a second refresh rate different from the first refresh rate, the driving method comprising: The processor of the display device outputs a frequency change command signal to the timing controller of the display device, the frequency change command signal representing a switching request between the first refresh rate and the second refresh rate; as well as The timing controller controls the timing of refresh rate changes between the first refresh rate and the second refresh rate for the plurality of pixels based on the timing of the frequency change command signal received from the processor. The different times for controlling the refresh rate change include: In response to the timing controller receiving the frequency change command signal during the last skip frame of a plurality of skip frames, the timing controller controls the time by which the refresh rate of the plurality of pixels changes between the first refresh rate and the second refresh rate according to the first synchronization signal. Specifically, in response to the timing controller receiving the frequency change command signal during a hop frame preceding the last hop frame among the plurality of hop frames, the timing controller controls the time by which the refresh rate of the plurality of pixels changes between the first refresh rate and the second refresh rate according to the second synchronization signal. The first synchronization signal and the second synchronization signal have the same period and different phases.

12. The driving method of claim 11, wherein the plurality of pixels are driven at the first refresh rate during the plurality of skip frames and the first refresh frame, which are distinct from each other relative to the first synchronization signal, and the plurality of pixels are driven at the second refresh rate during the plurality of second refresh frames, which are distinct from each other relative to the first synchronization signal. The first image data is applied to the plurality of pixels during the first refresh frame, and the first image data is maintained in the plurality of pixels during at least one of the plurality of skip frames.

13. The driving method according to claim 12, wherein the time for controlling the refresh rate change according to the first synchronization signal includes: The timing controller determines whether the frequency change command signal is received from the processor during the last frame skip. as well as During the last frame skip, based on the first synchronization signal, a transmission request signal for the second image data for refresh driving is output to the processor, the pixel driving voltage applied to the plurality of pixels is changed from a first voltage to a second voltage greater than the first voltage, and the refresh rate is changed from the first refresh rate to a second refresh rate greater than the first refresh rate.

14. The driving method according to claim 12, wherein, The time for controlling the refresh rate change according to the second synchronization signal includes: The timing controller determines whether the frequency change command signal is received during a hop frame earlier than the last hop frame; and During a frame skipping period following the second synchronization signal, the timing controller controls the time during which the refresh rate changes between the first refresh rate and the second refresh rate, depending on whether the frequency change command signal is received during a frame skipping period before or after the second synchronization signal.

15. The driving method of claim 14, wherein controlling the refresh rate change at different times includes: In response to receiving the frequency change command signal during a frame skipping period earlier than the second synchronization signal, the timing controller outputs a transmission request signal for second image data for refresh driving to the processor during the frame skipping period based on the second synchronization signal, changes the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage, and changes the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

16. The driving method of claim 14, wherein controlling the refresh rate change at different times comprises: In response to receiving the frequency change command signal during a frame skipping period following the second synchronization signal, the timing controller outputs a transmission request signal for second image data for refresh driving to the processor during another frame skipping period following the first frame skipping period in the plurality of frames, based on the second synchronization signal; changes the pixel driving voltage applied to the plurality of pixels from a first voltage to a second voltage greater than the first voltage; and changes the refresh rate from the first refresh rate to a second refresh rate greater than the first refresh rate.

17. The driving method according to any one of claims 13, 15 and 16, wherein the pixel driving voltage is a voltage used to initialize the anode of the light-emitting device constituting each pixel.

18. The driving method of claim 17, wherein in the refresh frame, the pixel driving voltage is controlled to a second voltage having a first level by using the timing controller; and in the skip frame, the pixel driving voltage is controlled to a first voltage having a second level lower than the first level by using the timing controller.

19. The driving method of claim 18, wherein when the frequency change command signal is received from the processor in the last skip frame, the pixel driving voltage is shifted from the second level to the first level by using the timing controller for refresh driving of the next refresh frame.

20. The driving method of claim 11, wherein controlling the refresh rate change at different times includes: By using the timing controller to identify interrupt information contained in the frequency change command signal, and in response to the interrupt information, performing the refresh rate change operation in the skip frames arranged at the reception time of the frequency change command signal, the refresh rate is irregularly changed before the first refresh rate operation is completed.

Images