Antifuse device
By connecting the antifuse and sensing circuit in series, the problem of circuit misjudgment caused by abnormal resistance values of the antifuse in the recorded and unrecorded states is solved, and the robustness of the antifuse latching information is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-02-11
- Publication Date
- 2026-07-10
Smart Images
Figure CN116417050B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an information latching circuit, and more particularly to an antifuse device. Background Technology
[0002] Anti-fuses can be used in various electronic circuits to latch different information (anti-fuse latching information). For example, dynamic random-access memory (DRAM) chips use anti-fuses to determine which redundant row and / or redundant column to turn on. For anti-fuses, blown anti-fuses have low resistance, while unblown anti-fuses have high resistance. Depending on the anti-fuse material, in some embodiments, the resistance of blown anti-fuses can be in the range of 2–100 kΩ, while the resistance of unblown anti-fuses can be in the range of 5000–20000 kΩ. A sensing circuit can sense the resistance state of the anti-fuse to determine its blown state. However, sometimes, for various reasons, the resistance of unblown anti-fuses may be abnormally low (e.g., less than 100 kΩ). An un-coded antifuse exhibiting an abnormally low resistance value is known as an unexpected blown. Conversely, sometimes, for various reasons, the resistance of a coded antifuse may be abnormally high (e.g., greater than 5000KΩ). Whether it's an "abnormally high resistance value with coded antifuse" or an "abnormally low resistance value with un-coded antifuse," these anomalies can cause misjudgments in subsequent circuits. Improving the robustness of antifuse latch-up information is one of the many important issues in this technical field. Summary of the Invention
[0003] This invention provides an anti-fuse device to improve the robustness of anti-fuse latch information of an anti-fuse unit.
[0004] In an embodiment of the present invention, the above-described antifuse device includes an antifuse unit and a sensing circuit. The antifuse unit includes a first antifuse and a second antifuse connected in series between a first terminal and a second terminal of the antifuse unit. The sensing circuit is coupled to the first and second terminals of the antifuse unit to sense the blown state of the antifuse unit.
[0005] Based on the above, the antifuse unit in the embodiments of the present invention includes a first antifuse and a second antifuse connected in series. When one of the first and second antifuses in the antifuse unit, which is in an un-blown state, is unexpectedly blown, the other of the first and second antifuses can maintain the unblown state and provide a normal high resistance value. Therefore, the antifuse unit in the unblown state can maintain a high resistance state to correctly indicate the "unblown state". Thus, the antifuse device can improve the robustness of the antifuse latching information. Attached Figure Description
[0006] Figure 1 This is a schematic diagram of a circuit block for an anti-fuse device according to an embodiment of the present invention;
[0007] Figure 2 This is a circuit block diagram of an antifuse device according to another embodiment of the present invention;
[0008] Figure 3 This is described according to an embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit shown is shown.
[0009] Figure 4 This is described according to another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit shown is shown.
[0010] Figure 5 This is described according to another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit shown is shown.
[0011] Figure 6 This is described according to yet another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit shown is shown.
[0012] Explanation of reference numerals in the attached figures
[0013] 100, 200: Anti-fuse device
[0014] 110: Anti-fuse unit
[0015] 120: Sensing Circuit
[0016] 210_1, 210_2, 210_3, 210_n: Antifuse circuits
[0017] 211, 220_1, 220_2, 220_3, 220_n, 232: Read switches
[0018] 212: Recording switch
[0019] 213: Recording pad
[0020] 230: Reading circuit
[0021] 231: Reading the resistor
[0022] 233: Latch circuit
[0023] FUSE11, FUSE12, FUSE41, FUSE42, FUSE51, FUSE61: Anti-fuse
[0024] Vdd: Power voltage source
[0025] Vss: Reference voltage source Detailed Implementation
[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0027] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.
[0028] Figure 1 This is a schematic diagram of a circuit block of an anti-fuse device 100 according to an embodiment of the present invention. Figure 1 The antifuse device 100 shown includes an antifuse unit 110 and a sensing circuit 120. The antifuse unit 110 includes an antifuse FUSE 11 and an antifuse FUSE 12 connected in series between a first terminal and a second terminal of the antifuse unit 110. The sensing circuit 120 is coupled to the first and second terminals of the antifuse unit 110. The sensing circuit 120 can sense the blown state of the antifuse unit 110.
[0029] The sensing circuit 120 can sense the resistance states of antifuse 11 and FUSE 12, thereby determining the recording state of the antifuse unit 110. The recorded antifuse (blown antifuse) has a low resistance value, while the un-blown antifuse has a high resistance value. Depending on the antifuse material, in some embodiments, the resistance value of the recorded antifuse can be in the range of 2 to 100 KΩ, while the resistance value of the un-blown antifuse can be in the range of 5000 to 20000 KΩ. For ease of explanation, it is assumed here that the resistance value of the recorded antifuse is 100 KΩ (low resistance value), and the resistance value of the un-blown antifuse is 5000 KΩ (high resistance value). When the antifuse unit 110 is in the "unwritten" state, both antifuses FUSE11 and FUSE12 have high resistance values, so the total resistance of antifuses FUSE11 and FUSE12 is 5000KΩ + 5000KΩ = 10000KΩ. When the antifuse unit 110 is in the "written" state, both antifuses FUSE11 and FUSE12 have low resistance values, so the total resistance of antifuses FUSE11 and FUSE12 is 100KΩ + 100KΩ = 200KΩ. Therefore, the sensing circuit 120 can easily determine the writing state of the antifuse unit 110 based on the total resistance of antifuses FUSE11 and FUSE12.
[0030] However, sometimes, due to certain reasons, although the probability of occurrence is extremely small (perhaps one in ten thousand), the resistance of an un-coded antifuse may be abnormally low (e.g., less than or equal to 100KΩ). This phenomenon of an un-coded antifuse having an abnormally low resistance is called an unexpected blown. Let's assume that antifuse FUSE11 blows unexpectedly, resulting in a resistance of 100KΩ (abnormally low). When antifuse FUSE11, which should be in an uncoded state, blows unexpectedly, antifuse FUSE12 can maintain its uncoded state and provide a normal high resistance (e.g., 5000KΩ). Therefore, the total resistance of antifuse FUSE11 and FUSE12 is 100KΩ + 5000KΩ = 5100KΩ, and this total resistance of 5100KΩ is much greater than the total resistance of 200KΩ in the "coded state". Therefore, even if the antifuse 11 burns out accidentally, the antifuse unit 110, which is in an unrecorded state, can maintain a high resistance state to correctly indicate the "unrecorded state". Thus, the antifuse device 100 can improve the robustness of the antifuse latching information.
[0031] Figure 2 This is a circuit block diagram of an antifuse device 200 according to another embodiment of the present invention. Figure 2 The anti-fuse device 200 shown can be referred to Figure 1The relevant descriptions of the anti-fuse device 100 shown are as follows, and by analogy. Figure 2 The anti-fuse device 200 shown can be used as Figure 1 This is one of many implementation examples of the anti-fuse device 100 shown. Figure 2 The illustrated antifuse device 200 includes multiple antifuse circuits (e.g., antifuse circuits 210_1, 210_2, 210_3, ..., 210_n), multiple read switches (e.g., read switches 220_1, 220_2, 220_3, ..., 220_n), and a read circuit 230. The number n of antifuse circuits can be determined according to the actual design. The first terminals of these read switches 220_1 to 220_n are coupled to these antifuse circuits 210_1 to 210_n in a one-to-one manner. The second terminals of these read switches 220_1 to 220_n are coupled to the read circuit 230. Based on the switching operation of these read switches 220_1 to 220_n, these antifuse circuits 210_1 to 210_n can share the read circuit 230 in a time-sharing manner. The readout circuit 230 can sense the anti-fuse resistance state of these anti-fuse circuits 210_1 to 210_n at different times, and thus know the recording state of these anti-fuse circuits 210_1 to 210_n. Figure 2 Any of these antifuse circuits 210_1 to 210_n shown is connected to... Figure 2 The reading circuit 230 shown can be referenced. Figure 1 The descriptions of the antifuse unit 110 and the sensing circuit 120 shown are further elaborated and deduced by analogy. Figure 2 Any of these antifuse circuits 210_1 to 210_n shown is connected to... Figure 2 The reading circuit 230 shown can be used as Figure 1 This is one of many implementation examples of the antifuse unit 110 and the sensing circuit 120 shown (details to follow).
[0032] exist Figure 2In the illustrated embodiment, the read circuit 230 includes a read resistor 231, a read switch 232, and a latching circuit 233. A first terminal of the read resistor 231 is coupled to a power voltage source Vdd, and a second terminal of the read resistor 231 is coupled to the second terminals of the read switches 220_1 to 220_n. The voltage level of the power voltage source Vdd and the resistance value of the read resistor 231 can be determined according to the actual design. For example (but not limited to), the voltage level of the power voltage source Vdd can be 1.2V, and the resistance value of the read resistor 231 can be a value in the range of 0Ω to 1500KΩ. A first terminal of the read switch 232 is coupled to the second terminals of the read switches 220_1 to 220_n. When reading these antifuse circuits 210_1 to 210_n, the read switch 232 is turned on. When not reading these antifuse circuits 210_1 to 210_n, the read switch 232 is turned off. The latch circuit 233 is coupled to the second terminal of the read switch 232. When the read switch 232 is on, the latch circuit 233 can latch the recording state of one of the antifuse circuits 210_1 to 210_n.
[0033] Figure 3 This is described according to an embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit 210_1 is shown. Figure 3 The antifuse circuit 210_1 shown can be used as Figure 2 This is one of many implementation examples of the antifuse circuit 210_1 shown. Figure 2 The other antifuse circuits 210_2 to 210_n and other read switches 220_2 to 220_n shown can be referenced. Figure 3 The antifuse circuit 210_1 and the read switch 220_1 shown are explained and deduced by analogy.
[0034] exist Figure 3 In the illustrated embodiment, the antifuse circuit 210_1 includes an antifuse unit 110, a read switch 211, a write switch 212, and a write pad 213. The write pad 213 is coupled to a first terminal of the antifuse unit 110. During writing to the antifuse unit 110, the write pad 213 can be coupled to an external write voltage source (not shown) to provide a write voltage to the first terminal of the antifuse unit 110. The first terminal of the write switch 212 is coupled to a second terminal of the antifuse unit 110, and the second terminal of the write switch 212 is also coupled to a reference voltage source Vss. The level of the reference voltage source Vss can be determined according to the actual design. For example, the reference voltage source Vss can provide ground voltage or other fixed voltages.
[0035] exist Figure 3In the illustrated embodiment, the antifuse unit 110 includes antifuses FUSE11 and FUSE12. A first end of antifuse FUSE11 is coupled to a first end of antifuse unit 110. A second end of antifuse FUSE11 is coupled to a first end of antifuse FUSE12. A second end of antifuse FUSE12 is coupled to a second end of antifuse unit 110. Figure 3 The antifuse unit 110, antifuse FUSE11 and antifuse FUSE12 shown can be referenced. Figure 1 The descriptions of the antifuse unit 110, antifuse FUSE11 and antifuse FUSE12 shown are omitted here.
[0036] When the antifuse unit 110 is being programmed, the programming pad 213 can be coupled to an external programming voltage source (not shown), the programming switch 212 is on, and the read switches 211 and 220_1 are off. Therefore, programming current can flow from the programming pad 213 through the antifuse FUSE11, antifuse FUSE12, and programming switch 212 to the reference voltage source Vss. The programming current can change the programming state of antifuse FUSE11 and FUSE12 from "unprogrammed" to "programmed". When the antifuse unit 110 is not being programmed, the programming switch 212 is off, and the programming pad 213 is not coupled to any external programming voltage source.
[0037] Figure 3 The read switch 211, read switch 220_1 and read circuit 230 shown can be used as Figure 1 The components of the sensing circuit 120 shown. That is, in some embodiments, Figure 1 The sensing circuit 120 shown may include Figure 3 The diagram shows read switch 211, read switch 220_1, and read circuit 230. The first terminal of read switch 211 is coupled to the first terminal of antifuse unit 110. The second terminal of read switch 211 is coupled to the reference voltage source Vss. The first terminal of read switch 220_1 is coupled to the second terminal of antifuse unit 110. Read circuit 230 is coupled to the second terminal of read switch 220_1. Figure 3 The reading circuit 230 shown can be referenced. Figure 2 The relevant descriptions of the reading circuit 230 shown are omitted here.
[0038] In the absence of Figure 3 When reading the antifuse unit 110 of the antifuse circuit 210_1 shown, the read switches 211 and 220_1 are off. Figure 3When the antifuse unit 110 is being read, read switches 211, 220_1, and 232 are turned on. Therefore, the read current can flow from the power voltage source Vdd through the read resistor 231, read switch 220_1, antifuse FUSE12, antifuse FUSE11, and read switch 211 to the reference voltage source Vss. The read circuit 230 can sense the recording state of the antifuse unit 110 when read switches 211, 220_1, and 232 are turned on.
[0039] Figure 4 This is described according to another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit 210_1 is shown. Figure 4 The antifuse circuit 210_1 shown can be used as Figure 2 This is one of many implementation examples of the antifuse circuit 210_1 shown. Figure 2 The other antifuse circuits 210_2 to 210_n and other read switches 220_2 to 220_n shown can be referenced. Figure 4 The antifuse circuit 210_1 and the read switch 220_1 shown are explained and deduced by analogy.
[0040] Figure 4 The antifuse circuit 210_1 shown includes an antifuse unit 110, a read switch 211, a write switch 212, and a write pad 213. Figure 4 The antifuse unit 110, read switch 211, write switch 212, and write pad 213 shown can be referenced. Figure 3 The descriptions of the anti-fuse unit 110, read switch 211, write switch 212, and write pad 213 shown are similar and will not be repeated here.
[0041] exist Figure 4 In the embodiment shown, the antifuse unit 110 includes antifuse FUSE11, FUSE12, FUSE41 and FUSE42. Figure 4 The antifuse FUSE11 and FUSE12 shown can be referenced. Figure 3 The related descriptions of antifuse FUSE11 and FUSE12 are shown and can be extrapolated from here, so they will not be repeated. The first end of antifuse FUSE41 is coupled to the first end of antifuse FUSE11. The first end of antifuse FUSE42 is coupled to the second end of antifuse FUSE41. The second end of antifuse FUSE42 is coupled to the second end of antifuse FUSE12.
[0042] The sensing circuit 120 can sense the resistance states of antifuses FUSE11, FUSE12, FUSE41, and FUSE42, thereby determining the recording state of the antifuse unit 110. For ease of explanation, it is assumed here that the resistance of the recorded antifuse is 100KΩ (low resistance), while the resistance of the unrecorded antifuse is 5000KΩ (high resistance). When the recording state of the antifuse unit 110 is "unrecorded", the resistances of antifuses FUSE11, FUSE12, FUSE41, and FUSE42 are all 5000KΩ, therefore the equivalent resistance of the antifuse unit 110 (the total resistance of antifuses FUSE11, FUSE12, FUSE41, and FUSE42) is 5000KΩ. When the antifuse unit 110 is in the "written" state, the resistance of antifuses FUSE11, FUSE12, FUSE41, and FUSE42 is all 100KΩ. Therefore, the equivalent resistance of the antifuse unit 110 is 100KΩ. Thus, the sensing circuit 120 can easily determine the written state of the antifuse unit 110 based on its equivalent resistance.
[0043] Even if any of the antifuses FUSE11, FUSE12, FUSE41, and FUSE42 burns out, the sensing circuit 120 can still sense correctly. Figure 4 The diagram shows the recorded state of antifuse unit 110. It is assumed that antifuse FUSE11 burns out accidentally, resulting in a resistance of 100KΩ (abnormally low resistance). When antifuse FUSE11, which should be in the unrecorded state, burns out accidentally, antifuses FUSE12, FUSE41, and FUSE42 can remain in the unrecorded state, providing a normal high resistance (e.g., 5000KΩ). Therefore, the equivalent resistance of antifuse unit 110 (the total resistance of antifuses FUSE11, FUSE12, FUSE41, and FUSE42) is 3377.483443708609KΩ, which is significantly greater than the normal total resistance of 100KΩ in the "recorded state." Therefore, even if antifuse FUSE11 burns out accidentally, antifuse unit 110 in the unrecorded state can maintain a high resistance to correctly indicate the "unrecorded state." Therefore, the antifuse device 200 can improve the robustness of the antifuse latch information.
[0044] Conversely, sometimes, due to certain reasons, although the probability of occurrence is extremely small (perhaps one in ten thousand), the resistance value of the antifuse after being etched is abnormally high (e.g., greater than or equal to 5000KΩ). This phenomenon, where the etched antifuse has an abnormally high resistance value, is called "unable to etch." Even when any of the antifuses FUSE11, FUSE12, FUSE41, and FUSE42 fails to etch, the sensing circuit 120 can still sense correctly. Figure 4The diagram shows the recorded state of antifuse unit 110. It is assumed that antifuse FUSE11 fails to be recorded, resulting in a resistance of 5000KΩ (abnormally high resistance). When antifuse FUSE11, which should be in the recorded state, fails to be recorded, antifuses FUSE12, FUSE41, and FUSE42 can maintain their recorded state, providing normal low resistance (e.g., 100KΩ). Therefore, the equivalent resistance of antifuse unit 110 (the total resistance of antifuses FUSE11, FUSE12, FUSE41, and FUSE42) is 192.4528301886792KΩ, which is significantly lower than the normal total resistance of 5000KΩ in the "unrecorded state." Therefore, even if the antifuse 11 fails to be recorded, the antifuse unit 110 in the recorded state can maintain a low resistance state to correctly indicate the "recorded state". Thus, the antifuse device 200 can improve the robustness of the antifuse latching information.
[0045] Figure 5 This is described according to another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit 210_1 is shown. Figure 5 The antifuse circuit 210_1 shown can be used as Figure 2 This is one of many implementation examples of the antifuse circuit 210_1 shown. Figure 2 The other antifuse circuits 210_2 to 210_n and other read switches 220_2 to 220_n shown can be referenced. Figure 5 The antifuse circuit 210_1 and the read switch 220_1 shown are explained and deduced by analogy. Figure 5 The antifuse circuit 210_1 shown includes an antifuse unit 110, a read switch 211, a write switch 212, and a write pad 213. Figure 5 The antifuse unit 110, read switch 211, write switch 212, and write pad 213 shown can be referenced. Figure 3 The descriptions of the antifuse unit 110, read switch 211, write switch 212, and write pad 213 shown are analogous and will not be repeated here. Figure 5 In the embodiment shown, the antifuse unit 110 includes antifuses FUSE11, FUSE12 and FUSE51. Figure 5 The antifuse FUSE11 and FUSE12 shown can be referenced. Figure 3 The related descriptions of antifuse FUSE11 and FUSE12 are shown and can be extrapolated from here, so they will not be repeated. The first end of antifuse FUSE51 is coupled to the first end of antifuse FUSE11. The second end of antifuse FUSE51 is coupled to the second end of antifuse FUSE12.
[0046] Figure 6This is described according to yet another embodiment of the present invention. Figure 2 The circuit block diagram of the antifuse circuit 210_1 is shown. Figure 6 The antifuse circuit 210_1 shown can be used as Figure 2 This is one of many implementation examples of the antifuse circuit 210_1 shown. Figure 2 The other antifuse circuits 210_2 to 210_n and other read switches 220_2 to 220_n shown can be referenced. Figure 6 The antifuse circuit 210_1 and the read switch 220_1 shown are explained and deduced by analogy. Figure 6 The antifuse circuit 210_1 shown includes an antifuse unit 110, a read switch 211, a write switch 212, and a write pad 213. Figure 6 The antifuse unit 110, read switch 211, write switch 212, and write pad 213 shown can be referenced. Figure 3 The descriptions of the antifuse unit 110, read switch 211, write switch 212, and write pad 213 shown are analogous and will not be repeated here. Figure 6 In the embodiment shown, the antifuse unit 110 includes antifuse FUSE11, FUSE12 and FUSE61. Figure 6 The antifuse FUSE11 and FUSE12 shown can be referenced. Figure 3 The related descriptions of antifuse FUSE11 and FUSE12 are shown and can be extrapolated from here, so they will not be repeated. The first end of antifuse FUSE61 is coupled to the first end of antifuse FUSE11. The second end of antifuse FUSE61 is coupled to the second end of antifuse FUSE11.
[0047] In summary, the antifuse unit 110 described in the above embodiments includes multiple antifuses, such as antifuses FUSE11 and FUSE12 connected in series. When one of the multiple antifuses in the un-recorded antifuse unit 110 burns out, the equivalent resistance of the antifuse unit 110 can still maintain a high resistance state to correctly indicate the "unrecorded state". Therefore, the antifuse unit 110 can improve the robustness of antifuse latching information.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. An anti-fuse device, characterized in that, The anti-fuse device includes: An antifuse unit, wherein the antifuse unit includes a first antifuse and a second antifuse connected in series between a first end of the antifuse unit and a second end of the antifuse unit; and A sensing circuit, coupled to the first and second terminals of the antifuse unit, is used to sense the recording state of the antifuse unit, wherein the sensing circuit includes: A first read switch has a first terminal and a second terminal respectively coupled to the first terminal of the antifuse unit and a reference voltage source; A second read switch has a first terminal coupled to a second terminal of the antifuse unit, wherein the first read switch and the second read switch are on when the antifuse unit is being read, and the first read switch and the second read switch are off when the antifuse unit is not being read; and A read circuit, coupled to the second terminal of the second read switch, is used to sense the recording state of the antifuse unit when the second read switch is on, wherein the read circuit includes: A read resistor has a first terminal and a second terminal respectively coupled to a power voltage source and the second terminal of the second read switch; A third read switch has a first terminal coupled to the second terminal of the second read switch, wherein the third read switch is turned on when the antifuse unit is read; and A latching circuit is coupled to the second terminal of the third read switch.
2. The anti-fuse device according to claim 1, characterized in that, The first end of the first antifuse is coupled to the first end of the antifuse unit, the second end of the first antifuse is coupled to the first end of the second antifuse, and the second end of the second antifuse is coupled to the second end of the antifuse unit.
3. The anti-fuse device according to claim 2, characterized in that, The antifuse unit further includes: A third antifuse wire, wherein a first end of the third antifuse wire is coupled to a first end of the first antifuse wire, and a second end of the third antifuse wire is coupled to a second end of the first antifuse wire.
4. The anti-fuse device according to claim 2, characterized in that, The antifuse unit also includes: A third antifuse wire, wherein a first end of the third antifuse wire is coupled to a first end of the first antifuse wire, and a second end of the third antifuse wire is coupled to a second end of the second antifuse wire.
5. The anti-fuse device according to claim 2, characterized in that, The antifuse unit further includes: A third antifuse wire, wherein a first end of the third antifuse wire is coupled to a first end of the first antifuse wire; and A fourth antifuse, wherein a first end of the fourth antifuse is coupled to a second end of the third antifuse, and a second end of the fourth antifuse is coupled to a second end of the second antifuse.
6. The anti-fuse device according to claim 1, characterized in that, The anti-fuse device also includes: A recording pad, coupled to the first end of the antifuse unit, is used to couple to an external recording voltage source when recording the antifuse unit; and A recording switch has a first terminal and a second terminal respectively coupled to the second terminal of the antifuse unit and a reference voltage source, wherein the recording switch is turned on when the antifuse unit is being recorded, and the recording switch is turned off when the antifuse unit is not being recorded.