A method for manufacturing an LED chip and an LED chip

Abstract

This application provides a method for fabricating an LED chip and the LED chip itself. The method includes: providing a substrate, forming an epitaxial structure on the substrate, and forming a P-electrode and an N-electrode on the epitaxial structure. Forming the P-electrode includes: forming a first gold layer at a first evaporation rate, forming a second gold layer at a second evaporation rate, and forming a third gold layer at a third evaporation rate. Forming the N-electrode includes: forming a fourth gold layer at a first evaporation rate, forming a fifth gold layer at a second evaporation rate, and forming a sixth gold layer at a third evaporation rate. The second evaporation rate is greater than or less than the first and third evaporation rates, so that the pores of adjacent gold layers in the P-electrode and N-electrode are staggered, thereby suppressing the presence of pores penetrating the entire gold layer in the gold layers of the P-electrode and N-electrode as much as possible, reducing the possibility of chloride ions entering the electrode interior in a salt spray environment, and improving the reliability of the LED chip in a salt spray environment.

Description

Technical Field

[0001] This application relates to the field of LED chip technology, and in particular to a method for preparing an LED chip and an LED chip prepared using the method. Background Technology

[0002] LEDs (Light Emitting Diodes) are made of semiconductor materials and emit light using the special structure of semiconductors. LEDs have many advantages, including energy saving, environmental friendliness, long lifespan, and adjustable color.

[0003] However, due to the inherent characteristics of the electrode structure, when the LED chip is exposed to salt spray and light, the electrodes will corrode, which can lead to electrode detachment in severe cases. It can also cause metal in the P electrode to migrate to the vicinity of the N electrode, resulting in the loss of the gold layer of the P electrode, which affects the wire bonding and conductivity efficiency of the LED chip. Summary of the Invention

[0004] In view of this, this application provides a method for fabricating an LED chip, as follows:

[0005] A method for fabricating an LED chip, the method comprising:

[0006] Provide a substrate;

[0007] An epitaxial structure is formed on one side surface of the substrate;

[0008] A P electrode and an N electrode are formed on the side of the epitaxial structure opposite to the substrate. The P electrode includes, from bottom to top, a first gold layer, a second gold layer, and a third gold layer. The N electrode includes, from bottom to top, a fourth gold layer, a fifth gold layer, and a sixth gold layer.

[0009] Forming the P electrode includes: depositing the first gold layer at a first evaporation rate, depositing the second gold layer at a second evaporation rate, and depositing the third gold layer at a third evaporation rate;

[0010] Forming the N electrode includes: depositing the fourth gold layer at the first evaporation rate, depositing the fifth gold layer at the second evaporation rate, and depositing the sixth gold layer at the third evaporation rate;

[0011] Wherein, the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, or the second evaporation rate is less than the first evaporation rate and the third evaporation rate.

[0012] Optionally, when the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, the first evaporation rate is in the range of 0 to 10 angstroms / second, the second evaporation rate is in the range of 5 angstroms / second to 15 angstroms / second, and the third evaporation rate is in the range of 0 to 10 angstroms / second.

[0013] When the second evaporation rate is less than the first evaporation rate and the third evaporation rate, the first evaporation rate ranges from 5 Å / s to 15 Å / s, the second evaporation rate ranges from 0 to 10 Å / s, and the third evaporation rate ranges from 5 Å / s to 15 Å / s.

[0014] Optionally, the first gold layer and the fourth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms; the second gold layer and the fifth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms; and the third gold layer and the sixth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms.

[0015] Optionally, forming the P electrode further includes: sequentially depositing the first gold layer, the second gold layer, and the third gold layer at a preset temperature;

[0016] The formation of the N electrode further includes: sequentially depositing the fourth gold layer, the fifth gold layer, and the sixth gold layer at the preset temperature;

[0017] The preset temperature ranges from 80℃ to 90℃, including the endpoint values.

[0018] Optionally, before forming the first gold layer and the fourth gold layer, forming the P electrode further includes:

[0019] The first stacked metal layer is formed at the fourth evaporation rate;

[0020] At the preset temperature, a second stacked metal layer is formed at a fifth evaporation rate, wherein the first stacked metal layer and the second stacked metal layer are located between the epitaxial structure and the first gold layer from bottom to top;

[0021] The formation of the N electrode further includes:

[0022] The third stacked metal layer is formed at the fourth evaporation rate;

[0023] At the preset temperature, a fourth stacked metal layer is formed at the fifth evaporation rate, wherein the third stacked metal layer and the fourth stacked metal layer are located between the epitaxial structure and the fourth gold layer from bottom to top;

[0024] The fourth evaporation rate ranges from 0 to 5 angstroms per second, and the fifth evaporation rate ranges from 1 angstrom per second to 5 angstroms per second.

[0025] Optionally, the first and third stacked metal layers, from bottom to top, include a nickel layer and an aluminum layer, and the first and third stacked metal layers have the same thickness, ranging from 1000 angstroms to 1500 angstroms.

[0026] The second and fourth stacked metal layers, from bottom to top, consist of a titanium layer and a platinum layer, and the second and fourth stacked metal layers have the same thickness, ranging from 300 angstroms to 5000 angstroms.

[0027] Optionally, forming an epitaxial structure on one side surface of the substrate includes:

[0028] An N-type layer, an active layer, and a P-type layer are sequentially formed on one side surface of the substrate, wherein the active layer exposes a portion of the N-type layer, and the P-type layer covers the active layer;

[0029] The P electrode is located on the side of the P-type layer away from the substrate, and the N electrode is located on the exposed portion of the N-type layer away from the substrate.

[0030] Optionally, the preparation method further includes: forming a transparent conductive layer on the side of the P-type layer away from the substrate, wherein the transparent conductive layer covers the edge region of the P-type layer and exposes the middle region of the P-type layer;

[0031] The P electrode is located in the middle region of the P-type layer on the side opposite to the substrate.

[0032] Optionally, the fabrication method further includes: forming an insulating layer on the side of the transparent conductive layer opposite to the substrate, the insulating layer covering the surface of the exposed portion of the epitaxial structure and the transparent conductive layer;

[0033] The surface of the exposed portion of the epitaxial structure is the side of the exposed portion of the epitaxial structure that faces away from the substrate.

[0034] An LED chip, wherein the LED chip is prepared by the preparation method described in any of the above embodiments, comprises:

[0035] Substrate;

[0036] An epitaxial structure located on one side surface of the substrate;

[0037] The P electrode and N electrode are located on the side of the epitaxial structure opposite to the substrate. The P electrode includes, from bottom to top, a first gold layer, a second gold layer and a third gold layer. The N electrode includes, from bottom to top, a fourth gold layer, a fifth gold layer and a sixth gold layer.

[0038] Wherein, the evaporation rate of the second gold layer is greater than the evaporation rates of the first gold layer and the third gold layer, and the evaporation rate of the fifth gold layer is greater than the evaporation rates of the fourth gold layer and the sixth gold layer; or, the evaporation rate of the second gold layer is less than the evaporation rates of the first gold layer and the third gold layer, and the evaporation rate of the fifth gold layer is less than the evaporation rates of the fourth gold layer and the sixth gold layer.

[0039] Compared to existing technologies, the beneficial effects of this application are as follows:

[0040] This application provides a method for fabricating an LED chip and the LED chip itself. The method includes: providing a substrate, forming an epitaxial structure on the substrate, and forming a P-electrode and an N-electrode on the epitaxial structure. Forming the P-electrode includes: depositing a first gold layer at a first evaporation rate, depositing a second gold layer at a second evaporation rate, and depositing a third gold layer at a third evaporation rate. Forming the N-electrode includes: depositing a fourth gold layer at a first evaporation rate, depositing a fifth gold layer at a second evaporation rate, and depositing a sixth gold layer at a third evaporation rate. The second evaporation rate is greater than the first and third evaporation rates, or the second evaporation rate is less than the first and third evaporation rates. It is evident that the evaporation rates of adjacent gold layers in the P and N electrodes are different, and the evaporation rate changes from large to small to large, or from small to large to small. This causes the pores in the adjacent gold layers of the P and N electrodes to be staggered, minimizing the presence of pores penetrating the entire gold layer in the P and N electrodes. This reduces the possibility of chloride ions entering the electrode interior in the salt spray environment, thereby inhibiting damage or even failure of the LED chip in the salt spray environment and improving the reliability of the LED chip in the salt spray environment. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0043] Figure 1 This is a schematic diagram of the structure of an existing LED chip;

[0044] Figure 2 A flowchart illustrating a method for fabricating an LED chip provided in this application;

[0045] Figures 3 to 13 This is a cross-sectional view of the structure formed after different steps in the fabrication method of an LED chip provided in this application. Detailed Implementation

[0046] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely one area of ​​this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0047] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] like Figure 1 The diagram shows the structure of a conventional LED chip, which includes, in sequence: a substrate 1, an N-type layer 2, an active layer 3, a P-type layer 4, a transparent conductive layer 5, a P-electrode 6, an N-electrode 7, and an insulating layer 8. The inventors discovered that the metal electrodes of conventional blue-green display LED chips are Ni / Al / Au layered structures, specifically the P-electrode 6 and N-electrode 7. Furthermore, the constant evaporation rate of the top gold layer in the metal electrodes results in voids penetrating the gold layer. This allows chloride ions from a salt spray environment to enter the electrode through these voids, potentially corroding the Al in the electrode and causing it to detach.

[0049] Furthermore, when the LED chip is in a salt spray environment and exposed to sunlight, the gold layer in the electrode will be electrochemically corroded due to the entry of chloride ions. Also, due to the external photoelectric effect, mobile charge carriers are generated under light conditions, thereby forming an electric field. Under the action of the electric field, the corroded gold layer of P electrode 6 will migrate to the vicinity of N electrode 7, resulting in the loss of gold layer of P electrode 6, which affects the wire bonding and conductivity efficiency of the LED chip.

[0050] Based on this, this application provides a method for fabricating an LED chip, such as... Figure 2 As shown, the preparation method includes:

[0051] S1: Provide a substrate 100, such as Figure 3 As shown. The substrate 100 can be a sapphire substrate, a gallium nitride substrate, or a silicon substrate, etc. This application does not limit it and it depends on the specific circumstances.

[0052] S2: An epitaxial structure 110 is formed on one side surface of the substrate 100, such as... Figure 4 As shown.

[0053] S3: As Figure 5 As shown, a P-electrode 120 and an N-electrode 130 are formed on the side of the epitaxial structure 110 away from the substrate 100. The P-electrode 120 includes, from bottom to top, a first gold layer 121, a second gold layer 122, and a third gold layer 123, specifically, along the direction away from the side of the substrate 100 with the epitaxial structure 110, the first gold layer 121, the second gold layer 122, and the third gold layer 123 are included in sequence. The N-electrode 130 includes, from bottom to top, a fourth gold layer 131, a fifth gold layer 132, and a sixth gold layer 133, specifically, along the direction away from the side of the substrate 100 with the epitaxial structure 110, the fourth gold layer 131, the fifth gold layer 132, and the sixth gold layer 133 are included in sequence.

[0054] For step S3, forming the P electrode 120 includes: depositing the first gold layer 121 at a first evaporation rate, depositing the second gold layer 122 at a second evaporation rate, and depositing the third gold layer 123 at a third evaporation rate.

[0055] For step S3, forming the N electrode 130 includes: depositing the fourth gold layer 131 at the first evaporation rate, depositing the fifth gold layer 132 at the second evaporation rate, and depositing the sixth gold layer 133 at the third evaporation rate. It should be noted that the P electrode 120 and the N electrode 130 are formed in the same process step. Specifically, the first gold layer 121 and the fourth gold layer 131 are formed in the same evaporation step, the second gold layer 122 and the fifth gold layer 132 are formed in the same evaporation step, and the third gold layer 123 and the sixth gold layer 133 are formed in the same evaporation step. Therefore, the evaporation rates of the first gold layer 121 and the fourth gold layer 131 are the same, the evaporation rates of the second gold layer 122 and the fifth gold layer 132 are the same, and the evaporation rates of the third gold layer 123 and the sixth gold layer 133 are the same. Furthermore, the first gold layer 121, the second metal layer 122, and the third gold layer 123 constitute the gold layer of the P electrode 120, and the fourth gold layer 131, the fifth gold layer 132, and the sixth gold layer 133 constitute the gold layer of the N electrode 130.

[0056] Wherein, the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, or the second evaporation rate is less than the first evaporation rate and the third evaporation rate.

[0057] Specifically, in this embodiment, the P-electrode 120 of the LED chip fabricated using this LED chip fabrication method includes a first gold layer 121, a second gold layer 122, and a third gold layer 123 stacked sequentially, and the N-electrode 130 includes a fourth gold layer 131, a fifth gold layer 132, and a sixth gold layer 133. When fabricating the P-electrode 120, the first gold layer 121 is deposited at a first evaporation rate, the second gold layer 122 is deposited at a second evaporation rate, and the third gold layer 123 is deposited at a third evaporation rate. When fabricating the N-electrode 130, the fourth gold layer 131 is deposited at a first evaporation rate, the fifth gold layer 132 is deposited at a second evaporation rate, and the sixth gold layer 133 is deposited at a third evaporation rate. The second evaporation rate is greater than the first and third evaporation rates, or the second evaporation rate is less than the first and third evaporation rates. Therefore, the evaporation rates of the two adjacent gold layers in P electrode 120 and N electrode 130 are different, and the evaporation rates of P electrode 120 and N electrode 130 change during their fabrication process as follows: large-small-large, or small-large-small. This causes the pores of the adjacent gold layers in P electrode 120 and N electrode 130 to be misaligned, meaning that there are dislocations between the adjacent gold layers in P electrode 120 and N electrode 130. This minimizes the presence of pores penetrating the entire gold layer in P electrode 120 and N electrode 130, reducing the possibility of chloride ions entering the electrode interior in the salt spray environment. This, in turn, inhibits damage or even destruction of the LED chip in the salt spray environment, and improves the reliability of the LED chip in the salt spray environment.

[0058] Optionally, in one embodiment of this application, when the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, the first evaporation rate ranges from 0 to 10 angstroms per second, excluding the right-hand limit; the second evaporation rate ranges from 5 to 15 angstroms per second; and the third evaporation rate ranges from 0 to 10 angstroms per second, excluding the right-hand limit. When the second evaporation rate is less than the first evaporation rate and the third evaporation rate, the first evaporation rate ranges from 5 to 15 angstroms per second; the second evaporation rate ranges from 0 to 10 angstroms per second, excluding the right-hand limit; and the third evaporation rate ranges from 5 to 15 angstroms per second. However, this application does not limit this; depending on the actual situation, the first, second, and third evaporation rates can also be other ranges, depending on the specific circumstances.

[0059] Based on the above embodiments, in a preferred embodiment of this application, the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, wherein the first evaporation rate is 5 angstroms / second, the second evaporation rate is 10 angstroms / second, and the third evaporation rate is 5 angstroms / second.

[0060] In one embodiment of this application, the first gold layer and the fourth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoints; the second gold layer and the fifth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoints; the third gold layer and the sixth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoints. However, this application does not impose any limitations on this, and the specific thickness depends on the circumstances.

[0061] It should be noted that the temperature during the vapor deposition of the gold layers of the P electrode 120 and N electrode 130 also has a certain influence on the porosity of the gold layers of the P electrode 120 and N electrode 130. Generally, within a certain range, the higher the vapor deposition temperature, the smaller the porosity in the gold layer. Therefore, in one embodiment of this application, forming the P electrode 120 further includes: sequentially vapor deposition of the first gold layer 121, the second gold layer 122, and the third gold layer 123 at a preset temperature. Forming the N electrode 130 further includes: sequentially vapor deposition of the fourth gold layer 131, the fifth gold layer 132, and the sixth gold layer 133 at the preset temperature. The preset temperature ranges from 80°C to 90°C, including the endpoints, to heat the gold layers in the P electrode 120 and N electrode 130 during vapor deposition. This results in smaller pores in the gold layers of the P electrode 120 and N electrode 130, effectively improving the density of the gold layers in the P electrode 120 and N electrode 130, suppressing chloride ions from entering the electrode interior in the salt spray environment, and improving the reliability of the LED chip in the salt spray environment.

[0062] Based on the above embodiments, in a preferred embodiment of this application, the preset temperature for vapor deposition of the gold layer in the P electrode 120 and N electrode 130 is 85°C.

[0063] It should be noted that the P-electrode and N-electrode of an LED chip typically comprise multiple stacked metal layers. Therefore, in one embodiment of this application, given that the P-electrode 120 has a first gold layer 121, a second gold layer 122, and a third gold layer 123, and the N-electrode 130 has a fourth gold layer 131, a fifth gold layer 132, and a sixth gold layer 133, before forming the first gold layer 121 and the fourth gold layer 131, that is, before forming the gold layers of the P-electrode 120 and the N-electrode 130, as follows... Figure 6 As shown, for step S3, forming the P electrode 120 further includes: forming a first multilayer metal layer 124 at a fourth evaporation rate; after forming the first multilayer metal layer 124, forming a second multilayer metal layer 125 at a fifth evaporation rate at the preset temperature, wherein the first multilayer metal layer 124 and the second multilayer metal layer 125 are located from bottom to top between the epitaxial structure 110 and the first gold layer 121, that is, the first multilayer metal layer 124 and the second multilayer metal layer 125 are located from bottom to top between the epitaxial structure 110 and the gold layer of the P electrode 120.

[0064] For step S3, continue as follows Figure 6As shown, forming the N electrode 130 further includes: depositing a third multilayer metal layer 134 at the fourth evaporation rate; after forming the third multilayer metal layer 134, depositing a fourth multilayer metal layer 135 at the fifth evaporation rate at the preset temperature. The third multilayer metal layer 134 and the fourth multilayer metal layer 135 are located from bottom to top between the epitaxial structure 110 and the fourth gold layer 131, that is, the third multilayer metal layer 134 and the fourth multilayer metal layer 135 are located from bottom to top between the epitaxial structure 110 and the gold layer of the N electrode 130. It should be noted that the first stacked metal layer 124 and the third stacked metal layer 134 are formed in the same vapor deposition step, and the second stacked metal layer 125 and the fourth stacked metal layer 135 are formed in the same vapor deposition step. Therefore, the vapor deposition rates of the first stacked metal layer 124 and the third stacked metal layer 134 are the same, and the vapor deposition rates of the second stacked metal layer 125 and the fourth stacked metal layer 135 are the same.

[0065] Optionally, based on the above embodiments, in one embodiment of this application, the fourth evaporation rate ranges from 0 to 5 angstroms / second, and the fifth evaporation rate ranges from 1 angstrom / second to 5 angstroms / second.

[0066] Optionally, in one embodiment of this application, the first and third stacked metal layers sequentially comprise a nickel layer and an aluminum layer from bottom to top, and the first and third stacked metal layers have the same thickness, ranging from 1000 angstroms to 1500 angstroms, including endpoint values; the second and fourth stacked metal layers sequentially comprise a titanium layer and a platinum layer from bottom to top, and the second and fourth stacked metal layers have the same thickness, ranging from 300 angstroms to 5000 angstroms, including endpoint values. However, this application does not limit this. In other embodiments of this application, the thickness of the first stacked metal layer 124 and the third stacked metal layer 134, as well as the thickness of the second stacked metal layer 125 and the fourth stacked metal layer 135, can be other ranges of values. Furthermore, the metal layers in the first stacked metal layer 124 and the third stacked metal layer 134, and the metal layers in the second stacked metal layer 125 and the fourth stacked metal layer 135, can also be other metal layers, depending on the specific circumstances.

[0067] Based on any of the above embodiments, in one embodiment of this application, such as Figure 7As shown, forming an epitaxial structure 110 on one side surface of the substrate includes: sequentially forming an N-type layer 111, an active layer 112, and a P-type layer 113 on one side surface of the substrate 100. The active layer 112 exposes a portion of the N-type layer 111, and the P-type layer 113 covers the active layer 112 to form the epitaxial structure 110. The P-electrode 120 is located on the side of the P-type layer 113 facing away from the substrate 100, and the N-electrode 130 is located on the exposed portion of the N-type layer 111 facing away from the substrate 100, so that the P-electrode 120 is electrically connected to the P-type layer 113, and the N-electrode 130 is electrically connected to the N-type layer 111. This, in turn, allows the P-electrode 120 and the N-electrode 130 to be electrically connected to the epitaxial structure 110, providing power to the LED chip. It should be noted that in the embodiments of this application, the P-type layer is a P-type gallium nitride layer and the N-type layer is an N-type gallium nitride layer, but this application does not limit this and it depends on the specific situation.

[0068] Based on the above embodiments, in one embodiment of this application, such as Figure 8 As shown, the fabrication method further includes: forming a transparent conductive layer 114 on the side of the P-type layer 113 facing away from the substrate 100. The transparent conductive layer 114 covers the edge region of the P-type layer 113 and exposes the middle region of the P-type layer 113. Specifically, the transparent conductive layer 114 covers the edge region of the surface of the P-type layer 113 facing away from the substrate 110 and exposes the middle region of the surface of the P-type layer 113 facing away from the substrate 110, so that the epitaxial structure 110 has a transparent conductive layer 114. The transparent conductive layer 114 makes the fabricated LED chip have good current expansion and high luminous brightness. At the same time, because the transparent conductive layer 114 has high transparency, it will not affect the emission of light emitted from the active layer. The P-electrode 120 is located in the middle region of the P-type layer 113 on the side facing away from the substrate 100, so that the P-electrode 120 can be electrically connected to the P-type layer 113. It should be noted that the transparent conductive layer 114 is a material with high conductivity and high transmittance, such as indium zinc oxide.

[0069] Based on the above embodiments, in one embodiment of this application, such as Figure 9As shown, the fabrication method further includes: forming an insulating layer 115 on the side of the transparent conductive layer 114 facing away from the substrate 100. The insulating layer 115 covers the surface of the exposed portion of the epitaxial structure 110 and the transparent conductive layer 114. The surface of the exposed portion of the epitaxial structure 110 is the surface of the exposed portion of the epitaxial structure 110 facing away from the substrate. Specifically, the surface of the exposed portion of the epitaxial structure 110 refers to the portion of the surface of the epitaxial structure 110 facing away from the substrate 100 that is not covered by the transparent conductive layer 114, and the portion that is not covered by the P electrode 120 and the N electrode 130. That is, the insulating layer 115 exposes the P electrode 120 and the N electrode 130, and covers other areas not covered by the P electrode and the N electrode. In this preparation method, an insulating layer 115 is formed on the side of the transparent conductive layer 114 away from the substrate 100, which can passivate and protect the prepared LED chip. Furthermore, the insulating layer 115 exposes the P electrode 120 and the N electrode 130, so that while the insulating layer 115 plays a passivation and protection role, it also retains the ability of the LED chip to connect to external devices.

[0070] The specific process of preparing LED chips using the preparation method provided in this application is described below.

[0071] First, a substrate 100 is provided, such as Figure 3 As shown. An epitaxial structure 110 is grown on one side surface of the substrate 100. This epitaxial structure, from bottom to top, includes: an N-type layer 111, an active layer 112, and a P-type layer 113, as shown. Figure 10 As shown. Then, dry etching is performed on the active layer 112 and P-type layer 113 formed in the previous step to expose a portion of the N-type layer 111, as shown. Figure 7 As shown. A single transparent conductive layer 114 is formed on the surface of the structure created in the previous step, as shown. Figure 11 As shown. The formed transparent conductive layer 114 is wet-etched, so that the etched transparent conductive layer 114 covers the edge region of the P-type layer 113, exposing the middle region of the P-type layer 113 and part of the N-type layer 111. This part of the N-type layer 111 refers to the N-type layer 111 exposed by the active layer 112, i.e., etching out the P-electrode holes, as shown. Figure 12 As shown. A complete silicon dioxide insulating layer 115 is then formed on the surface of the structure created in the previous step, followed by dry etching to create the P-electrode holes and N-electrode holes, as shown. Figure 13As shown. Finally, the P electrode 120 and N electrode 130 are vapor-deposited, specifically, the first stacked metal layer 124 and the third stacked metal layer 134 are formed at the fourth vapor deposition rate. Then, the temperature is raised to a preset temperature of 85°C, and the second stacked metal layer 125 and the fourth stacked metal layer 135 are vapor-deposited. Finally, at the preset temperature of 85°C, the first gold layer 121 and the fourth gold layer 131, the second gold layer 122 and the fifth gold layer 132, the third gold layer 123 and the sixth gold layer 133 are vapor-deposited sequentially, as shown. Figure 9 As shown. After the metal electrodes are fabricated, they are annealed at 270℃ to complete the fabrication of the LED chip.

[0072] It should be noted that if the insulating layer 115 also covers the P electrode and N electrode except for their surface portions, the preparation of the P electrode and N electrode also includes forming a titanium layer on the top layer of the P electrode and N electrode respectively to enhance the adhesion between the insulating layer and the metal electrode.

[0073] It should also be noted that this preparation method only describes the main process of preparing LED chips. In practical applications, other corresponding steps are also included, depending on the specific circumstances.

[0074] Accordingly, this application also provides an LED chip, such as Figure 5 As shown, the LED chip includes:

[0075] Substrate 100.

[0076] An epitaxial structure 110 located on one side surface of the substrate 100.

[0077] The P electrode 120 and N electrode 130 are located on the side of the epitaxial structure 110 opposite to the substrate 100. The P electrode 120 includes, from bottom to top, a first gold layer 121, a second gold layer 122 and a third gold layer 123 stacked together. The N electrode 130 includes, from bottom to top, a fourth gold layer 131, a fifth gold layer 132 and a sixth gold layer 133 stacked together.

[0078] Wherein, the evaporation rate of the second gold layer 122 is greater than the evaporation rate of the first gold layer 121 and the third gold layer 123, and the evaporation rate of the fifth gold layer 132 is greater than the evaporation rate of the fourth gold layer 131 and the sixth gold layer 133; or, the evaporation rate of the second gold layer 122 is less than the evaporation rate of the first gold layer 121 and the third gold layer 123, and the evaporation rate of the fifth gold layer 132 is less than the evaporation rate of the fourth gold layer 131 and the sixth gold layer 133.

[0079] It should be noted that the evaporation rates of the first gold layer 121 and the fourth gold layer 131 are the same, the evaporation rates of the second gold layer 122 and the fifth gold layer 132 are the same, and the evaporation rates of the third gold layer 123 and the sixth gold layer 133 are the same. Furthermore, the first gold layer 121, the second gold layer 122, and the third gold layer 123 constitute the gold layer of the P electrode 120, and the fourth gold layer 131, the fifth gold layer 132, and the sixth gold layer 133 constitute the gold layer of the N electrode 130.

[0080] Specifically, in this embodiment of the application, the P electrode 120 of the LED chip includes a first gold layer 121, a second gold layer 122, and a third gold layer 123 stacked sequentially, and the N electrode 130 includes a fourth gold layer 131, a fifth gold layer 132, and a sixth gold layer 133. The evaporation rate of the second gold layer 122 is greater than the evaporation rates of the first gold layer 121 and the third gold layer 123, and the evaporation rate of the fifth gold layer 132 is greater than the evaporation rates of the fourth gold layer 131 and the sixth gold layer 133. Alternatively, the evaporation rate of the second gold layer 122 is less than the evaporation rates of the first gold layer 121 and the third gold layer 123, and the evaporation rate of the fifth gold layer 132 is less than the evaporation rates of the fourth gold layer 131 and the sixth gold layer 133. Therefore, the evaporation rates of the two adjacent gold layers in P electrode 120 and N electrode 130 are different, and the evaporation rates of P electrode 120 and N electrode 130 change during their fabrication process as follows: large-small-large, or small-large-small. This causes the pores of the adjacent gold layers in P electrode 120 and N electrode 130 to be misaligned, meaning that there are dislocations between the adjacent gold layers in P electrode 120 and N electrode 130. This minimizes the presence of pores penetrating the entire gold layer in P electrode 120 and N electrode 130, reducing the possibility of chloride ions entering the electrode interior in the salt spray environment. This, in turn, inhibits damage or even destruction of the LED chip in the salt spray environment, and improves the reliability of the LED chip in the salt spray environment.

[0081] Optionally, in one embodiment of this application, the first gold layer and the fourth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoint values; the second gold layer and the fifth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoint values; and the third gold layer and the sixth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms, including the endpoint values. However, this application does not impose any limitations on this, and the specific thickness depends on the circumstances.

[0082] It should be noted that the P-electrode and N-electrode of an LED chip typically comprise multiple stacked metal layers. Therefore, based on the above embodiments, in one embodiment of this application, such as... Figure 6As shown, the P electrode further includes a first stacked metal layer 124 and a second stacked metal layer 125, which are located from bottom to top between the epitaxial structure 110 and the first gold layer 121, that is, from bottom to top between the epitaxial structure 110 and the gold layer of the P electrode 120. The N electrode further includes a third stacked metal layer 134 and a fourth stacked metal layer 135, which are located from bottom to top between the epitaxial structure 110 and the fourth gold layer 131, that is, from bottom to top between the epitaxial structure 110 and the gold layer of the N electrode 130.

[0083] Optionally, in one embodiment of this application, the first and third stacked metal layers, from bottom to top, sequentially include a nickel layer and an aluminum layer, and the first and third stacked metal layers have the same thickness, ranging from 1000 angstroms to 1500 angstroms, including the endpoint values; the second and fourth stacked metal layers, from bottom to top, sequentially include a titanium layer and a platinum layer, and the second and fourth stacked metal layers have the same thickness, ranging from 300 angstroms to 5000 angstroms, including the endpoint values. However, this application does not limit this. In other embodiments of this application, the thicknesses of the first and third stacked metal layers 124 and 134, and the thicknesses of the second and fourth stacked metal layers 125 and 135, can be other ranges, and the metal layers in the first and third stacked metal layers 124 and 134, and the metal layers in the second and fourth stacked metal layers 125 and 135, can also be other metal layers, depending on the specific circumstances.

[0084] In one embodiment of this application, such as Figure 7 As shown, the epitaxial structure 110 sequentially includes an N-type layer 111, an active layer 112, and a P-type layer 113. The active layer 112 exposes a portion of the N-type layer 111, and the P-type layer 113 covers the active layer 112. The P-electrode 120 is located on the side of the P-type layer 113 facing away from the substrate 100, and the N-electrode 130 is located on the exposed portion of the N-type layer 111 facing away from the substrate 100, so that the P-electrode 120 is electrically connected to the P-type layer 113, and the N-electrode 130 is electrically connected to the N-type layer 111, thereby electrically connecting the P-electrode 120 and the N-electrode 130 to the epitaxial structure 110 to supply power to the LED chip.

[0085] Based on the above embodiments, in one embodiment of this application, such as Figure 8As shown, the LED chip also includes a transparent conductive layer 114 located on the side of the P-type layer 113 facing away from the substrate 100. The transparent conductive layer 114 covers the edge region of the P-type layer 113 and exposes the middle region of the P-type layer 113. Specifically, the transparent conductive layer 114 covers the edge region of the surface of the P-type layer 113 facing away from the substrate 110 and exposes the middle region of the surface of the P-type layer 113 facing away from the substrate 110, so that the epitaxial structure 110 has a transparent conductive layer 114. The transparent conductive layer 114 makes the LED chip have good current spreadability and high luminous brightness. At the same time, because the transparent conductive layer 114 has high transparency, it will not affect the emission of light emitted from the active layer. The P electrode 120 is located on the side of the middle region of the P-type layer 113 facing away from the substrate 100, so that the P electrode 120 can be electrically connected to the P-type layer 113. It should be noted that the transparent conductive layer 114 is a material with high conductivity and high transmittance, such as indium zinc oxide.

[0086] Based on the above embodiments, in one embodiment of this application, such as Figure 9 As shown, the LED chip also includes an insulating layer 115 located on the side of the transparent conductive layer 114 facing away from the substrate 100. The insulating layer 115 exposes the P electrode 120 and the N electrode 130 and covers other areas not covered by the P electrode and the N electrode, so that the insulating layer 115 provides passivation protection for the LED chip. While providing passivation protection, the insulating layer 115 also retains the ability of the LED chip to connect to external devices.

[0087] In summary, this application provides a method for fabricating an LED chip and the LED chip itself. The method includes: providing a substrate, forming an epitaxial structure on the substrate, and forming a P electrode and an N electrode on the epitaxial structure. Forming the P electrode includes: depositing a first gold layer at a first evaporation rate, depositing a second gold layer at a second evaporation rate, and depositing a third gold layer at a third evaporation rate. Forming the N electrode includes: depositing a fourth gold layer at a first evaporation rate, depositing a fifth gold layer at a second evaporation rate, and depositing a sixth gold layer at a third evaporation rate. The second evaporation rate is greater than the first and third evaporation rates, or the second evaporation rate is less than the first and third evaporation rates. It is evident that the evaporation rates of adjacent gold layers in the P and N electrodes are different, and the evaporation rate changes from large to small to large, or from small to large to small. This causes the pores of adjacent gold layers in the P and N electrodes to be staggered, minimizing the presence of pores penetrating the entire gold layer in the P and N electrodes. This reduces the possibility of chloride ions entering the electrode interior in the salt spray environment, thereby inhibiting damage or even destruction of the LED chip in the salt spray environment and improving the reliability of the LED chip in the salt spray environment.

[0088] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical areas between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method area.

[0089] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0090] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0091] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an LED chip, characterized in that, The preparation method includes: Provide a substrate; An epitaxial structure is formed on one side surface of the substrate; A P electrode and an N electrode are formed on the side of the epitaxial structure opposite to the substrate. The P electrode includes, from bottom to top, a first gold layer, a second gold layer, and a third gold layer. The N electrode includes, from bottom to top, a fourth gold layer, a fifth gold layer, and a sixth gold layer. Forming the P electrode includes: depositing the first gold layer at a first evaporation rate, depositing the second gold layer at a second evaporation rate, and depositing the third gold layer at a third evaporation rate; Forming the N electrode includes: depositing the fourth gold layer at the first evaporation rate, depositing the fifth gold layer at the second evaporation rate, and depositing the sixth gold layer at the third evaporation rate; Wherein, the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, or the second evaporation rate is less than the first evaporation rate and the third evaporation rate.

2. The preparation method according to claim 1, characterized in that, When the second evaporation rate is greater than the first evaporation rate and the third evaporation rate, the value range of the first evaporation rate is 0 to 10 angstroms / second, the value range of the second evaporation rate is 5 angstroms / second to 15 angstroms / second, and the value range of the third evaporation rate is 0 to 10 angstroms / second. When the second evaporation rate is less than the first evaporation rate and the third evaporation rate, the first evaporation rate ranges from 5 Å / s to 15 Å / s, the second evaporation rate ranges from 0 to 10 Å / s, and the third evaporation rate ranges from 5 Å / s to 15 Å / s.

3. The preparation method according to claim 1, characterized in that, The first gold layer and the fourth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms; the second gold layer and the fifth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms; the third gold layer and the sixth gold layer have the same thickness, ranging from 3000 angstroms to 5000 angstroms.

4. The preparation method according to claim 1, characterized in that, The formation of the P electrode further includes: sequentially depositing the first gold layer, the second gold layer, and the third gold layer at a preset temperature; The formation of the N electrode further includes: sequentially depositing the fourth gold layer, the fifth gold layer, and the sixth gold layer at the preset temperature; The preset temperature ranges from 80℃ to 90℃, including the endpoint values.

5. The preparation method according to claim 4, characterized in that, Before forming the first gold layer and the fourth gold layer, forming the P electrode further includes: The first stacked metal layer is formed at the fourth evaporation rate; At the preset temperature, a second stacked metal layer is formed at a fifth evaporation rate, wherein the first stacked metal layer and the second stacked metal layer are located between the epitaxial structure and the first gold layer from bottom to top; The formation of the N electrode further includes: The third stacked metal layer is formed at the fourth evaporation rate; At the preset temperature, a fourth stacked metal layer is formed at the fifth evaporation rate, wherein the third stacked metal layer and the fourth stacked metal layer are located between the epitaxial structure and the fourth gold layer from bottom to top; The fourth evaporation rate ranges from 0 to 5 angstroms per second, and the fifth evaporation rate ranges from 1 angstrom per second to 5 angstroms per second.

6. The preparation method according to claim 5, characterized in that, The first and third stacked metal layers, from bottom to top, comprise a nickel layer and an aluminum layer, and the first and third stacked metal layers have the same thickness, ranging from 1000 angstroms to 1500 angstroms. The second and fourth stacked metal layers, from bottom to top, consist of a titanium layer and a platinum layer, and the second and fourth stacked metal layers have the same thickness, ranging from 300 angstroms to 5000 angstroms.

7. The preparation method according to claim 1, characterized in that, Forming an epitaxial structure on one side surface of the substrate includes: An N-type layer, an active layer, and a P-type layer are sequentially formed on one side surface of the substrate, wherein the active layer exposes a portion of the N-type layer, and the P-type layer covers the active layer; The P electrode is located on the side of the P-type layer away from the substrate, and the N electrode is located on the exposed portion of the N-type layer away from the substrate.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: forming a transparent conductive layer on the side of the P-type layer away from the substrate, wherein the transparent conductive layer covers the edge region of the P-type layer and exposes the middle region of the P-type layer; The P electrode is located in the middle region of the P-type layer on the side opposite to the substrate.

9. The preparation method according to claim 8, characterized in that, The preparation method further includes: forming an insulating layer on the side of the transparent conductive layer away from the substrate, the insulating layer covering the surface of the exposed portion of the epitaxial structure and the transparent conductive layer; The surface of the exposed portion of the epitaxial structure is the side of the exposed portion of the epitaxial structure that faces away from the substrate.

10. An LED chip, characterized in that, An LED chip prepared by the preparation method according to any one of claims 1 to 9, the LED chip comprising: Substrate; An epitaxial structure located on one side surface of the substrate; The P electrode and N electrode are located on the side of the epitaxial structure opposite to the substrate. The P electrode includes, from bottom to top, a first gold layer, a second gold layer and a third gold layer. The N electrode includes, from bottom to top, a fourth gold layer, a fifth gold layer and a sixth gold layer. Wherein, the evaporation rate of the second gold layer is greater than the evaporation rates of the first gold layer and the third gold layer, and the evaporation rate of the fifth gold layer is greater than the evaporation rates of the fourth gold layer and the sixth gold layer; or, the evaporation rate of the second gold layer is less than the evaporation rates of the first gold layer and the third gold layer, and the evaporation rate of the fifth gold layer is less than the evaporation rates of the fourth gold layer and the sixth gold layer.

Images