Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, belonging to the field of display technologies. Among them, the display panel includes: a substrate having a display area and a first peripheral area, a plurality of first pixels located in the display area, and a plurality of second pixels located in the first peripheral area. Moreover, a first light-emitting element in the first pixel can emit light under the drive of a first pixel circuit, and a second light-emitting element in the second pixel can emit light under the drive of a data signal provided by a data line, that is, both the first pixels located in the display area and the second pixels located in the first peripheral area can emit light normally. Thus, it is possible to achieve better consistency in the visual effects of the display area and the first peripheral area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels are widely used in various display devices due to their advantages such as self-luminescence, small thickness, light weight, and high luminous efficiency.

[0003] In related technologies, an OLED display panel generally includes: a substrate having a display area and a peripheral area surrounding the display area, a plurality of light-emitting pixels located in the display area, and a plurality of dummy pixels located in the peripheral area. Among them, the light-emitting pixels can emit light to achieve image display. The dummy pixels do not emit light and are used to match the structure of the light-emitting pixels in the display area to ensure a good manufacturing yield of the OLED display panel.

[0004] However, since the light-emitting pixels located in the display area can emit light while the dummy pixels located in the peripheral area do not emit light, the visual effect consistency between the display area and the peripheral area of the OLED display panel is poor. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display panel and a display device, which can solve the problem of poor visual effect consistency between the display area and the peripheral area of the display panel in related technologies. The technical solutions are as follows:

[0006] On the one hand, a display panel is provided. The display panel includes:

[0007] A substrate having a display area and a first peripheral area at least partially surrounding the display area;

[0008] A plurality of first pixels located in the display area. The first pixels include a first pixel circuit and a first light-emitting element. The first pixel circuit is respectively coupled to a data line and a first pole of the first light-emitting element. The second pole of the first light-emitting element is coupled to a first power supply line. The first pixel circuit is configured to transmit a light-emitting driving signal to the first pole of the first light-emitting element based on a data signal provided by the data line. The first light-emitting element is configured to emit light based on the light-emitting driving signal and a first power supply signal provided by the first power supply line;

[0009] And a plurality of second pixels located in the first peripheral area. The second pixels include a second light-emitting element. The first pole of the second light-emitting element is coupled to the data line. The second pole of the second light-emitting element is coupled to the first power supply line. The second light-emitting element is configured to emit light based on the data signal and the first power supply signal.

[0010] Optionally, the plurality of second pixels include at least one first color pixel, at least one second color pixel, and at least one third color pixel;

[0011] The second light-emitting elements in the at least one first color pixel and the second light-emitting elements in the at least one second color pixel are coupled to the same data line;

[0012] Wherein, the potential difference between the data signal required to drive the first color pixel to emit light and the data signal required to drive the second color pixel to emit light is less than a difference threshold.

[0013] Optionally, the second light-emitting element in each adjacent first color pixel and the second light-emitting element in a second color pixel are coupled to the same data line.

[0014] Optionally, the plurality of second pixels are arranged in an array, and each row of the second pixels is arranged in the order of one first color pixel, one second color pixel, and one third color pixel.

[0015] Optionally, the first color is red, the second color is green, and the third color is blue.

[0016] Optionally, the second pixel further includes: a second pixel circuit;

[0017] The second pixel circuit is respectively coupled to a first reset control line, a reset signal line, and a first pole of the second light-emitting element. The second pixel circuit is configured to respond to a first reset control signal provided by the first reset control line and transmit the reset signal provided by the reset signal line to the first pole of the second light-emitting element to reset the first pole of the second light-emitting element.

[0018] Optionally, the second pixel circuit and the first pixel circuit are also respectively coupled to a gate line, a light-emitting control line, a second reset control line, and a second power supply line; the first pixel circuit is also respectively coupled to the first reset control line and the reset signal line; the second pixel circuit is also coupled to the data line;

[0019] Wherein, the first pixel circuit is configured to transmit the light-emitting drive signal to the first pole of the first light-emitting element based on the data signal, the first reset control signal, the reset signal, the gate drive signal provided by the gate line, the light-emitting control signal provided by the light-emitting control line, the second power supply signal provided by the second power supply line, and the second reset control signal provided by the second reset control line.

[0020] Optionally, the structure of the second pixel circuit is the same as the structure of the first pixel circuit.

[0021] Optionally, the multiple first pixels include: at least one red pixel, at least one green pixel, and at least one blue pixel, and the first pixel circuit includes: a driving transistor;

[0022] Among them, in the multiple first pixels, the channel width-to-length ratio of the driving transistor in the first pixel circuit included in the blue pixel is greater than that of the driving transistor in the first pixel circuit included in the red pixel, and greater than that of the driving transistor in the first pixel circuit included in the green pixel.

[0023] Optionally, the substrate further has: a second peripheral region at least partially surrounding the first peripheral region, and a third peripheral region at least partially surrounding the second peripheral region; the display panel further includes:

[0024] A gate driving circuit located in the second peripheral region, the gate driving circuit is coupled to the gate line and is configured to transmit the gate driving signal to the gate line;

[0025] The orthographic projection of the second pole of the first light-emitting element and the second pole of the second light-emitting element on the substrate covers the display area, the first peripheral region, the second peripheral region, and the third peripheral region.

[0026] Optionally, both the first pixel circuit and the second pixel circuit include: an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, and an insulating layer stacked in sequence along a direction away from the substrate;

[0027] The first pole of the first light-emitting element is located on a side of the insulating layer included in the first pixel circuit away from the substrate; the first pole of the second light-emitting element is located on a side of the insulating layer included in the second pixel circuit away from the substrate;

[0028] The display panel further includes: a pixel defining layer and a pixel support layer stacked in sequence along a direction away from the substrate on a side of the first pole of the first light-emitting element away from the substrate and a side of the first pole of the second light-emitting element away from the substrate;

[0029] The second poles of the first light-emitting element and the second light-emitting element are both located on a side of the pixel support layer away from the substrate.

[0030] Optionally, the insulating layer includes: a passivation layer and a planarization layer stacked in sequence along a direction away from the substrate;

[0031] The first pixel circuit further includes: a second source-drain metal layer located between the passivation layer and the planarization layer;

[0032] The second peripheral region at least partially overlaps with the first peripheral region.

[0033] Optionally, the second peripheral region coincides with the first peripheral region;

[0034] The gate driving circuit and the first pixel circuit are on the same layer, and the data lines coupled to the second light-emitting elements are stacked in sequence in a direction away from the substrate.

[0035] On the other hand, a display device is provided, which includes: a display panel as described in the above aspect, and a driving circuit;

[0036] The driving circuit is coupled to the data lines in the display panel, and the driving circuit is configured to provide data signals to the data lines.

[0037] Optionally, the driving circuit includes: a master control sub-circuit and a source driver;

[0038] The master control sub-circuit is coupled to the source driver, and the master control sub-circuit is configured to transmit control signals to the source driver;

[0039] The source driver is coupled to the data lines, and the source driver is configured to transmit data signals to the data lines based on the control signals.

[0040] In summary, the beneficial effects brought by the technical solutions provided in the present disclosure may at least include:

[0041] A display panel and a display device are provided. Among them, the display panel includes: a substrate having a display area and a first peripheral area, a plurality of first pixels located in the display area, and a plurality of second pixels located in the first peripheral area. Moreover, the first light-emitting element in the first pixel can emit light under the drive of the first pixel circuit, and the second light-emitting element in the second pixel can emit light under the drive of the data signals provided by the data lines, that is, both the first pixels in the display area and the second pixels in the first peripheral area can emit light normally. In this way, the visual effect consistency between the display area and the first peripheral area can be better. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is an equivalent schematic diagram of abnormal display of a display panel provided by an embodiment of the present disclosure;

[0044] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0045] Figure 3 It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0046] Figure 4 It is a schematic structural diagram of yet another display panel provided by an embodiment of the present disclosure;

[0047] Figure 5 It is a schematic structural diagram of still another display panel provided by an embodiment of the present disclosure;

[0048] Figure 6 It is a schematic structural diagram of a first pixel provided by an embodiment of the present disclosure;

[0049] Figure 7 It is a schematic structural diagram of a second pixel provided by an embodiment of the present disclosure;

[0050] Figure 8 It is a schematic structural diagram of another second pixel provided by an embodiment of the present disclosure;

[0051] Figure 9 It is a structural layout diagram of an active layer provided by an embodiment of the present disclosure;

[0052] Figure 10 It is a structural layout diagram of an active layer and a first gate metal layer provided by an embodiment of the present disclosure;

[0053] Figure 11 It is a structural layout diagram of an active layer, a first gate metal layer, and a second gate metal layer provided by an embodiment of the present disclosure;

[0054] Figure 12 It is a structural layout diagram of an active layer, a first gate metal layer, a second gate metal layer, and an interlayer dielectric layer provided by an embodiment of the present disclosure;

[0055] Figure 13 It is a structural layout diagram of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, and a first source / drain metal layer provided by an embodiment of the present disclosure;

[0056] Figure 14 It is a structural layout diagram of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, and a planarization layer provided by an embodiment of the present disclosure;

[0057] Figure 15 It is a structural layout diagram of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, and a passivation layer provided by an embodiment of the present disclosure;

[0058] Figure 16 It is the structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, a passivation layer, and a second source / drain metal layer provided by an embodiment of the present disclosure;

[0059] Figure 17 It is another structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, a passivation layer, and a second source / drain metal layer provided by an embodiment of the present disclosure;

[0060] Figure 18 It is the structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, a passivation layer, a second source / drain metal layer, and an anode provided by an embodiment of the present disclosure;

[0061] Figure 19 It is the structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, a passivation layer, a second source / drain metal layer, an anode, and a pixel definition layer provided by an embodiment of the present disclosure;

[0062] Figure 20 It is the structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a planarization layer, a passivation layer, a second source / drain metal layer, an anode, a pixel definition layer, and a pixel support layer provided by an embodiment of the present disclosure;

[0063] Figure 21 It is yet another structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, and a first source / drain metal layer provided by an embodiment of the present disclosure;

[0064] Figure 22 It is another structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, and a first source / drain metal layer provided by an embodiment of the present disclosure;

[0065] Figure 23 It is the equivalent structural diagram of a display panel provided by an embodiment of the present disclosure;

[0066] Figure 24 It is yet another structural layout of an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, and a first source / drain metal layer provided by an embodiment of the present disclosure;

[0067] Figure 25 It is the structural layout of a part of the active layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0068] Figure 26It is a structural layout of a partial active layer and a first gate metal layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0069] Figure 27 It is a structural layout of a partial active layer, a first gate metal layer and a second gate metal layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0070] Figure 28 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer and an interlayer dielectric layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0071] Figure 29 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer and a first source-drain metal layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0072] Figure 30 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer and a planarization layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0073] Figure 31 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, a planarization layer and an anode in a second pixel circuit provided by an embodiment of the present disclosure;

[0074] Figure 32 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, a second source-drain metal layer, a planarization layer and a passivation layer in a second pixel circuit provided by an embodiment of the present disclosure;

[0075] Figure 33 It is a structural layout of a partial active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, a second source-drain metal layer, a planarization layer, a passivation layer and an anode in a second pixel circuit provided by an embodiment of the present disclosure;

[0076] Figure 34 It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0077] Figure 35 It is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0078] Figure 36 It is another partial cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0079] Figure 37 It is a cross-sectional view of a display panel including a first pixel and a second pixel provided by an embodiment of the present disclosure;

[0080] Figure 38 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0081] Figure 39 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure;

[0082] Figure 40 is a schematic structural diagram of yet another display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0083] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0084] In all embodiments of the present disclosure, the transistors employed may be thin-film transistors, field-effect transistors, or other devices with the same characteristics. According to their functions in the circuit, the transistors adopted in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, the source is referred to as the first pole and the drain as the second pole; or, the drain is referred to as the first pole and the source as the second pole. According to the morphology in the drawings, the middle line of the transistor is defined as the gate, the signal input line as the source, and the signal output line as the drain. In addition, the switching transistors adopted in the embodiments of the present disclosure may include either P-type switching transistors or N-type switching transistors. Among them, the P-type switching transistor conducts when the gate is at a low level and cuts off when the gate is at a high level, and the N-type switching transistor conducts when the gate is at a high level and cuts off when the gate is at a low level.

[0085] Currently, each dummy pixel disposed in the peripheral area only includes a pixel circuit and a cathode, and does not include film layers such as an anode and a light-emitting layer. On this basis, as recorded in the background art, the dummy pixel does not emit light. As a result, the visual effect (i.e., visual effect) consistency between the peripheral area and the display area it surrounds is relatively poor. Moreover, for some medium and large-sized display panels, due to the relatively poor fitting accuracy between the peripheral area and the display area, bright stripes as shown in Figure 1 are likely to appear at the adjacent position between the peripheral area and the display area, thereby resulting in a relatively poor display effect of the display panel. The peripheral area provided with dummy pixels may also be referred to as a dummy area.

[0086] The embodiments of the present disclosure provide a display panel in which the pixels located in the display area and the dummy pixels located in the peripheral area can both emit light. In this way, the visual effect consistency between the display area and the peripheral area is improved.

[0087] Figure 2It is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As Figure 2 shown, the display panel includes: a substrate 01 having a display area (active area, AA) and at least a part of a first peripheral area B1 surrounding the display area AA. For example, referring to Figure 2 , it shows that the first peripheral area B1 surrounds the display area AA, that is, the display area AA is surrounded by the first periphery B1. Generally speaking, the area of the display area AA is much larger than the area of the first peripheral area B1 to ensure that the display panel can effectively display images.

[0088] Figure 3 It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As Figure 3 shown, the display panel further includes: a plurality of first pixels 02 located in the display area AA and a plurality of second pixels 03 located in the first peripheral area B1. Here, the first peripheral area B1 is the Dummy area described in the above embodiment, and correspondingly, the second pixel 03 is the Dummy pixel described in the above embodiment.

[0089] Among them, each first pixel 02 includes a first pixel circuit 021 and a first light-emitting element L1. The first pixel circuit 021 is respectively coupled to the data line D1 and the first pole of the first light-emitting element L1, and the second pole of the first light-emitting element L1 is coupled to the first power line V1. The first pixel circuit 021 is configured to transmit a light-emitting driving signal (such as a driving current) to the first pole of the first light-emitting element L1 based on the data signal provided by the data line D1. The first light-emitting element L1 is configured to emit light based on the light-emitting driving signal and the first power signal provided by the first power line V1. That is, the first light-emitting element L1 can emit light under the drive of the first pixel circuit 021.

[0090] Each second pixel 03 includes a second light-emitting element L2. The first pole of the second light-emitting element L2 is coupled to the data line D1, and the second pole of the second light-emitting element L2 is coupled to the first power line V1. The second light-emitting element L2 is configured to emit light based on the data signal and the first power signal. That is, the second light-emitting element L2 can directly emit light under the drive of the data signal provided by the data line D1 without an additional pixel circuit to provide a light-emitting driving signal to drive it to emit light.

[0091] Combined with the description in the above embodiment, it can be known that in the display panel provided by the embodiment of the present disclosure, both the first light-emitting element L1 located in the display area AA and the second light-emitting element L2 located in the first peripheral area B1 (that is, the Dummy pixel located in the Dummy area) can emit light normally. In this way, the problem of poor visual effect consistency between the display area AA and the first peripheral area B1 of the display panel in the related art can be solved.

[0092] Optionally, in the embodiment of the present disclosure, referring toFigure 3 The first poles of the first light-emitting element L1 and the second light-emitting element L2 can both be anodes, and correspondingly, the second poles of the first light-emitting element L1 and the second light-emitting element L2 are both cathodes. Of course, in some embodiments, the first poles of the first light-emitting element L1 and the second light-emitting element L2 can also both be cathodes, and correspondingly, the second poles of the first light-emitting element L1 and the second light-emitting element L2 are both anodes.

[0093] In summary, the embodiments of the present disclosure provide a display panel. The display panel includes: a substrate having a display area and a first peripheral area, a plurality of first pixels located in the display area, and a plurality of second pixels located in the first peripheral area. Moreover, the first light-emitting element in the first pixel can emit light under the drive of the first pixel circuit, and the second light-emitting element in the second pixel can emit light under the drive of the data signal provided by the data line, that is, both the first pixels located in the display area and the second pixels located in the first peripheral area can emit light normally. In this way, the visual effects of the display area and the first peripheral area can have better consistency.

[0094] Optionally, in the embodiments of the present disclosure, the second pixels 03 that can emit light normally in the first peripheral area B1 can be reused to achieve an illumination effect. Correspondingly, the display panel provided by the embodiments of the present disclosure can also be referred to as an illuminable display screen. This illuminable design concept can be applied to various scenarios to improve the user experience.

[0095] For example, for a terminal with a self-shooting function (such as a mobile phone), when it has the display panel provided by the embodiments of the present disclosure, the illuminable design of the display panel can meet the spotlight effect during self-shooting.

[0096] Figure 4 is a schematic structural diagram of another display panel provided by the embodiments of the present disclosure. As Figure 4 shown, the second pixel 03 may further include: a second pixel circuit 031.

[0097] Among them, the second pixel circuit 031 can be respectively coupled to the first reset control line Rst1, the reset signal line Vin1, and the first pole of the second light-emitting element L2. The second pixel circuit 031 can be configured to respond to the first reset control signal provided by the first reset control line Rst1 and transmit the reset signal provided by the reset signal line Vin1 to the first pole of the second light-emitting element L2 to reset the first pole of the second light-emitting element L2.

[0098] In this way, the luminance uniformity of each second light-emitting element L2 can be ensured to be relatively good to a certain extent. For example, it can be ensured that when the plurality of second pixels 03 are used for illumination, the illumination color does not deviate greatly from the actually required illumination color.

[0099] Figure 5 It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As Figure 5 shown, the first pixel circuit 021 and the second pixel circuit 031 can also be respectively coupled to the gate line G1, the emission control line EM1, the second reset control line Rst2, and the second power supply line V2. The first pixel circuit 021 can also be respectively coupled to the first reset control line Rst1 and the reset signal line Vin1. The second pixel circuit 031 can also be coupled to the data line D1.

[0100] Among them, the first pixel circuit 021 can be used to transmit an emission driving signal to the first pole of the first light-emitting element L1 based on the data signal, the first reset control signal, the reset signal, the gate driving signal provided by the gate line G1, the emission control signal provided by the emission control line EM1, the second power supply signal provided by the second power supply line V2, and the second reset control signal provided by the second reset control line Rst2. That is, the first pixel circuit 021 can operate in response to the signals provided by each signal line to which it is coupled to drive the coupled first light-emitting element L1 to emit light.

[0101] The second pixel circuit 031 is only coupled to the first reset control line Rst1, the reset signal line Vin1, the gate line G1, the emission control line EM1, the data line D1, the second reset control line Rst2, and the second power supply line V2, and does not drive the second light-emitting element L2 to emit light in response to the signals provided by these signal lines. And in combination with the above embodiments, it can be known that the first pole of the second light-emitting element L2 is directly and effectively coupled to the data line D1, and can emit light only under the drive of the data signal provided by the data line D1, and the driving method is simple.

[0102] Optionally, in combination with Figure 4 and Figure 5 , in some embodiments, the second pixel circuit 031 can transmit the reset signal provided by the reset signal line Vin1 to the first pole of the second light-emitting element L2 in response to the first reset control signal provided by the first reset control line Rst1 to reset the first pole of the second light-emitting element L2. In other embodiments, the second pixel circuit 031 may not transmit the reset signal provided by the reset signal line Vin1 to the first pole of the second light-emitting element L2 in response to the first reset control signal provided by the first reset control line Rst1, that is, the first pole of the second light-emitting element L2 is not reset.

[0103] Optionally, in the embodiments of the present disclosure, the structure of the first pixel circuit 021 and the structure of the second pixel circuit 031 may be the same. For example, with reference to Figures 6 to 8 , the first pixel circuit 021 and the second pixel circuit 031 may both include: seven transistors T1 to T7, and a capacitor Cst.

[0104] Among them, the reference Figure 6 It can be seen that the coupling points of each transistor in the first pixel circuit 021 are all solid dots, indicating effective coupling. Figure 6 The circles filled with black in it represent solid dots. Thus, the first pixel circuit 021 can reliably transmit the light-emitting drive signal to the first light-emitting element L1 based on the signals provided by the respective signal lines to which it is coupled, so as to drive the first light-emitting element L1 to emit light.

[0105] Reference Figure 7 It can be seen that the coupling points (such as the coupling point of the transistor T7, the transistor T6, and the first pole of the second light-emitting element L2) on at least the path for driving the second light-emitting element L2 to emit light in the second pixel circuit 031 are all hollow dots, indicating virtual connection. Figure 7 The dotted circles in it represent hollow dots. Only the coupling point of the data line D1 and the first pole of the second light-emitting element L2 is a solid dot, that is, effective coupling. Thus, the second pixel circuit 031 does not transmit any signal to the second light-emitting element L2. And, the data line D1 can reliably transmit the data signal to the first pole of the second light-emitting element L2 to drive the second light-emitting element L2 to emit light.

[0106] Comparison Figure 7 , reference Figure 8 It can be seen that the coupling point of the transistor T7 and the first pole of the second light-emitting element L2 in the second pixel circuit 031 is a solid dot, that is, effective coupling, and the transistor T7 is also effectively coupled to the first reset control line Rst1 and the reset signal line Vin1 respectively. On this basis, combined with the description in the above embodiment, it can be known that the transistor T7 can respond to the first reset control signal provided by the first reset control line Rst1 and transmit the reset signal provided by the reset signal line Vin1 to the first pole of the second light-emitting element L2 to reset the first pole of the second light-emitting element L2.

[0107] Optionally, combined with Figures 6 to 8 it can be known that in the embodiment of the present disclosure, the first power supply line V1 can be a pull-down power supply line ELVSS, and the second power supply line V2 can be a charging power supply line ELVDD. Correspondingly, the potential of the first power supply signal provided by the first power supply line V1 is less than the potential of the second power supply signal provided by the second power supply line V2. Of course, in some other embodiments, the potential of the first power supply signal can also be greater than the potential of the second power supply signal.

[0108] Taking Figure 6 the shown structure as an example, on the basis that each node is effectively coupled, the working principles of each transistor in the first pixel circuit 021 are introduced as follows:

[0109] Among them, the gate of transistor T1 can be coupled to gate line G1, the first pole of transistor T1 can be coupled to the gate of transistor T3, and the second pole of transistor T1 can be coupled to the second pole of transistor T3. Transistor T1 can adjust the potential of the gate of transistor T3 and the potential of the second pole of transistor T3 in response to a gate driving signal to achieve compensation for the threshold voltage Vth of transistor T3. Correspondingly, transistor T1 can also be referred to as a compensation transistor.

[0110] The gate of transistor T2 can be coupled to second reset control line Rst2, the first pole of transistor T2 can be coupled to reset signal line Vin1, and the second pole of transistor T2 can be coupled to the gate of transistor T3. Transistor T2 can transmit a reset signal to the gate of transistor T3 in response to a second reset control signal to achieve reset of the gate of transistor T3. Correspondingly, transistor T2 can also be referred to as a reset transistor.

[0111] The gate of transistor T4 can be coupled to gate line G1, the first pole of transistor T4 can be coupled to data line D1, and the second pole of transistor T4 can be coupled to the first pole of transistor T3. Transistor T4 can transmit a data signal to the first pole of transistor T3 in response to a gate driving signal to achieve charging of the first pole of transistor T3. Correspondingly, transistor T4 can also be referred to as a data writing transistor. Transistor T3 can generate a driving signal based on the potential of its gate and the potential of its first pole.

[0112] The gates of transistor T5 and transistor T6 can both be coupled to emission control line EM1. The first pole of transistor T5 can be coupled to second power supply line V2, and the second pole of transistor T5 can be coupled to the first pole of transistor T3. The first pole of transistor T6 can be coupled to the second pole of transistor T3, and the second pole of transistor T6 can be coupled to the first pole of first light-emitting element L1. Transistor T5 can control the conduction between second power supply line V2 and the first pole of transistor T3 in response to an emission control signal. Transistor T6 can control the conduction between the second pole of transistor T3 and the first pole of first light-emitting element L1 in response to an emission control signal. When second power supply line V2 is conducted with the first pole of transistor T3 and the second pole of transistor T3 is conducted with the first pole of first light-emitting element L1, the driving signal generated by transistor T3 can be changed into a light-emitting driving signal through transistor T6 and transmitted to first light-emitting element L1, thereby driving first light-emitting element L1 to emit light. Correspondingly, transistor T3 can also be referred to as a driving transistor. Transistor T5 and transistor T6 can both be referred to as emission control transistors.

[0113] The gate of transistor T7 can be coupled to the first reset control line Rst1, the first pole of transistor T7 can be coupled to the reset signal line Vin1, and the second pole of transistor T7 can be coupled to the first pole of the first light-emitting element L1. Transistor T7 can transmit a reset signal to the first pole of the first light-emitting element L1 in response to the first reset control signal to reset the first pole of the first light-emitting element L1. Correspondingly, transistor T7 can also be referred to as a reset transistor.

[0114] One end of capacitor Cst can be coupled to the gate of transistor T3, and the other end can be coupled to the second power supply line V2. Capacitor Cst can be used to adjust the potential of the gate of transistor T3 based on the second power supply signal.

[0115] Combining the operating principles of the above various transistors, it can be seen that for Figure 7 the structure shown, all the transistors in the second pixel circuit 031 do not work. For Figure 8 the structure shown, only transistor T7 in the second pixel circuit 031 works, and transistor T7 is used to reset the first pole of the second light-emitting element L2.

[0116] It should be noted that in the embodiments of the present disclosure, in addition to being Figures 6 to 8 the 7T1C (i.e., seven transistors and one capacitor) structure shown, the first pixel circuit 021 and the second pixel circuit 031 can also be structures including other numbers of transistors, such as the 4T1C structure.

[0117] Optionally, in the embodiments of the present disclosure, the multiple first pixels 02 may include: at least one red (R) pixel, at least one green (G) pixel, and at least one blue (B) pixel. And, as described in the above embodiments, the first pixel circuit 021 may include: a driving transistor, that is, transistor T3.

[0118] Among them, in the multiple first pixels 02, the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the blue B pixel is greater than the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the red R pixel, and is greater than the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the green G pixel. That is, the channel width-to-length ratio W / L of the driving transistor T3 included in the blue B pixel, the channel width-to-length ratio W / L of the driving transistor T3 included in the red R pixel, and the channel width-to-length ratio W / L of the driving transistor T3 included in the green G pixel are different, and the channel width-to-length ratio W / L of the driving transistor T3 included in the blue B pixel can be the largest.

[0119] After testing, the potential of the data signal driving the blue B pixel to emit light is generally greater than that of the data signal driving the red R pixel to emit light, and greater than that of the data signal driving the green G pixel to emit light. Therefore, by setting the channel width-to-length ratio W / L of the driving transistor T3 included in the blue B pixel to be the largest, reliable driving of the blue B pixel can be ensured, enabling the blue B pixel to be effectively lit. In addition, by setting the channel width-to-length ratio W / L of the driving transistor T3 included in the red R pixel and the channel width-to-length ratio W / L of the driving transistor T3 included in the green G pixel to be smaller, the overall resolution of the display panel can be ensured to be relatively good.

[0120] Optionally, as described in the above embodiment, the structures of the second pixel circuit 031 and the first pixel circuit 021 can be the same. Furthermore, although the second pixel circuit 031 is not used to drive the second light-emitting element L2 to emit light, in the embodiments of the present disclosure, based on the fact that multiple second pixels 03 also include at least one red R pixel, at least one green G pixel, and at least one blue B pixel, it is also possible to set that in multiple second pixels 03, the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the blue B pixel is greater than the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the red R pixel, and greater than the channel width-to-length ratio W / L of the driving transistor T3 in the first pixel circuit 021 included in the green G pixel.

[0121] Optionally, in the embodiments of the present disclosure, multiple first pixels 02 located in the display area AA and multiple second pixels 03 located in the first peripheral area B1 can both be arranged in an array. On this basis, taking Figure 6 and Figure 7 the structure shown as an example of 2 rows and 3 columns of adjacent pixels in the display area AA and the first peripheral area B1, Figures 9 to 20 a structure layout of each film layer in a display panel is shown.

[0122] Referring to Figures 9 to 20 it can be seen that both the first pixel circuit 021 and the second pixel circuit 031 can include: an active layer (poly) P1, a first gate metal layer Gate1, a second gate metal layer Gate2, an inter-level dielectric layer (ILD), a first source-drain metal layer SD1, and an insulating layer J1, which are sequentially stacked in a direction away from the substrate 01.

[0123] On this basis, the first electrode (e.g., the anode) of the first light-emitting element L1 can be located on the side of the insulating layer J1 included in the first pixel circuit 021 away from the substrate 01. The first electrode (e.g., the anode) of the second light-emitting element L2 can be located on the side of the insulating layer J1 included in the second pixel circuit 021 away from the substrate 01.

[0124] Optionally, in combination with Figure 14 and Figure 15 It can be seen that the insulating layer J1 may include: a passivation layer PVX and a planarization layer PLN that are sequentially stacked in a direction away from the substrate 01. Moreover, the passivation layer PVX may be located on a side of the planarization layer PLN away from the substrate 01.

[0125] Optionally, referring to Figure 16 It can be seen that the first pixel circuit 021 may further include: a second source-drain metal layer SD2 located on a side of the passivation layer PVX away from the planarization layer PLN. On this basis, the display panel may further include: an insulating layer located between the second source-drain metal layer SD2 and the first electrode of the first light-emitting element L1. This insulating layer may also be the planarization layer PLN. Figure 15 In [reference], the planarization layer PLN located on a side of the passivation layer PVX away from the second source-drain metal layer SD2 is labeled as PLN1. Figure 17 In [reference], the planarization layer PLN located between the second source-drain metal layer SD2 and the first electrode (e.g., anode) of the first light-emitting element L1 is labeled as PLN2.

[0126] Continuing to refer to Figure 19 and Figure 20 It can be seen that the display panel provided by the embodiments of the present disclosure may further include: a pixel definition layer PDL and a pixel support layer PS that are located on a side of the first electrode of the first light-emitting element L1 away from the substrate 01 and on a side of the first electrode of the second light-emitting element L2 away from the substrate 01, and are sequentially stacked in a direction away from the substrate 01. On this basis, the second electrodes (e.g., cathodes) of the first light-emitting element L1 and the second light-emitting element L2 may both be located on a side of the pixel support layer PS away from the substrate 01. Figure 20 The cathode is not shown in [reference].

[0127] Optionally, referring to Figure 21 , in the embodiments of the present disclosure, the second pixel circuit 031 may also include: a second source-drain metal layer SD2 and a planarization layer PLN2 that are located between the passivation layer PVX and the first electrode (e.g., anode) of the second light-emitting element L2, and are sequentially stacked in a direction away from the substrate 01.

[0128] Optionally, in combination with Figures 6 to 8 , a part of the first gate metal layer Gate1 may serve as one capacitor plate of the capacitor Cst, and another part may serve as the gate of the transistor and be coupled to the corresponding signal line. For example, for the first pixel circuit 021, a part of the first gate metal layer Gate1 may serve as the gate of the transistor T4 and be coupled to the gate line G1.

[0129] A part of the second gate metal layer Gate2 can serve as another capacitor plate of the capacitor Cst, and another part can also serve as the gate of a transistor, which is coupled to the corresponding signal line. For example, for the first pixel circuit 021, a part of the second gate metal layer Gate2 can serve as the gate of the transistor T7 and is coupled to the first reset control line Rst1.

[0130] The first source-drain metal layer SD1 can serve as the source and drain of a transistor and is coupled to the corresponding signal line or coupling point. For example, for the first pixel circuit 021, a part of the first source-drain metal layer SD1 can serve as the source of the transistor T4 and is coupled to the data line D1; and, another part of the first source-drain metal layer SD1 can serve as the source of the transistor T5 and is coupled to the second power supply line V2. For example, for the second pixel circuit 031, the first source-drain metal layer SD1 can serve as the source of the transistor T4 and is coupled to the data line D1.

[0131] The second source-drain metal layer SD2 can serve as the source and drain of a transistor and is coupled to the corresponding signal line or coupling point. For example, for the first pixel circuit 021, the second source-drain metal layer SD2 can serve as the source of the transistor T5 and is coupled to the second power supply line V2. That is, the second power supply line V2 can include a double-layer source-drain metal layer. In this way, it can be ensured that the second power supply signal provided by the second power supply line V2 is relatively stable. For the second pixel circuit 031, when it includes the second source-drain metal layer SD2, this second source-drain metal layer SD2 can also serve as the source of the transistor T4 and is coupled to the data line D1. That is, the data line D1 to which the transistor T4 in the second pixel circuit 031 is coupled can include a double-layer source-drain metal layer. In this way, it can be ensured that the data signal provided by the data line D1 is relatively stable. Of course, in some other embodiments, the first pixel circuit 021 can only include the first source-drain metal layer SD1 and does not include the second source-drain metal layer SD2. Such as Figure 20 the second pixel circuit 031 can only include the first source-drain metal layer SD1 and does not include the second source-drain metal layer SD2.

[0132] The insulating layer (including the planarization layers PLN1, PLN2 and the passivation layer PVX described in the above embodiments) can be used to insulate the adjacent upper and lower conductive layers to avoid signal crosstalk. On this basis, in order to ensure effective overlap of the conductive layers on both sides of the insulating layer, the insulating layer can have vias, and the conductive layers on both sides of the insulating layer can be overlapped with each other through the vias penetrating the insulating layer.

[0133] Reference Figures 9 to 20It can be seen that in the first pixel 02 only located in the display area AA, the first pixel circuit 021 and the anode of the first light-emitting element L1 are effectively overlapped through a via hole. However, in the second pixel 03 located in the first peripheral area B1, no via holes are made in the respective film layers of the second pixel circuit 031, and the second pixel circuit 031 is not coupled to the anode of the second light-emitting element L2. In addition, the anode of the second light-emitting element L2 is coupled to the first source-drain metal layer SD1 coupled to the data line D1, and the cathode of the second light-emitting element L2 is coupled to the first power supply line V1, that is, the two ends of the second light-emitting element L2 are directly coupled by the data line D1 and the cathode.

[0134] Take Figure 8 as an example. Figure 22 Another structural layout including an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, and a first source-drain metal layer is shown. Comparing Figure 13 and Figure 21 it can be seen that the reset signal line Vin1 controlled by the first reset control line Rst1 can be connected to the via hole opened on the interlayer dielectric layer ILD and effectively coupled to the anode of the second light-emitting element L2 through this via hole, so as to increase the access of the reset signal to the anode of the second light-emitting element L2, thereby realizing the reset of the anode of the second light-emitting element L2.

[0135] Take Figures 9 to 22 as an example. Figure 23 A structural layout of a display panel is shown. Referring to Figure 23 it can be seen that in this display panel, not only does the first light-emitting element L1 in the first pixel 02 located in the display area AA include an anode, but also the second light-emitting element L2 in the second pixel 03 located in the first peripheral area B1 (i.e., Figure 23 the Dummy area shown) includes an anode. Thus, it can be determined that both the first pixel 02 located in the display area and the second pixel 03 located in the Dummy area in this display panel can emit light normally.

[0136] Moreover, by setting that the first peripheral area B1 further includes a second pixel circuit 031 and setting the structure of the second pixel circuit 031 to be the same as that of the first pixel circuit 021 included in the display area AA, the same routing design can be adopted for the display area AA and the first peripheral area B1, and further, the manufacturing process uniformity of the display area AA and the first peripheral area B1 can be ensured to be better. In addition, on the premise that the second pixel circuit 031 is not coupled to the anode of the second light-emitting element L2, even if there are deviations in the manufacturing process of the second pixel circuit 031, it will not affect the light-emitting effect of the second light-emitting element L2. For example, it will not cause problems such as poor illumination of the second light-emitting element L2.

[0137] Optionally, in the embodiments of the present disclosure, the multiple second pixels 03 may include at least one first-color pixel, at least one second-color pixel, and at least one third-color pixel. Moreover, the second light-emitting elements L2 in the at least one first-color pixel and the second light-emitting elements L2 in the at least one second-color pixel may be coupled to the same data line D1. That is, one data line D1 can be shared. In this way, the number of pins (which can also be referred to as Pin feet) of the source driver that is coupled to the data line D1 to provide a data signal can be reduced. Furthermore, it is beneficial to the narrow bezel design of the display device.

[0138] Among them, the potential difference between the data signal potential required to drive the first-color pixel to emit light and the data signal potential required to drive the second-color pixel to emit light is less than the difference threshold. That is, the potential difference between the data signals required for the two pixels sharing the same data line D1 to emit light is small and relatively close. In this way, on the premise of reducing the number of pins, the uniformity of the light emission of the second pixels 03 of different colors can be ensured to be good.

[0139] Optionally, in the embodiments of the present disclosure, it may be that the second light-emitting element L2 in each adjacent first-color pixel and the second light-emitting element L2 in a second-color pixel are coupled to the same data line D1. In this way, it is beneficial to wiring, and thus beneficial to the improvement of the display panel resolution.

[0140] Optionally, referring to Figure 24 , in the embodiments of the present disclosure, the multiple second pixels 03 may be arranged in an array, and each row of the second pixels 03 may be arranged in the order of one first-color pixel, one second-color pixel, and one third-color pixel. Among them, the first color may be red R, the second color may be green G, and the third color may be blue B.

[0141] That is, in the embodiments of the present disclosure, among the multiple second pixels 03, the adjacent red R pixels and green G pixels may share the same data line D1. After testing, generally, the potential of the data signal for driving the red R pixel to emit light and the potential of the data signal for driving the green G pixel to emit light are both between 2.8 volts (V) and 7V, and the difference is not large. The potential of the data signal for driving the blue B pixel to emit light is generally between 1.2V and 7V. Thus, as described in the above embodiments, by setting the adjacent red R pixels and green G pixels to share the same data line D1, not only can the wiring be simplified, but also the uniformity of the light emission of the second pixels 03 of different colors can be ensured to be good.

[0142] Taking Figure 24 as an example, Figures 25 to 33 partial layer structure layouts of three adjacent second pixels 03 are respectively shown, and the three adjacent second pixels 03 are a red R pixel, a green G pixel, and a blue B pixel respectively.

[0143] Among them, Figure 25 shows the structural layout of the active layer P1 it includes; Figure 26 shows the structural layout of the active layer P1 and the first gate metal layer Gate1 it includes; Figure 27 shows the structural layout of the active layer P1, the first gate metal layer Gate1 and the second gate metal layer Gate2 it includes; Figure 28 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2 and the interlayer dielectric layer ILD it includes; Figure 29 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD and the first source / drain metal layer SD1 it includes. Figure 30 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD, the first source / drain metal layer SD1 and the planarization layer PLN it includes. Figure 31 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD, the first source / drain metal layer SD1, the planarization layer PLN and the anode of the second light-emitting element L2 it includes. Figure 32 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD, the first source / drain metal layer SD1, the passivation layer PVX and the second source / drain metal layer SD2 it includes. Figure 33 shows the structural layout of the active layer P1, the first gate metal layer Gate1, the second gate metal layer Gate2, the interlayer dielectric layer ILD, the first source / drain metal layer SD1, the passivation layer PVX, the second source / drain metal layer SD2 and the anode of the second light-emitting element L2 it includes.

[0144] That is, Figures 29 to 31 the second pixel circuit 031 shown only includes the first source / drain metal layer SD1, and this first source / drain metal layer SD1 serves as the data line D1 for receiving data signals. Figure 32 and Figure 33 the second pixel circuit 031 shown includes the first source / drain metal layer SD1 and the second source / drain metal layer SD2, and both the first source / drain metal layer SD1 and the second source / drain metal layer SD2 serve as the data line D1. Refer to Figure 29 and Figure 32 It can be seen that for the second pixel 03 including one layer of source / drain metal layer or the second pixel 03 including two layers of source / drain metal layers, adjacent red R pixels and green G pixels can share the same data line D1.

[0145] Optionally, Figure 34It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As Figure 34 shown, the substrate 01 may further have: a second peripheral region B2 at least partially surrounding the first peripheral region B1, and a third peripheral region B3 at least partially surrounding the second peripheral region B2. As Figure 34 shown, it shows that the second peripheral region B2 surrounds the first peripheral region B1, that is, the first peripheral region B1 is surrounded by the second peripheral region B2. And it shows that the third peripheral region B3 surrounds the second peripheral region B2, that is, the second peripheral region B2 is surrounded by the third peripheral region B3. That is, along the direction away from the display area AA, the first peripheral region B1, the second peripheral region B2, and the third peripheral region B3 are arranged in sequence.

[0146] On this basis, the display panel may further include: a gate driving circuit 04 located in the second peripheral region B2. The gate driving circuit 04 may be coupled to the gate line G1 described in the above embodiment and is used to transmit a gate driving signal to the gate line G1. The gate driving circuit 04 may also be referred to as a gate drive on array (GOA) circuit. Correspondingly, the second peripheral region B2 may also be referred to as a GOA circuit region.

[0147] Moreover, the positive projection of the second pole of the first light-emitting element L1 and the second pole of the second light-emitting element L2 on the substrate 01 may cover the display area AA, the first peripheral region B1, the second peripheral region B2, and the third peripheral region B3. Among them, as described in the above embodiment, the second pole may be a cathode, that is, a common electrode. Correspondingly, the third peripheral region B3 may also be a common electrode overlapping region.

[0148] In Figure 34 taking the display panel shown as an example where the display panel only includes one layer of source-drain metal layer, Figure 35 a cross-sectional view of a display panel in the MM' direction is shown. Taking the display panel including two layers of source-drain metal layers as an example, Figure 36 another cross-sectional view of a display panel in the MM' direction is shown. In addition, Figure 37 a cross-sectional view of a first pixel 02 and a second pixel 03 in the MM' direction is also shown.

[0149] Referring to Figures 35 to 37 it can be seen that a light-emitting layer is further included between the anode and the cathode of the first light-emitting element L1 and between the anode and the cathode of the second light-emitting element L2. Figure 35 And Figure 36 the light-emitting layer is represented by red R, green G, and blue B in

[0150] In the display area AA, the first pixel circuit 021, the anode of the first light-emitting element L1, the light-emitting layer of the first light-emitting element L1, the pixel definition layer PDL, and the cathode of the first light-emitting element L1 can be stacked in sequence in a direction away from the substrate 01. Moreover, there is a linking layer (which can also be referred to as an insulating layer) between the first pixel circuit 021 and the anode of the first light-emitting element L1. The linking layer has a via hole, and the first pixel circuit 021 and the anode of the first light-emitting element L1 can be effectively coupled through the via hole. Furthermore, the first pixel circuit 021 can reliably transmit a light-emitting driving signal to the anode of the first light-emitting element L1 to drive the first light-emitting element L1 to emit light.

[0151] In the first peripheral area B1, the data line D1, the anode of the second light-emitting element L2, the light-emitting layer of the second light-emitting element L2, the pixel definition layer PDL, and the cathode of the second light-emitting element L2 can be stacked in sequence in a direction away from the substrate 01. Also, there is a linking layer between the data line D1 and the anode of the second light-emitting element L2. The linking layer has a via hole, and the data line D1 and the anode of the second light-emitting element L2 can be effectively coupled through the via hole. Furthermore, the data line D1 can reliably transmit a data signal to the anode of the second light-emitting element L2 to drive the second light-emitting element L2 to emit light.

[0152] Moreover, the anode of the first light-emitting element L1 and the anode of the second light-emitting element L2 can be located in the same layer, the light-emitting layer of the first light-emitting element L1 and the light-emitting layer of the second light-emitting element L2 can be located in the same layer, and the cathode of the first light-emitting element L1 and the cathode of the second light-emitting element L2 can be located in the same layer and are of an integral structure.

[0153] In addition, when only one layer of source-drain metal layer is included, the first peripheral area B1 and the second peripheral area B2 do not overlap, and the data line D1 to which the first pixel circuit 021 is coupled to the second light-emitting element L2 can be located in the same layer. When two layers of source-drain metal layers are included, the second peripheral area B2 and the first peripheral area B1 can at least partially overlap. For example, referring to Figure 36 , which shows that the second peripheral area B2 coincides with the first peripheral area B1. Correspondingly, the GOA circuit located in the second peripheral area B2 can be located in this overlapping area. And on this basis, the GOA circuit 04 can be located in the same layer as the first pixel circuit 021 and can be stacked in sequence in a direction away from the substrate 01 with the data line D1 to which the second light-emitting element L2 is coupled. Correspondingly, as Figure 36 shown, it can include a linking layer located between the GOA circuit 04 and the data line D1, and another linking layer located between the data line D1 and the anode. That is, compared with the structure with only one layer of source-drain metal layer, an additional film layer can be added to lead out the data line D1. By setting the second peripheral area B2 and the first peripheral area B1 to at least partially overlap or coincide, it is beneficial to the narrow border design of the display device.

[0154] In addition, referring to Figure 37 it can also be seen that pixel support layers PS are both provided on the side of the pixel definition layer PDL of the first light-emitting element L1 away from the substrate 01 and on the side of the pixel definition layer PDL of the second light-emitting element L2 away from the substrate 01. And, referring to Figure 35 and Figure 36 it can also be seen that the display panel provided by the embodiment of the present disclosure may further include: a thin-film encapsulation (TFE) layer, a polarizer, and a cover plate that are sequentially stacked on the side of the cathode away from the substrate 01.

[0155] Among them, the encapsulation layer TFE can be used to encapsulate and protect the structures (such as pixel circuits and light-emitting elements) on the side close to the substrate 01 to prevent water vapor intrusion. The polarizer can be used to perform polarization processing on the outgoing light to improve the contrast of the display panel in a bright environment. The side of the cover plate away from the substrate 01 is the light-emitting side of the display panel. Correspondingly, the cover plate is mostly made of a transparent cover plate that can transmit light, such as a glass cover plate.

[0156] In summary, the embodiment of the present disclosure provides a display panel. The display panel includes: a substrate having a display area and a first peripheral area, a plurality of first pixels located in the display area, and a plurality of second pixels located in the first peripheral area. And, the first light-emitting element in the first pixel can emit light under the drive of the first pixel circuit, and the second light-emitting element in the second pixel can emit light under the drive of the data signal provided by the data line, that is, both the first pixels located in the display area and the second pixels located in the first peripheral area can emit light normally. In this way, the visual effects of the display area and the first peripheral area can be made to have better consistency.

[0157] Figure 38 is a schematic structural diagram of a display device provided by the embodiment of the present disclosure. As Figure 38 shown, the display device includes: a driving circuit 10, and a display panel 00 as shown in any one of Figure 2 to Figure 36 shown.

[0158] Among them, the driving circuit 10 is coupled to the data line D1 ( Figure 38 not shown) in the display panel 00. The driving circuit 10 is used to provide a data signal to the data line D1.

[0159] Figure 39 is a schematic structural diagram of another display device provided by the embodiment of the present disclosure. As Figure 39 shown, the driving circuit 10 includes: a master control sub-circuit 101 and a source driver (Driver Integrated Circuit, Driver IC) 102.

[0160] Among them, the master control sub-circuit 101 is coupled to the source driver 102, and the source driver 102 is coupled to the data line D1. The master control sub-circuit 101 is used to transmit a control signal to the source driver 102, and the source driver 102 is used to transmit a data signal to the data line D1 based on the control signal. That is, the source driver 102 can transmit a data signal to the data line D1 in the display panel 00 under the control of the master control sub-circuit 101.

[0161] Figure 40 It is a schematic structural diagram of another display device provided by an embodiment of the present disclosure. As Figure 40 shown, the master control sub-circuit 101 has a power interface, and the power interface can be externally connected to a power source (such as mains power), and the master control sub-circuit 101 can work reliably based on the electrical energy provided by the external power source. The master control sub-circuit 101 may include: a Flash memory located on a module (MDL) circuit board, a microcontroller unit (MCU), a timing controller (Tcon), a Gamma circuit (Gamma IC, G-IC), and a power (Power) circuit. The source driver Driver IC 102 can be packaged using chip on film (COF) technology. The Driver IC 102 after COF packaging is respectively coupled to the data line D1 in the display panel and the MDL circuit board. In addition, Figure 40 the shown display panel 00 includes a display area AA, a first peripheral area B1, a second peripheral area B2, and a third peripheral area B3.

[0162] Among them, the Flash memory can be coupled to the MCU, and the required Gamma data and some algorithm data required for the operation of the MCU can be stored in the Flash memory for the MCU to call. The Power circuit can be coupled to the MCU and is used to provide the required enable and DC level signals to the MCU to drive the MCU to work properly. The G-IC can be coupled to the Tcon and is used to provide Gamma data to the Tcon. The Gamma data mainly includes a gray scale / brightness curve, that is, it defines the correspondence between the gray scale and the brightness. The MCU can also be coupled to the Tcon. The Tcon can also be coupled to the Driver IC 102. The Tcon can, under the control of the MCU, further control the Driver IC 102 to transmit a data signal to the data line D1 based on the Gamma data provided by the G-IC.

[0163] It should be noted that the data signals transmitted by the Driver IC 102 to the first pixel 02 located in the display area AA are generally different from the data signals transmitted to the second pixel 03 located in the first peripheral area B1.

[0164] Among them, for the first pixel 02 located in the display area AA, the data signal transmitted by the Driver IC 102 is generally data generated based on the required display screen, and the required display screen can be generated by the MCU. Correspondingly, the display area AA can display the screen normally, that is, display the image.

[0165] For the second pixel 03 located in the first peripheral area B1, the data signal transmitted by the Driver IC 102 can be optimally configured according to the light-emitting material in the second pixel 03 and / or the display substrate to which it belongs. The data signals transmitted by the Driver IC 102 to the second pixel 03 in different display substrates are different. Based on this, it can be known that a lookup table can also be used in the Flash memory to store the potential of the data signal to be transmitted to the second pixel 03, and the MCU can directly call and drive the Tcon to control the Driver IC 102 to transmit this data signal to the second pixel 03. For the red second pixel 03, the green second pixel 03, and the blue second pixel 03, the Driver IC 102 can transmit data signals with different potentials to them, so that the second pixel 03 of different colors can display white light, yellow light, green light, or light generated by mixing red, green, and blue. It can also be determined from this that the second pixel 03 is generally used for simple color mixing illumination rather than for displaying images.

[0166] Optionally, the display device can be: an OLED device, an active-matrix organic light-emitting diode (AMOLED) display device, a liquid crystal display (LCD) device, a sub-millimeter mini-LED display device, a micro Micro-LED display device, a mobile phone, a tablet computer, a television, a monitor, or any product or component with a display function.

[0167] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning understood by those of ordinary skill in the field to which the present disclosure belongs.

[0168] For example, the "first", "second", or "third" and similar words used in the specification and claims of the present patent application do not indicate any order, quantity, or importance, but are only used to distinguish different components.

[0169] Similarly, words such as "a" or "one" do not indicate a quantity limitation, but indicate the existence of at least one.

[0170] Words such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, without excluding other elements or objects.

[0171] Terms such as "upper", "lower", "left" or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationships may also change accordingly. "Connection" or "coupling" means electrical connection.

[0172] "And / or" indicates three possible relationships. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0173] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate (01) having a display area (AA) and a first peripheral area (B1) at least partially surrounding the display area (AA); a plurality of first pixels (02) located in the display area (AA), the first pixels (02) including a first pixel circuit (021) and a first light-emitting element (L1), the first pixel circuit (021) being respectively coupled to a data line (D1) and a first pole of the first light-emitting element (L1), a second pole of the first light-emitting element (L1) being coupled to a first power supply line (V1), the first pixel circuit (021) being configured to transmit a light-emitting driving signal to the first pole of the first light-emitting element (L1) based on a data signal provided by the data line (D1), and the first light-emitting element (L1) being configured to emit light based on the light-emitting driving signal and a first power supply signal provided by the first power supply line (V1); and a plurality of second pixels (03) located in the first peripheral area (B1), the second pixels (03) including a second light-emitting element (L2), a first pole of the second light-emitting element (L2) being coupled to the data line (D1), a second pole of the second light-emitting element (L2) being coupled to the first power supply line (V1), and the second light-emitting element (L2) being configured to emit light based on the data signal and the first power supply signal.

2. The display panel according to claim 1, wherein The plurality of second pixels (03) include at least one first-color pixel, at least one second-color pixel, and at least one third-color pixel; the second light-emitting element (L2) in the at least one first-color pixel and the second light-emitting element (L2) in the at least one second-color pixel are coupled to the same data line (D1); wherein a difference between a potential of the data signal required to drive the first-color pixel to emit light and a potential of the data signal required to drive the second-color pixel to emit light is less than a difference threshold.

3. The display panel according to claim 2, wherein The second light-emitting element (L2) in each adjacent first-color pixel and the second light-emitting element (L2) in a second-color pixel are coupled to the same data line (D1).

4. The display panel according to claim 2, wherein The plurality of second pixels (03) are arranged in an array, and each row of the second pixels (03) is arranged in an order of one first-color pixel, one second-color pixel, and one third-color pixel.

5. The display panel according to any one of claims 2 to 4, characterized in that, The first color is red (R), the second color is green (G), and the third color is blue (B).

6. The display panel according to any one of claims 1 to 4, characterized in that The second pixel (03) further includes: a second pixel circuit (031); the second pixel circuit (031) is respectively coupled to a first reset control line (Rst1), a reset signal line (Vin1), and a first pole of the second light-emitting element (L2), and the second pixel circuit (031) is configured to transmit a reset signal provided by the reset signal line (Vin1) to the first pole of the second light-emitting element (L2) in response to a first reset control signal provided by the first reset control line (Rst1) to reset the first pole of the second light-emitting element (L2).

7. The display panel according to claim 6, wherein The second pixel circuit (031) and the first pixel circuit (021) are also respectively coupled to a gate line (G1), a light emission control line (EM1), a second reset control line (Rst2), and a second power supply line (V2); the first pixel circuit (021) is also respectively coupled to the first reset control line (Rst1) and the reset signal line (Vin1); the second pixel circuit (031) is also coupled to the data line (D1); Wherein, the first pixel circuit (021) is configured to transmit the light emission driving signal to a first pole of the first light emitting element (L1) based on the data signal, the first reset control signal, the reset signal, the gate driving signal provided by the gate line (G1), the light emission control signal provided by the light emission control line (EM1), the second power supply signal provided by the second power supply line (V2), and the second reset control signal provided by the second reset control line (Rst2).

8. The display panel according to claim 7, characterized in that, The structure of the second pixel circuit (031) is the same as that of the first pixel circuit (021).

9. The display panel according to claim 8, wherein The plurality of first pixels (02) include: at least one red (R) pixel, at least one green (G) pixel, and at least one blue (B) pixel, and the first pixel circuit (021) includes: a driving transistor; Wherein, among the plurality of first pixels (02), the channel width-to-length ratio of the driving transistor in the first pixel circuit (021) included in the blue (B) pixel is greater than the channel width-to-length ratio of the driving transistor in the first pixel circuit (021) included in the red (R) pixel, and is greater than the channel width-to-length ratio of the driving transistor in the first pixel circuit (021) included in the green (G) pixel.

10. The display panel according to claim 7, characterized in that, The substrate (01) further has: a second peripheral region (B2) at least partially surrounding the first peripheral region (B1), and a third peripheral region (B3) at least partially surrounding the second peripheral region (B2); The display panel further includes: A gate driving circuit (04) located in the second peripheral region (B2), the gate driving circuit (04) being coupled to the gate line (G1) and configured to transmit the gate driving signal to the gate line (G1); The positive projection on the substrate (01) of the second poles of the first light emitting element (L1) and the second light emitting element (L2) covers the display area (AA), the first peripheral region (B1), the second peripheral region (B2), and the third peripheral region (B3).

11. The display panel according to claim 10, wherein The first pixel circuit (021) and the second pixel circuit (031) both include: an active layer (P1), a first gate metal layer (Gate1), a second gate metal layer (Gate2), an interlayer dielectric layer (ILD), a first source-drain metal layer (SD1), and an insulating layer (J1) stacked in sequence in a direction away from the substrate (01); The first pole of the first light-emitting element (L1) is located on the side of the insulating layer (J1) included in the first pixel circuit (021) that is away from the substrate (01); the first pole of the second light-emitting element (L2) is located on the side of the insulating layer (J1) included in the second pixel circuit (031) that is away from the substrate (01). The display panel further includes: a pixel definition layer (PDL) and a pixel support layer (PS) that are located on the side of the first pole of the first light-emitting element (L1) away from the substrate (01) and on the side of the first pole of the second light-emitting element (L2) away from the substrate (01), and are stacked in sequence along the direction away from the substrate (01). The second poles of the first light-emitting element (L1) and the second light-emitting element (L2) are both located on the side of the pixel support layer (PS) away from the substrate (01).

12. The display panel according to claim 11, wherein The insulating layer (J1) includes: a passivation layer (PVX) and a planarization layer (PLN) that are stacked in sequence along the direction away from the substrate (01). The first pixel circuit (021) further includes: a second source-drain metal layer (SD2) that is located between the passivation layer (PVX) and the planarization layer (PLN). The second peripheral region (B2) at least partially overlaps with the first peripheral region (B1).

13. The display panel according to claim 12, wherein, The second peripheral region (B2) coincides with the first peripheral region (B1). The gate driving circuit (04) is on the same layer as the first pixel circuit (021), and the data line (D1) coupled to the second light-emitting element (L2) is stacked in sequence along the direction away from the substrate (01).

14. A display device, characterized in that, The display device includes: a display panel (00) according to any one of claims 1 to 13, and a driving circuit (10). The driving circuit (10) is coupled to the data line (D1) in the display panel (00), and the driving circuit (10) is configured to provide a data signal to the data line (D1).

15. The display device according to claim 14, wherein The driving circuit (10) includes: a master control sub-circuit (101) and a source driver (102). The master control sub-circuit (101) is coupled to the source driver (102), and the master control sub-circuit (101) is configured to transmit a control signal to the source driver (102). The source driver (102) is coupled to the data line (D1), and the source driver (102) is configured to transmit a data signal to the data line (D1) based on the control signal.

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