Design method of semiconductor integrated circuit device, semiconductor integrated circuit device, and computer-readable recording medium

Abstract

In a design method of a semiconductor integrated circuit device, a plurality of macros are arranged in a circuit arrangement region of the semiconductor integrated circuit device in which a plurality of power switch circuits are arranged according to a first rule. A narrow region having a width smaller than a first value is detected from a first region in the circuit arrangement region where no macro is arranged. In the detected narrow region, a power switch circuit is arranged according to a second rule different from the first rule, and in the first region other than the narrow region, a power switch circuit is arranged according to the first rule.

Description

Technical Field

[0001] The present invention relates to a design method of a semiconductor integrated circuit device, a semiconductor integrated circuit device, and a program. Background Art

[0002] One of the techniques for achieving low power consumption of a semiconductor integrated circuit device is a power cut-off technique. The so-called power cut-off technique is a technique of dividing the inside of a semiconductor integrated circuit device into a plurality of power domains (circuit blocks) and suppressing leakage current that causes power consumption by cutting off the power supply of an inoperative power domain. In the power cut-off technique, a power switch circuit that switches the connection / cut-off of a global power wiring provided for the entire circuit disposed on a chip and a local power wiring provided for the circuit of the power domain is used.

[0003] In Patent Document 1, as Figure 9A shown, a structure in which a plurality of power switch circuits (PSW) 902 for power control are arranged in a stepped manner in a power domain of a semiconductor integrated circuit device 901 is disclosed. A plurality of power switch circuits 902 are arranged at a constant interval in the horizontal direction and at positions shifted from the columns of adjacent power switch circuits 902 in the vertical direction.

[0004] When a plurality of power switch circuits 902 are arranged in a regular arrangement pattern as Figure 9A shown, there are the following problems: If a macro (functional circuit) that implements a specified function is arranged in a semiconductor integrated circuit device, due to the arrangement of the macro, the power switch circuits sometimes cannot be arranged in the same arrangement pattern. For example, as Figure 9A shown, if a macro 903 is arranged in a semiconductor integrated circuit device 901, the power switch circuit 902A whose arrangement position does not overlap with the macro 903 can be arranged according to the specified arrangement pattern, but the power switch circuit 902B whose arrangement position overlaps with the macro 903 cannot be arranged. If the power switch circuit 902B is not arranged, the power supply voltage fluctuation (IR - Drop) during operation in this circuit region becomes large and cannot satisfy the constraints (criteria), or the power supply to this circuit region cannot be performed. The occurrence of violations of such power supply voltage fluctuations (IR - Drop) (violations of criteria) causes rework in the design process of the semiconductor integrated circuit device.

[0005] As a method of avoiding this problem, it is considered to arrange the power switch circuits 902 by shifting the arrangement positions of the power switch circuits 902 that are not arranged while following the specified arrangement pattern, as Figure 9B shown. In Figure 9BIn this case, within the portion surrounded by the dashed line, the power switch circuit 902 is slid and configured such that the configured position does not overlap with the macro 903. In this way, it may be possible to suppress the power supply voltage variation (IR - Drop) during operation and meet the constraints (criteria). However, the power switch circuit 902, the corresponding global power supply wiring 911, and the local power supply wiring 912 are provided in the narrow area between the macros 903. As a result, the available standard cell area becomes smaller, and in addition, the available wiring resources for signal wiring input / output and passing through in the standard cells and macros become smaller. The reduction in the available standard cell area and wiring resources increases the possibility of rework in the design process of the semiconductor integrated circuit device.

[0006] Patent Document 1: International Publication No. WO2017 / 208888. Summary of the Invention

[0007] An object of the present invention is to provide a design method for a semiconductor integrated circuit device capable of appropriately arranging a power switch circuit.

[0008] In one aspect of the design method of a semiconductor integrated circuit device, a plurality of macros are arranged within the circuit configuration area of the semiconductor integrated circuit device in which a plurality of power switch circuits are arranged according to a first rule. A narrow area having a width less than a first value is detected from a first area within the circuit configuration area where no macro is arranged. A power switch circuit is arranged in the detected narrow area according to a second rule different from the first rule, and a power switch circuit is arranged in the first area other than the narrow area according to the first rule.

[0009] The disclosed design method of a semiconductor integrated circuit device can appropriately arrange a power switch circuit. Brief Description of the Drawings

[0010] Figure 1 It is a diagram for explaining the outline of the design method of the semiconductor integrated circuit device in the present embodiment.

[0011] Figure 2 It is a flowchart showing an example of the detection process of the narrow area in the present embodiment.

[0012] Figure 3A It is a diagram for explaining the division of the circuit configuration area.

[0013] Figure 3B It is a diagram showing an example of the determination criterion of the narrow area.

[0014] Figure 4A It is a flowchart showing an example of the arrangement process of the power switch circuit in the first embodiment.

[0015] Figure 4BIt is a flowchart showing an example of the configuration process of the power switch circuit in the first embodiment.

[0016] Figure 5A It is a flowchart showing an example of the configuration process of the power switch circuit in the second embodiment.

[0017] Figure 5B It is a flowchart showing an example of the configuration process of the power switch circuit in the second embodiment.

[0018] Figure 6A It is a diagram showing an example of the configuration pattern in this embodiment.

[0019] Figure 6B It is a diagram showing an example of the configuration pattern in this embodiment.

[0020] Figure 6C It is a diagram showing an example of the configuration pattern in this embodiment.

[0021] Figure 7 It is a diagram explaining an example of the semiconductor integrated circuit device in this embodiment.

[0022] Figure 8 It is a diagram showing a structural example of a computer capable of implementing the design method of the semiconductor integrated circuit device in this embodiment.

[0023] Figure 9A It is a diagram explaining an example of the configuration of the power switch circuit in the semiconductor integrated circuit device.

[0024] Figure 9B It is a diagram explaining another example of the configuration of the power switch circuit in the semiconductor integrated circuit device. Detailed Embodiment

[0025] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings.

[0026] In the semiconductor integrated circuit device to be designed in the embodiments described below, it is a semiconductor integrated circuit device having a power domain that controls power supply. In the power domain, a power switch circuit (PSW) is provided that controls the connection state of the global power wiring provided for the entire circuit configured on the chip and the local power wiring provided for the circuit in the power domain, and is configured to be able to switch whether to electrically connect the global power wiring and the local power wiring through a control signal. The power supplied from the global power wiring is supplied to the circuit in the power domain via the local power wiring connected through the power switch circuit.

[0027] The global power wiring, local power wiring, and power switch circuit can be provided on the power potential side or the ground potential side. In the following, an example will be described in which a global power wiring supplying a power potential and a local power wiring supplying a power potential are provided, and a power switch circuit is provided between the global power wiring supplying a power potential and the local power wiring supplying a power potential.

[0028] (First Embodiment)

[0029] The first embodiment of the present invention will be described.

[0030] Figure 1 This is a diagram showing an outline of a design method for a semiconductor integrated circuit device in the present embodiment. The design method for the semiconductor integrated circuit device in the present embodiment can be implemented by a computer (design device), for example, and each process of the design method for the semiconductor integrated circuit device in the present embodiment is executed by its processor (CPU or the like).

[0031] In step S101, the processor configures macros (functional circuits) in the circuit configuration area of the semiconductor integrated circuit device based on logic circuit information read from an external storage device or the like and design data including a netlist. A macro is a circuit block that has been designed to implement a specified function, and is, for example, a memory macro or the like.

[0032] Next, in step S102, the processor detects a narrow area in the circuit configuration area after the macros are configured. Here, the so-called narrow area is, for example, an area within the circuit configuration area where no macros are configured (standard cell configuration area), and the distance between macros or the distance between a macro and the outer edge of the circuit configuration area is less than a specified value.

[0033] Then, in steps S103 and S104, the processor configures a power switch circuit (PSW) in the area within the circuit configuration area where no macros are configured (standard cell configuration area) and performs wiring related to power supply (power wiring). In step S103, the processor configures the power switch circuit and performs power wiring in the area other than the narrow area detected in step S102 according to a first rule. The configuration pattern under the first rule is, for example, Figure 9A the stepped configuration pattern as shown. In step S104, the processor configures the power switch circuit and performs power wiring in the narrow area detected in step S102 according to a second rule different from the first rule. In addition, the execution order of steps S103 and S104 can also be different, and after the power switch circuit is configured and power wiring is performed in the narrow area, the power switch circuit is configured and power wiring is performed in the area other than the narrow area.

[0034] Next, in step S105, the processor configures circuit units (standard cells, etc.) in the standard cell configuration area within the circuit configuration area based on the design data, and performs wiring such as signal wiring.

[0035] Next, in step S106, the processor analyzes the power supply voltage variation (IR - Drop) during the operation of the semiconductor integrated circuit device in which macros and circuit units are configured within the circuit configuration area based on the design data and power supply wiring and signal wiring are performed. For the analysis process of the power supply voltage variation (IR - Drop) during the operation of the semiconductor integrated circuit device, a well-known technique can be used to execute.

[0036] Next, in step S107, the processor performs configuration of the power switch circuit, correction of the power supply wiring, etc. according to the analysis result of the power supply voltage variation (IR - Drop) performed in step S106, etc. For example, when a violation of the constraint (violation of the criterion) occurs in the analysis of the power supply voltage variation (IR - Drop) in step S106, the processor configures the power switch circuit and corrects the power supply wiring so as to eliminate the violation of the constraint (violation of the criterion).

[0037] Figure 2 represents Figure 1 The flowchart showing an example of the detection process of the narrow area in step S102 shown.

[0038] In the detection process of the narrow area, first, in step S201, the processor horizontally divides the area (standard cell configuration area) in which no macros are configured within the circuit configuration area. Here, the horizontal direction refers to the direction perpendicular to the extending direction of the power supply wiring. As Figure 3A shown in an example, the processor divides the standard cell configuration area within the circuit configuration area 301 into divided areas with opposing sides that are rectangles with the right or left side of the macro 302, or the right or left side of the outer edge portion of the circuit configuration area 301. In Figure 3A the example shown, the processor divides it into eight divided areas Z1 to Z8.

[0039] Next, in step S202, the processor determines whether there is a user - specified user - instruction value as the threshold value used in the detection of the narrow area. When the processor determines that there is a user - instruction value (in step S202, "No"), it proceeds to step S203, and when it determines that there is no user - instruction value (in step S202, "Yes"), it proceeds to step S204.

[0040] In step S203, the processor sets the width x of the narrow area determination criterion used for determining whether it is a narrow area to a user-specified user instruction value, and proceeds to step S205.

[0041] In step S204, the processor sets the width x of the narrow area determination criterion to a specified value, and proceeds to step S205. This specified value is a value specified in consideration of the spacing (arrangement interval) of the power switch circuits when arranging the power switch circuits according to the first rule. For example, as Figure 3B shown in an example, the specified value is the width 313 obtained by adding the width of one power switch circuit 312 and twice the length of the spacing of the power switch circuit 312. Here, the spacing is the interval between corresponding parts of adjacent power switch circuits. For example, it is the horizontal interval between the left sides of adjacent power switch circuits. In Figure 3B it, 311 is a macro (functional circuit).

[0042] The following repeated processing of steps S205 to S208 is performed for each divided area divided in step S201. In step S205, the processor selects an unprocessed divided area from the divided areas divided in step S201.

[0043] Next, in step S206, the processor determines whether the width of the target divided area is less than the width x of the narrow area determination criterion. When the processor determines that the width of the target divided area is less than the width of the determination criterion (Yes in step S206), it proceeds to step S207. When it determines that the width of the target divided area is not less than the width of the determination criterion (No in step S206), it proceeds to step S208.

[0044] In step S207, the processor registers the target divided area in the narrow area table, thereby adding the target divided area to the narrow areas, and proceeds to step S208.

[0045] In step S208, when there is an unprocessed divided area in the divided areas divided in step S201, the processor returns to step S205. When there is no unprocessed divided area, that is, when the processing of all divided areas is completed, the narrow area detection process ends.

[0046] In addition, in the detection process of the above-mentioned narrow area, the standard cell configuration area is arranged within the horizontal division circuit configuration area, but it can also be divided vertically (in the same direction as the direction in which the power supply wiring extends). In this case, the processor divides the standard cell configuration area within the circuit configuration area 301 into divided areas with opposite sides that are rectangles with the upper or lower side of the macro 302 or the upper or lower side of the outer edge portion of the circuit configuration area 301 as the sides, and performs the same processing as the above-mentioned processing.

[0047] Next, with reference to Figure 4A and Figure 4B , the configuration process of the power switch circuit in the first embodiment will be described. Figure 4A and Figure 4B The processing shown corresponds to the processing of steps S102 to S104 in Figure 1 . In the first embodiment, the power switch circuits are arranged in the same arrangement pattern for all the narrow areas within the circuit configuration area. Figure 4A and Figure 4B are flowcharts showing examples of the configuration process of the power switch circuit in the first embodiment.

[0048] In step S401, the processor detects a narrow area in the circuit configuration area of the semiconductor integrated circuit device in which a macro (functional circuit) is arranged. For example, as shown in Figure 2 .

[0049] In step S402, the processor refers to the narrow area table and arranges the power switch circuits in accordance with the first rule for the areas other than the narrow areas in the area (standard cell configuration area) within the circuit configuration area where no macro is arranged. The arrangement pattern of the power switch circuit in the first rule is, for example, the arrangement pattern arranged in a stepped shape as shown in Figure 9A .

[0050] In addition, through the repeated processing of steps S403 to S405, the processor arranges the power switch circuits for each narrow area in the area (standard cell configuration area) within the circuit configuration area where no macro is arranged. In step S403, the processor refers to the narrow area table and selects one narrow area in which the power switch circuit has not been arranged from within the narrow areas.

[0051] Next, in step S404, the processor arranges the power switch circuit in the target narrow area with the initial arrangement pattern. The initial arrangement pattern of this power switch circuit is an arrangement pattern under a rule different from the arrangement pattern of the power switch circuit under the first rule.

[0052] Next, in step S405, when there is a narrow area in the narrow area table where the power switch circuit has not been configured, the processor returns to step S403. When there is no narrow area where the power switch circuit has not been configured, that is, when the power switch circuit has been configured in all the narrow areas of the narrow area table with the initial configuration pattern, the processor proceeds to step S406.

[0053] In addition, the order of configuring the power switch circuit for the area outside the narrow area and the power switch circuit for the narrow area, which is performed in steps S402 to S405, is arbitrary. It is also possible to configure the power switch circuit for the area outside the narrow area after configuring the power switch circuit for the narrow area.

[0054] In step S406, the processor performs power wiring related to the power switch circuit configured as described above. The processor performs global power wiring and local power wiring that are connected to the power switch circuit to supply the power potential, and power wiring to supply the ground potential, etc.

[0055] In step S407, the processor briefly configures and wires circuit units (standard cells, etc.) and signal wiring in the standard cell configuration area within the circuit configuration area.

[0056] Next, in step S408, the processor performs a detection process for wiring congestion to evaluate the margin of wiring in the standard cell configuration area within the circuit configuration area that has been configured and wired as described above. In the detection process for wiring congestion, when there is more wiring than the amount corresponding to the size of the area being the object of the detection process, it is considered wiring congestion. The wiring amount corresponding to the size of the area is determined in advance. For the detection process for wiring congestion, a known technique can be used to execute. After performing the detection process for wiring congestion, the processor proceeds to Figure 4B step S409 shown.

[0057] In step S409, the processor determines whether there is wiring congestion in the narrow areas within the circuit configuration area. When the processor determines that there is no wiring congestion in all the narrow areas within the circuit configuration area (in step S409, "No"), it proceeds to step S411. When the processor determines that there is wiring congestion in at least one narrow area within the circuit configuration area (in step S409, "Yes"), it proceeds to step S431.

[0058] When it is determined that there is no wiring congestion in all the narrow areas, the processor, through the repeated processing of steps S411 to S414, changes the configuration pattern of each narrow area to a configuration pattern that has a stronger ability to cope with IR - Drop (power supply voltage fluctuation) compared to the current configuration pattern, and configures the power switch circuit. That is, the processor determines whether there is a configuration pattern that has a stronger ability to cope with IR - Drop compared to the current configuration pattern (S412). When the processor determines that there is a configuration pattern with a stronger ability to cope with IR - Drop (in step S412, "Yes"), it configures the power switch circuit in the narrow area with a configuration pattern that has a stronger ability to cope with IR - Drop (further suppressing the power supply voltage fluctuation and making it smaller) (S413). On the other hand, when the processor determines that there is no configuration pattern with a stronger ability to cope with IR - Drop (in step S412, "No"), it ends the repeated processing of steps S411 to S414. A configuration pattern with a stronger ability to cope with IR - Drop is, for example, a configuration pattern in which the number of power switch circuits configured in the area is increased.

[0059] Here, referring to Figure 6A and Figure 6B , an example of the process of changing the configuration pattern to a configuration pattern with a stronger ability to cope with IR - Drop (smaller power supply voltage fluctuation) will be described. Figure 6A shows the original configuration pattern, Figure 6B shows an example of a configuration pattern with a stronger ability to cope with IR - Drop than Figure 6A . In Figure 6A and Figure 6B , 611 and 621 are power switch circuits, 612 and 622 are local power supply wirings, and 613 and 623 are global power supply wirings. In addition, 631 and 632 are macros (such as memory macros).

[0060] In Figure 6A the original configuration pattern shown, in area 601 which is not a narrow area, the power switch circuit 611 is configured in a stepped shape according to the first rule. In addition, in the narrow area 602, the power switch circuit 621 is configured in a column (624A) along one macro 631 according to a rule different from the first rule. The local power supply wiring 612 and the global power supply wiring 613 are connected to the power switch circuit 611, and the local power supply wiring 622 and the global power supply wiring 623 are connected to the power switch circuit 621.

[0061] As Figure 6A shown, the local power supply wiring 612 connected to the power switch circuit 611 configured in area 601 is wired as long as it can be wired, and the global power supply wiring 613 connected to the power switch circuit 611 is only wired in area 601. Therefore, in Figure 6AIn the shown configuration pattern, the local power supply wiring 612A connected to the power switch circuit 611 is wired not only in the area 601 but also in the narrow area 602. On the other hand, the global power supply wiring 613A connected to the power switch circuit 611 can be wired in the narrow area 602 but is only wired in the area 601. In this way, by not wiring the global power supply wiring 613 connected to the power switch circuit 611 in the narrow area 602, the wiring resources are ensured.

[0062] In Figure 6B the shown configuration pattern, in the area 601 which is not a narrow area, the power switch circuit 611 is connected to Figure 6A the shown configuration pattern, similarly, it is configured in a stepped shape according to the first rule. In addition, in the narrow area 602, the power switch circuit 621 is configured in two columns (624A, 624B) along the macros 631 and 632 respectively according to a rule different from the first rule. Similar to Figure 6A the shown configuration pattern, a local power supply wiring 612 and a global power supply wiring 613 are connected to the power switch circuit 611, and a local power supply wiring 622 and a global power supply wiring 623 are connected to the power switch circuit 621.

[0063] In addition, in Figure 6B the shown configuration pattern, similar to Figure 6A the shown configuration pattern, the local power supply wiring 612 connected to the power switch circuit 611 configured in the area 601 is wired as long as it can be wired, and the global power supply wiring 613 connected to the power switch circuit 611 is only wired in the area 601. Therefore, in Figure 6B the shown configuration pattern, the local power supply wiring 612A connected to the power switch circuit 611 is wired not only in the area 601 but also in the narrow area 602. On the other hand, the global power supply wiring 613A connected to the power switch circuit 611 can be wired in the narrow area 602 but is only wired in the area 601.

[0064] In this way, in the narrow area 602, by configuring two columns of power switch circuits 621, compared with Figure 6A the shown configuration pattern, the IR - Drop (power supply voltage fluctuation) can be suppressed to become smaller. On the other hand, since power supply wirings are configured for the two columns of power switch circuits 621, the wiring resources are reduced.

[0065] Return to Figure 4BIn the process shown, after changing the configuration pattern in the narrow area through the repeated processes of steps S411 to S414, the processor performs power supply wiring (S415), briefly configures and routes circuit units (such as standard cells) and signal wiring, etc. (S416), and performs a detection process for wiring congestion (S417), in the same way as steps S406 to S408 described above.

[0066] Next, in step S418, the processor determines whether there is wiring congestion in the narrow area. When the processor determines that there is no wiring congestion in all the narrow areas (in step S418, "No"), it returns to step S411 and performs a process of changing the configuration pattern in the narrow area to a configuration pattern with stronger IR - Drop resistance.

[0067] When it is determined in step S418 that there is wiring congestion in at least one narrow area (Yes), the processor proceeds to step S419 and determines and fixes the configuration pattern in the narrow area through the repeated processes of steps S419 to S422. In the narrow area, the processor changes the configuration pattern to the one before the configuration pattern that caused wiring congestion in step S418, that is, a configuration pattern with greater wiring resources compared to the configuration pattern that caused wiring congestion (S420), and fixes the configuration pattern of the target narrow area (S421). Then, the configuration process of the power switch circuit ends.

[0068] When it is determined in step S409 that there is wiring congestion in at least one narrow area, the processor configures the power switch circuit for each narrow area by changing to a configuration pattern with greater wiring resources compared to the current configuration pattern through the repeated processes of steps S431 to S434. That is, the processor determines whether there is a configuration pattern with greater wiring resources compared to the current configuration pattern (S432). When the processor determines that there is a configuration pattern with greater wiring resources (in step S432, "Yes"), it configures the power switch circuit in the narrow area with the configuration pattern having greater wiring resources (S433). On the other hand, when the processor determines that there is no configuration pattern with greater wiring resources (in step S432, "No"), it ends the repeated processes of steps S431 to S434.

[0069] Here, with reference to Figure 6A and Figure 6C , an example of the process of changing the configuration pattern to a configuration pattern with greater wiring resources will be described. Figure 6A shows the original configuration pattern, Figure 6C shows an example of a configuration pattern with greater wiring resources than Figure 6A . For Figure 6A , it has been described, so the description here is omitted. In Figure 6CAmong them, 611 and 621 are power switch circuits, 612 and 622 are local power wirings, and 613 and 623 are global power wirings. Additionally, 631 and 632 are macros (such as memory macros).

[0070] In Figure 6C In the configuration pattern shown, in area 601 which is not a narrow area, power switch circuit 611 and Figure 6A Similar to the configuration pattern shown, it is configured in a stepped shape according to the first rule. Additionally, in narrow area 602, power switch circuit 621 and Figure 6A Similar to the configuration pattern shown, it is configured in a column (624A) along one macro 631 according to a rule different from the first rule. Local power wiring 612 and global power wiring 613 are connected to power switch circuit 611, and local power wiring 622 and global power wiring 623 are connected to power switch circuit 621.

[0071] In Figure 6C In the configuration pattern shown, local power wiring 612 and global power wiring 613 connected to power switch circuit 611 configured in area 601 are only wired in area 601. Therefore, in Figure 6C In the configuration pattern shown, local power wiring 612B and global power wiring 613A connected to power switch circuit 611 can also be wired in narrow area 602, but are only wired in area 601. In this way, by not wiring local power wiring 612 and global power wiring 613 connected to power switch circuit 611 in narrow area 602, wiring resources larger than those in Figure 6A the configuration pattern shown are ensured.

[0072] Returning to Figure 4B the process shown, after changing the configuration pattern in the narrow area through the repeated processes of steps S431 to S434, the processor performs power wiring (S435) in the same way as steps S406 to S408 above, performs brief configuration and wiring of circuit units (standard units, etc.), signal wiring, etc. (S436), and performs a detection process for wiring congestion (S437).

[0073] Next, in step S438, the processor determines whether there is wiring congestion in the narrow area. When the processor determines that there is wiring congestion in at least one narrow area (in step S438, "Yes"), it returns to step S431 and performs a process of changing the configuration pattern in the narrow area to a configuration pattern with larger wiring resources.

[0074] When it is determined in step S438 that there is no wiring congestion in all the narrow areas (No), the processor proceeds to step S439, and through the repeated processing of steps S439 to S441, determines and fixes the configuration pattern in the narrow areas. The processor fixes the configuration pattern when it is determined that there is no wiring congestion in all the narrow areas as the configuration pattern of the target narrow area (S440). Then, the configuration process of the power switch circuit ends.

[0075] In addition, in the above-described embodiment, after creating a narrow area table through the narrow area detection process and listing all the narrow areas, the initial configuration of the power switch circuit and the process of changing the configuration pattern are executed. However, it is not limited to this, and the listing of narrow areas may not be performed, and the configuration of the power switch circuit and the process of changing the pattern may be executed sequentially at the stage of detecting each narrow area.

[0076] As described above, in the first embodiment, when there is no wiring congestion in the narrow areas with the initial configuration pattern, the processor explores a configuration pattern with stronger IR - Drop resistance (smaller power supply voltage variation) within the range where no wiring congestion occurs. The processor updates to a configuration pattern with stronger IR - Drop resistance until wiring congestion occurs in the narrow areas. When wiring congestion occurs, it changes to the previous configuration pattern with a larger wiring resource and fixes the configuration pattern of the narrow area. When there is no candidate configuration pattern to be updated, it fixes with the current configuration pattern.

[0077] On the other hand, when there is wiring congestion in the narrow areas with the initial configuration pattern, the processor explores a configuration pattern with a larger wiring resource. In the narrow areas, the processor updates to a configuration pattern with a larger wiring resource and fixes the configuration pattern that reduces the degree of wiring congestion as the configuration pattern of the narrow area. When there is no candidate configuration pattern to be updated, it fixes with the current configuration pattern.

[0078] In this way, according to the first embodiment, it is possible to appropriately configure the power switch circuit in consideration of the constraints (criteria) of power supply voltage variation (IR - Drop) and wiring resources. By performing the configuration considering the constraints (criteria) of power supply voltage variation (IR - Drop) and wiring resources, it is possible to suppress the occurrence of rework operations in the design process of the semiconductor integrated circuit device.

[0079] (Second Embodiment)

[0080] Next, a second embodiment of the present invention will be described.

[0081] In the above-described first embodiment, the power switch circuits are arranged in the same arrangement pattern in all the narrow areas within the circuit arrangement area of the semiconductor integrated circuit device. In the second embodiment described below, the arrangement pattern of the power switch circuit is determined independently for each narrow area, and the power switch circuits are arranged in each narrow area in an arrangement pattern that does not depend on the arrangement patterns of other narrow areas. In the second embodiment, the power switch circuits can be arranged in each narrow area within the circuit arrangement area in an appropriate arrangement pattern.

[0082] Except for the arrangement process of the power switch circuits, it is the same as the above-described first embodiment, and thus the description is omitted. Hereinafter, the arrangement process of the power switch circuits in the second embodiment will be described. Figure 5A And Figure 5B is a flowchart showing an example of the arrangement process of the power switch circuits in the second embodiment.

[0083] In step S501, the processor detects narrow areas in the circuit arrangement area of the semiconductor integrated circuit device in which macros (functional circuits) are arranged. For example, as Figure 2 shown, narrow areas are detected.

[0084] In step S502, the processor refers to the narrow area table and arranges the power switch circuits in the areas other than the narrow areas in the area where no macros are arranged (standard cell arrangement area) within the circuit arrangement area according to the first rule. The arrangement pattern of the power switch circuit in the first rule is, for example, Figure 9A an arrangement pattern arranged in a stepped shape as shown.

[0085] In addition, through the repeated processes of steps S503 to S505, the processor arranges the power switch circuits in each narrow area of the area where no macros are arranged (standard cell arrangement area) within the circuit arrangement area in an initial arrangement pattern. The initial arrangement pattern is an arrangement pattern under a rule different from the arrangement pattern of the power switch circuit in the first rule.

[0086] Furthermore, the order of arranging the power switch circuits in steps S502 to S505 is arbitrary. It is also possible to arrange the power switch circuits in the areas other than the narrow areas after arranging the power switch circuits in the narrow areas.

[0087] After the power switch circuit is configured for the area outside the narrow area and the narrow area, the processor performs power wiring related to the power switch circuit, etc. (S506), briefly configures and routes circuit units (standard cells, etc.), signal wiring, etc. in the standard cell configuration area within the circuit configuration area (S507), and performs detection processing for wiring congestion and estimation of IR-Drop (power supply voltage variation) (S508). For the detection processing of wiring congestion and the estimation processing of power supply voltage variation (IR-Drop), well-known techniques can be used to execute.

[0088] After the detection processing of wiring congestion and the estimation of IR-Drop (power supply voltage variation) are performed, the processor executes the processing of steps S509 to S519 for each narrow area where the configuration pattern is not fixed. In step S509, the processor selects a narrow area to be processed from the narrow areas where the configuration pattern is not fixed.

[0089] Next, in step S510, the processor determines whether there is wiring congestion in the narrow area to be processed and whether there is a state of IR-Drop (power supply voltage variation) that violates the constraints (violates the criteria) in the narrow area and the surrounding macros. When the processor determines that there is wiring congestion in the narrow area to be processed and there is an IR-Drop that violates the constraints in the narrow area and the surrounding macros (in step S510, "yes"), it proceeds to step S511. When it is not the case (in step S510, "no"), it proceeds to step S512.

[0090] In step S511, since there is wiring congestion and there is an IR-Drop that violates the constraints, the processor is insufficient in dealing with the change of the configuration pattern related to the power switch circuit, so it gives an instruction to correct the macro configuration for the narrow area to be processed. After that, the processor proceeds to step S519.

[0091] In step S512, the processor determines whether there is wiring congestion in the narrow area to be processed. When the processor determines that there is wiring congestion in the narrow area to be processed (in step S512, "yes"), it proceeds to step S513. When the processor determines that there is no wiring congestion in the narrow area to be processed (in step S512, "no"), it proceeds to step S515.

[0092] In step S513, the processor determines whether there is a configuration pattern with a larger routing resource than the current configuration pattern. That is, the processor determines whether there is a configuration pattern with a larger routing resource. When the processor determines that there is a configuration pattern with a larger routing resource (Yes in step S513), it proceeds to step S514. On the other hand, when the processor determines that there is no configuration pattern with a larger routing resource (No in step S513), since there is no configuration pattern that can be a change candidate, it proceeds to step S518.

[0093] In step S514, the processor changes the configuration pattern in the narrow area of the processing object to the configuration pattern with a large routing resource, and proceeds to step S519. For an example of the process of changing the configuration pattern to the configuration pattern with a large routing resource, as described in the first embodiment using Figure 6A and Figure 6C as described.

[0094] In step S515, the processor determines whether there is an IR-Drop that violates the constraints in the narrow area of the processing object and the surrounding macros. When the processor determines that there is an IR-Drop that violates the constraints (Yes in step S515), it proceeds to step S516. When the processor determines that there is no IR-Drop that violates the constraints (No in step S515), it proceeds to step S518.

[0095] In step S516, the processor determines whether there is a configuration pattern with a stronger IR-Drop handling ability than the current configuration pattern. That is, the processor determines whether there is a configuration pattern with a stronger IR-Drop handling ability. When the processor determines that there is a configuration pattern with a stronger IR-Drop handling ability (Yes in step S516), it proceeds to step S517. On the other hand, when the processor determines that there is no configuration pattern with a stronger IR-Drop handling ability (No in step S516), since there is no configuration pattern that can be a change candidate, it proceeds to step S518.

[0096] In step S517, the processor changes the configuration pattern in the narrow area of the processing object to the configuration pattern with a strong IR-Drop handling ability, and proceeds to step S519. For an example of the process of changing the configuration pattern to the configuration pattern with a strong IR-Drop handling ability, as described in the first embodiment using Figure 6A and Figure 6B as described.

[0097] In step S518, since there is no configuration pattern that can be a change candidate for the narrow area of the processing object, the processor fixes the configuration pattern of the narrow area of the processing object to the current configuration pattern. Then, the processor proceeds to step S519.

[0098] In step S519, when the processor has an unprocessed narrow area within the narrow area where the configuration pattern is not fixed, it returns to step S509. When there is no unprocessed narrow area, it proceeds to step S520.

[0099] In step S520, the processor determines whether there is an indication to correct the macro configuration. When the processor determines that there is an indication to correct the macro configuration (Yes in step S520), it ends the process and returns to the macro configuration process. When it determines that there is no indication to correct the macro configuration (No in step S520), it proceeds to step S521.

[0100] In step S521, the processor determines whether the configuration pattern has been changed in one of the narrow areas. When the processor determines that the configuration pattern has been changed in one of the narrow areas (Yes in step S521), it returns to step S506 and executes the processes after step S506 again. On the other hand, when the processor determines that the configuration pattern has not been changed in any of the narrow areas (No in step S521), it determines that the configuration pattern has been fixed in all the narrow areas and ends the process.

[0101] In the second embodiment, when the processor confirms either wiring congestion or IR - Drop (power supply voltage variation) that violates the constraints (violates the criteria) in the narrow area, it changes the configuration pattern to improve the situation. When wiring congestion occurs in the narrow area, it changes the configuration pattern to a pattern with more wiring resources. When there is IR - Drop that violates the constraints, it changes the configuration pattern to a pattern with stronger IR - Drop handling ability. When there is no candidate configuration pattern for change, it fixes with the current configuration pattern. In addition, when the processor confirms both wiring congestion and IR - Drop that violates the constraints in the narrow area, since the change of the configuration pattern alone is insufficient, it gives an indication to correct the macro configuration. The processor performs this process for each narrow area within the circuit configuration area.

[0102] Thereby, it is possible to appropriately arrange the power switch circuits in consideration of the constraints (criteria) of power supply voltage variation (IR - Drop) and wiring resources for each narrow area. By arranging while considering the constraints (criteria) of power supply voltage variation (IR - Drop) and wiring resources, it is possible to suppress the occurrence of rework operations in the design process of the semiconductor integrated circuit device.

[0103] (Third Embodiment)

[0104] Figure 7This is a diagram showing an example of a semiconductor integrated circuit device having a layout corresponding to the design method of the semiconductor integrated circuit device described above. A macro 702 is arranged in the circuit configuration area 701 of the semiconductor integrated circuit device, and a power switch circuit (PSW) 703 is arranged in an area (standard cell configuration area) where the macro 702 is not arranged in the circuit configuration area 701. In areas Z1, Z2, Z3, Z5 where the width of the divided area is equal to or greater than the width of the determination criterion for a narrow area (areas other than the narrow area), the power switch circuit 703 is arranged according to the first rule (as an example, in a stepped configuration pattern). In areas Z4, Z6, Z7, Z8 where the width of the divided area is less than the width of the determination criterion for a narrow area (narrow areas), the power switch circuit 703 is arranged according to a rule different from the first rule (as an example, in a columnar configuration pattern).

[0105] In addition, in the above-described embodiment, Figure 6A the shown configuration pattern is taken as an example of the original configuration pattern, and through Figure 6B and Figure 6C , examples of a configuration pattern with stronger IR - Drop resistance and a configuration pattern with more wiring resources are respectively shown, but it is not limited thereto. More configuration patterns with different IR - Drop intensities and wiring resource amounts can be prepared in advance, and sequences can be added to the configuration patterns considering IR - Drop and routability for application.

[0106] Furthermore, the design method of the semiconductor integrated circuit device in the above-described embodiment can be realized, for example, by a computer having a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), etc. executing a program stored in a storage unit. The above program is included in the embodiments of the present invention. In addition, a program for causing a computer to execute each process of the design method of the semiconductor integrated circuit device is recorded on a recording medium such as a CD - ROM, and can be realized by causing the computer to read it. The recording medium recording the above program is included in the embodiments of the present invention. As the recording medium for recording the above program, in addition to a CD - ROM, a floppy disk, a hard disk, a magnetic tape, an optical disk, a non - volatile memory card, etc. can be used.

[0107] In addition, a program product for a computer to execute the program for processing, thereby implementing each process of the above-described design method of a semiconductor integrated circuit device, is included in an embodiment of the present invention. As the above program product, there are a program itself for implementing the processes of the above-described design method of a semiconductor integrated circuit device, and a computer for reading in the above program. In addition, as the above program product, there are a transmission device capable of providing the above program to a computer communicably connected via a network, a network system including the transmission device, and the like.

[0108] In addition, in a case where the supplied program cooperates with an OS (operating system) or other application software running on a computer to implement the processes of the above-described design method of a semiconductor integrated circuit device, the above program is also included in an embodiment of the present invention. In addition, in a case where all or part of the processes of the supplied program are implemented by a function expansion board or a function expansion unit of a computer to implement the processes of the above-described design method of a semiconductor integrated circuit device, the above program is also included in an embodiment of the present invention. In addition, in order to utilize the present invention in a network environment, all or part of the program may be executed by another computer.

[0109] For example, the design method of a semiconductor integrated circuit device in the above-described embodiment can be implemented by Figure 8 a computer (design device) as shown, and the operations of the design method of a semiconductor integrated circuit device in the above-described embodiment are implemented by the CPU. Figure 8 FIG. is a diagram showing a structural example of a computer capable of implementing the design method of a semiconductor integrated circuit device in the present embodiment. A CPU 802, a ROM 803, a RAM 804, a network interface 805, an input device 806, an output device 807, and an external storage device 808 are connected to a bus 801.

[0110] The CPU 802 processes and operates data, and controls each component connected via the bus 801. A boot program is pre-stored in the ROM 803, and the computer is started by the CPU 802 executing the boot program. A computer program is stored in the external storage device 808, and the computer program is copied into the RAM 804 and executed by the CPU 802 to perform, for example, each process of the above-described design method of a semiconductor integrated circuit device. The RAM 804 is used for input / output of data, a working memory for transmission and reception, and a temporary storage for control of each component.

[0111] The external storage device 808 is, for example, a hard disk drive (HDD), a solid state drive (SSD), a CD-ROM, etc., and the stored content does not disappear even when the power is cut off. The network interface 805 is an interface for connecting to a network. The input device 806 is, for example, a keyboard, a pointing device (mouse), etc., and can perform various specifications, inputs, etc. The output device 807 is a display, a printer, etc., and can perform display, printing, etc.

[0112] In addition, the above-described embodiments are merely examples of the specific implementation when implementing the present invention, and thus do not limit the interpretation of the technical scope of the present invention. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

[0113] Industrial Applicability

[0114] According to the present invention, it is possible to provide a design method of a semiconductor integrated circuit device in which a power switch circuit is appropriately arranged in a circuit configuration area of the semiconductor integrated circuit device.

Claims

1. A design method for a semiconductor integrated circuit device, characterized in that: In a circuit configuration area of a semiconductor integrated circuit device in which a plurality of power switch circuits are arranged in a stepped configuration pattern according to a first rule, a plurality of macros are arranged. A narrow area having a width smaller than a first value is detected from a first area in the circuit configuration area where the macros are not arranged. In the detected narrow area, the power switch circuits are arranged in a columnar configuration pattern according to a second rule different from the first rule. In an area other than the narrow area in the first area, the power switch circuits are arranged according to the first rule.

2. The design method for a semiconductor integrated circuit device according to claim 1, characterized in that: The first value is a value defined based on at least one of the width of the power switch circuit and the arrangement interval when the power switch circuit is arranged according to the first rule.

3. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: When wiring congestion occurs due to arranging the power switch circuits in a first arrangement pattern in the narrow area, the arrangement pattern is changed to a second arrangement pattern with more wiring resources than the first arrangement pattern to arrange the power switch circuits.

4. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: When a power supply voltage variation that violates a constraint occurs due to arranging the power switch circuits in a first arrangement pattern in the narrow area, the arrangement pattern is changed to a third arrangement pattern that more suppresses the power supply voltage variation to arrange the power switch circuits.

5. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: The first area is divided into a plurality of rectangular areas based on the arranged macros to detect the narrow areas.

6. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: The power switch circuits are arranged in the same arrangement pattern in all the detected narrow areas.

7. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: When wiring congestion does not occur due to arranging the power switch circuits in a first arrangement pattern in the narrow area, the arrangement pattern is changed to a fourth arrangement pattern that more suppresses the power supply voltage variation to arrange the power switch circuits.

8. The design method for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that: For each of the detected narrow areas, the power switch circuits are arranged in an arrangement pattern independent of the arrangement patterns of the other narrow areas.

9. A semiconductor integrated circuit device having a circuit configuration area, characterized in that: The semiconductor integrated circuit device has: A plurality of macros arranged in the circuit configuration area; A plurality of first power switch circuits are arranged in a stepped configuration pattern according to a first rule in an area other than a narrow area having a width less than a first value in a first area within the circuit configuration area where the macro is not arranged; and A plurality of second power switch circuits are arranged in a columnar configuration pattern according to a second rule different from the first rule in the narrow area within the first area.

10. The semiconductor integrated circuit device according to claim 9, wherein The first value is a value defined based on at least one of the width of the first power switch circuit and the arrangement interval when the first power switch circuit is arranged according to the first rule.

11. The semiconductor integrated circuit device according to claim 9 or 10, wherein The second power switch circuits are arranged in the same configuration pattern in all the narrow areas.

12. The semiconductor integrated circuit device according to claim 9 or 10, wherein For each of the narrow areas, the second power switch circuits are arranged in a configuration pattern independent of the configuration patterns of the other narrow areas.

13. A computer-readable recording medium storing a program for causing a computer to execute the following processing: Arranging a plurality of macros in a circuit configuration area of a semiconductor integrated circuit device in which a plurality of power switch circuits are arranged in a stepped configuration pattern according to a first rule; Detecting a narrow area having a width less than a first value from a first area within the circuit configuration area where the macro is not arranged; In the detected narrow area, arranging the power switch circuits in a columnar configuration pattern according to a second rule different from the first rule; And In an area other than the narrow area within the first area, arranging the power switch circuits according to the first rule.

14. The computer-readable recording medium according to claim 13, wherein The first value is a value defined based on at least one of the width of the power switch circuit and the arrangement interval when the power switch circuit is arranged according to the first rule.

15. The computer-readable recording medium according to claim 13 or 14, wherein In the process of arranging the power switch circuits in the narrow area, when wiring congestion occurs due to arranging the power switch circuits in a first configuration pattern in the narrow area, the power switch circuits are arranged in a second configuration pattern having more wiring resources than the first configuration pattern.

16. The computer-readable recording medium according to claim 13 or 14, wherein In the process of arranging the power switch circuits in the narrow area, when a power supply voltage variation that violates a constraint occurs due to arranging the power switch circuits in a first configuration pattern in the narrow area, the power switch circuits are arranged in a third configuration pattern that more suppresses the power supply voltage variation than the first configuration pattern.

17. The computer-readable recording medium according to claim 13 or 14, wherein In the process of detecting the narrow area, the first area is divided into a plurality of rectangular areas based on the configured macro to detect the narrow area.

18. The computer-readable recording medium according to claim 13 or 14, characterized in that In the process of configuring the power switch circuit in the narrow area, the power switch circuit is configured with the same configuration pattern in all the detected narrow areas.

19. The computer-readable recording medium according to claim 13 or 14, characterized in that In the process of configuring the power switch circuit in the narrow area, when the power switch circuit is configured with the first configuration pattern in the narrow area and no wiring congestion occurs, it is changed to a fourth configuration pattern that more suppresses power supply voltage fluctuations compared to the first configuration pattern to configure the power switch circuit.

20. The computer-readable recording medium according to claim 13 or 14, characterized in that In the process of configuring the power switch circuit in the narrow area, for each detected narrow area, the power switch circuit is configured with a configuration pattern that does not depend on the configuration patterns of other narrow areas.

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