Data processing method and apparatus, terminal, and storage medium
By employing M sub-threads to process N input data simultaneously in the zero-knowledge proof domain, the problem of high data transmission overhead and low computational efficiency caused by unreasonable threading in NTT and INTT calculations is solved, achieving efficient data processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUNLUNE (SINGAPORE) PTE LTD
- Filing Date
- 2023-01-04
- Publication Date
- 2026-05-22
AI Technical Summary
In the field of zero-knowledge proofs, the threads used for NTT and INTT computations are unreasonable, resulting in high data transfer overhead and low computational efficiency.
M sub-threads are used to process N input data simultaneously. Each sub-thread processes different N/M input data. Multi-level butterfly operations, reverse operations, and fixed-value multiplication operations are implemented through the main thread clock control to improve computational efficiency.
By rationally allocating sub-thread tasks, data transmission overhead is reduced, computational efficiency is improved, and efficient processing of NTT and INTT calculations is achieved.
Smart Images
Figure CN116472700B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a data processing method, apparatus, terminal, and storage medium. Background Technology
[0002] Zero-knowledge proofs are increasingly widely used as cryptographic protocols in the communications industry. Fast Number Theoretic Transforms (NTT) and Fast Inverse Number Theoretic Transforms (INTT) are key operations in the field of zero-knowledge proofs.
[0003] Currently, calculations related to NTT and INTT require interaction between the main thread and sub-threads. That is, the main thread controls different sub-threads to handle different operations. For example, in the butterfly operation and reverse operation in NTT calculation, the main thread first opens a sub-thread, retrieves input data from memory, performs the butterfly operation, exits this sub-thread, and then opens another sub-thread to perform the reverse operation.
[0004] However, in the field of zero-knowledge proofs, the amount of data computed by NTT and INTT requires data scheduling with memory every time the main thread starts a child thread, which leads to complex scheduling of the main thread and each child thread, unreasonable allocation of child threads, large data transmission overhead, and low computational efficiency. Summary of the Invention
[0005] The main objective of this application is to provide a data processing method, apparatus, terminal, and storage medium to solve the problems of unreasonable threading, high data transmission overhead, and low computational efficiency.
[0006] To achieve the above objectives, firstly, this application provides a data processing method, comprising:
[0007] Receive N input data, where the N input data correspond to M sub-threads, where N is a power of 2 and M is an integer greater than 1;
[0008] For each of the M child threads, obtain N / M input data corresponding to each child thread from the N input data, wherein the N / M input data corresponding to each child thread are different;
[0009] The first processing is performed on N / M input data to obtain N / M output data corresponding to each sub-thread;
[0010] The N / M output data corresponding to each sub-thread are summarized to obtain the output result, which includes N output data.
[0011] In some implementations, the first processing is fast number theory transformation, and each sub-thread includes multi-level butterfly operation units and reverse operation units;
[0012] The first processing of N / M input data yields N / M output data for each sub-thread, including:
[0013] The parameters required for a multi-level butterfly arithmetic unit are determined based on N / M input data.
[0014] Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on N / M input data to obtain the butterfly operation results;
[0015] The butterfly operation results are processed using the reverse order operation unit to obtain N / M output data corresponding to each sub-thread.
[0016] In some implementations, N / M input data correspond to N / M butterfly operation units, and each butterfly operation in the N / M butterfly operation units includes first input data and second input data;
[0017] The parameters required for a multi-level butterfly arithmetic unit are determined based on N / M input data, including:
[0018] For each butterfly operation in N / M butterfly operation units, the interval between the first input data and the second input data is defined, where the interval is used to characterize the positional interval between the two data;
[0019] Divide the coordinates of the multi-level butterfly operation by the interval to obtain the number of multi-level butterfly operations;
[0020] Based on the coordinates, intervals, and number of multi-level butterfly operations, the coordinates of the first input data and the coordinates of the original root are calculated respectively.
[0021] The coordinates and intervals of the first input data are summed to obtain the coordinates of the second input data.
[0022] The parameters required for each butterfly operation unit, including the coordinates of the first input data, the coordinates of the second input data, and the coordinates of the original root, are summarized to obtain the parameters required for the multi-level butterfly operation unit.
[0023] In some implementations, the coordinates of the first input data and the coordinates of the original root are calculated based on the coordinates, intervals, and number of multi-level butterfly operations, including:
[0024] The coordinates of the first input data are obtained by summing the product of the coordinates and intervals of the multi-level butterfly operation and the number of multi-level butterfly operations.
[0025] The difference between the product of the coordinates and intervals of the multi-level butterfly operation and the number of multi-level butterfly operations is calculated to obtain the number of primitive roots.
[0026] The product of the increment of the primitive root and the number of primitive root types is used as the exponent. The primitive root and the exponent are then exponentially operated on to obtain the coordinates of the primitive root.
[0027] In some implementations, the butterfly operation results are processed using a reverse arithmetic unit to obtain N / M output data corresponding to each child thread, including:
[0028] The reverse order operation unit sorts the butterfly operation results according to the result number, and obtains N / M sorted output data corresponding to each sub-thread.
[0029] In some implementations, the first processing is a fast number theory inverse transformation, and each sub-thread includes a multi-level butterfly operation unit, a reverse operation unit, and a fixed-value multiplication operation unit;
[0030] The first processing of N / M input data yields N / M output data for each sub-thread, including:
[0031] The parameters required for a multi-level butterfly arithmetic unit are determined based on N / M input data.
[0032] Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on N / M input data to obtain the butterfly operation results;
[0033] The butterfly operation results are processed using the reverse order operation unit to obtain the sorted butterfly operation results;
[0034] The fixed-value multiplication unit multiplies each data point in the sorted butterfly operation result by a preset value to obtain N / M output data points for each sub-thread.
[0035] In some implementations, the number of levels in a multi-level butterfly operation is determined by N.
[0036] In some implementations, each of the M child threads achieves clock synchronization of the various levels of butterfly operation units, reverse operation units, and fixed-value multiplication operation units in the multi-level butterfly operation through the clock control of the main thread.
[0037] Secondly, embodiments of the present invention provide a data processing apparatus, comprising:
[0038] The receiving module is used to receive N input data, where the N input data correspond to M sub-threads, and N is a power of 2;
[0039] The acquisition module is used to acquire N / M input data corresponding to each of the M sub-threads from N input data, wherein the N / M input data corresponding to each sub-thread are different;
[0040] The calculation module is used to perform the first processing on N / M input data to obtain N / M output data corresponding to each sub-thread;
[0041] The aggregation module is used to aggregate the N / M output data corresponding to each sub-thread to obtain the output result, where the output result includes N output data.
[0042] Thirdly, embodiments of the present invention provide a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the above data processing methods.
[0043] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above data processing methods. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a flowchart illustrating the implementation of a data processing method provided in an embodiment of the present invention;
[0046] Figure 2 This is a schematic diagram illustrating an application scenario of a data processing method provided in an embodiment of the present invention;
[0047] Figure 3 This is a schematic diagram of the structure of a data processing device provided in an embodiment of the present invention;
[0048] Figure 4 This is a schematic diagram of the terminal provided in an embodiment of the present invention. Specific Implementation
[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0051] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.
[0052] It should be understood that in the various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0053] It should be understood that in this invention, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.
[0054] It should be understood that in this invention, "multiple" refers to two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, "and / or B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Contains A, B, and C", "Contains A, B, and C" means that all three A, B, and C are contained; "Contains A, B, or C" means that one of A, B, and C is contained; "Contains A, B, and / or C" means that any one, two, or three of A, B, and C are contained.
[0055] It should be understood that in this invention, "B corresponding to A", "B corresponding to A", "A and B correspond", or "B and A correspond" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. Matching A and B is defined as a similarity between A and B that is greater than or equal to a preset threshold.
[0056] Depending on the context, "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection."
[0057] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0058] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.
[0059] In one embodiment, such as Figure 1 As shown, the present invention provides a data processing method, including the following steps:
[0060] Step S101: Receive N input data.
[0061] There are N input data points corresponding to M sub-threads, where N is a power of 2 and M is an integer greater than 1.
[0062] like Figure 2 As shown, the data processing method of this application includes a main thread and M sub-threads. The M sub-threads process the received N input data to obtain the output results. Each of the M sub-threads is configured with the same data processing method. For example, sub-thread 1, sub-thread 2... sub-thread M are all configured with data processing method 1 and data processing method 2, so that multiple sub-threads can execute the data processing process simultaneously, thereby improving the data processing efficiency.
[0063] In this invention, M sub-threads are used to process N input data simultaneously, with each sub-thread performing the same amount of computation, thus making the allocation of sub-threads reasonable and improving computational efficiency.
[0064] In this invention, the main thread and child threads can be multiple threads running on a single-core processor or multiple threads running on a multi-core processor.
[0065] The main thread controls the clock of M child threads, causing all M child threads to execute any one of the data processing methods simultaneously. For example, the main thread controls all M child threads to execute data processing method 1 simultaneously. After all child threads have finished executing data processing method 1, the main thread controls all child threads to execute data processing method 2 simultaneously.
[0066] Step S102: For each of the M child threads, obtain N / M input data corresponding to each child thread from the N input data.
[0067] Each sub-thread has N / M different input data.
[0068] In this application, the M sub-threads can dynamically adjust the number of input data points each thread calculates based on the size of the input data N. For example, if N=4 and M=2, then each of the two sub-threads will process 2 input data points.
[0069] Step S103: Perform the first processing on the N / M input data to obtain N / M output data corresponding to each sub-thread.
[0070] The first processing includes, but is not limited to, algorithms such as fast number-theoretic transform, fast inverse number-theoretic transform, or Fourier transform.
[0071] The following section uses the fast number theory transform and the fast number theory inverse transform as examples to illustrate the process of performing the first processing on N / M input data to obtain N / M output data corresponding to each sub-thread.
[0072] In one embodiment, since the fast number theory transformation includes multi-level butterfly operation units and reversal operation units, when the first processing is the fast number theory transformation, each sub-thread includes multi-level butterfly operation units and reversal operation units. Each sub-thread first performs multi-level butterfly operations on the input data, obtains the butterfly operation results, and then performs reversal operations to obtain the output results. Specifically, it is necessary to first determine the parameters required by the multi-level butterfly operation units based on N / M input data, then perform multi-level butterfly operations on the N / M input data based on the parameters required by the multi-level butterfly operation units to obtain the butterfly operation results, and then use the reversal operation units to process the butterfly operation results to obtain N / M output data corresponding to each sub-thread. Here, the N / M input data correspond to N / M butterfly operation units, and each butterfly operation in the N / M butterfly operation units includes first input data and second input data.
[0073] For example, assuming there are N input data points and M sub-threads, each sub-thread processes N / M input data points. That is, if N / M input data points are input into any sub-thread, this sub-thread can directly perform L-level butterfly operations and reverse operations on the N / M input data points. Here, L is the level of the butterfly operation, determined by the number of input data points N.
[0074] Since the L-stage butterfly operation unit in the fast number theory transform requires three key parameters, before each sub-thread performs the L-stage butterfly operation on N / M input data, the sub-thread needs to base its operation on the memory ( Figure 2The N / M input data obtained from the memory determine the three parameters required for the multi-level butterfly operation unit. Specifically, the sub-thread needs to define the interval between the first and second input data for each of the N / M butterfly operations. This interval characterizes the positional distance between two data points. For example, if there are three input data points, and the first, second, and third input data are arranged sequentially, then the positional interval between the first and second input data is 1, and the positional interval between the first and third input data is 2.
[0075] Then, the sub-thread divides the coordinates of the multi-level butterfly operation by the interval to obtain the number of multi-level butterfly operations. Based on the coordinates, interval, and number of multi-level butterfly operations, it calculates the coordinates of the first input data and the coordinates of the original root, and sums the coordinates of the first input data and the interval to obtain the coordinates of the second input data. Finally, it summarizes the parameters required by each butterfly operation unit, including the coordinates of the first input data, the coordinates of the second input data, and the coordinates of the original root, to obtain the parameters required by the multi-level butterfly operation unit.
[0076] Specifically, based on the coordinates, intervals, and number of multi-level butterfly operations, the coordinates of the first input data and the coordinates of the primitive root are calculated respectively. First, the coordinates of the multi-level butterfly operation are summed with the products of the intervals and the number of multi-level butterfly operations to obtain the coordinates of the first input data. Then, the difference between the coordinates of the multi-level butterfly operation and the products of the intervals and the number of multi-level butterfly operations is calculated to obtain the number of primitive root types. Finally, the product of the primitive root increment and the number of primitive root types is used as the exponent, and the primitive root and the exponent are exponentially operated to obtain the coordinates of the primitive root.
[0077] For example, suppose there are N input data, N=4, namely a1, a2, a3, and a4, and M sub-threads, M=2. Then each sub-thread processes two input data, that is, the first sub-thread processes data a1 and a2, and the second sub-thread processes data a3 and a4. Taking the first sub-thread as an example, since the L-level butterfly operation has two inputs, the interval B between the first input data a1 and the second input data a2 is defined.
[0078] First, calculate the number of multi-level butterfly operations using formula (1), as follows:
[0079] ii=i / B(1)
[0080] Where i is the coordinate of the multi-level butterfly operation.
[0081] Then, the coordinates r of the first input data a1 are calculated using formula (2), as follows:
[0082] r=i+B ii(2)
[0083] Then, the coordinates g of the original root are calculated using formulas (3) and (4), as follows:
[0084] j=i-ii B(3)
[0085] g=w k j (4)
[0086] Where w is the primitive root, j is the number of primitive root species, and k is the increment of the primitive root.
[0087] Finally, the coordinates p of the second input data a2 are calculated using formula (5), as follows:
[0088] P = r + B (5)
[0089] Using the above formula, the coordinates r of the first input data, the coordinates P of the second input data, and the coordinates g of the primitive root, required for the L-level butterfly operation, can be obtained. The butterfly operation can then be performed based on these parameters. After the first sub-thread performs the butterfly operation on the first input data a1 and the second input data a2, the corresponding butterfly operation results are obtained: the butterfly operation result b1 corresponding to the first input data a1, and the butterfly operation result b2 corresponding to the second input data a2.
[0090] After obtaining the butterfly operation results, the reverse order operation unit needs to process the butterfly operation results to obtain N / M output data corresponding to each sub-thread. That is, the reverse order operation unit sorts the butterfly operation results according to the result sequence number to obtain N / M sorted output data corresponding to each sub-thread.
[0091] Based on the above embodiment, the butterfly operation results of the first sub-thread are b1 and b2. b1 and b2 need to be sorted according to their result numbers, either in forward or reverse order. For example, if b1 and b2 are sorted in forward order, the output data (or sorted output results) of the first sub-thread will be b1 and b2. Conversely, if sorted in reverse order, the sorted output results of the first sub-thread will be b2 and b1.
[0092] It should be noted that the processing of the output data corresponding to the second sub-thread in the above embodiment is similar to that of the first sub-thread, and will not be repeated here.
[0093] In another embodiment, since the Fast Inverse Number Theory Transform (FNTT) includes multi-level butterfly operation units, reversal operation units, and fixed-value multiplication operation units, when the first processing is FNTT, each sub-thread includes multi-level butterfly operation units, reversal operation units, and fixed-value multiplication operation units. Each sub-thread first performs multi-level butterfly operations on the input data, obtains the butterfly operation results, then performs reversal operations, and finally performs fixed-value multiplication operations to obtain the output results. Specifically, the parameters required for the multi-level butterfly operation units need to be determined based on N / M input data. Then, multi-level butterfly operations are performed on the N / M input data based on the parameters required for the multi-level butterfly operation to obtain the butterfly operation results. The reversal operation units are then used to process the butterfly operation results to obtain sorted butterfly operation results. Finally, the fixed-value multiplication operation units multiply each data in the sorted butterfly operation results by a preset value to obtain N / M output data corresponding to each sub-thread. Among them, N / M input data correspond to N / M butterfly operation units, and each butterfly operation in the N / M butterfly operation units includes first input data and second input data.
[0094] For example, assuming there are N input data points and M sub-threads, each sub-thread processes N / M input data points. That is, if N / M input data points are input into any sub-thread, this sub-thread can directly perform L-level butterfly operations, reverse operations, and fixed-value multiplication on the N / M input data points. Here, L is the level of the butterfly operations, determined by the number of input data points N.
[0095] Since the L-stage butterfly operation unit in the fast number theory transform requires three key parameters, before each sub-thread performs the L-stage butterfly operation on N / M input data, the sub-thread needs to base its operation on the memory ( Figure 2 The N / M input data obtained from the memory in the sub-thread determine the three parameters required for the multi-level butterfly operation unit. Specifically, the sub-thread needs to define the interval between the first and second input data for each butterfly operation in the N / M butterfly operation units. The interval characterizes the positional distance between two data points. For example, if there are three input data points, and the first, second, and third input data are arranged sequentially, then the positional interval between the first and second input data is 1, and the positional interval between the first and third input data is 2.
[0096] Then, the sub-thread divides the coordinates of the multi-level butterfly operation by the interval to obtain the number of multi-level butterfly operations. Based on the coordinates, interval, and number of multi-level butterfly operations, it calculates the coordinates of the first input data and the coordinates of the original root, and sums the coordinates of the first input data and the interval to obtain the coordinates of the second input data. Finally, it summarizes the parameters required by each butterfly operation unit, including the coordinates of the first input data, the coordinates of the second input data, and the coordinates of the original root, to obtain the parameters required by the multi-level butterfly operation unit.
[0097] Specifically, based on the coordinates, intervals, and number of multi-level butterfly operations, the coordinates of the first input data and the coordinates of the primitive root are calculated respectively. First, the coordinates of the multi-level butterfly operation are summed with the products of the intervals and the number of multi-level butterfly operations to obtain the coordinates of the first input data. Then, the difference between the coordinates of the multi-level butterfly operation and the products of the intervals and the number of multi-level butterfly operations is calculated to obtain the number of primitive root types. Finally, the product of the primitive root increment and the number of primitive root types is used as the exponent, and the primitive root and the exponent are exponentially operated to obtain the coordinates of the primitive root.
[0098] For example, suppose there are N input data, N=4, namely a1, a2, a3, and a4, and M sub-threads, M=2. Then each sub-thread processes two input data, that is, the first sub-thread processes data a1 and a2, and the second sub-thread processes data a3 and a4. Taking the first sub-thread as an example, since the L-level butterfly operation has two inputs, the interval B between the first input data a1 and the second input data a2 is defined.
[0099] First, calculate the number of multi-level butterfly operations using formula (1), as follows:
[0100] ii=i / B(1)
[0101] Where i is the coordinate of the multi-level butterfly operation.
[0102] Then, the coordinates r of the first input data a1 are calculated using formula (2), as follows:
[0103] r=i+B ii(2)
[0104] Then, the coordinates g of the original root are calculated using formulas (3) and (4), as follows:
[0105] j=i-ii B(3)
[0106] g=w k j (4)
[0107] Where w is the primitive root, j is the number of primitive root species, and k is the increment of the primitive root.
[0108] Finally, the coordinates p of the second input data a2 are calculated using formula (5), as follows:
[0109] P = r + B (5)
[0110] Using the above formula, the coordinates r of the first input data, the coordinates P of the second input data, and the coordinates g of the primitive root, required by the L-level butterfly operation unit, can be obtained. Based on these parameters, butterfly operations can be performed. After the first sub-thread performs butterfly operations on the first input data a1 and the second input data a2, the corresponding butterfly operation results are obtained: butterfly operation result b1 corresponding to the first input data a1, and butterfly operation result b2 corresponding to the second input data a2.
[0111] After obtaining the above butterfly operation results, the reverse order operation unit needs to process the butterfly operation results to obtain sorted butterfly operation results. That is, the reverse order operation unit sorts the butterfly operation results according to the result sequence number to obtain sorted butterfly operation results.
[0112] Based on the above embodiment, the butterfly operation results of the first sub-thread are b1 and b2. b1 and b2 need to be sorted according to their result numbers, either in a forward or reverse order. For example, if b1 and b2 are sorted in a forward order, the sorted butterfly operation results for the first sub-thread are b1 and b2. Conversely, if sorted in a reverse order, the sorted butterfly operation results for the first sub-thread are b2 and b1.
[0113] Finally, the fixed-value multiplication unit multiplies each data point in the sorted butterfly operation result by a preset value to obtain N / M output data points for each sub-thread.
[0114] For example, suppose the sorted butterfly operation results corresponding to the first child thread are b1 and b2, with a preset value of q. Then, multiplying b1 and b2 by q will yield the output data qb1 and qb2 corresponding to the first child thread.
[0115] It should be noted that the processing of the output data corresponding to the second sub-thread in the above embodiment is similar to that of the first sub-thread, and will not be repeated here.
[0116] In addition, each of the M sub-threads achieves clock synchronization of the various levels of butterfly operation units, reverse operation units, and fixed-value multiplication operation units in the multi-level butterfly operation through the clock control of the main thread.
[0117] For example, if there is a main thread and two child threads, and each child thread executes the butterfly operation and the reverse operation in the fast number theory transformation in sequence, then the main thread will control the first child thread and the second child thread to execute the butterfly operation simultaneously at the first moment. After the first child thread and the second child thread have completed the butterfly operation, the main thread will control the first child thread and the second child thread to execute the reverse operation simultaneously at the second moment.
[0118] Step S104: Summarize the N / M output data corresponding to each sub-thread to obtain the output result.
[0119] The output results include N output data.
[0120] Based on the above embodiment, let N=4 and M=2. Taking the fast number theory transformation as an example, the output results of the first sub-thread are b1 and b2, and the output results of the second sub-thread are b3 and b4. Then, the output results of the first sub-thread and the second sub-thread need to be summarized to obtain the output results b1, b2, b3 and b4 of the four input data a1, a2, a3 and a4.
[0121] This invention provides a data processing method, comprising: receiving N input data, wherein the N input data correspond to M sub-threads; for each of the M sub-threads, obtaining N / M input data corresponding to each sub-thread from the N input data; performing a first processing on the N / M input data to obtain N / M output data corresponding to each sub-thread; and summing the N / M output data corresponding to each sub-thread to obtain an output result. In this invention, each of the M sub-threads can actively select the N / M input data to be processed from the N input data based on the amount of input data, and perform a series of operations on the N / M input data until the corresponding N / M output data are obtained, thus realizing a complete NTT or INTT calculation. Furthermore, this invention uses M sub-threads to process N input data simultaneously, with each sub-thread performing the same amount of computation, making the allocation of sub-threads reasonable and improving computational efficiency.
[0122] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0123] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.
[0124] Figure 3The diagram illustrates the structure of a data processing device according to an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment are shown. The data processing device includes a receiving module 31, an acquiring module 32, a calculation module 33, and a summarizing module 34, as detailed below:
[0125] The receiving module 31 is used to receive N input data, where the N input data correspond to M sub-threads, and N is a power of 2;
[0126] The acquisition module 32 is used to acquire N / M input data corresponding to each of the M sub-threads from N input data, wherein the N / M input data corresponding to each sub-thread are different;
[0127] The calculation module 33 is used to perform the first processing on N / M input data to obtain N / M output data corresponding to each sub-thread;
[0128] The aggregation module 34 is used to aggregate the N / M output data corresponding to each sub-thread to obtain the output result, wherein the output result includes N output data.
[0129] In some implementations, the first processing is fast number theory transformation, and each sub-thread includes multi-level butterfly operation units and reverse operation units;
[0130] The calculation module 33 is also used to determine the parameters required for the multi-level butterfly arithmetic unit based on N / M input data;
[0131] Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on N / M input data to obtain the butterfly operation results;
[0132] The butterfly operation results are processed using the reverse order operation unit to obtain N / M output data corresponding to each sub-thread.
[0133] In some implementations, N / M input data correspond to N / M butterfly operation units, and each butterfly operation in the N / M butterfly operation units includes first input data and second input data;
[0134] The calculation module 33 is also used to define the interval between the first input data and the second input data for each butterfly operation in the N / M butterfly operation units, wherein the interval is used to characterize the positional interval between the two data;
[0135] Divide the coordinates of the multi-level butterfly operation by the interval to obtain the number of multi-level butterfly operations;
[0136] Based on the coordinates, intervals, and number of multi-level butterfly operations, the coordinates of the first input data and the coordinates of the original root are calculated respectively.
[0137] The coordinates and intervals of the first input data are summed to obtain the coordinates of the second input data.
[0138] The parameters required for each butterfly operation unit, including the coordinates of the first input data, the coordinates of the second input data, and the coordinates of the original root, are summarized to obtain the parameters required for the multi-level butterfly operation unit.
[0139] In some implementations, the calculation module 33 is also used to sum the product of the coordinates and interval of the multi-level butterfly operation and the number of multi-level butterfly operations to obtain the coordinates of the first input data;
[0140] The difference between the product of the coordinates and intervals of the multi-level butterfly operation and the number of multi-level butterfly operations is calculated to obtain the number of primitive roots.
[0141] The product of the increment of the primitive root and the number of primitive root types is used as the exponent. The primitive root and the exponent are then exponentially operated on to obtain the coordinates of the primitive root.
[0142] In some implementations, the butterfly operation results are processed using reverse order operations to obtain N / M output data corresponding to each child thread, including:
[0143] The reverse order operation unit sorts the butterfly operation results according to the result number, and obtains N / M sorted output data corresponding to each sub-thread.
[0144] In some implementations, the first processing is a fast number theory inverse transformation, and each sub-thread includes a multi-level butterfly operation unit, a reverse operation unit, and a fixed-value multiplication operation unit;
[0145] The calculation module 33 is also used to determine the parameters required for the multi-level butterfly arithmetic unit based on N / M input data;
[0146] Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on N / M input data to obtain the butterfly operation results;
[0147] The butterfly operation results are processed using the reverse order operation unit to obtain the sorted butterfly operation results;
[0148] The fixed-value multiplication unit multiplies each data point in the sorted butterfly operation result by a preset value to obtain N / M output data points for each sub-thread.
[0149] In some implementations, the number of levels in a multi-level butterfly operation is determined by N.
[0150] In some implementations, each of the M child threads achieves clock synchronization of the various levels of butterfly operation units, reverse operation units, and fixed-value multiplication operation units in the multi-level butterfly operation through the clock control of the main thread.
[0151] Figure 4 This is a schematic diagram of a terminal provided in an embodiment of the present invention. Figure 4 As shown, the terminal 4 in this embodiment includes a processor 401, a memory 402, and a computer program 403 stored in the memory 402 and executable on the processor 401. When the processor 401 executes the computer program 403, it implements the steps described in the various data processing method embodiments above, for example... Figure 1 Steps 101 to 104 are shown. Alternatively, when processor 401 executes computer program 403, it implements the functions of each module / unit in the above-described data processing device embodiments, for example... Figure 3 The functions of modules / units 31 to 34 shown.
[0152] The present invention also provides a readable storage medium storing a computer program, which, when executed by a processor, is used to implement the data processing methods provided in the various embodiments described above.
[0153] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of computer programs from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application-Specific Integrated Circuit (ASIC). Alternatively, the ASIC can be located in a user equipment. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0154] The present invention also provides a program product including executable instructions stored in a readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the execution of the executable instructions by the at least one processor causes the device to implement the data processing methods provided in the various embodiments described above.
[0155] In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.
[0156] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A data processing method, wherein, include: Receive N input data, where the N input data correspond to M sub-threads, where N is a power of 2 and M is an integer greater than 1; For each of the M sub-threads, N / M input data corresponding to each sub-thread are obtained from the N input data, wherein the N / M input data corresponding to each sub-thread are different; The N / M input data are processed to obtain N / M output data corresponding to each sub-thread; The N / M output data corresponding to each sub-thread are summarized to obtain the output result, wherein the output result includes N output data; The main thread controls the clock for M child threads, so that all of the M child threads can execute any one of the data processing methods simultaneously.
2. The data processing method as described in claim 1, wherein, The first processing is a fast number theory transformation, and each sub-thread includes a multi-level butterfly operation unit and a reverse operation unit; The first processing of the N / M input data to obtain N / M output data corresponding to each sub-thread includes: The parameters required for the multi-level butterfly operation unit are determined based on the N / M input data. Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on the N / M input data to obtain the butterfly operation result; The butterfly operation result is processed using the reverse operation unit to obtain N / M output data corresponding to each sub-thread.
3. The data processing method as described in claim 2, wherein, The N / M input data correspond to N / M butterfly operation units, and each butterfly operation in the N / M butterfly operation units includes first input data and second input data; The process of determining the parameters required for the multi-level butterfly arithmetic unit based on the N / M input data includes: For each butterfly operation in the N / M butterfly operation units, the interval between the first input data and the second input data is defined, wherein the interval is used to characterize the positional interval between the two data; Divide the coordinates of the multi-level butterfly operation by the interval to obtain the number of multi-level butterfly operations; Based on the coordinates of the multi-level butterfly operation, the interval, and the number of multi-level butterfly operations, the coordinates of the first input data and the coordinates of the primitive root are calculated respectively. The coordinates of the second input data are obtained by summing the coordinates of the first input data and the interval. The parameters required for each butterfly operation unit, including the coordinates of the first input data, the coordinates of the second input data, and the coordinates of the original root, are summarized to obtain the parameters required for the multi-level butterfly operation unit.
4. The data processing method as described in claim 3, wherein, The calculation of the coordinates of the first input data and the coordinates of the primitive root based on the coordinates of the multi-level butterfly operation, the interval, and the number of multi-level butterfly operations includes: The coordinates of the first input data are obtained by summing the product of the coordinates of the multi-level butterfly operation and the interval and the number of multi-level butterfly operations. The difference between the coordinates of the multi-level butterfly operation and the product of the interval and the number of multi-level butterfly operations is calculated to obtain the number of primitive roots. The product of the increment of the primitive root and the number of types of primitive roots is used as the exponent, and the primitive root and the exponent are exponentially operated on to obtain the coordinates of the primitive root.
5. The data processing method as described in claim 2, wherein, The process of using the reverse order operation unit to process the butterfly operation result yields N / M output data corresponding to each sub-thread, including: The reverse order operation unit sorts the butterfly operation results according to the result sequence number to obtain N / M sorted output data corresponding to each sub-thread.
6. The data processing method as described in claim 1, wherein, The first processing is a fast number theory inverse transform, and each sub-thread includes a multi-level butterfly operation unit, a reverse operation unit, and a fixed-value multiplication operation unit; The first processing of the N / M input data to obtain N / M output data corresponding to each sub-thread includes: The parameters required for the multi-level butterfly operation unit are determined based on the N / M input data. Based on the parameters required by the multi-level butterfly operation unit, multi-level butterfly operations are performed on the N / M input data to obtain the butterfly operation result; The butterfly operation result is processed using the reverse order operation unit to obtain the sorted butterfly operation result; The fixed-value multiplication unit multiplies each data point in the sorted butterfly operation result by a preset value to obtain N / M output data points corresponding to each sub-thread.
7. The data processing method according to any one of claims 2-6, wherein, The number of levels in the multi-level butterfly operation is determined by N.
8. The data processing method according to any one of claims 1-6, wherein, Each of the M sub-threads achieves clock synchronization of the various levels of butterfly operation units, reverse operation units, and fixed-value multiplication operation units in the multi-level butterfly operation through the clock control of the main thread.
9. A data processing apparatus, comprising: The receiving module is used to receive N input data, wherein the N input data correspond to M sub-threads, and N is a power of 2; The acquisition module is used to acquire N / M input data corresponding to each of the M sub-threads from the N input data, wherein the N / M input data corresponding to each sub-thread are different; The calculation module is used to perform a first processing on the N / M input data to obtain N / M output data corresponding to each sub-thread; The aggregation module is used to aggregate the N / M output data corresponding to each sub-thread to obtain an output result, wherein the output result includes N output data. The main thread controls the clock for M child threads, so that all of the M child threads can execute any one of the data processing methods simultaneously.
10. A terminal, wherein, Includes a memory, and one or more processors communicatively connected to the memory; The memory stores instructions that can be executed by the one or more processors to cause the one or more processors to implement the data processing method as described in any one of claims 1 to 8.
11. A computer-readable storage medium, wherein, Includes a program or instructions that, when run on a computer, implement the data processing method according to any one of claims 1 to 8.