Body voltage generator for tracking current

Abstract

The present disclosure relates to a body voltage generator for tracking current. Systems and devices are provided for tracking a bandgap current generated by a bandgap circuit and reducing leakage current regardless of changes in PVT conditions. An apparatus may include one or more power amplifiers that power components of the apparatus and include transistors. The apparatus may further include a bandgap current mirror processing circuitry that generates a mirror current that mirrors a received current independent of process, voltage, and temperature (PVT). The apparatus may further include a body voltage generator circuit that includes an amplifier having an input coupled to the bandgap current mirror processing circuitry. A body voltage control circuitry is coupled to an output of the amplifier and generates a body voltage based on a relationship between the mirror current and the leakage current.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to voltage generation for body terminals in an electronic device. For example, a body voltage generation circuit may be used to track the bandgap current of a body voltage generator and control operations to reduce leakage current from one or more transistors (e.g., PMOS). Background Art

[0002] Various operations in a memory device and / or other electronic device may rely on a power amplifier that utilizes one or more transistors. For example, the one or more transistors may include p-channel metal-oxide-semiconductor (PMOS) transistors and / or n-channel metal-oxide-semiconductor (NMOS) transistors. The power amplifier may utilize the one or more transistors to provide a relatively large current (e.g., 1 mA) for the memory device and / or the electronic device. However, the one or more transistors may leak some current during a standby mode. For example, when the one or more transistors are turned off, the one or more transistors may leak a cut-off current (Ioff). This leakage current increases power consumption and may cause undesired electrical behavior.

[0003] In some embodiments, the body terminals of the one or more transistors may be connected to corresponding source terminals, thus providing the source voltage to the body terminals via the connection between the source and the body terminals. However, a body voltage generation circuit may be used to provide a constant (e.g., fixed) body voltage (Vb) to the body terminals to adjust the threshold voltage of the one or more transistors without relying on the voltage from the source terminals. Thus, the threshold voltage may be increased by adjusting the body voltage to reverse bias the one or more transistors, thereby reducing the leakage current magnitude when the one or more transistors are turned off.

[0004] However, the leakage current magnitude may vary with changes in the voltage applied to the transistor, the current flowing through the transistor, the ambient temperature, etc. In other words, changes in process, voltage, temperature (PVT) conditions may cause changes in the leakage current magnitude. It should be understood that although the present disclosure refers to PMOS, any circuit component (e.g., n-channel metal-oxide-semiconductor (NMOS)) that may be used in a body voltage generation circuit is covered in the present disclosure.

[0005] Embodiments of the present disclosure may address one or more of the problems set forth above. Summary of the Invention

[0006] One aspect of the present disclosure is directed to an apparatus that includes: one or more power amplifiers configured to power components of the apparatus and including transistors; and a bandgap current mirror processing circuit system configured to generate a mirrored current that mirrors a received current independent of process, voltage, and temperature (PVT); and a body voltage generator circuit including: an amplifier, wherein the bandgap current mirror processing circuit system is coupled to an input terminal of the amplifier; and a body voltage control circuit system coupled to an output of the amplifier, wherein the body voltage control circuit system is configured to generate a body voltage based at least in part on a relationship between the mirrored current and a leakage current leaking from the transistor.

[0007] Another aspect of the present disclosure is directed to a circuit system for generating a body voltage, the circuit system including: a bandgap current mirror processing circuit system configured to generate a mirrored current that mirrors a received current independent of process, voltage, and temperature (PVT); and a voltage generator circuit system coupled to the bandgap current mirror processing circuit system, wherein the voltage generator circuit system is configured to generate the body voltage for a transistor based at least in part on a relationship between the mirrored current and a leakage current that occurs when the electronic device is in an off mode.

[0008] Yet another aspect of the present disclosure is directed to a body voltage generation circuit including: a bandgap current mirror processing circuit system configured to generate a mirrored current that mirrors a received current independent of process, voltage, and temperature (PVT), wherein the mirrored current is configured to discharge charge from a node configured to receive charge of a leakage current from a transistor; and a voltage generator circuit system including: an amplifier, wherein the node is coupled to an input of the amplifier; and a body voltage control circuit system coupled to an output of the amplifier, wherein the body voltage control circuit system is configured to generate the body voltage based at least in part on a relationship between the mirrored current and the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present disclosure may be better understood after reading the following detailed description and with reference to the drawings, in which:

[0010] Figure 1 is a simplified block diagram of a semiconductor device including a body voltage generation circuit according to an embodiment of the present disclosure;

[0011] Figure 2 is a schematic diagram of a metal-oxide-semiconductor (MOS) transistor according to an embodiment of the present disclosure;

[0012] Figure 3Schematic diagram of a body voltage generation circuit according to an embodiment of the present disclosure;

[0013] Figure 4 Another schematic diagram of a body voltage generation circuit according to an embodiment of the present disclosure; and

[0014] Figure 5 Graph of leakage current and temperature of a body voltage generation circuit according to an embodiment of the present disclosure. Detailed implementation manners

[0015] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be routine for those skilled in the art who will benefit from the present disclosure in design, construction, and manufacturing.

[0016] When introducing elements of various embodiments of the present disclosure, the articles "a" and "the" are intended to indicate the presence of one or more of the recited elements. The terms "comprising", "including", and "having" are intended to be inclusive and mean that additional elements may exist in addition to the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be construed as excluding the existence of additional embodiments incorporating the recited features.

[0017] An electronic device such as a semiconductor device, a memory chip, a microprocessor chip, an image chip, etc. may include circuitry that performs various operations based on the provided voltage and current. In some cases, when the semiconductor device enters a standby mode and / or a power-off mode (e.g., a shutdown mode), the voltage and current provided to the circuitry may be cut off to, for example, reduce battery consumption. During shutdown, due to the physical properties of the circuit components, current may still flow in parts of the circuitry. This current may cause undesired electrical behavior, such as charging parts of the circuitry and / or wasting power.

[0018] The present disclosure generally relates to an electronic device that uses a power amplifier to power a portion of the electronic device and a body voltage generation circuit that reduces leakage current generated by the power amplifier. Generally, an electronic device may include one or more power operational amplifiers that generate an amplified output to a drive circuitry within the electronic device. For example, a semiconductor device such as a high bandwidth memory (HBM) device may include multiple high-gain power amplifiers to provide a high magnitude operating current to the remainder of the semiconductor device. Each power amplifier may include one or more p-channel metal oxide semiconductor (PMOS) transistors, each of which generates a large current output to provide a high magnitude operating current.

[0019] When the semiconductor device enters a standby mode and / or a power-off mode (e.g., to reduce battery consumption), the power amplifier may be deactivated. Specifically, when driving the source terminal of the PMOS with a peripheral voltage (VPERI), the gate terminal of the PMOS may be coupled (e.g., pulled up) to an external voltage source (e.g., drain-to-drain voltage (VDD)). Once the gate terminal and the source terminal of the PMOS are at substantially equivalent voltages, the PMOS is effectively turned off because the voltage difference between the gate terminal and the source terminal (e.g., Vgs) is no longer below the operating voltage threshold. That is, since the electric potential at the terminals is no longer large enough to drive the carriers, the active current does not flow through the PMOS.

[0020] However, even when the PMOS is effectively turned off, leakage current may still flow through the transistor. Specifically, due to the non-ideal behavior of the PMOS, an unwanted current may flow through the PMOS device. For example, the leakage current may include a current (e.g., junction leakage) that flows due to a reverse bias formed between the diffusion region and the well of the PMOS when the PMOS is turned off. As another example, the leakage current may include a current (e.g., sub-threshold conduction) that flows between the drain terminal and the source terminal of the PMOS due to the supply voltage at the source terminal scaling with the transistor size. Additionally or alternatively, the leakage current may include a current (e.g., gate oxide leakage) that flows between the terminals due to breakdown of the dielectric layer at the gate terminal.

[0021] In any case, the magnitude of the leakage current may vary with changes in the voltage applied to the PMOS, the current flowing through the PMOS, the ambient temperature, and so on. In other words, changes in the process, voltage, temperature (PVT) conditions may cause a change in the current magnitude. It should be understood that although the present disclosure refers to PMOS, any suitable circuit component (e.g., an n-channel metal-oxide semiconductor (NMOS) using a different polarity connection to its gate terminal) that can be used in a body voltage generation circuit is covered in the present disclosure.

[0022] As previously discussed, a body voltage generation circuit can be used to adjust the threshold voltage of one or more transistors and reduce the leakage current through the one or more transistors. In some cases, the body voltage generation circuit can use an operational amplifier to provide a constant (e.g., fixed) body voltage (Vb) to the body terminal to reduce the leakage current. Additionally, the body voltage magnitude can be greater than an external voltage source (e.g., VDD, VPERI) provided to the source terminal. However, because the magnitude of the leakage current can vary with process, the voltage applied to the transistor, the current flowing through the transistor, the ambient temperature, etc., as described above, a constant voltage technique that cannot track changes in the leakage current may not sufficiently reduce the leakage current under all testable PVT conditions.

[0023] Additionally or alternatively, because a constant voltage technique can increase the threshold voltage of a transistor, it can adversely affect the performance of a semiconductor device. For example, a slow (SS) corner may have a different ideal threshold voltage compared to a fast (FF) corner. However, setting the threshold voltage for all corners to accommodate the slow corner can result in a reduced execution speed, additional power consumption, lower current, increased leakage at other corners, and / or other undesirable factors for the semiconductor device. In some cases, a semiconductor device can include a bandgap circuit to provide voltage and current in a manner independent of process variations, power supply variations, temperature changes, etc. In other words, the bandgap current and voltage can be independent of PVT condition variations, but a power amplifier receiving such voltage and current may still experience PVT variations if the problem is not solved.

[0024] Accordingly, the present disclosure provides systems and techniques for reducing leakage current under different PVT conditions (including corner cases) by using a body voltage generation circuit that tracks a bandgap current. In some embodiments, the body voltage generation circuit can include an operational amplifier that helps track the bandgap current and reduce the leakage current. Additional details regarding leakage current under PVT condition variations will be described below with reference to Figures 1-5 describe additional details regarding leakage current under PVT condition variations.

[0025] In view of this, Figure 1 illustrate a semiconductor device 10 including a body voltage generation circuit 42 according to an embodiment of the present disclosure. Although the following description of the semiconductor device 10 will be described in the context of a memory device, it should be noted that the embodiments described herein can be used in any suitable electronic device. In fact, the following description of the memory device is provided to explain certain aspects of the body voltage generation circuit 42 of the present disclosure, and thus, the embodiments described herein should not be limited to memory devices.

[0026] The semiconductor device 10 can be any suitable memory device, such as a low-power double data rate type 4 (LPDDR4) synchronous dynamic random access memory (SDRAM) integrated onto a single semiconductor chip, a low-power double data rate type 5 (LPDDR5), a double data rate type 4 (DDR4), a double data rate type 5 (DDR5), a high bandwidth memory (HBM) device, or other electronic devices that can utilize the body voltage generation circuit 42 to reduce leakage current. The semiconductor device 10 can be mounted on an external substrate 2 such as a memory module substrate, a motherboard, etc. The semiconductor device 10 can include any number of memory banks, each having a plurality of memory cell arrays 11. Each memory cell array 11 can include any number of word lines WL, any number of bit lines BL, and any number of memory cells MC arranged at the intersections of the word lines WL and the bit lines BL. The selection of the word line WL is performed by the row decoder 12, and the selection of the bit line BL is performed by the column decoder 13. The sense amplifier (SAMP) 18 is coupled to the corresponding bit line BL and connected to the local input / output (I / O) line pair LIOT / B. The local IO line pair LIOT / B is connected to the main IO line pair MIOT / B through a transmission gate (TG) 19, and the transmission gate acts as a switch to control the signal flow.

[0027] The semiconductor device 10 may also include any number of external terminals that can communicate with other electrical components / devices. The external terminals may further include address terminals 21, command terminals 22, data terminals 24, and power supply terminals 25 (e.g., VDD, VPERI) 26 (e.g., VDDQ, VSSQ). Specifically, the address terminals 21 receive an address signal ADD and a bank address signal BADD. The address signal ADD and the bank address signal BADD supplied to the address terminals 21 are transmitted to the address decoder 32 via the address input circuit 31. The address decoder 32 receives the address signal ADD and supplies the decoded row address signal XADD to the row decoder 12 and supplies the decoded column address signal YADD to the column decoder 13. The address decoder 32 also receives the bank address signal BADD and supplies the bank address signal BADD to the row decoder 12 and the column decoder 13.

[0028] The command terminals 22 receive a command signal COM. The command signal COM can include one or more individual signals. The command terminals 22 transmit the command signal COM to the command decoder 34 via the command input circuit 33. The command decoder 34 decodes the command signal COM to generate various internal command signals. For example, the internal commands can include a row command signal for selecting the word line WL and a column command signal for selecting the bit line BL, such as a read command or a write command. Additionally, the data terminals 24 can be coupled to an output buffer for a memory read operation or coupled to an input buffer for a memory read / write access.

[0029] Although the address terminal 21 and the command terminal 22 are described as separate terminals, it should be understood that in some embodiments, the address input circuit 31 and the command input circuit 33 may receive the address signal ADD and the command signal COM via the same terminal. For example, the address and command terminal may provide the address signal (e.g., synchronized with the falling clock edge) at the falling clock edge, and the command signal (e.g., synchronized with the rising clock edge) at the rising clock edge. Additionally, the data terminal 24 may also be a single terminal that alternately receives the data signals (DQ, DQS, DM).

[0030] Accordingly, the address signals ADD, BADD, and the command signal COM can be used to access the memory cells MC in the memory cell array 11. As an example, when the command signal COM indicating a read operation is timely supplied to the word line WL and the bit line BL represented by the corresponding row address and column address of the address signal ADD, data can be read from the memory cell MC associated with the row address and column address. The read data DQ can be output from the data terminal 24 to the outside through the read / write amplifier 15 and the input / output circuit 17. Similarly, when the command signal COM indicating a write operation is timely supplied to the word line WL and the bit line BL indicated by the corresponding row address and column address of the address signal ADD, the data DQ can be written into the memory cell MC associated with the row address and column address. After receiving the write data DQ from the data terminal 24, the input / output circuit 17, and the read / write amplifier 15, the write data DQ can be supplied to the memory cell MC.

[0031] In some embodiments, the input / output circuit 17 may include an input buffer that stores data for processing and / or transmission. Additionally, the input / output circuit 17 receives a timing signal from an external clock, which controls the input timing of the read data DQ and the output timing of the write data DQ. The input / output circuit 17 may be powered using dedicated power potentials VDDQ and VSSQ, such that the power noise generated by the input / output circuit 17 does not propagate to other circuit blocks. The power potentials VDDQ and VSSQ may have the same potential as the power potentials VDD and VSS supplied to the power terminals 25, 27, respectively.

[0032] Specifically, power potentials (e.g., VDD, VPERI, VSS) may be supplied to the bandgap circuit 40. In some embodiments, the bandgap circuit 40 may output a constant (e.g., fixed) voltage (V bgr ) that is independent of process variations (e.g., circuit load), power supply variations, temperature changes, etc. In other words, V bgrThe voltage can be independent of PVT condition variations. Additionally or alternatively, the bandgap circuit 40 can output a constant (e.g., fixed) current (Iptat) that is independent of process variations, power supply variations, temperature changes, and so on. In other words, the Iptat current can be independent of PVT condition variations. The bandgap circuit 40 can generate various internal potentials VPP, VOD, VARY to supply to the circuit elements of the semiconductor device 10. For example, the internal potential VPP can be mainly used in the row decoder 12 and the reference current circuit 38, and the internal potentials VOD and VARY can be mainly used in the sense amplifiers 18 included in the memory cell array 11.

[0033] The supply potential can also be supplied to the body voltage generation circuit 42 to assist in tracking leakage current, mirroring the Iptat current, and generating a body voltage 43 to reduce the magnitude of the leakage current within the semiconductor device 10. For example, the semiconductor device 10 can include multiple power amplifiers, and the power amplifiers can in turn include transistors, such as PMOS transistors. When the semiconductor device 10 is in the off mode, due to the transistor physics, the PMOS transistors can generate leakage current. The leakage current can affect the voltage in parts of the circuitry of the semiconductor device 10, thereby reducing the performance of the semiconductor device 10, the service life of the circuit components, and / or adversely affecting the power consumption of the semiconductor device 10. Thus, the body voltage generation circuit 42 can be used to generate the body voltage 43 to reduce the magnitude of the leakage current. In some embodiments, the body voltage generation circuit 42 can transmit the body voltage 43 to one or more transistors within the semiconductor device 10 via routing (e.g., trace routing and / or edge routing).

[0034] Figure 2 Schematic diagram illustrating a PMOS transistor 52 that generates a leakage current 54 according to an embodiment of the present disclosure. As discussed above, the PMOS transistor 52 can generate a leakage current 54 during the off mode. Specifically, in the off mode, the amplifier can be deactivated by coupling the PMOS source terminal 56 and the PMOS gate terminal 58 to the supply terminal 25. Additionally, the drain terminal 60 can be tied to another voltage (e.g., 0V, ground, VSS, etc.) and the body terminal 62 can be coupled to the source terminal 56 and thus to the supply potential. However, due to the physics of the PMOS transistor 52, even when the PMOS transistor 52 is off, a relatively large leakage current (e.g., up to 300 μA) can flow at the drain terminal 60.

[0035] Figure 3Schematic diagram of an exemplary embodiment of a body voltage generation circuit 42 according to an embodiment of the present disclosure. The body voltage generation circuit 42 can generate a constant (e.g., fixed) body voltage 43 to supply to the body terminal of the PMOS 52. The body voltage generation circuit 42 can include a voltage generator circuit system 72, and the voltage generator circuit system 72 includes an amplifier 74, which is driven (e.g., powered) by a power supply potential provided by a power supply terminal 25 and generated outside the semiconductor device 10. Driving the amplifier 74 with the power supply potential can promote power savings compared to using an internally generated power supply potential (e.g., VPP), because the power supply potential generally has a lower voltage level compared to the internally generated power supply potential.

[0036] The amplifier 74 can receive the power supply potential at, for example, the positive input terminal 76 of the amplifier 74. In some embodiments, the power supply potential can be received at the negative input terminal 78 of the amplifier 74. Additionally, the amplifier 74 can also receive a feedback voltage (V fb ) 80 at the remaining input terminal, which is the negative input terminal 78 of the amplifier 74 in the illustrated embodiment. The output 82 of the amplifier 74 can be coupled to a PMOS cell 84, and the PMOS cell 84 provides the body voltage 43 to the PMOS transistor 52. The PMOS cell 84 can include a PMOS transistor 88, which has a source terminal 90 tied to a power supply potential 92 (e.g., VDD1), a gate terminal 94 tied to the output 82, and a drain terminal 96 tied to a voltage divider 98 and the body terminal 62 of the PMOS transistor 52. In some embodiments, the power supply potential 92 can be greater than the power supply potential provided by the power supply terminal 25. For example, the power supply potential 92 can be a certain amount (e.g., 0.1 - 0.9 volts) greater than VDD. For example, this difference between VDD and the power supply potential 92 can be equal to or greater than the threshold voltage of the PMOS transistor 88.

[0037] The negative input terminal 78 can be coupled to a voltage divider 98 that divides the body voltage 43 to generate Vfb 80. For example, the voltage divider 98 includes a first resistor 100 and a second resistor 102. The resistance value R1 of the first resistor 100 and / or the resistance value R2 of the second resistor 102 can be selected to provide a constant (e.g., fixed) body voltage 43 with an expected value (e.g., 1.0 - 1.9 volts), thereby setting the ratio between the body voltage 43 and Vfb 80. Due to the amplifier structure and the voltage divider 98, the node 104 coupling the output of the voltage divider 98 and the negative input terminal 78 can have the same potential as the power supply potential provided by the power supply terminal 25. That is, the feedback voltage (Vfb) 80 can have the same potential as VDD. If Vfb 80 varies from VDD, the amplifier 74 can correct such fluctuations.

[0038] Thus, by coupling the output 82 to the gate terminal 94 and tying the voltage divider 98 to the drain terminal 96, the voltage generation circuit 72 can be used as a voltage regulator to generate a constant (e.g., fixed) body voltage 43 for the body terminal 62 of the PMOS transistor 52. However, and as discussed above, the PMOS transistor of the amplifier can generate a leakage current 54 that can vary with process, the voltage applied to the transistor, the current flowing through the transistor, the ambient temperature, etc. Thus, a constant voltage amount technique that cannot track changes in the leakage current 54 may not sufficiently reduce the leakage current 54 under all testable PVT conditions at different process corners. Additionally or alternatively, because the constant voltage amount technique can increase the threshold voltage of the transistor, for at least some corners, the performance of the semiconductor device can be adversely affected. For example, a slow (SS) corner may have a different ideal threshold voltage compared to a fast (FF) corner. However, setting the threshold voltage for all corners to accommodate the slow corner can result in a reduced execution speed, additional power consumption, lower current, increased leakage at other corners, and / or other undesirable factors for the semiconductor device.

[0039] Figure 4Schematic diagram illustrating another exemplary embodiment of a body voltage generation circuit 42 that may facilitate tracking leakage current 54 attributed to PVT variations. The body voltage generation circuit 42 includes a voltage generator circuitry 106 that includes an amplifier 108 driven (e.g., powered) using a supply potential 92 generated external to the semiconductor device 10. The amplifier 108 may receive a reference voltage 110 as an input into, for example, the positive input terminal 112 of the amplifier 108. In some embodiments, the reference voltage 110 may be received at the negative input terminal 114 of the amplifier 108. The reference voltage 110 may be less than the supply potential provided by the supply terminal 25 and / or less than the supply potential 92. For example, the reference voltage 110 may be less than 1 volt (e.g., 0.9 volts, 0.8 volts, 0.7 volts). Additionally, the amplifier 108 may also receive a feedback voltage 116 at the remaining input terminal, which in this case is the negative input terminal 118 of the amplifier 108. The negative input terminal 118 may be coupled to a current mirror 120 (e.g., a bandgap current mirror processing circuitry) that has a mirrored current 122 that mirrors (e.g., tracks / emulates) a current 124 (e.g., a received current Iptat) received from the bandgap circuit 40 that is independent of process variations, supply variations, temperature changes, etc. Thus, the mirrored current 122 that mirrors the current 124 may also be independent of PVT condition variations. The current mirror 120 may include an NMOS transistor 128 having a source terminal tied to the supply terminal 25 and a drain terminal tied to another voltage (e.g., 0V, VSS, ground).

[0040] Thus, by mirroring the current 124 generated by the bandgap circuit 40 with the mirror current 122, the mirror current 122 can be independent of the PVT condition variations. The current mirror 120 may further include an NMOS transistor 130 having a gate terminal tied to the gate terminal of the NMOS transistor 128 and a drain terminal tied to a common return line (e.g., 0V, VSS, ground). The node 126 may be coupled to the source terminal of the NMOS transistor 130, may be coupled to the negative input terminal 118 of the amplifier 108, and / or may be coupled to the drain terminal 60 of the PMOS transistor 52. The node 126 may provide the feedback voltage 116 to the negative input terminal 118 of the amplifier 108 based on the relationship between the mirror current 122 and the leakage current 54. Additionally or alternatively, the body voltage generation circuit 42 may generate the body voltage 43 based on the relationship between the mirror current 122 and the leakage current 54. For example, if the mirror current 122 is less than the leakage current 54, the excess current increases the feedback voltage 116. Thus, due to the increase in the feedback voltage 116 being higher than the reference voltage 110, the amplifier 108 increases the voltage level of its output 132. As another example, if the mirror current 122 is greater than the leakage current 54, more charge leaves the node 126 via the mirror current 122 compared to the charge entering the node 126 via the leakage current 54, resulting in a decrease in the feedback voltage 116. Thus, due to the decrease in the feedback voltage 116 being lower than the reference voltage 110, the amplifier 108 decreases the voltage level of its output 132. If the mirror current 122 is the same as the leakage current 54, the feedback voltage 116 remains similar to the reference voltage, and the output 132 remains unchanged.

[0041] The output 132 of the amplifier 108 may be coupled to the body voltage control circuitry 134, which provides the body voltage 43 to the PMOS transistor 52. The body voltage control circuitry 134 generates the body voltage 43 based on the relationship between the mirror current 122 and the leakage current 54. The body voltage control circuitry 134 may include a PMOS transistor 138 having a source terminal 140 tied to the power supply potential 92, a gate terminal 142 tied to the output 132, and a drain terminal 144 tied to the power supply terminal 25 via a resistor 145. The drain terminal 144 is also tied to the body terminal 64 of the PMOS transistor 52. In some embodiments, the power supply potential 92 may be greater than the power supply potential provided by the power supply terminal 25.

[0042] Thus, by coupling the output 132 to the gate terminal 142, tying the source terminal 140 to the power supply potential 92, and tying the drain terminal 144 to the power supply terminal 25, the voltage generator circuit system 106 can be used as a voltage regulator to generate different (e.g., not fixed) voltage levels for the body voltage 43 of the body terminal 62 of the PMOS transistor 52. For example, the voltage generator circuit system 106 can provide a body voltage 43 within a voltage range that is between the power supply potential provided by the power supply terminal 25 and the power supply potential 92 and includes the power supply potential provided by the power supply terminal 25 and the power supply potential 92.

[0043] In operation, the voltage generator circuit system 106 can generate the body voltage 43 based on the relationship between the leakage current 54 and the mirror current 122. For example, when the leakage current 54 is less than the mirror current 122, the feedback voltage 116 is pulled down below the reference voltage 110 (e.g., pulled down to 0V). Thus, the amplifier 108 functions similarly to a comparator and compares the potential at the positive terminal 112 (e.g., the reference voltage 110) with the potential at the negative terminal 118 (e.g., the feedback voltage 116). Consequently, since the reference voltage 110 is greater than the feedback voltage 116, the voltage level of the output 132 can be increased to or near the power supply potential 92. This increased level of the output 132 provided to the gate terminal 142 turns off the PMOS transistor 138. Thus, the power supply potential provided by the power supply terminal 25 is provided as the body voltage 43 to the body terminal 62 of the PMOS transistor 52. Similar to Figure 2 , in this scenario (e.g., leakage current 54 < mirror current 122, leakage current 54 < current 124), the body terminal 62 receives the same power supply potential as the source terminal 56. Thus, when the leakage current 54 is relatively small (e.g., less than the current 124), the power consumption of the semiconductor device 10 can be reduced because a large body voltage does not have to be used.

[0044] In another scenario, the leakage current 54 can be equal to or approximately equal to the mirror current 122. Thus, the feedback voltage 116 can have the same level as the reference voltage 110. Therefore, the amplifier 108 provides an output 132 having a voltage level equal to or less than the difference between the power supply potential 92 and the threshold voltage of the PMOS transistor 138. Consequently, the output 132 can turn on the PMOS transistor 138 to provide the body voltage 43 at a potential between the power supply potential 92 and the power supply potential provided by the power supply terminal 25 to the body terminal 62. Thus, the threshold voltage of the PMOS transistor 52 can be adjusted, and the leakage current 54 can be reduced. For example, the leakage current 54 can be reduced to generally match the mirror current 122 (e.g., within 0.2 mA of the mirror current 122).

[0045] In yet another scenario, when the leakage current 54 is significantly greater than the mirror current 122 (e.g., by 0.1 mA), the feedback voltage 116 is pulled up to the power supply potential provided by the power supply terminal 25. Thus, the amplifier 108 functions similarly to a comparator. Consequently, since the power supply potential at the negative input terminal 118 is greater than the analog reference voltage 110 at the positive input terminal 112, the output 132 is at a low voltage, e.g., 0 V. The output 132 turns on the PMOS transistor 138 and supplies the power supply potential 92 as the body voltage 43 to the body terminal 62 of the PMOS transistor 52. Thus, the threshold voltage of the PMOS transistor 52 can be adjusted and the leakage current 54 can be reduced. For example, the leakage current 54 can be reduced towards the mirror current 122. Consequently, the leakage current 54 can track the mirror current 122. In other words, the leakage current 54 can be independent of PVT variations.

[0046] Figure 5 A graph 150 showing the leakage current 54 and the temperature 154 in accordance with an embodiment of the present disclosure. Line 156 represents Figure 2 the leakage current 54 of the PMOS transistor 52 where Figure 2 the body voltage 43 of the PMOS transistor 52 is equal to the power supply potential provided by the power supply terminal 25. As shown, the leakage current 54 of line 156 continues to increase with the temperature 154.

[0047] Line 158 represents Figure 3 the leakage current 54 of the PMOS transistor 52 where Figure 3 the body voltage 43 of the PMOS transistor 52 is set at a constant level greater than the power supply potential provided by the power supply terminal 25. As shown, due to the higher body voltage potential applied to Figure 3 the PMOS transistor 52, the leakage current 54 of line 158 is lower than the leakage current 54 of line 156. However, as discussed above, the leakage current 54 of line 158 continues to increase with temperature increase and / or process variations.

[0048] Line 160 represents Figure 4 the leakage current 54 of the PMOS transistor 52, Figure 4 the body voltage 43 of the PMOS transistor 52 varies between the power supply potential provided by the power supply terminal 25 and the power supply potential 92 based on the leakage current 54 compared to a current independent of PVT. As shown, the leakage current 54 of line 160 increases with the temperature until the temperature of the PMOS transistor 52 reaches a first temperature T1. When the PMOS transistor 52 is at or above the first temperature, the leakage current 54 can be greater than the bandgap current. Thus, the body voltage generator circuit 42 (e.g., Figure 4The voltage generator circuitry 106) therein can provide a body voltage 43 at a potential greater than the supply potential provided by the supply terminal 25 and up to the supply potential 92. Accordingly, the leakage current 54 of line 160 then decreases and stabilizes near a first leakage current LC1. In some embodiments, the first leakage current LC1 can be substantially equal to the mirror current 122. As shown, when the temperature of the PMOS transistor 52 crosses a second temperature T2, the leakage current 54 of line 158 can be greater than the leakage current 54 of line 160.

[0049] Although Figure 5 a graph illustrating the leakage current 54 and temperature 154 is shown, any PVT variation can be graphically represented relative to the leakage current to show a similar behavior of the body voltage generation circuit 42. For example, a graph of the leakage current 54 and voltage can show that the leakage current 54 remains stable above a specific voltage for a PMOS transistor 52 of Figure 2 and 3 while the leakage current 54 continues to increase for a PMOS transistor 52 of Figure 4

[0050] Embodiments of the present disclosure relate to dynamically adjusting the leakage current 54 regardless of PVT variations. The body voltage generation circuit 42 can achieve automatic tracking of the PVT-independent current generated by the bandgap circuit 40, thereby achieving a reduction in the leakage current under PVT variations.

[0051] Although the present disclosure may have various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Indeed, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0052] The technologies presented and claimed herein are referenced and applied to substantial objects and specific instances of a practical nature, which substantially improve the technical field in an arguable manner and are thus not abstract, intangible, or purely theoretical. Further, if any claim appended to this specification contains one or more elements designated as "means for [performing][function]..." or "steps for [performing][function]...", then such elements are intended to be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim item containing elements designated in any other way, it is not intended that such elements be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. An apparatus, comprising: One or more power amplifiers configured to power components of the apparatus and including transistors; and A bandgap current mirror processing circuit system configured to generate a mirror current that mirrors a received current independent of process, voltage, and temperature (PVT); And A body voltage generator circuit, comprising: An amplifier, wherein the bandgap current mirror processing circuit system is coupled to an input terminal of the amplifier; And A body voltage control circuit system coupled to an output of the amplifier, wherein the body voltage control circuit system is configured to generate a body voltage at least in part based on a relationship between the mirror current and a leakage current leaking from the transistor.

2. The apparatus according to claim 1, comprising a node coupled to the bandgap current mirror processing circuit system and the transistor, wherein the node is configured to provide a feedback voltage to the input terminal of the amplifier at least in part based on the relationship between the mirror current and the leakage current.

3. The apparatus according to claim 2, wherein a second input terminal of the amplifier is configured to receive a reference voltage.

4. The apparatus according to claim 1, wherein the leakage current leaks from the transistor when the transistor of the one or more power amplifiers is in an off mode.

5. The apparatus according to claim 1, wherein the transistor comprises a P-channel metal oxide semiconductor (PMOS) transistor, wherein a gate terminal of the PMOS transistor and a source terminal of the PMOS transistor are connected to a voltage source, wherein a drain terminal of the PMOS transistor is coupled to the input terminal of the amplifier, wherein a body terminal of the PMOS transistor is coupled to the body voltage control circuit system, and wherein the body terminal is configured to receive the body voltage generated by the body voltage control circuit system.

6. The apparatus according to claim 1, wherein the bandgap current mirror processing circuit system comprises an N-channel metal oxide semiconductor (NMOS) transistor, wherein a gate terminal of the NMOS transistor is connected to a voltage source, wherein a drain terminal of the NMOS transistor is coupled to ground, and wherein a source terminal of the NMOS transistor is coupled to the input terminal of the amplifier.

7. The apparatus according to claim 1, wherein the body voltage control circuit system comprises a P-channel metal oxide semiconductor (PMOS) transistor, wherein a source terminal of the PMOS transistor is connected to a voltage source, wherein a gate terminal of the PMOS transistor is coupled to the output of the amplifier, and wherein a drain terminal of the PMOS transistor is coupled to the body voltage terminal of the transistor.

8. The apparatus according to claim 7, comprising a second voltage source, wherein the body voltage comprises a voltage range between the voltage source and the second voltage source.

9. The apparatus according to claim 8, wherein the voltage source is greater than the second voltage source.

10. A circuit system for generating a body voltage, comprising: A bandgap current mirror processing circuit system configured to generate a mirror current that mirrors a received current and is independent of process, voltage, and temperature (PVT). And A voltage generator circuit system coupled to the bandgap current mirror processing circuit system, wherein the voltage generator circuit system is configured to generate the body voltage for a transistor based at least in part on a relationship between the mirror current and a leakage current that occurs when the electronic device is in an off mode.

11. The circuit system of claim 10, comprising the transistor, wherein the leakage current includes a current flowing through the transistor when the electronic device is in the off mode.

12. The circuit system of claim 11, wherein the transistor includes a P-channel metal oxide semiconductor (PMOS) transistor, wherein a gate terminal of the PMOS transistor and a source terminal of the PMOS transistor are connected to a voltage source, wherein a drain terminal of the PMOS transistor is coupled to a feedback of the voltage generator circuit system, wherein a body terminal of the PMOS transistor is coupled to an output of the voltage generator circuit system, and wherein the body terminal is configured to receive the body voltage generated by the voltage generator circuit system.

13. The circuit system of claim 10, wherein the bandgap current mirror processing circuit system includes an N-channel metal oxide semiconductor (NMOS) transistor, wherein a gate terminal of the NMOS transistor is connected to a voltage source, wherein a drain terminal of the NMOS transistor is coupled to ground, and wherein a source terminal of the NMOS transistor is coupled to the voltage generator circuit system.

14. The circuit system of claim 10, wherein the voltage generator circuit system is configured to reduce the leakage current based on the relationship between the mirror current and the leakage current when the leakage current exceeds the mirror current.

15. A body voltage generation circuit, comprising: A bandgap current mirror processing circuit system configured to generate a mirror current that mirrors a received current and is independent of process, voltage, and temperature (PVT), wherein the mirror current is configured to discharge charge from a node configured to receive charge of a leakage current from a transistor; And A voltage generator circuit system, comprising: An amplifier, wherein the node is coupled to an input of the amplifier; And A body voltage control circuit system coupled to an output of the amplifier, wherein the body voltage control circuit system is configured to generate the body voltage based at least in part on the relationship between the mirror current and the leakage current.

16. The body voltage generation circuit of claim 15, wherein the transistor is part of one or more power amplifiers.

17. The body voltage generation circuit according to claim 15, wherein the body voltage control circuit system includes a P-channel metal oxide semiconductor (PMOS) transistor, wherein a source terminal of the PMOS transistor is connected to a voltage source, wherein a gate terminal of the PMOS transistor is coupled to the output of the amplifier, and wherein a drain terminal of the PMOS transistor is coupled to the body terminal of the transistor to supply the body voltage to the transistor.

18. The body voltage generation circuit according to claim 15, wherein the transistor includes a P-channel metal oxide semiconductor (PMOS) transistor, wherein a gate terminal of the PMOS transistor and a source terminal of the PMOS transistor are connected to a voltage source, wherein a drain terminal of the PMOS transistor is coupled to the node, wherein a body terminal of the PMOS transistor is coupled to the body voltage control circuit system, and wherein the body terminal is configured to receive the body voltage generated by the body voltage control circuit system.

19. The body voltage generation circuit according to claim 18, wherein the body voltage is equal to or greater than the voltage source.

20. The body voltage generation circuit according to claim 18, wherein the body voltage control circuit system is configured to generate the body voltage greater than the voltage source when the leakage current is greater than the mirror current.

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