A programmer for JTAG programming type OTP configuration chip

Abstract

The present application discloses a programmer for JTAG programming type OTP configuration chip, which relates to the field of semiconductor technology. The FPGA main control module in the programmer writes a set of data to be programmed into the register inside the configuration chip to be programmed through the JTAG programming interface of the programmer, and the FPGA main control module controls the voltage control module, and uses the first power supply interface and the second power supply interface of the programmer to provide the power supply voltage required for different programming stages to the configuration chip to be programmed through different power supply units inside the power supply module. The programmer is designed for the characteristics of the JTAG programming type OTP configuration chip, and through the cooperation of the internal FPGA main control module and the voltage control module, the consistency of the JTAG programming instruction and the burning voltage timing is achieved, and the efficient and stable programming of the JTAG programming type OTP configuration chip can be completed, which has important theoretical significance and engineering practice application value.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a programmer for a JTAG programming type OTP configuration chip. Background Art

[0002] As humans explore outer space, various aircraft are increasingly active in the vast universe. The precise movements of aircraft are the result of the interaction of various chips. Among them, storage chips, as one of many chips, play a vital role.

[0003] However, due to the presence of large doses of radiation in space, these radiations act on the chip, which will seriously affect the chip function and even cause device failure, resulting in immeasurable losses. Anti-fuse configuration chips have excellent radiation resistance and extremely high stability in space, so they play an irreplaceable role in the aerospace field. In the research process of anti-fuse configuration chips, the design of programmers is particularly important. At present, general-purpose programmers are mainly used to complete the programming of various anti-fuse configuration chips. However, due to the different characteristics and programming requirements of different anti-fuse configuration chips, the use of general-purpose programmers has certain limitations, and the stability and efficiency are not ideal. Summary of the invention

[0004] In view of the above problems and technical requirements, the applicant has proposed a programmer for JTAG programming type OTP configuration chip. The technical solution of this application is as follows:

[0005] A programmer for a JTAG programming type OTP configuration chip, the programmer comprising an FPGA main control module, a level conversion circuit, a power supply module and a voltage control module;

[0006] The IO port of the FPGA main control module is connected to the JTAG programming interface of the programmer through a level conversion circuit, the multiple power supply units in the power supply module are connected to the first power supply interface and the second power supply interface of the programmer through the voltage control module, and the FPGA main control module is connected to and controls the voltage control module;

[0007] The JTAG programming interface of the programmer is connected to the JTAG programming interface of the configuration chip to be programmed, the first power supply interface of the programmer is connected to the PEN programming high voltage pin of the configuration chip to be programmed, the second power supply interface of the programmer is connected to the VDD power supply pin of the configuration chip to be programmed, and the configuration chip to be programmed is a JTAG programming type OTP configuration chip;

[0008] The method for a programmer to program a configuration chip to be programmed includes: the FPGA main control module writes a group of data to be programmed into the register inside the configuration chip to be programmed through the JTAG programming interface of the programmer, and the FPGA main control module controls the voltage control module to provide the configuration chip to be programmed with the power supply voltage required for different programming stages by using the first power supply interface and the second power supply interface of the programmer through different power supply units inside the power supply module, wherein the group of data to be programmed includes an address signal and a data signal.

[0009] Its further technical solution is that the power supply module includes a first power supply unit, a second power supply unit, a third power supply unit and a fourth power supply unit, the first power supply unit and the second power supply unit are connected to the first power supply interface of the programmer through the voltage control module, and the third power supply unit and the fourth power supply unit are connected to the second power supply interface of the programmer through the voltage control module;

[0010] The voltage provided by the first power supply unit is V1, the voltage provided by the second power supply unit is V2, the voltage provided by the third power supply unit is V3, the voltage provided by the fourth power supply unit is V4, and V1>V2>V4, V2=V3.

[0011] Its further technical solution is that the method for the FPGA main control module to control the voltage control module includes:

[0012] In the signal writing stage, the FPGA main control module controls the voltage control module so that the V2 voltage is provided to the PEN programming high-voltage pin of the configuration chip to be programmed by the second power supply unit using the first power supply interface, and the V3 voltage is provided to the VDD power pin of the configuration chip to be programmed by the third power supply unit using the second power supply interface;

[0013] In the pre-charging stage, the FPGA main control module controls the voltage control module to switch to providing V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed by using the first power supply unit and the first power supply interface, and to keep providing V3 voltage to the VDD power pin of the configuration chip to be programmed by using the second power supply interface through the third power supply unit;

[0014] In the high-voltage programming stage, the FPGA main control module controls the voltage control module to keep providing the V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed using the first power supply interface through the first power supply unit, and keep providing the V3 voltage to the VDD power pin of the configuration chip to be programmed using the second power supply interface through the third power supply unit;

[0015] During the cooling stage, the FPGA main control module controls the voltage control module so that the first power supply unit and the second power supply unit are disconnected from the first power supply interface, and the fourth power supply unit uses the second power supply interface to provide V4 voltage to the VDD power pin of the configuration chip to be programmed.

[0016] A further technical solution is that the method for the programmer to program the configuration chip to be programmed further includes:

[0017] In the cooling stage, the FPGA master control module reads back the data to be programmed from the configuration chip to be programmed through the JTAG programming interface of the programmer to verify;

[0018] When the read-back verification fails, the programmer switches to using the first power supply interface to provide V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed, and uses the second power supply interface to provide V3 voltage to the VDD power pin of the configuration chip to be programmed, and reprograms the current set of programming data to the configuration chip to be programmed through the pre-charging stage and the high-voltage burning stage;

[0019] When the read back verification passes, the programmer continues to program the next set of programming data to the programming configuration chip.

[0020] A further technical solution is that the voltage control module includes a driving circuit, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube;

[0021] The output end of the first power supply unit is connected to the source of the first MOS tube, the output end of the second power supply unit is connected to the source of the second MOS tube, and the drain of the first MOS tube and the drain of the second MOS tube are both connected to the first power supply interface of the programmer;

[0022] The output end of the third power supply unit is connected to the source of the third MOS tube, the output end of the fourth power supply unit is connected to the source of the fourth MOS tube, and the drain of the third MOS tube and the drain of the fourth MOS tube are both connected to the second power supply interface of the programmer;

[0023] The driving circuit is connected to the gate of the first MOS tube, the gate of the second MOS tube, the gate of the third MOS tube and the gate of the fourth MOS tube. The FPGA main control module controls the on and off of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube through the driving circuit to change the voltage output by the first power supply interface and the second power supply interface of the programmer.

[0024] A further technical solution is that the FPGA main control module controls the four MOS tubes through the driving circuit, including:

[0025] In the signal writing stage, the second MOS tube and the third MOS tube are controlled to be turned on, and the first MOS tube and the fourth MOS tube are controlled to be turned off;

[0026] In the pre-charging stage and the high-voltage burning stage, the first MOS tube and the third MOS tube are controlled to be turned on, and the second MOS tube and the fourth MOS tube are controlled to be turned off;

[0027] In the cooling stage, the fourth MOS tube is controlled to be turned on, and the first MOS tube, the second MOS tube and the third MOS tube are controlled to be turned off.

[0028] A further technical solution is that the voltages provided by the four power supply units in the power supply module include: V1=9V, V2=V3=5V, V4=3.3V.

[0029] A further technical solution is that the level conversion circuit includes a first level conversion chip, a second level conversion chip, a third level conversion chip and a fourth level conversion chip:

[0030] The input end of the first level conversion chip is connected to an IO port of the FPGA main control module, and the output end is connected to the TMS pin in the JTAG programming interface of the programmer;

[0031] The input end of the second level conversion chip is connected to an IO port of the FPGA master control module, and the output end is connected to the TCK pin in the JTAG programming interface of the programmer;

[0032] The input end of the third level conversion chip is connected to an IO port of the FPGA master control module, and the output end is connected to the TDI pin in the JTAG programming interface of the programmer;

[0033] The input end of the fourth level conversion chip is connected to the TDO pin in the JTAG programming interface of the programmer, and the output end is connected to an IO port of the FPGA main control module.

[0034] Its further technical solution is that the programmer also includes an FPGA configuration chip connected to the FPGA main control module; the FPGA main control module is connected to the host computer and obtains the data to be programmed from the host computer, and the FPGA configuration chip provides a loading program for the FPGA main control module in a main string manner.

[0035] Its further technical solution is that the programmer also includes a USB to JTAG chip, the input end of the USB to JTAG chip is connected to the USB interface of the programmer, the output end of the USB to JTAG chip is connected to the IO port of the FPGA master control module, and the programmer is connected to the host computer through the USB interface.

[0036] The beneficial technical effects of this application are:

[0037] The present application discloses a programmer for JTAG programming type OTP configuration chip. The programmer is designed according to the characteristics of the JTAG programming type OTP configuration chip. Through the cooperation of the internal FPGA main control module and the voltage control module, the programmer realizes the consistency of the JTAG programming instruction and the PEN and VDD pin programming voltage timing during the programming and burning process of the JTAG programming type OTP configuration chip. The programmer can complete the efficient and stable programming of the JTAG programming type OTP configuration chip, which has important theoretical significance and engineering practice application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the connection structure between the programmer, the configuration chip to be programmed and the host computer in one embodiment of the present application.

[0039] Figure 2 It is a timing waveform diagram of a programming process of a programming configuration chip to be programmed using a programmer in one embodiment of the present application. DETAILED DESCRIPTION

[0040] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0041] The present application discloses a programmer for a JTAG programming type OTP configuration chip, wherein the programmer is used to program the configuration chip to be programmed, and the configuration chip to be programmed is a JTAG (Joint Test Action Group) programming type OTP (One Time Programmable) configuration chip.

[0042] This programmer is designed for the characteristics of JTAG programming OTP configuration chips. Please refer to Figure 1 As shown in the circuit structure diagram, the programmer includes an FPGA main control module, a level conversion circuit, a power supply module and a voltage control module. The programmer provides a JTAG programming interface, a first power supply interface V_PEN and a second power supply interface V_VDD. The JTAG programming interface of the programmer is connected to the JTAG programming interface of the configuration chip to be programmed, and the TMS pin, TCK pin, TDI pin and TDO pin in the JTAG programming interface of the programmer are respectively connected to the same pins in the JTAG programming interface of the configuration chip to be programmed. The first power supply interface V_PEN of the programmer is connected to the PEN programming high-voltage pin of the configuration chip to be programmed, and the second power supply interface V_VDD of the programmer is connected to the VDD power pin of the configuration chip to be programmed.

[0043] Inside the programmer:

[0044] The IO port of the FPGA main control module is connected to the JTAG programming interface provided by the programmer to the outside through a level conversion circuit. In one embodiment, the level conversion circuit includes a first level conversion chip T1, a second level conversion chip T2, a third level conversion chip T3 and a fourth level conversion chip T4. The input end of the first level conversion chip T1 is connected to an IO port of the FPGA main control module, and the output end is connected to the TMS pin in the JTAG programming interface of the programmer. The input end of the second level conversion chip T2 is connected to an IO port of the FPGA main control module, and the output end is connected to the TCK pin in the JTAG programming interface of the programmer. The input end of the third level conversion chip T3 is connected to an IO port of the FPGA main control module, and the output end is connected to the TDI pin in the JTAG programming interface of the programmer. The input end of the fourth level conversion chip T4 is connected to the TDO pin in the JTAG programming interface of the programmer, and the output end is connected to an IO port of the FPGA main control module.

[0045] The power supply module includes multiple power supply units for providing different voltage values. The multiple power supply units in the power supply module are connected to the first power supply interface V_PEN and the second power supply interface V_VDD of the programmer through the voltage control module. The FPGA main control module is connected to and controls the voltage control module.

[0046] In one embodiment, please refer to Figure 1 , the power supply module includes a first power supply unit P1, a second power supply unit P2, a third power supply unit P3 and a fourth power supply unit P4, the voltage provided by the first power supply unit P1 is V1, the voltage provided by the second power supply unit P2 is V2, the voltage provided by the third power supply unit P3 is V3, the voltage provided by the fourth power supply unit P4 is V4, and V1>V2>V4, V2=V3. In one embodiment, according to the actual programming and use requirements of the JTAG programming type OTP configuration chip, V1=9V, V2=V3=5V, V4=3.3V.

[0047] The first power supply unit P1 and the second power supply unit P2 are connected to the first power supply interface V_PEN of the programmer through a voltage control module, and the third power supply unit P3 and the fourth power supply unit P4 are connected to the second power supply interface V_VDD of the programmer through a voltage control module.

[0048] In one embodiment, the voltage control module includes a driving circuit, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4. The output end of the first power supply unit P1 is connected to the source of the first MOS tube M1, the output end of the second power supply unit P2 is connected to the source of the second MOS tube M2, and the drain of the first MOS tube M1 and the drain of the second MOS tube M2 are both connected to the first power supply interface V_PEN of the programmer. The output end of the third power supply unit P3 is connected to the source of the third MOS tube M3, the output end of the fourth power supply unit P4 is connected to the source of the fourth MOS tube M4, and the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4 are both connected to the second power supply interface V_VDD of the programmer.

[0049] The driving circuit connects the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4. The FPGA main control module controls the on and off of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 through the driving circuit to change the voltage output by the first power supply interface V_PEN and the second power supply interface V_VDD of the programmer.

[0050] In one embodiment, the driving circuit includes a first driving chip T5, a second driving chip T6, a third driving chip T7 and a fourth driving chip T8. The FPGA main control module is connected to the input ends of the four driving chips through four IO ports, the output end of the first driving chip T5 is connected to the gate of the first MOS tube M1, the output end of the second driving chip T6 is connected to the gate of the second MOS tube M2, the output end of the third driving chip T7 is connected to the gate of the third MOS tube M3, and the output end of the fourth driving chip T8 is connected to the gate of the fourth MOS tube M4.

[0051] The method for programming a configuration chip to be programmed by the programmer of the present application includes: the FPGA main control module writes a set of data to be programmed into the register inside the configuration chip to be programmed through the JTAG programming interface of the programmer, and the set of data to be programmed includes an address signal (Address) of the data to be written and a data signal (Data) to be written at the address signal. The FPGA main control module controls the voltage control module, and uses the first power supply interface V_PEN and the second power supply interface V_VDD of the programmer to provide the configuration chip to be programmed with the power supply voltage required for different programming stages through different power supply units inside the power supply module.

[0052] In one embodiment, the data to be programmed written by the programmer when programming the configuration chip to be programmed is stored inside the programmer, but in order to reduce the storage requirements of the programmer. Figure 1As shown, the programmer also includes an FPGA configuration chip connected to the FPGA main control module, the FPGA main control module is connected to the host computer and obtains the programming data required to be programmed in the configuration chip to be programmed from the host computer, and then writes the obtained programming data into the configuration chip to be programmed. The FPGA configuration chip provides a loader for the FPGA main control module in a master string manner. Among them, the programmer also includes a USB to JTAG chip, the input end of the USB to JTAG chip is connected to the USB interface of the programmer, the output end of the USB to JTAG chip is connected to the IO port of the FPGA main control module, and the programmer is connected to the host computer via the USB interface.

[0053] The programmer programs the configuration chip as follows. Please refer to Figure 2 The programming timing diagram shown:

[0054] (1) During the signal writing phase from time t0 to time t1, the FPGA main control module writes a set of data to be programmed into the register inside the configuration chip to be programmed through the JTAG programming interface of the programmer. The FPGA main control module controls the voltage control module so that the second power supply unit P2 uses the first power supply interface V_PEN to provide the V2 voltage to the PEN programming high voltage pin of the configuration chip to be programmed, and the third power supply unit P3 uses the second power supply interface V_VDD to provide the V3 voltage to the VDD power pin of the configuration chip to be programmed. The FPGA main control module controls the second MOS tube M2 and the third MOS tube M3 to be turned on through the driving circuit, and controls the first MOS tube M1 and the fourth MOS tube M4 to be turned off.

[0055] (2) In the pre-charging stage from time t1 to time t2, at time t1, the programmer has written the data to be programmed into the configuration chip to be programmed, so at time t1, the FPGA main control module controls the voltage control module to switch to providing the V1 voltage to the PEN programming high voltage pin of the configuration chip to be programmed through the first power supply unit P1 using the first power supply interface V_PEN, and maintaining the V3 voltage to the VDD power pin of the configuration chip to be programmed through the third power supply unit P3 using the second power supply interface V_VDD. Including: the FPGA main control module controls the first MOS tube M1 and the third MOS tube M3 to be turned on through the driving circuit, and controls the second MOS tube M2 and the fourth MOS tube M4 to be turned off.

[0056] (3) During the high-voltage programming phase from time t2 to time t3, the FPGA main control module controls the voltage control module to keep providing the V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed through the first power supply unit P1 using the first power supply interface V_PEN, and to keep providing the V3 voltage to the VDD power pin of the configuration chip to be programmed through the third power supply unit P3 using the second power supply interface V_VDD, thereby realizing high-voltage programming of the internal storage unit of the configuration chip to be programmed.

[0057] That is, in the high-voltage programming stage, the FPGA main control module controls to maintain the states of the MOS tubes unchanged, keeps the first MOS tube M1 and the third MOS tube M3 turned on, and controls the second MOS tube M2 and the fourth MOS tube M4 to be turned off.

[0058] (4) In the cooling stage from time t3 to time t4, the FPGA main control module controls the voltage control module so that the first power supply unit P1 and the second power supply unit P2 are both disconnected from the first power supply interface V_PEN, and the V4 voltage is provided to the VDD power supply pin of the to-be-programmed configuration chip through the fourth power supply unit P4 using the second power supply interface V_VDD. This includes: the FPGA main control module controls the fourth MOS tube M4 to be turned on through the driving circuit, and controls the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 to be turned off. This causes the PEN programming high-voltage pin of the to-be-programmed configuration chip to drop from V1 to 0V, and the VDD power supply pin to drop from V3 to V4.

[0059] In addition, during the cooling stage, the FPGA master control module also reads back the programming data from the configuration chip to be programmed through the JTAG programming interface of the programmer to determine whether the programming data is correctly burned. When the read-back verification fails, the programmer switches to using the first power supply interface to provide the V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed, and uses the second power supply interface to provide the V3 voltage to the VDD power pin of the configuration chip to be programmed, and reprograms the current set of programming data for the configuration chip to be programmed through the pre-charging stage and the high-voltage burning stage. When the read-back verification passes, the programmer continues to program the next set of programming data for the configuration chip to be programmed.

[0060] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A programmer for a JTAG programming type OTP configuration chip, characterized in that: The programmer includes an FPGA main control module, a level conversion circuit, a power supply module and a voltage control module; The IO port of the FPGA main control module is connected to the JTAG programming interface of the programmer through the level conversion circuit, the multiple power supply units in the power supply module are connected to the first power supply interface and the second power supply interface of the programmer through the voltage control module, and the FPGA main control module is connected to and controls the voltage control module; The JTAG programming interface of the programmer is connected to the JTAG programming interface of the configuration chip to be programmed, the first power supply interface of the programmer is connected to the PEN programming high-voltage pin of the configuration chip to be programmed, and the second power supply interface of the programmer is connected to the VDD power pin of the configuration chip to be programmed, and the configuration chip to be programmed is a JTAG programming type OTP configuration chip; The method for programming the configuration chip to be programmed by the programmer comprises: the FPGA main control module writes a group of data to be programmed into the register inside the configuration chip to be programmed through the JTAG programming interface of the programmer, and the FPGA main control module controls the voltage control module to provide the configuration chip to be programmed with power supply voltages required for different programming stages by using the first power supply interface and the second power supply interface of the programmer through different power supply units inside the power supply module, wherein the group of data to be programmed includes an address signal and a data signal; The power supply module includes a first power supply unit, a second power supply unit, a third power supply unit and a fourth power supply unit, the first power supply unit and the second power supply unit are connected to the first power supply interface of the programmer through the voltage control module, and the third power supply unit and the fourth power supply unit are connected to the second power supply interface of the programmer through the voltage control module; wherein, the voltage provided by the first power supply unit is V1, the voltage provided by the second power supply unit is V2, the voltage provided by the third power supply unit is V3, the voltage provided by the fourth power supply unit is V4, and V1>V2>V4, V2=V3; The method for the FPGA main control module to control the voltage control module includes: in a signal writing stage, the FPGA main control module controls the voltage control module so that the second power supply unit uses the first power supply interface to provide a V2 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed, and the third power supply unit uses the second power supply interface to provide a V3 voltage to the VDD power pin of the configuration chip to be programmed; in a pre-charging stage, the FPGA main control module controls the voltage control module so that it switches to using the first power supply unit to provide a V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed using the first power supply interface, and keeps using the third power supply unit to provide a V3 voltage to the VDD power pin of the configuration chip to be programmed using the second power supply interface. The VDD power pin of the configuration chip to be programmed provides a V3 voltage; in the high-voltage burning stage, the FPGA main control module controls the voltage control module to keep providing the V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed through the first power supply unit using the first power supply interface, and keeps providing the V3 voltage to the VDD power pin of the configuration chip to be programmed through the third power supply unit using the second power supply interface; in the cooling stage, the FPGA main control module controls the voltage control module so that the first power supply unit and the second power supply unit are both disconnected from the first power supply interface, and provides the V4 voltage to the VDD power pin of the configuration chip to be programmed through the fourth power supply unit using the second power supply interface.

2. The programmer for the JTAG programming type OTP configuration chip according to claim 1, characterized in that: The method for the programmer to program the configuration chip to be programmed also includes: In the cooling stage, the FPGA master control module reads back and verifies the data to be programmed from the configuration chip to be programmed through the JTAG programming interface of the programmer; When the read-back verification fails, the programmer switches to using the first power supply interface to provide a V1 voltage to the PEN programming high-voltage pin of the configuration chip to be programmed, and uses the second power supply interface to provide a V3 voltage to the VDD power pin of the configuration chip to be programmed, and reprograms the current set of programming data for the configuration chip to be programmed through the pre-charging stage and the high-voltage burning stage; When the read-back verification passes, the programmer continues to program the next set of programming data to the configuration chip to be programmed.

3. The programmer for the JTAG programming type OTP configuration chip according to claim 1, characterized in that: The voltage control module includes a driving circuit, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; The output end of the first power supply unit is connected to the source of the first MOS tube, the output end of the second power supply unit is connected to the source of the second MOS tube, and the drain of the first MOS tube and the drain of the second MOS tube are both connected to the first power supply interface of the programmer; The output end of the third power supply unit is connected to the source of the third MOS tube, the output end of the fourth power supply unit is connected to the source of the fourth MOS tube, and the drain of the third MOS tube and the drain of the fourth MOS tube are both connected to the second power supply interface of the programmer; The driving circuit is connected to the gate of the first MOS tube, the gate of the second MOS tube, the gate of the third MOS tube and the gate of the fourth MOS tube. The FPGA main control module controls the on and off of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube through the driving circuit to change the voltage output by the first power supply interface and the second power supply interface of the programmer.

4. The programmer according to claim 3, characterized in that: The method for controlling four MOS tubes by the FPGA main control module through the driving circuit includes: In the signal writing stage, the second MOS tube and the third MOS tube are controlled to be turned on, and the first MOS tube and the fourth MOS tube are controlled to be turned off; In the pre-charging stage and the high-voltage programming stage, the first MOS tube and the third MOS tube are controlled to be turned on, and the second MOS tube and the fourth MOS tube are controlled to be turned off; In the cooling stage, the fourth MOS tube is controlled to be turned on, and the first MOS tube, the second MOS tube and the third MOS tube are controlled to be turned off.

5. The programmer according to claim 1, characterized in that: The voltages provided by the four power supply units in the power supply module include: V1=9V, V2=V3=5V, and V4=3.3V.

6. The programmer according to claim 1, characterized in that: The level conversion circuit includes a first level conversion chip, a second level conversion chip, a third level conversion chip and a fourth level conversion chip: The input end of the first level conversion chip is connected to an IO port of the FPGA master control module, and the output end is connected to the TMS pin in the JTAG programming interface of the programmer; The input end of the second level conversion chip is connected to an IO port of the FPGA master control module, and the output end is connected to the TCK pin in the JTAG programming interface of the programmer; The input end of the third level conversion chip is connected to an IO port of the FPGA main control module, and the output end is connected to the TDI pin in the JTAG programming interface of the programmer; The input end of the fourth level conversion chip is connected to the TDO pin in the JTAG programming interface of the programmer, and the output end is connected to an IO port of the FPGA main control module.

7. The programmer according to claim 1, characterized in that: The programmer also includes an FPGA configuration chip connected to the FPGA main control module; the FPGA main control module is connected to a host computer and obtains data to be programmed from the host computer, and the FPGA configuration chip provides a loading program for the FPGA main control module in a main string manner.

8. The programmer according to claim 7, characterized in that: The programmer also includes a USB to JTAG chip, the input end of the USB to JTAG chip is connected to the USB interface of the programmer, the output end of the USB to JTAG chip is connected to the IO port of the FPGA master control module, and the programmer is connected to the host computer via the USB interface.

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