A CoaXPress link performance detection method and system based on FPGA

Abstract

The present invention proposes a CoaXPress link performance detection method and system based on FPGA, which includes: configuring a test instruction for the link where each CXP cable is located according to the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable; starting the PoCXP function test and data transmission function test of the link unit to be tested in sequence according to the test instruction; obtaining the PoCXP power supply voltage value according to the PoCXP function test and judging whether the PoCXP function is normal; obtaining processed data and temporarily stored data according to the data transmission function test and judging whether the data transmission function is normal; and displaying the final test result. The present invention designs a CXP link performance test circuit that integrates a PoCXP function test circuit and a data transmission performance test circuit, and the CXP link performance test circuit is controlled by a host computer, thereby realizing automatic completion of a complete test of the CXP link performance and improving test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of data transmission testing, and in particular to a CoaXPress link performance detection method and system based on FPGA. Background Art

[0002] With the advancement of technology, the demand for high-speed, high-precision machine vision inspections is placing increasing demands on the resolution and frame rate of industrial cameras, necessitating higher data bandwidth for image transmission. CoaxPress (CXP), the world's leading high-speed imaging standard for professional and industrial imaging applications, combines the simplicity of coaxial cables with state-of-the-art high-speed serial data technology to achieve data transmission rates on the order of 10Gbps, effectively meeting these demands. With the application of the CXP protocol standard in signal transmission links, the need for performance testing of these links has also emerged.

[0003] A CXP link uses a single coaxial cable to transmit low-speed upstream signals and high-speed downstream signals between the host and device. The host can also power the device through the cable (this feature is called PoCXP, or Power over CoaXPress). Therefore, a complete CXP link test includes both data signal transmission testing and PoCXP functional testing.

[0004] The current method for testing CoaXPress link performance involves directly connecting a CoaXPress device (camera) to a CoaXPress host (capture card). This requires manually switching the CoaXPress device's power supply mode to PoCXP. Verifying the link's PoCXP power supply functionality can be done by checking the device's operation or by using an external device such as an oscilloscope or multimeter to measure voltage. The host's connection scan results confirm the link's uplink low-speed signal transmission performance. Image data transmission performance can also be tested by manually adjusting the capture card and camera parameters to achieve specific test conditions. Furthermore, the CXP protocol has multiple link data signal transmission rate standards, and the CXP cable interfaces used for each standard vary. Therefore, testing CXP links with different rate standards requires using a CoaXPress camera that meets the corresponding signal transmission rate standard.

[0005] In summary, the shortcomings of the existing technology are as follows:

[0006] During the PoCXP functional test, the actual power supply current required for camera operation does not reach the upper limit specified in the CXP protocol, resulting in the test results not fully reflecting the PoCXP functional performance of the CXP link.

[0007] Implementing data transmission tests under certain specific or extreme conditions requires cumbersome operations.

[0008] It is not compatible with CXP links of multiple rates. To test CXP links of different rates, you need to replace the camera with the corresponding rate.

[0009] The large amount of manual operations and frequent equipment replacement during testing lead to low testing efficiency and make it difficult to meet the needs of actual production testing. Summary of the Invention

[0010] The present invention proposes a CoaXPress link performance detection method and system based on FPGA, which can solve at least one of the above technical problems.

[0011] To achieve the above objectives, the present invention proposes the following technical solutions:

[0012] A CoaXPress link performance detection method based on FPGA, comprising:

[0013] Configure the test instructions for the link where each CXP cable is located based on the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable;

[0014] According to the test instructions, the PoCXP function test and the data transmission function test of the link unit to be tested are started in sequence;

[0015] The PoCXP functional test includes simulating a working state in which PoCXP provides a maximum power supply current, and monitoring a PoCXP power supply voltage value of the link unit under test in the simulated working state;

[0016] The data transmission function test includes generating a plurality of test data containing different code values and different effective data rates, and sending the test data to the link unit under test; the link unit under test obtains the processed data and temporarily stores the data;

[0017] According to the PoCXP power supply voltage value, determine whether the PoCXP function is normal; according to the processed data and the temporarily stored data, determine whether the data transmission function is normal; according to the determination results of the PoCXP function and the data transmission function, obtain the final test result.

[0018] Furthermore, before configuring the test instructions for the link where each CXP cable is located based on the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable, the method further includes: the link unit to be tested sends a low-speed signal through the CXP cable to obtain a response result; based on the response result, determining whether the low-speed signal transmission function of the link where the CXP cable is located is normal and whether the connection of the link where the CXP cable is located is normal.

[0019] Furthermore, the PoCXP functional test further includes simulating a working state of PoCXP switch control and simulating a working state of PoCXP providing power supply currents of different magnitudes, and monitoring a PoCXP power supply voltage value of the link unit under test in the simulated working state.

[0020] Furthermore, the effective data rate is the ratio of the amount of effective data actually transmitted to the total amount of data transmitted in any CXP link.

[0021] Furthermore, judging whether the PoCXP function is normal according to the PoCXP power supply voltage value includes: comparing the PoCXP power supply voltage value with a preset voltage range in the simulated working state; if the PoCXP power supply voltage value is within the preset voltage range, the PoCXP function is normal; otherwise, it is abnormal.

[0022] Furthermore, judging whether the data transmission function is normal based on the processed data and the temporarily stored data includes: obtaining CRC check information and link connection loss information by reading the processed data; obtaining verification information by checking the temporarily stored data; and comprehensively judging whether the data transmission function is normal based on the CRC check information, link connection loss information and the verification information.

[0023] On the other hand, the present invention also proposes a CoaXPress link performance detection system based on FPGA, comprising:

[0024] The link unit to be tested includes several CXP cables and a link module to be tested; one end of the link module to be tested is connected to the CXP cable interface of the test board via the CXP cable; the other end of the link module to be tested is connected to the host computer; the link unit to be tested is used to send a low-speed signal to verify the connection of the link where the CXP cable is located; and is also used to receive, process and temporarily store test data sent by the test board, obtain processed data and temporarily stored data, and send them to the host computer.

[0025] A test board including several CXP cable interfaces and several CXP link performance test circuits; each CXP link performance test circuit includes a data transmission test circuit and a PoCXP test circuit;

[0026] The data transmission test circuit is configured to receive a low-speed signal sent by the link unit under test, generate a plurality of test data containing different code values and different effective data rates, and send the test data to the link unit under test; and the PoCXP function test circuit is configured to simulate the working state of PoCXP, monitor the PoCXP voltage value of the link unit under test in the simulated working state, and feed back the PoCXP voltage value to the host computer.

[0027] Furthermore, it also includes:

[0028] The host computer is used to configure test instructions for the link where each CXP cable is located and send the test instructions to the test board; the host computer is also used to receive the PoCXP power supply voltage value and determine whether the PoCXP function is normal by comparing the PoCXP power supply voltage value with a preset voltage range under the simulated working state; the host computer is also used to receive the processed data and temporarily stored data, and determine whether the data transmission function is normal by reading the processed data and verifying the temporarily stored data; the host computer is also used to display the final test result.

[0029] Furthermore, the plurality of CXP cable interfaces correspond to a plurality of signal transmission rate standards, and a plurality of CXP cable interfaces that comply with any signal transmission rate standard are provided.

[0030] Furthermore, the test board further includes:

[0031] FPGA chip, used to realize the functions of the above test board;

[0032] FLASH chip, used to store the configuration information of the FPGA chip.

[0033] The beneficial effects of the present invention are as follows:

[0034] The test board proposed in the present invention is provided with a link test circuit that integrates a PoCXP functional test circuit and a data transmission performance test circuit, and the link test circuit is controlled by a host computer, which not only simplifies the CXP link performance test process and realizes the automatic completion of the CXP link performance test, but also can quickly and completely complete the CXP link performance test, thereby improving the test efficiency.

[0035] The PoCXP function test circuit proposed in the present invention solves the problem that actual cameras cannot fully test the PoCXP function of the CXP link by simulating different PoCXP operating states, especially simulating the operating state where PoCXP provides maximum power supply current, and realizes complete testing of the PoCXP function of the CXP link.

[0036] The data transmission performance test circuit proposed in the present invention can transmit test data containing different code values and different effective data rates, so as to realize the data transmission performance test of the CoaXPress link under the conditions of specific code values and transmission speed limits.

[0037] The test board proposed in the present invention is provided with several CXP interfaces corresponding to different signal transmission rate standards. The tester can conveniently connect the cable to the test equipment by selecting the corresponding cable according to the signal transmission rate standard of the CXP link to be tested, without having to change the test equipment, and can test multiple rates and multiple CXP links at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the test system of the present invention;

[0039] Figure 2 It is a schematic structural diagram of the test board of the present invention;

[0040] Figure 3 is a schematic diagram of a test circuit of the present invention;

[0041] Figure 4 This is a schematic diagram of the operation of the FPGA of the present invention in the PoCXP functional test circuit;

[0042] Figure 5 This is a schematic diagram of the operation of the FPGA of the present invention in a data transmission test circuit;

[0043] Figure 6 It is a schematic diagram of the test software of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0045] The present invention proposes a CoaXPress link performance detection method based on FPGA, comprising:

[0046] Configure the test instructions for the link where each CXP cable is located based on the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable;

[0047] According to the test instructions, the PoCXP function test and the data transmission function test of the link unit to be tested are started in sequence;

[0048] The PoCXP functional test includes simulating a working state in which PoCXP provides a maximum power supply current, and monitoring a PoCXP power supply voltage value of the link unit under test in the simulated working state;

[0049] The data transmission function test includes generating a plurality of test data containing different code values and different effective data rates, and sending the test data to the link unit under test; the link unit under test obtains the processed data and temporarily stores the data;

[0050] According to the PoCXP power supply voltage value, determine whether the PoCXP function is normal; according to the processed data and the temporarily stored data, determine whether the data transmission function is normal; according to the test judgment results of the PoCXP function and the data transmission function, obtain the final test result.

[0051] Among them, according to the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable, before configuring the test instructions for the link where each CXP cable is located, it also includes: the link unit to be tested sends a low-speed signal through the CXP cable to obtain a response result; based on the response result, it is determined whether the low-speed signal transmission function of the link where the CXP cable is located is normal and whether the connection of the link where the CXP cable is located is normal.

[0052] The PoCXP functional test further includes simulating the working state of PoCXP switch control and simulating the working state of PoCXP providing power supply currents of different sizes, and monitoring the PoCXP power supply voltage value of the link unit under test in the simulated working state.

[0053] The effective data rate is the ratio of the amount of effective data actually transmitted to the total amount of data transmitted in any CXP link.

[0054] The step of determining whether the PoCXP function is normal according to the PoCXP power supply voltage value includes: comparing the PoCXP power supply voltage value with a preset voltage range in the simulated working state; if the PoCXP power supply voltage value is within the preset voltage range, the PoCXP function is normal; otherwise, the PoCXP function is abnormal.

[0055] Among them, judging whether the data transmission function is normal based on the processed data and the temporarily stored data includes: obtaining CRC check information and link connection loss information by reading the processed data; and obtaining verification information by checking the temporarily stored data.

[0056] Whether the data transmission function is normal is comprehensively judged based on the CRC check information, the link connection loss information and the verification information.

[0057] like Figure 1 As shown, the present invention also proposes a CoaXPress link performance detection system based on FPGA, which includes: a link unit to be tested, a host computer and a test board.

[0058] The link unit to be tested includes several CXP cables and a link module to be tested; one end of the link module to be tested is connected to the CXP cable interface of the test board via the CXP cable; the other end of the link module to be tested is connected to the host computer; the link unit to be tested is used to send a low-speed signal to verify the connection of the link where the CXP cable is located; and is also used to receive and temporarily store test data sent by the test board, obtain processed data and temporarily stored data, and send them to the host computer.

[0059] like Figure 2 As shown, the test board includes several CXP cable interfaces, several CXP link performance test circuits, an FPGA chip, a FLASH chip, a crystal oscillator, and a power supply circuit. Several CXP cable interfaces correspond to various signal transmission rate standards, and multiple CXP cable interfaces that meet any signal transmission rate standard are provided. The FPGA chip implements the test board's functions; the FLASH chip stores FPGA chip configuration information; the power supply circuit converts the external power supply voltage into the required supply voltage for the FPGA and FLASH chips; and the crystal oscillator provides the FPGA chip with the required clock signal.

[0060] like Figure 3 As shown, any CXP link performance test circuit includes a data transmission test circuit and a PoCXP test circuit.

[0061] The PoCXP functional test circuit includes simulating the PoCXP operating state, monitoring the PoCXP voltage value of the link unit under test in the simulated operating state, and feeding back the PoCXP voltage value to the host computer. The simulated operating state includes simulating the operating state of PoCXP providing maximum power supply current, which enables the measurement of the extreme performance of PoCXP power supply under extreme test conditions and fully tests the PoCXP function of the CXP link. Furthermore, the simulated operating state also includes simulating the operating state of PoCXP switch control and simulating the operating state of PoCXP providing different power supply currents.

[0062] like Figure 4As shown, the working principle of the FPGA in the PoCXP function test circuit in this embodiment is as follows: the test board receives the test instructions configured by the host computer, and the FPGA configures the PoCXP working state control signal generation module according to the test instructions. The PoCXP working state control signal generation module generates a control signal and sends it to the PoCXP working state control circuit; and simulates the working state of the PoCXP power supply function. At the same time, the PoCXP power supply voltage monitoring circuit monitors the PoCXP voltage value of the link unit under test in the simulated working state, and transmits the voltage signal to the built-in ADC of the FPGA through the analog signal input pin. The built-in ADC samples the real-time voltage value of the PoCXP power supply and feeds it back to the host computer to determine whether the PoCXP power supply function is normal. Among them, the simulated working state includes simulating the working state of PoCXP providing the maximum power supply current, simulating the working state of PoCXP switch control, and simulating the working state of PoCXP providing different power supply currents. This achieves the measurement of the extreme performance of PoCXP power supply under extreme test conditions and fully tests the PoCXP function of the CXP link.

[0063] The data transmission test circuit generates test data containing different code values and effective data rates, and sends the test data to the link unit under test. The FPGA enables the parallel generation and transmission of multi-channel, multi-rate test data, with each channel operating independently, enabling simultaneous testing of the data transmission performance of multiple, multi-rate CXP links. Furthermore, the FPGA can generate test data containing different code values and effective data rates to meet different test conditions, particularly those for CXP links transmitting error-prone code values and data at the maximum effective data rate, facilitating data transmission testing of CXP links.

[0064] like Figure 5 As shown, the working principle of the FPGA in the data transmission test circuit in this embodiment is as follows: the test board receives the test instructions configured by the host computer, configures each channel of the FPGA high-speed serial transceiver according to the test instructions, so that the high-speed signal rate sent by each channel matches the link where the CXP cable is located, and at the same time, the transmission working clock generated by the high-speed transceiver of each channel is led to the corresponding test data generation module; the test data generation module generates test data according to this clock and transmits the test data to the high-speed transceiver; the high-speed transceiver sends the test data. The design of the data transmission test circuit of the present invention ensures that the test data generation speed and transmission speed of each channel match, and realizes that the rate of test data transmission of each link is independently adjustable; at the same time, each test channel works independently, realizing the simultaneous testing of the data transmission performance of multiple CXP links with multiple rates.

[0065] like Figure 6As shown, the test software (test instructions) for the link where each CXP cable is located configured by the host computer includes test interface selection, link connection, test start, result display and test close. Among them, the test interface selection is used to select the CXP cable interface of the test board to which the CXP cable is connected, so as to facilitate the configuration of the corresponding test instructions; the link connection is used to realize the communication connection between the host computer and the test board, and perform the connection test of the CXP link; the test start is used to start the automated test process; the result display shows that the corresponding result will be displayed in the software interface after each functional test is completed; the test is closed, and clicking on the test close can clear the test result and disconnect the communication connection between the host computer and the test board. The present invention realizes the automated operation of the CXP link performance test by using the host computer to control the test board, and only by clicking on the software process of the host computer, and the host computer directly displays the test results, thereby improving the test efficiency.

[0066] The detection process of the detection system of the present invention is as follows:

[0067] Based on the known signal transmission rate standard of the CXP cable in the link unit to be tested, the CXP cable selects a CXP cable interface on the test board that matches it, so that the link unit to be tested is connected to the test board.

[0068] Based on the known number of CXP cables in the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable, the host computer configures the test instructions for the link where each CXP cable is located, and controls the test board to test the PoCXP function test and data transmission function test of the link unit to be tested.

[0069] The link unit to be tested sends a low-speed signal to the test board through the link where any CXP cable is located. The test board recognizes the low-speed signal and feeds back a response message to the host computer. The host computer receives and processes the response message and displays the judgment result. If the host computer displays "connected correctly", it indicates that the low-speed signal transmission function of the link where the CXP cable is located is normal, and the connection of the link where the CXP cable is located is normal. The host computer passes the verification and can send a test instruction. Otherwise, the verification fails.

[0070] The host computer sends a set test process instruction to the test board to control the test board to start the CXP link performance test, which includes a data transmission test and a PoCXP power supply test.

[0071] The data transmission test circuit test specifically includes: the test board receives the test instructions sent by the test board, generates a number of test data containing different code values and different effective data rates, and sends the test data to the link unit to be tested; the link unit to be tested receives and temporarily stores the test data, and sends the processed data and temporarily stored data to the host computer.

[0072] The host computer receives and reads the processed data to obtain CRC check information and link connection loss information; the host computer receives the temporarily stored data and verifies the temporarily stored data according to the generation conditions of the test data generated by the test board to obtain verification information; based on the CRC check information, the link connection loss information and the verification information, it is comprehensively judged whether the data transmission function is normal.

[0073] The PoCXP power supply test specifically includes: the test board receives the test instruction sent by the test board, simulates the working state of PoCXP providing maximum power supply current, simulates the working state of PoCXP switch control, and simulates the working state of PoCXP providing power supply currents of different sizes, monitors the PoCXP power supply voltage value of the link unit to be tested in any simulated working state, and feeds back to the host computer.

[0074] Preferably, the PoCXP power supply test in this embodiment further includes: dividing the monitored PoCXP power supply voltage value, inputting the divided voltage signal into the FPGA through the analog signal input pin of the FPGA, obtaining the real-time voltage value of the PoCXP power supply through the built-in ADC of the FPGA and feeding it back to the host computer.

[0075] The host computer receives the PoCXP power supply voltage value, and determines whether the PoCXP function is normal by comparing the PoCXP power supply voltage value with a preset voltage range in the simulated working state.

[0076] The host computer displays the final test result according to the judgment result of the data transmission function and the judgment result of the PoCXP function, and the final test result is "test passed" or "test failed".

[0077] After the test is completed, the connection between the host computer and the test board is disconnected.

[0078] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A CoaXPress link performance detection method based on FPGA, characterized in that: include: The host computer configures the test instructions for each CXP cable link based on the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable, and sends the test instructions to the test board; The test board starts the PoCXP function test and data transmission function test of the link unit to be tested in sequence according to the test instructions; The PoCXP functional test includes simulating a working state in which PoCXP provides a maximum power supply current, monitoring a PoCXP power supply voltage value of the link unit under test in the simulated working state, and feeding back the PoCXP power supply voltage value to a host computer; The data transmission function test includes generating a plurality of test data containing different code values and different effective data rates, and sending the test data to the link unit under test; the link unit under test obtains the processed data and the temporarily stored data, and sends them to the host computer; A test board includes a plurality of CXP cable interfaces and a plurality of CXP link performance test circuits; the plurality of CXP cable interfaces correspond to a plurality of signal transmission rate standards, and a plurality of CXP cable interfaces that comply with any signal transmission rate standard are provided; The host computer determines whether the PoCXP function is normal according to the PoCXP power supply voltage value; the host computer determines whether the data transmission function is normal according to the processed data and the temporarily stored data; The host computer obtains the final test result based on the test results of the PoCXP function and the data transmission function.

2. The FPGA-based CoaXPress link performance detection method according to claim 1, characterized in that: Before configuring the test instructions for the link where each CXP cable is located based on the number of CXP cables that need to be connected to the link unit to be tested and the signal transmission rate standard corresponding to each CXP cable, the method further includes: the link unit to be tested sends a low-speed signal to the test board through the CXP cable, so that the test board feeds back a response result to the host computer; and the host computer determines, based on the response result, whether the low-speed signal transmission function of the link where the CXP cable is located is normal and whether the connection of the link where the CXP cable is located is normal.

3. The FPGA-based CoaXPress link performance detection method according to claim 1, characterized in that: The PoCXP functional test further includes simulating the working state of PoCXP switch control and simulating the working state of PoCXP providing power supply currents of different sizes, and monitoring the PoCXP power supply voltage value of the link unit to be tested in the simulated working state.

4. The FPGA-based CoaXPress link performance detection method according to claim 1, characterized in that: The effective data rate is the ratio of the amount of effective data actually transmitted to the total amount of data transmitted in any CXP link.

5. The FPGA-based CoaXPress link performance detection method according to claim 1, characterized in that: The host computer determines whether the PoCXP function is normal according to the PoCXP power supply voltage value, including: comparing the PoCXP power supply voltage value with a preset voltage range in the simulated working state; if the PoCXP power supply voltage value is within the preset voltage range, the PoCXP function is normal; otherwise, it is abnormal.

6. The FPGA-based CoaXPress link performance detection method according to claim 1, characterized in that: The host computer determines whether the data transmission function is normal based on the processed data and the temporarily stored data, including: the host computer obtains CRC check information and link connection loss information by reading the processed data; the host computer verifies the temporarily stored data and verifies the temporarily stored data according to the generation conditions of the test data generated by the test board to obtain verification information; and comprehensively determines whether the data transmission function is normal based on the CRC check information, the link connection loss information and the verification information.

7. A CoaXPress link performance detection system based on FPGA, characterized in that: include: The link unit to be tested includes several CXP cables and a link module to be tested; one end of the link module to be tested is connected to the CXP cable interface of the test board through the CXP cable; The other end of the link module to be tested is connected to the host computer; the link unit to be tested is used to send a low-speed signal to verify the connection of the link where the CXP cable is located; it is also used to receive, process and temporarily store the test data sent by the test board, obtain the processed data and the temporarily stored data, and send them to the host computer; A test board including several CXP cable interfaces and several CXP link performance test circuits; each CXP link performance test circuit includes a data transmission test circuit and a PoCXP function test circuit; Several CXP cable interfaces correspond to multiple signal transmission rate standards, and multiple CXP cable interfaces that comply with any signal transmission rate standard are provided; The data transmission test circuit is configured to receive a low-speed signal sent by the link unit under test, generate a plurality of test data containing different code values and different effective data rates, and send the test data to the link unit under test. The PoCXP function test circuit is configured to simulate the working state of PoCXP, monitor the PoCXP power supply voltage value of the link unit under test in the simulated working state, and feed back the PoCXP power supply voltage value to the host computer.

8. The FPGA-based CoaXPress link performance detection system according to claim 7, characterized in that: Also includes: The host computer is used to configure the test instructions of the link where each CXP cable is located and send the test instructions to the test board; The host computer is further configured to receive the PoCXP power supply voltage value, and determine whether the PoCXP function is normal by comparing the PoCXP power supply voltage value with a preset voltage range under the simulated working state; the host computer is further configured to receive the processed data and temporarily stored data, and determine whether the data transmission function is normal by reading the processed data and verifying the temporarily stored data; the host computer is further configured to display the final test result.

9. The FPGA-based CoaXPress link performance detection system according to claim 7, characterized in that: The test board also includes: FPGA chip, used to implement the functions of the test board as claimed in claim 7; FLASH chip, used to store the configuration information of the FPGA chip.

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