Memory device and manufacturing method and driving method thereof

Abstract

This application relates to the field of semiconductor manufacturing technology, and more particularly to a memory device and its manufacturing and driving methods. The memory device includes: a substrate; a stacked structure including a first gate layer, a second gate layer, and an interlayer isolation layer, the interlayer isolation layer being located between the first gate layer and the second gate layer, and between the first gate layer and the substrate; and a memory structure including a via penetrating the stacked structure and a channel structure filling the via. This application enables the memory device to be used as a non-volatile memory with different memory modes, thereby achieving the multi-functionality of the memory device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a memory device and its manufacturing method and driving method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] However, with the rapid development of the semiconductor industry, not only semiconductor companies are pursuing profit maximization, but consumers also expect semiconductor products to be multifunctional. However, existing memory devices have relatively simple functions due to their structural limitations.

[0004] Therefore, how to realize the functions of storage devices and thus expand their application areas is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The storage device and its manufacturing method and driving method provided in some embodiments of this application are used to solve the problem of the current storage device having limited functionality.

[0006] According to some embodiments, this application provides a storage device, including:

[0007] Substrate;

[0008] A stacked structure, the stacked structure including a first gate layer, a second gate layer and an interlayer isolation layer, the interlayer isolation layer being located between the first gate layer and the second gate layer, and between the first gate layer and the substrate;

[0009] The storage structure includes through-holes penetrating the stacked structure and channel structures filling the through-holes.

[0010] In some embodiments, the channel structure includes a tunneling layer covering the inner wall of the via, a charge trapping layer covering the surface of the tunneling layer, a ferroelectric layer covering the surface of the charge trapping layer, a buffer layer covering the surface of the ferroelectric layer, and a channel layer covering the surface of the buffer layer.

[0011] In some embodiments, the channel layer extends through the tunneling layer, the charge trapping layer, the ferroelectric layer, and the buffer layer at the bottom of the via, and the bottom surface of the channel layer contacts the substrate; the storage device further includes:

[0012] The drain electrode is in contact with the top surface of the channel layer.

[0013] In some embodiments, the channel structure also covers the top surface of the stacked structure;

[0014] The drain electrode penetrates the channel structure located on the top surface of the stacked structure.

[0015] In some embodiments, the number of the storage structures is multiple, and the multiple storage structures are arranged in an array along a first direction and a second direction.

[0016] In some embodiments, the first gate layer includes a plurality of first gate structures arranged in parallel and spaced apart along a second direction, and the second gate layer includes a plurality of second gate structures arranged in parallel and spaced apart along a second direction, the second gate structures being located above the first gate structures, and the plurality of memory structures arranged in parallel along the first direction sharing the first gate structure and the second gate structure.

[0017] In some embodiments, it also includes:

[0018] A separation structure extends through the stacked structure in a direction perpendicular to the top surface of the substrate and is located between two adjacent first gate structures and two adjacent second gate structures.

[0019] In some embodiments, the first gate structure is made of a metallic material, and the second gate structure is made of polycrystalline silicon.

[0020] According to other embodiments, this application also provides a method for manufacturing a storage device, comprising the following steps:

[0021] Provide substrate;

[0022] A stacked layer is formed, the stacked layer comprising a first interlayer isolation layer, a sacrificial layer, a second interlayer isolation layer, and a second gate layer sequentially stacked on the substrate;

[0023] The stacked layers are etched to form through-holes penetrating the stacked layers;

[0024] A channel structure is formed within the through hole;

[0025] The sacrificial layer is removed and replaced with a conductive material to form a first gate layer.

[0026] In some embodiments, the specific steps of forming a through-hole through the stacked layers include:

[0027] The stacked layer is etched to form a plurality of through-holes penetrating the stacked layer, and the plurality of through-holes are arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction.

[0028] In some embodiments, the specific steps of forming a channel structure within the through hole include:

[0029] A tunneling layer is formed on the inner wall of the through hole and the top surface of the stacked layer;

[0030] A charge trapping layer is formed on the surface of the tunneling layer;

[0031] A ferroelectric layer is formed on the surface of the charge trapping layer;

[0032] A buffer layer is formed on the surface of the ferroelectric layer;

[0033] A channel layer is formed on the surface of the buffer layer.

[0034] In some embodiments, the specific steps of forming a channel layer on the surface of the buffer layer include:

[0035] The buffer layer, the ferroelectric layer, the charge trapping layer, and the tunneling layer at the bottom of the via are etched to form a through-hole that exposes the substrate;

[0036] The channel layer is formed to fill the through holes and cover the surface of the buffer layer.

[0037] In some embodiments, the method further includes:

[0038] At least a portion of the channel structure located on the top surface of the stacked layer is etched to form a drain via that exposes the channel layer within the via.

[0039] The drain electrode is formed by filling the drain hole.

[0040] In some embodiments, the specific steps for forming the first gate layer include:

[0041] The stacked layer is etched to form a plurality of partition trenches arranged in parallel along the second direction and extending to the top surface of the first interlayer isolation layer. Each partition trench is located between two adjacent vias arranged in parallel along the second direction, so as to divide the second gate layer into a plurality of second gate structures arranged in parallel along the second direction.

[0042] The sacrificial layer is removed along the dividing groove to form a void region;

[0043] The first gate layer is formed by filling the gap region with conductive material along the partition groove.

[0044] In some embodiments, it also includes:

[0045] Remove all of the conductive material located within the partition groove;

[0046] An insulating material is filled into the partition groove to form a partition structure, which divides the first gate layer into a plurality of first gate structures arranged in parallel along the second direction.

[0047] In some embodiments, the first gate layer is made of a metal material, and the second gate layer is made of polycrystalline silicon.

[0048] According to other embodiments, this application also provides a method for driving a storage device as described in one of the preceding embodiments, comprising the following steps:

[0049] In the first storage mode, a first turn-on voltage is applied to the second gate layer, and a first storage voltage is applied to the first gate layer to write information to the ferroelectric layer;

[0050] In the second storage mode, a second turn-on voltage is applied to the second gate layer, and a second storage voltage is applied to the first gate layer to write information to the charge trapping layer.

[0051] In some embodiments, the following steps are also included:

[0052] In the first storage mode, a first read voltage is applied to the first gate layer to read the information stored in the ferroelectric layer;

[0053] In the second storage mode, a second read voltage is applied to the first gate layer to read information in the charge trapping layer.

[0054] In some embodiments, the following steps are also included:

[0055] In the first storage mode, a first erase voltage is applied to the first gate layer to erase the information stored in the ferroelectric layer;

[0056] In the second storage mode, a second erase voltage is applied to the first gate layer to erase the information stored in the charge trapping layer.

[0057] The storage device and its manufacturing and driving methods provided in some embodiments of this application, by setting a storage structure including a first gate layer, a second gate layer, and a stacked structure located between the first gate layer and the second gate layer and between the first gate layer and the substrate, and by setting a through-hole through the stacked structure and a channel structure filling the through-hole, enables the storage device to be used as a non-volatile memory with different storage modes, thereby realizing the multifunctionality of the storage device and expanding the application field of the storage device. Attached Figure Description

[0058] Appendix Figure 1A This is a cross-sectional schematic diagram of the storage device in a specific embodiment of this application;

[0059] Appendix Figure 1B This is a cross-sectional schematic diagram of the channel structure in a specific embodiment of this application;

[0060] Appendix Figure 2 This is a schematic diagram of the principle of the storage device used as a ferroelectric memory in a specific embodiment of this application.

[0061] Appendix Figure 3 This is a schematic diagram of the principle of the storage device used as a flash memory in a specific embodiment of this application;

[0062] Appendix Figure 4 This is a three-dimensional structural diagram of the storage device in a specific embodiment of this application;

[0063] Appendix Figure 5 This is a flowchart of the manufacturing method of the storage device in a specific embodiment of this application;

[0064] Appendix Figures 6A-6P This is a cross-sectional schematic diagram along the first direction of the main process steps in the manufacturing process of the storage device according to a specific embodiment of this application.

[0065] Appendix Figures 7A-7P This is a cross-sectional schematic diagram along the second direction of the main process steps in the manufacturing of the storage device according to a specific embodiment of this application.

[0066] Appendix Figure 8 This is a flowchart of the driving method for the storage device in a specific embodiment of this application. Detailed Implementation

[0067] The following detailed description, with reference to the accompanying drawings, describes the specific implementation methods of the storage device, its manufacturing method, and its driving method provided in this application.

[0068] This specific embodiment provides a storage device, with attachment Figure 1A This is a cross-sectional schematic diagram of the storage device in a specific embodiment of this application, attached. Figure 1BThis is a cross-sectional schematic diagram of the channel structure in a specific embodiment of this application, attached. Figure 2 This is a schematic diagram illustrating the principle of the storage device in a specific embodiment of this application when used as a ferroelectric memory. Figure 3 This is a schematic diagram illustrating the principle of the storage device used as a flash memory in a specific embodiment of this application, attached. Figure 4 This is a three-dimensional structural diagram of the storage device according to a specific embodiment of this application. For example... Figure 1A , Figure 1B , Figures 2-4 As shown, the storage device includes:

[0069] Substrate 10;

[0070] The stacked structure 11 includes a first gate layer 112, a second gate layer 114, and an interlayer isolation layer, wherein the interlayer isolation layer is located between the first gate layer 112 and the second gate layer 114, and between the first gate layer 112 and the substrate 10.

[0071] The storage structure 12 includes a through-hole penetrating the stacked structure 11 and a channel structure filling the through-hole.

[0072] Specifically, the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The interlayer isolation layer includes a first interlayer isolation layer 111 located between the first gate layer 112 and the substrate 10, and a second interlayer isolation layer 113 located between the first gate layer 112 and the second gate layer 114. The top surface of the via is flush with the top surface of the stacked structure 11 (i.e., the top surface of the second gate layer 114 in the stacked structure 11). When storing information using the storage device, by applying an enable voltage to the second gate layer 114, the channel structure connected to the first gate layer 112 can be opened; then, by applying a storage voltage to the first gate layer 112, information can be written. By adjusting the storage voltage applied to the first gate layer 112, information can be stored in different regions of the channel structure, thereby enabling the storage device to be used as both a ferroelectric memory (e.g., FeRAM) and a flash memory (e.g., NAND). In other words, the storage device can operate in two different storage modes, thus realizing the versatility of the storage device and expanding its application areas.

[0073] In some embodiments, the channel structure includes a tunneling layer 121 covering the inner wall of the through hole, a charge trapping layer 122 covering the surface of the tunneling layer 121, a ferroelectric layer 123 covering the surface of the charge trapping layer 122, a buffer layer 124 covering the surface of the ferroelectric layer 123, and a channel layer 125 covering the surface of the buffer layer 124.

[0074] Specifically, the tunneling layer 121, the charge trapping layer 122, the ferroelectric layer 123, the buffer layer 124, and the channel layer 125 are stacked sequentially along the inner wall of the via, pointing towards the center of the via. The tunneling layer 121 can be made of an oxide material, such as silicon dioxide. The charge trapping layer 122 can be made of silicon oxynitride, silicon nitride, silicon oxide composite material, or high-k dielectric composite material; in one embodiment, the charge trapping layer 122 is made of zinc silicon oxide (ZSO). The ferroelectric layer 123 can be made of hafnium oxide, zirconium oxide, lead zirconate titanate, or hafnium zirconium oxide (HZO); in one embodiment, the ferroelectric layer 123 is made of hafnium zirconium oxide. The buffer layer 124 can be made of an oxide material, such as silicon dioxide. The channel layer 125 can be made of polycrystalline silicon, silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). In one embodiment, the channel layer 125 is made of polycrystalline silicon.

[0075] like Figure 2 As shown, when the storage device provided in this specific embodiment is used as a non-volatile memory (FeRAM): during a write operation, after applying a first turn-on voltage to the second gate layer 114, a first storage voltage is applied to the first gate layer 112, causing the ferroelectric layer 123 to become polarized. After polarization, a charge is generated on the surface of the ferroelectric layer 123, thereby realizing the writing of information. During a read operation, for the channel structure where the polarized ferroelectric layer 123 is located, its turn-on voltage decreases. At this time, by applying a first read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned on, and the digital number 1 is read; for the channel structure where the non-polarized ferroelectric layer 123 is located, by applying a first read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned off, and the digital number 0 is read. During an erase operation, by applying a first erase voltage to the first gate layer 112, the measured hysteresis loop of the ferroelectric layer 123 is used for depolarization, thereby erasing the information stored in the storage device. Figure 2 The substrate 10 further includes a source region 101 and a drain region 102.

[0076] like Figure 3As shown, when the storage device provided in this specific embodiment is used as a non-volatile NAND flash memory: During a write operation, after applying a second turn-on voltage to the second gate layer 114, a second storage voltage is applied to the first gate layer 112, and the second storage voltage is greater than the first storage voltage. Electrons or holes pass through the tunneling layer 121 into the charge trapping layer 122 and are stored in the charge trapping layer 122. The electrons stored in the charge trapping layer 122 allow the polarization of the ferroelectric layer 123 to be preserved for a long time, thereby realizing the non-volatile storage function of the storage device. During a read operation, for the channel structure where the polarized ferroelectric layer 123 is located, its turn-on voltage decreases. At this time, by applying a second read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned on, and the digital number 1 is read; for the channel structure where the non-polarized ferroelectric layer 123 is located, by applying a second read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned off, and the digital number 0 is read. During the erase operation, a second erase voltage is applied to the first gate layer 112, and the measured hysteresis loop of the ferroelectric layer 123 is used for depolarization, thereby erasing the stored information in the storage device. Figure 2 The substrate 10 further includes a source region 101 and a drain region 102.

[0077] In some embodiments, the channel layer 125 penetrates the tunneling layer 121, the charge trapping layer 122, the ferroelectric layer 123, and the buffer layer 124 at the bottom of the via, and the bottom surface of the channel layer 125 contacts the substrate 10; the storage device further includes:

[0078] Drain 14 is in contact with the top surface of the channel layer 125.

[0079] In some embodiments, the channel structure also covers the top surface of the stacked structure 11;

[0080] The drain 14 penetrates the channel structure located on the top surface of the stacked structure 11.

[0081] Specifically, the bottom surface of the channel layer 125 is in contact with the source region inside the substrate 10, and the top surface of the channel layer 125 is in contact with the drain 14. The storage device also includes a first capping layer 13 covering the channel structure on the top surface of the stacked structure 11 to prevent subsequent processes from damaging the channel structure, especially the channel layer 125 within the channel structure. The drain 14 is positioned perpendicular to the top surface of the substrate 10 (e.g., Figure 1AThe channel structure (located on the top surface of the stacked structure 11) extends through the first cover layer 13 (in the Z-axis direction) to facilitate the subsequent outlining of the contacts of the drain 14. The storage device also includes a second cover layer 15 covering the first cover layer 13 and the drain 14. The first cover layer 13 may be made of an oxide material (e.g., silicon dioxide), and the second cover layer 15 may be made of a nitride material, such as silicon nitride.

[0082] In some embodiments, in order to increase the storage density of the storage device, the number of storage structures 12 is multiple, and the multiple storage structures 12 are arranged in an array along a first direction and a second direction.

[0083] In some embodiments, the first gate layer 112 includes a plurality of first gate structures 40 arranged in parallel and spaced along a second direction, and the second gate layer 114 includes a plurality of second gate structures 41 arranged in parallel and spaced along a second direction. The second gate structures 41 are located above the first gate structures 40, and the plurality of memory structures 12 arranged in parallel along the first direction share the first gate structure 40 and the second gate structure 41.

[0084] In some embodiments, the storage device further includes:

[0085] A separation structure 16 extends through the stacked structure 11 in a direction perpendicular to the top surface of the substrate 10 and is located between two adjacent first gate structures 40 and two adjacent second gate structures 41.

[0086] The following is Figure 4 Taking the X-axis as the first direction and the Y-axis as the second direction as an example, and with the X-axis perpendicular to the Y-axis, and the Z-axis perpendicular to both the X-axis and Y-axis, for example... Figure 1A and Figure 4 As shown, the storage device includes a plurality of storage region structures 12 arranged in a two-dimensional array along the X-axis and Y-axis directions. A partition structure 16 extends through the stacked structure 11 along the Z-axis direction. Each partition structure 16 extends along the X-axis direction, and the plurality of partition structures 16 are arranged in parallel along the Y-axis direction, thereby dividing the first gate layer 112 into a plurality of first gate structures 40 arranged parallel and spaced along the Y-axis direction, and dividing the second gate layer 114 into a plurality of second gate structures 41 arranged parallel and spaced along the Y-axis direction. Each first gate structure 40 and each second gate structure 41 extends along the X-axis direction. The partition structure 16 is made of an insulating material, such as silicon dioxide, to electrically isolate adjacent first gate structures 40 and adjacent second gate structures 41.

[0087] In some embodiments, the first gate structure 40 is made of a metal material, and the second gate structure 41 is made of polycrystalline silicon.

[0088] For example, the material of the first gate structure 40 may be, but is not limited to, tungsten. A second gate structure 41 is used to turn on all the memory structures 12 arranged along the first direction. Since the second gate structure 41 is closer to the top metal layer in the memory device than the first gate structure 40, the turn-on voltage of the second gate structure 41 differs significantly from that of the first gate structure 40 due to the influence of the electric field of the top metal layer. Therefore, the materials of the first gate structure 40 and the second gate structure 41 are set to be different to apply different voltages to the first gate structure 40 and the second gate structure 41. The top metal layer is a metal layer used to transmit control signals from the outside to the memory structure 12.

[0089] According to other embodiments, this specific embodiment also provides a method for manufacturing a storage device. Figure 5 This is a flowchart illustrating the manufacturing method of the storage device according to a specific embodiment of this application, attached. Figures 6A-6P This is a cross-sectional schematic diagram along the first direction of the main process steps in the manufacturing of the storage device according to a specific embodiment of this application. Figures 7A-7P This is a cross-sectional schematic diagram along the second direction showing the main process steps in manufacturing the storage device according to a specific embodiment of this application. A structural schematic diagram of the storage device manufactured according to this embodiment can be found in [reference needed]. Figure 1A , Figure 1B , Figures 2-4 .like Figure 4 , Figure 5 , Figures 6A-6P and Figures 7A-7P As shown, the method for manufacturing the storage device includes the following steps:

[0090] Step S51, provide substrate 10, such as Figure 6A and Figure 7A As shown.

[0091] Step S52, forming a stacked layer, the stacked layer including a first interlayer isolation layer 111, a sacrificial layer 60, a second interlayer isolation layer 113, and a second gate layer 114 sequentially stacked on the substrate 10, as follows: Figure 6B and Figure 7B As shown.

[0092] The substrate 10 may be, but is not limited to, a silicon substrate; this specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The sacrificial layer 60 should have a large etching selectivity ratio with the first interlayer isolation layer 111 and the second interlayer isolation layer 113 to facilitate subsequent selective removal of the sacrificial layer 60. In one example, the etching selectivity ratios between the sacrificial layer 60 and the first interlayer isolation layer 111, and between the sacrificial layer 60 and the second interlayer isolation layer 113, are both greater than 3. In one embodiment, the materials of the first interlayer isolation layer 111 and the second interlayer isolation layer 113 may both be oxide materials (e.g., silicon dioxide), and the material of the sacrificial layer 60 may be a nitride material (e.g., silicon nitride). The material of the second gate layer 114 may be polycrystalline silicon.

[0093] Step S53, etch the stacked layer to form a through-hole 61 penetrating the stacked layer, such as Figure 6C and Figure 7C As shown.

[0094] In some embodiments, the specific steps of forming the through-hole 61 through the stacked layers include:

[0095] The stacked layer is etched to form a plurality of through holes 61 penetrating the stacked layer, and the plurality of through holes 61 are arranged in an array along a first direction and a second direction. The first direction and the second direction are both parallel to the top surface of the substrate 10, and the first direction and the second direction intersect.

[0096] Specifically, a dry etching process can be used to etch the stacked layer along a direction perpendicular to the top surface of the substrate 10, forming a plurality of vias 61 arranged in a two-dimensional array along the first and second directions. Each via 61 penetrates the stacked layer along a direction perpendicular to the top surface of the substrate 10. The intersection of the first and second directions can be perpendicular or oblique. This specific embodiment is illustrated using the example of the first and second directions intersecting perpendicularly.

[0097] Step S54, a channel structure is formed within the through hole 61, such as... Figure 6I and Figure 7I As shown.

[0098] In some embodiments, the channel structure may include a tunneling layer 121 covering the inner wall of the through hole, a charge trapping layer 122 covering the surface of the tunneling layer 121, a ferroelectric layer 123 covering the surface of the charge trapping layer 122, a buffer layer 124 covering the surface of the ferroelectric layer 123, and a channel layer 125 covering the surface of the buffer layer 124.

[0099] In some embodiments, the specific steps of forming a channel structure within the through hole 61 include:

[0100] A tunneling layer 121 is formed on the inner wall of the through hole 61 and the top surface of the stacked layer, such as Figure 6D and Figure 7D As shown;

[0101] A charge trapping layer 122 is formed on the surface of the tunneling layer 121;

[0102] A ferroelectric layer 123 is formed on the surface of the charge trapping layer 122, such as Figure 6E and Figure 7E ;

[0103] A buffer layer 124 is formed on the surface of the ferroelectric layer 123, such as Figure 6F and Figure 7F As shown;

[0104] A channel layer 125 is formed on the surface of the buffer layer 124, such as Figure 6I and Figure 7I As shown.

[0105] In some embodiments, the specific steps of forming the channel layer 125 on the surface of the buffer layer 124 include:

[0106] The buffer layer 124, the ferroelectric layer 123, the charge trapping layer 122, and the tunneling layer 121 at the bottom of the via 61 are etched to form a through-hole exposing the substrate 10, such as... Figure 6H and Figure 7H As shown;

[0107] Forming the channel layer 125 that fills the through holes and covers the surface of the buffer layer 124, such as Figure 6I and Figure 7I As shown.

[0108] Specifically, after forming the via 61, the tunneling layer 121, the charge trapping layer 122, the ferroelectric layer 123, and the buffer layer 124 are sequentially deposited on the inner wall of the via 61, forming a structure as follows: Figure 6F and Figure 7F The structure is shown. Next, a patterned first mask layer 62 is formed on the buffer layer 124 on the top surface of the stacked layers. The first mask layer 62 has a first etched hole 621 exposing the via 61, as shown. Figure 6G and Figure 7G As shown. Then, the buffer layer 124, the ferroelectric layer 123, the charge trapping layer 122, and the tunneling layer 121 at the bottom of the via 61 are etched along the first etched hole 621 to form a through hole exposing the substrate 10, as shown. Figure 6H and Figure 7H As shown. After removing the first mask layer 62 and forming the channel layer 125 that fills the through holes and covers the surface of the buffer layer 124, and the first cover layer 13 that covers the top surface of the channel layer 125, the result is as shown. Figure 6I and Figure 7I The structure is shown. The tunneling layer 121 can be made of an oxide material, such as silicon dioxide. The charge trapping layer 122 can be made of silicon oxynitride, silicon nitride, silicon oxide composite material, or high-k dielectric composite material. In one embodiment, the charge trapping layer 122 is made of zinc silicon oxide (ZSO). The ferroelectric layer 123 can be made of hafnium oxide, zirconium oxide, lead zirconate titanate, or hafnium zirconium oxide (HZO). In one embodiment, the ferroelectric layer 123 is made of hafnium zirconium oxide. The buffer 124 can be made of an oxide material, such as silicon dioxide. The channel layer 125 can be made of polycrystalline silicon, silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). In one embodiment, the channel layer 125 is made of polycrystalline silicon. The first capping layer 13 is made of an insulating material, such as silicon dioxide.

[0109] In some embodiments, the method further includes:

[0110] At least a portion of the channel structure located on the top surface of the stacked layers is etched to form a drain via 63 exposing the channel layer 125 within the via 61, such as... Figure 6J and Figure 7J As shown;

[0111] The drain hole 63 is filled to form the drain 14, such as Figure 6K and Figure 7K As shown.

[0112] Specifically, a dry etching process can be used to etch the first capping layer 13 and part of the channel structure to form the drain via 63 that exposes the channel layer 125 within the via 61, such as... Figure 6J and Figure 7J As shown. Then, conductive materials such as tungsten metal are deposited within the drain hole 63 to form the drain 14, as shown. Figure 6K and Figure 7K As shown.

[0113] Step S55: Remove the sacrificial layer 60 and replace it with a conductive material to form the first gate layer 112, as shown below. Figure 6N and Figure 7N As shown.

[0114] In some embodiments, the specific steps for forming the first gate layer 112 include:

[0115] The stacked layers are etched to form a plurality of partition trenches 66 arranged parallel to the second direction and extending to the top surface of the first interlayer isolation layer 111. Each partition trench 66 is located between two adjacent vias 61 arranged parallel to the second direction, thereby dividing the second gate layer 114 into a plurality of second gate structures 41 arranged parallel to the second direction. Figure 7L and Figure 4 As shown;

[0116] The sacrificial layer 60 is removed along the partition groove 66 to form a void region 65, such as Figure 6M and Figure 7M As shown;

[0117] The conductive material is filled along the partition groove 66 into the void region 65 to form the first gate layer 112, as shown below. Figure 6N and Figure 7N As shown.

[0118] In some embodiments, the method of manufacturing the storage device further includes:

[0119] Remove all the conductive material located within the partition groove 66, such as Figure 7O As shown;

[0120] An insulating material is filled into the partition groove 66 to form a partition structure 16, which divides the first gate layer 112 into a plurality of first gate structures 40 arranged in parallel along the second direction.

[0121] Specifically, after forming the drain 14, a second cover layer 15 is formed covering the first cover layer 13 and the drain 14, and a patterned second mask layer 64 is formed on the second cover layer 15. The second mask layer 64 has second etched holes. The channel structures located in the first cover layer 13, on the stacked layers, and partially within the vias 61 are etched along the second etched holes to form a plurality of partition trenches 66 arranged parallel to each other along the second direction and extending to the top surface of the first interlayer isolation layer 111. Each partition trench 66 is located between two adjacent vias 61 arranged parallel to each other along the second direction, thereby dividing the second gate layer 114 into a plurality of second gate structures 41 arranged parallel to each other along the second direction. Figure 6L , Figure 7L and Figure 4 As shown. Next, a wet etching process is used to remove the sacrificial layer 60 along the partition groove 66, forming a void region 65, as shown. Figure 6M and Figure 7MAs shown. Then, conductive material is filled along the separator 66 to the void region 65, forming the first gate layer 112 filling the void region 65 and the filling structure 67 filling the separator 66, as shown. Figure 6N and Figure 7N As shown. The filling structure 67 in the partition trench 66 is etched back to completely remove the filling structure 67, thereby dividing the first gate layer 112 into a plurality of first gate structures 40 arranged parallel to each other along the second direction through the partition trench 66, as shown. Figure 6O , Figure 7O and Figure 4 As shown. Finally, insulating material is filled into the partition groove 66 to form a partition structure 16, as shown. Figure 6P and Figure 7P As shown.

[0122] In some embodiments, the first gate layer 112 is made of a metal material, and the second gate layer 114 is made of polycrystalline silicon.

[0123] According to other embodiments, this specific implementation also provides a driving method for a storage device as described in one of the preceding embodiments. Appendix Figure 8 This is a flowchart of the driving method for the storage device in a specific embodiment of this application. A schematic diagram of the structure of the storage device driven in this specific embodiment can be found in [reference needed]. Figure 1A , Figure 1B , Figures 2-4 The storage device driven by the driving method in this specific embodiment can be, for example, Figure 5 , Figures 6A-6P and Figures 7A-7P The storage device shown is formed by a method for forming the device. For example... Figures 1A-1B , Figure 4 and Figure 8 As shown, the driving method for the storage device includes the following steps:

[0124] Step S91: In the first storage mode, apply a first turn-on voltage to the second gate layer 114 and apply a first storage voltage to the first gate layer 112, and write information to the ferroelectric layer 123.

[0125] In step S92, in the second storage mode, a second turn-on voltage is applied to the second gate layer 114 and a second storage voltage is applied to the first gate layer 112, and information is written to the charge trapping layer 122.

[0126] For example, in the first storage mode, the storage device is used as a non-volatile memory (FeRAM). During a write operation, after applying a first enable voltage to the second gate layer 114, a first storage voltage is applied to the first gate layer 112, causing the ferroelectric layer 123 to polarize. After polarization, a charge is generated on the surface of the ferroelectric layer 123, thereby enabling information writing. In the second storage mode, the storage device is used as a non-volatile memory (NAND). During a write operation, after applying a second enable voltage to the second gate layer 114, a second storage voltage is applied to the first gate layer 112, and the second storage voltage is greater than the first storage voltage. Electrons or holes pass through the tunneling layer 121 into the charge trapping layer 122 and are stored there. The electrons stored in the charge trapping layer 122 allow the polarization of the ferroelectric layer 123 to be preserved for a long period, thus realizing the non-volatile storage function of the storage device. The second storage voltage is greater than the first storage voltage.

[0127] In some embodiments, the driving method for the storage device further includes the following steps:

[0128] In the first storage mode, a first read voltage is applied to the first gate layer 112 to read the information stored in the ferroelectric layer 123;

[0129] In the second storage mode, a second read voltage is applied to the first gate layer 112 to read the information in the charge trapping layer 122.

[0130] For example, in the first storage mode, the storage device is used as a non-volatile memory (FeRAM). In this case, during a read operation, the turn-on voltage of the channel structure where the polarized ferroelectric layer 123 is located decreases. At this time, by applying a first read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned on, and the number 1 is read. For the channel structure where the non-polarized ferroelectric layer 123 is located, by applying a first read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned off, and the number 0 is read. In the second storage mode, the storage device is used as a non-volatile NAND flash memory. In this mode, during a read operation, the turn-on voltage of the channel structure where the polarized ferroelectric layer 123 is located decreases. At this time, by applying a second read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned on, and the digital number 1 is read. For the channel structure where the non-polarized ferroelectric layer 123 is located, by applying a second read voltage to the first gate layer 112, the S / D circuit corresponding to the channel structure is turned off, and the digital number 0 is read.

[0131] In some embodiments, the driving method for the storage device further includes the following steps:

[0132] In the first storage mode, a first erase voltage is applied to the first gate layer 112 to erase the information stored in the ferroelectric layer 123;

[0133] In the second storage mode, a second erase voltage is applied to the first gate layer 112 to erase the information stored in the charge trapping layer 122.

[0134] For example, in the first storage mode, the storage device is used as a non-volatile memory (FeRAM). In this mode, during an erase operation, a first erase voltage is applied to the first gate layer 112, and the measured hysteresis loop of the ferroelectric layer 123 is used for depolarization, thereby erasing the stored information in the storage device. In the second storage mode, the storage device is used as a non-volatile memory (NAND). In this mode, during an erase operation, a second erase voltage is applied to the first gate layer 112, and the measured hysteresis loop of the ferroelectric layer 123 is used for depolarization, thereby erasing the stored information in the storage device.

[0135] The storage device and its manufacturing and driving methods provided in some embodiments of this specific implementation, by setting up a storage structure including a first gate layer, a second gate layer, and a stacked structure located between the first gate layer and the second gate layer and between the first gate layer and the substrate, and by setting through holes through the stacked structure and channel structures filling the through holes, enables the storage device to be used as a non-volatile memory with different storage modes, thereby realizing the multifunctionality of the storage device and expanding the application field of the storage device.

[0136] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A storage device, characterized in that, include: Substrate; A stacked structure, the stacked structure including a first gate layer, a second gate layer and an interlayer isolation layer, the interlayer isolation layer being located between the first gate layer and the second gate layer, and between the first gate layer and the substrate; The storage structure includes a through-hole penetrating the stacked structure and a channel structure filling the through-hole; The channel structure includes a tunneling layer covering the inner wall of the through-hole, a charge trapping layer covering the surface of the tunneling layer, a ferroelectric layer covering the surface of the charge trapping layer, a buffer layer covering the surface of the ferroelectric layer, and a channel layer covering the surface of the buffer layer. The storage device is configured to store information in the ferroelectric layer or the charge trapping layer according to different storage voltages.

2. The storage device according to claim 1, characterized in that, The channel layer penetrates the tunneling layer, the charge trapping layer, the ferroelectric layer, and the buffer layer at the bottom of the via, and the bottom surface of the channel layer is in contact with the substrate; The storage device further includes: The drain electrode is in contact with the top surface of the channel layer.

3. The storage device according to claim 2, characterized in that, The channel structure also covers the top surface of the stacked structure; The drain electrode penetrates the channel structure located on the top surface of the stacked structure.

4. The storage device according to claim 1, characterized in that, The number of storage structures is multiple, and the multiple storage structures are arranged in an array along the first direction and the second direction.

5. The storage device according to claim 4, characterized in that, The first gate layer includes a plurality of first gate structures arranged in parallel and spaced apart along a second direction, and the second gate layer includes a plurality of second gate structures arranged in parallel and spaced apart along a second direction. The second gate structures are located above the first gate structures, and the plurality of memory structures arranged in parallel along the first direction share the first gate structure and the second gate structure.

6. The storage device according to claim 5, characterized in that, Also includes: A separation structure extends through the stacked structure in a direction perpendicular to the top surface of the substrate and is located between two adjacent first gate structures and two adjacent second gate structures.

7. The storage device according to claim 5, characterized in that, The first gate structure is made of a metallic material, and the second gate structure is made of polycrystalline silicon.

8. A method for manufacturing a storage device according to any one of claims 1-7, characterized in that, Includes the following steps: Provide substrate; A stacked layer is formed, the stacked layer comprising a first interlayer isolation layer, a sacrificial layer, a second interlayer isolation layer, and a second gate layer sequentially stacked on the substrate; The stacked layers are etched to form through-holes penetrating the stacked layers; A channel structure is formed within the through hole; The sacrificial layer is removed and replaced with a conductive material to form a first gate layer.

9. The manufacturing method according to claim 8, characterized in that, The specific steps for forming a through-hole through the stacked layers include: The stacked layer is etched to form a plurality of through-holes penetrating the stacked layer, and the plurality of through-holes are arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects the second direction.

10. The manufacturing method according to claim 9, characterized in that, The specific steps for forming a channel structure within the through hole include: A tunneling layer is formed on the inner wall of the through hole and the top surface of the stacked layer; A charge trapping layer is formed on the surface of the tunneling layer; A ferroelectric layer is formed on the surface of the charge trapping layer; A buffer layer is formed on the surface of the ferroelectric layer; A channel layer is formed on the surface of the buffer layer.

11. The manufacturing method according to claim 10, characterized in that, The specific steps for forming a channel layer on the surface of the buffer layer include: The buffer layer, the ferroelectric layer, the charge trapping layer, and the tunneling layer at the bottom of the via are etched to form a through-hole that exposes the substrate; The channel layer is formed to fill the through holes and cover the surface of the buffer layer.

12. The manufacturing method according to claim 11, characterized in that, The method further includes: At least a portion of the channel structure located on the top surface of the stacked layer is etched to form a drain via that exposes the channel layer within the via. The drain electrode is formed by filling the drain hole.

13. The manufacturing method according to claim 8, characterized in that, The specific steps for forming the first gate layer include: The stacked layer is etched to form a plurality of partition trenches arranged in parallel along the second direction and extending to the top surface of the first interlayer isolation layer. Each partition trench is located between two adjacent vias arranged in parallel along the second direction, so as to divide the second gate layer into a plurality of second gate structures arranged in parallel along the second direction. The sacrificial layer is removed along the dividing groove to form a void region; The first gate layer is formed by filling the gap region with conductive material along the partition groove.

14. The manufacturing method according to claim 13, characterized in that, Also includes: Remove the conductive material located within the partition groove; An insulating material is filled into the partition groove to form a partition structure, which divides the first gate layer into a plurality of first gate structures arranged in parallel along the second direction.

15. The manufacturing method according to claim 8, characterized in that, The first gate layer is made of a metallic material, and the second gate layer is made of polycrystalline silicon.

16. A driving method for a storage device as described in any one of claims 1-7, characterized in that, Includes the following steps: In the first storage mode, a first turn-on voltage is applied to the second gate layer, and a first storage voltage is applied to the first gate layer to write information to the ferroelectric layer; In the second storage mode, a second turn-on voltage is applied to the second gate layer and a second storage voltage is applied to the first gate layer to write information to the charge trapping layer, wherein the second storage voltage is greater than the first storage voltage.

17. The driving method according to claim 16, characterized in that, It also includes the following steps: In the first storage mode, a first read voltage is applied to the first gate layer to read the information stored in the ferroelectric layer; In the second storage mode, a second read voltage is applied to the first gate layer to read information in the charge trapping layer.

18. The driving method according to claim 16 or 17, characterized in that, It also includes the following steps: In the first storage mode, a first erase voltage is applied to the first gate layer to erase the information stored in the ferroelectric layer; In the second storage mode, a second erase voltage is applied to the first gate layer to erase the information stored in the charge trapping layer.

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