Display substrate, driving method thereof, and display device

Abstract

The application provides a display substrate and a driving method thereof and a display device, and relates to the technical field of display, and aims to solve the problem that a virtual edge phenomenon is formed at the bottom of a display screen of a display product when a 3GSTV timing driving display product is used. The display substrate comprises n rows of sub-pixels, each of the sub-pixels in the first row of sub-pixels to the i-th row of sub-pixels comprises a first sub-pixel driving circuit, each of the sub-pixels in the i+1-th row of sub-pixels to the m-th row of sub-pixels comprises a second sub-pixel driving circuit, and each of the sub-pixels in the m+1-th row of sub-pixels to the n-th row of sub-pixels comprises a third sub-pixel driving circuit; the first sub-pixel driving circuit comprises a first capacitance storage unit, the second sub-pixel driving circuit comprises a second capacitance storage unit, and the third sub-pixel driving circuit comprises a third capacitance storage unit; the capacitance value of the first capacitance storage unit is smaller than that of the second capacitance storage unit, and the capacitance value of the second capacitance storage unit is smaller than that of the third capacitance storage unit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display substrate, its driving method, and a display device. Background Technology

[0002] Currently, wearable display products typically employ 3GSTV timing to improve thin-film transistor hysteresis and increase the first frame ratio (FFR). For example... Figure 1 and Figure 2 As shown, the 3GSTV timing refers to the timing in which the low level width of the frame start signal GSTV of the gate drive circuit wraps around the low level of the three first clock signals GCK.

[0003] However, when using 3GSTV timing-driven display products, a blurry edge phenomenon will appear at the bottom of the display screen. Summary of the Invention

[0004] The purpose of this invention is to provide a display substrate and its driving method and display device to solve the problem of a virtual edge phenomenon at the bottom of the display screen when using 3GSTV timing-driven display products.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A first aspect of the present invention provides a display substrate, comprising: a substrate and n rows of sub-pixels disposed on the substrate, wherein each sub-pixel in the first row to the i-th row includes a first sub-pixel driving circuit, each sub-pixel in the (i+1)-m-th row includes a second sub-pixel driving circuit, and each sub-pixel in the (m+1)-n-th row includes a third sub-pixel driving circuit; 1 < i < m, m < n;

[0007] The first sub-pixel driving circuit includes a first capacitor storage unit, the second sub-pixel driving circuit includes a second capacitor storage unit, and the third sub-pixel driving circuit includes a third capacitor storage unit.

[0008] The capacitance of the first capacitor storage unit is less than the capacitance of the second capacitor storage unit, and the capacitance of the second capacitor storage unit is less than the capacitance of the third capacitor storage unit.

[0009] Optionally, C3 = 3C1, C2 = 1.5C1; where,

[0010] C3 is the capacitance value of the third capacitor storage unit, C2 is the capacitance value of the second capacitor storage unit, and C1 is the capacitance value of the first capacitor storage unit.

[0011] Optionally, the display substrate further includes multiple power lines; the first sub-pixel driving circuit further includes driving transistors:

[0012] The first capacitor storage unit includes a first capacitor, the first plate of the first capacitor is coupled to the gate of the driving transistor, and the second plate of the first capacitor is coupled to the corresponding power line.

[0013] Optionally, the display substrate further includes multiple first control signal lines; the second sub-pixel driving circuit further includes a driving transistor and a first control transistor; the second capacitor storage unit includes a second capacitor and a third capacitor;

[0014] The first plate of the second capacitor is coupled to the gate of the driving transistor, and the second plate of the second capacitor is coupled to the corresponding power supply line; the first plate of the third capacitor is coupled to the gate of the driving transistor, and the second plate of the third capacitor is coupled to the first terminal of the first control transistor, the second terminal of the first control transistor is coupled to the corresponding power supply line, and the gate of the first control transistor is coupled to the corresponding first control signal line.

[0015] Optionally, the display substrate further includes at least two second control signal lines; the third sub-pixel driving circuit further includes a driving transistor, a first control transistor, and a second control transistor; the third capacitor storage unit includes a fourth capacitor, a fifth capacitor, and a sixth capacitor.

[0016] The first plate of the fourth capacitor is coupled to the gate of the driving transistor, and the second plate of the fourth capacitor is coupled to the corresponding power line.

[0017] The first plate of the fifth capacitor is coupled to the gate of the driving transistor, the second plate of the fifth capacitor is coupled to the first electrode of the first control transistor, the second electrode of the first control transistor is coupled to the corresponding power supply line, and the gate of the first control transistor is coupled to the corresponding first control signal line.

[0018] The first plate of the sixth capacitor is coupled to the gate of the driving transistor, the second plate of the sixth capacitor is coupled to the first plate of the second control transistor, the second plate of the second control transistor is coupled to the corresponding power supply line, and the gate of the second control transistor is coupled to the corresponding second control signal line.

[0019] Optionally, the capacitance value of the second capacitor is equal to the capacitance value of the first capacitor, and the capacitance value of the third capacitor is half of the capacitance value of the first capacitor.

[0020] Optionally, the first plate of the second capacitor and the first plate of the third capacitor are formed as an integral structure; the second plate of the second capacitor and the second plate of the third capacitor are disposed in the same layer, and the second plates of the second capacitor and the second plates of the third capacitor are arranged along a first direction.

[0021] Optionally, the driving transistor includes a driving active pattern; the orthographic projection of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the driving active pattern on the substrate.

[0022] Optionally, the capacitance value of the fourth capacitor is equal to the capacitance value of the first capacitor, the capacitance value of the fifth capacitor is half the capacitance value of the first capacitor, and the capacitance value of the sixth capacitor is 1.5 times the capacitance value of the first capacitor.

[0023] Optionally, the first plate of the fourth capacitor, the first plate of the fifth capacitor, and the first plate of the sixth capacitor are formed as an integral structure.

[0024] The second plates of the fourth capacitor, the fifth capacitor, and the sixth capacitor are disposed on the same layer. The second plates of the fourth capacitor and the fifth capacitor are arranged along a first direction. The second plates of the fourth capacitor and the sixth capacitor are arranged along the first direction. The second plates of the fifth capacitor and the sixth capacitor are arranged along a second direction, which intersects with the first direction.

[0025] Optionally, the driving transistor includes a driving active pattern; the orthographic projection of the second plate of the fifth capacitor on the substrate at least partially overlaps with the orthographic projection of the driving active pattern on the substrate; and / or, the orthographic projection of the second plate of the sixth capacitor on the substrate at least partially overlaps with the orthographic projection of the driving active pattern on the substrate.

[0026] Optionally, the second sub-pixel driving circuit and the third sub-pixel driving circuit further include a first conductive connection portion; the first control transistor includes a first control active pattern, the first control active pattern includes a first active portion and a second active portion coupled together, the first active portion extends along a first direction, the second active portion extends along a second direction, and the first direction intersects with the second direction.

[0027] The end of the first active portion away from the second active portion serves as the second electrode of the first control transistor, and the end of the second active portion away from the first active portion serves as the first electrode of the first control transistor. The end of the second active portion away from the first active portion is coupled to the second electrode of the third capacitor or the second electrode of the fifth capacitor through the first conductive connection portion.

[0028] Optionally, the first conductive connection portion includes a first sub-connection portion and a second sub-connection portion coupled together, wherein the first sub-connection portion extends along the first direction and the second sub-connection portion extends along the second direction;

[0029] The first sub-connection portion is coupled to the second active portion, and the second sub-connection portion is coupled to the second plate of the third capacitor or the second plate of the fifth capacitor.

[0030] Optionally, the display substrate further includes a plurality of light-emitting control signal lines, at least a portion of which extend along the first direction;

[0031] The orthographic projection of the first sub-connection portion on the substrate does not overlap with the orthographic projection of the light-emitting control signal line on the substrate, while the orthographic projection of the second sub-connection portion on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate.

[0032] Optionally, the first control signal line includes at least a portion extending along the first direction;

[0033] The orthographic projection of the first sub-connection portion on the substrate is located between the orthographic projection of the light emission control signal line on the substrate and the orthographic projection of the first control signal line on the substrate.

[0034] Optionally, the sub-pixels in the display substrate further include light-emitting elements, the light-emitting elements including an anode pattern; the orthographic projection of the first sub-connection portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern belonging to the same sub-pixel on the substrate.

[0035] Optionally, the third sub-pixel driving circuit further includes a second conductive connection portion; the second control transistor further includes a second control active pattern, the second control active pattern including at least a portion extending along a first direction, the first end of the second control active pattern serving as the first electrode of the second control transistor, the first end of the second control active pattern being coupled to the second electrode plate of the sixth capacitor through the second conductive connection portion, and the second end of the second control active pattern serving as the second electrode of the second control transistor.

[0036] Optionally, the display substrate further includes a plurality of gate lines, the gate lines including at least a portion extending along the first direction;

[0037] The orthographic projection of the second conductive connection portion on the substrate overlaps at least partially with the orthographic projection of the gate line on the substrate.

[0038] Optionally, the second control signal line includes a control body portion and a control protrusion coupled together. The control body portion includes at least a portion extending along the first direction. The orthographic projection of the control protrusion on the substrate is located between the orthographic projection of the control body portion on the substrate and the orthographic projection of the gate line on the substrate. The control protrusion is coupled to the gate of the second control transistor.

[0039] Optionally, the distance between two adjacent first sub-pixel driving circuits in the same row, the distance between two adjacent second sub-pixel driving circuits in the same row, and the distance between two adjacent third sub-pixel driving circuits in the same row are all the same.

[0040] On the same side of the center line extending along the second direction of the display substrate, the first boundary of the first sub-pixel driving circuit closest to the center line, the first boundary of the second sub-pixel driving circuit closest to the center line, and the first boundary of the third sub-pixel driving circuit closest to the center line are aligned.

[0041] The first boundary is the boundary facing the center line.

[0042] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode pattern, the anode pattern including an anode body portion and an anode connecting portion coupled together, the anode connecting portion being coupled to the sub-pixel driving circuit included in its sub-pixel;

[0043] The anode body portion of the anode pattern coupled to the first sub-pixel driving circuit, the anode body portion of the anode pattern coupled to the second sub-pixel driving circuit, and the anode body portion of the anode pattern coupled to the third sub-pixel driving circuit are arranged in an array.

[0044] Optional, i = n-4, m = n-2.

[0045] Based on the above-described display substrate technical solution, a second aspect of the present invention provides a display device including the above-described display substrate.

[0046] Based on the above-described technical solution for the display substrate, a third aspect of the present invention provides a driving method for the display substrate, the driving method comprising:

[0047] When charging sub-pixels from row i+1 to row m, the first control signal line controls the first control transistor to turn on.

[0048] When charging sub-pixels from row (m+1) to row (n), the first control signal line controls the first control transistor to turn on, and the second control signal line controls the second control transistor to turn on.

[0049] In the technical solution provided by the present invention, by setting the first sub-pixel driving circuit to include a first capacitor storage unit, the second sub-pixel driving circuit to include a second capacitor storage unit, and the third sub-pixel driving circuit to include a third capacitor storage unit; and by setting the capacitance value of the first capacitor storage unit to be smaller than the capacitance value of the second capacitor storage unit, and the capacitance value of the second capacitor storage unit to be smaller than the capacitance value of the third capacitor storage unit; the difference caused by the capacitor storage unit in V(1~i), V(i+1 / m), and V(m+1 / n) can be reduced, thereby effectively improving the phenomenon of dark actual brightness of the last few rows of sub-pixels on the display substrate and improving the virtual edge phenomenon of the display substrate. Attached Figure Description

[0050] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0051] Figure 1 The input and output signal timing diagram of the gate drive circuit provided in the embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram showing the connection of multiple shift register units provided in an embodiment of the present invention;

[0053] Figure 3 The timing diagram of the output signal of the gate drive circuit provided in the embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the circuit structure of the first sub-pixel driving circuit provided in an embodiment of the present invention;

[0055] Figure 5 This is a timing diagram of the first sub-pixel driving circuit provided in an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of the circuit structure of the second sub-pixel driving circuit provided in an embodiment of the present invention;

[0057] Figure 7 A schematic diagram of the circuit structure of the third sub-pixel driving circuit provided in an embodiment of the present invention;

[0058] Figure 8A timing diagram of the output signal and control signal of the gate drive circuit provided in an embodiment of the present invention;

[0059] Figure 9 This is a layout diagram of the active layer of the first sub-pixel driving circuit provided in an embodiment of the present invention;

[0060] Figure 10 A layout diagram of the active layer and the first gate metal layer of the first sub-pixel driving circuit provided in an embodiment of the present invention;

[0061] Figure 11 In order to be in Figure 10 Based on the layout diagram, a second gate metal layer is added;

[0062] Figure 12 In order to be in Figure 11 Based on the layout diagram of adding the first source / drain metal layer;

[0063] Figure 13 In order to be in Figure 12 Based on the layout diagram of the anode layer, add the layout diagram of the anode layer;

[0064] Figure 14 This is a layout diagram of the active layer of the second sub-pixel driving circuit provided in an embodiment of the present invention;

[0065] Figure 15 A layout diagram of the active layer and the first gate metal layer of the second sub-pixel driving circuit provided in an embodiment of the present invention;

[0066] Figure 16 In order to be in Figure 15 Based on the layout diagram, a second gate metal layer is added;

[0067] Figure 17 This is a layout diagram of the first source / drain metal layer of the second sub-pixel driving circuit provided in an embodiment of the present invention;

[0068] Figure 18 In order to be in Figure 16 Based on the layout diagram of adding the first source / drain metal layer;

[0069] Figure 19 In order to be in Figure 18 Based on the layout diagram of the anode layer, add the layout diagram of the anode layer;

[0070] Figure 20 The layout diagram of the active layer of the third sub-pixel driving circuit provided in the embodiment of the present invention;

[0071] Figure 21 A layout diagram of the active layer and the first gate metal layer of the third sub-pixel driving circuit provided in an embodiment of the present invention;

[0072] Figure 22 In order to be in Figure 21Based on the layout diagram, a second gate metal layer is added;

[0073] Figure 23 This is a layout diagram of the first source / drain metal layer of the third sub-pixel driving circuit provided in an embodiment of the present invention;

[0074] Figure 24 In order to be in Figure 22 Based on the layout diagram of adding the first source / drain metal layer;

[0075] Figure 25 In order to be in Figure 24 Based on the layout diagram of the anode layer, add the layout diagram of the anode layer;

[0076] Figure 26 This is a schematic diagram of the pixel layout of a display substrate provided in an embodiment of the present invention. Detailed Implementation

[0077] To further illustrate the display substrate, driving method, and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0078] like Figure 1 As shown, Figure 1 The diagram illustrates the timing of the frame start signal GSTV, the timing of the first clock signal GCK, the timing of the second clock signal GCB, the timing of the first gate drive signal GOUT1 output from the first gate drive signal output terminal, and the timing of the second gate drive signal GOUT2 output from the second gate drive signal output terminal.

[0079] like Figure 2 As shown, Figure 2 The diagram illustrates the connection relationship of multiple cascaded shift register units (GOAs). Figure 2 The diagram illustrates the corresponding gate drive signals output by each shift register unit, such as GOUT1 to GOUTn.

[0080] Research has revealed the following reasons why a blurry edge appears at the bottom of the display screen when using 3GSTV timing-driven display products:

[0081] like Figure 3As shown, taking a 384*384 resolution display product as an example, the data signal of the 379th row sub-pixel is written during the third pulse. Simultaneously with this data signal writing, the gate drive signals Gout(379) / Gout(381) / Gout(383) of the three rows of sub-pixels (379 / 381 / 383) are all at an active level, meaning that these three rows of sub-pixels are in data signal writing mode. The data signal charges the storage capacitors of these three rows of sub-pixels. After charging is complete, the gate of the driving transistor included in the sub-pixel driving circuit... The gate voltage is: V(379) = V(380) = Q / (3Cst + Cdata), where V(379) is the gate voltage of the driving transistor in the sub-pixel driving circuit of the 379th row, V(380) is the gate voltage of the driving transistor in the sub-pixel driving circuit of the 380th row, Q is the amount of charge stored between the first and second plates of the capacitor in the capacitor storage unit, Cst is the capacitance of the capacitor storage unit in the sub-pixel driving circuit, and Cdata is the parasitic capacitance on the data line. It is worth noting that... Figure 3 The timing of the Mux1 and Mux2 signals is also illustrated.

[0082] When the data signal is written to the sub-pixel in row 381, the gate drive signals Gout(381) / Gout(383) of the sub-pixels in rows 381 and 383 are both at an effective level, that is, the data signal writing mode is enabled for both sub-pixels in these two rows. The gate voltage of the driving transistor included in the sub-pixel driving circuit is: V(381)=V(382)=Q / (2Cst+Cdata), where V(381) is the gate voltage of the driving transistor included in the sub-pixel driving circuit in row 381, and V(382) is the gate voltage of the driving transistor included in the sub-pixel driving circuit in row 382.

[0083] When the 383rd row sub-pixel is writing data signals, only the gate drive signal Gout(383) of the 383rd row sub-pixel is at an effective level, that is, only the 383rd row sub-pixel is controlled to enable the data signal writing mode. The gate voltage of the driving transistor included in the sub-pixel driving circuit is: V(383)=V(384)=Q / (Cst+Cdata), where V(383) is the gate voltage of the driving transistor included in the sub-pixel driving circuit in the 383rd row sub-pixel, and V(384) is the gate voltage of the driving transistor included in the sub-pixel driving circuit in the 384th row sub-pixel.

[0084] Therefore, the gate voltage of the driving transistors in the driving circuits of each sub-pixel from row 1 to row 380 is different from the gate voltage of the driving transistors in the driving circuits of each sub-pixel in rows 381 and 382, ​​and also different from the gate voltage of the driving transistors in the driving circuits of each sub-pixel in rows 383 and 384. Moreover, V(384 / 383) > V(382 / 381) > V(380), resulting in the phenomenon that the brightness of the last few rows of sub-pixels is dark, which is called the virtual edge phenomenon.

[0085] It is worth noting that the technical solution provided by the present invention can solve the virtual edge phenomenon caused by the 3GSTV driving timing, but is not limited to the virtual edge phenomenon caused by the 3GSTV driving timing.

[0086] In view of the above problems, the present invention provides the following technical solution:

[0087] Please see Figure 4 , Figure 6 , Figure 7 and Figure 26 This invention provides a display substrate, comprising: a substrate and n rows of sub-pixels disposed on the substrate, wherein each sub-pixel in the first row to the i-th row includes a first sub-pixel driving circuit 11, each sub-pixel in the (i+1)-m-th row includes a second sub-pixel driving circuit 12, and each sub-pixel in the (m+1)-n-th row includes a third sub-pixel driving circuit 13; 1 < i < m, m < n, and i, m, and n are all positive integers; the first sub-pixel driving circuit 11 includes a first capacitor storage unit 110, the second sub-pixel driving circuit 12 includes a second capacitor storage unit 120, and the third sub-pixel driving circuit 13 includes a third capacitor storage unit 130;

[0088] The capacitance of the first capacitor storage unit 110 is less than the capacitance of the second capacitor storage unit 120, and the capacitance of the second capacitor storage unit 120 is less than the capacitance of the third capacitor storage unit 130.

[0089] For example, i = n-4, m = n-2.

[0090] For example, the display substrate includes a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels being divisible into n rows × j columns of sub-pixels. The display area of ​​the display substrate is divided into three regions: the sub-pixels in the first row to the i-th row are located in the first region, the sub-pixels in the (i+1)-m-th row are located in the second region, and the sub-pixels in the (m+1)-n-th row are located in the third region.

[0091] For example, all the first sub-pixel driving circuits 11, all the second sub-pixel driving circuits 12 and all the third sub-pixel driving circuits 13 included in the display substrate are arranged in an array.

[0092] For example, the first sub-pixel driving circuit 11, the second sub-pixel driving circuit 12, and the third sub-pixel driving circuit 13 all include a driving transistor T3. The first capacitor storage unit 110, the second capacitor storage unit 120, and the third capacitor storage unit 130 are all connected between the gate T3-g of the driving transistor T3 included in their respective sub-pixel driving circuits and the power supply line VDD.

[0093] For example, the number of sub-pixels included in each row of sub-pixels from the first row to the i-th row is greater than the number of sub-pixels included in each row of sub-pixels from the (i+1)-m-th row; and the number of sub-pixels included in each row of sub-pixels from the (i+1)-m-th row is greater than the number of sub-pixels included in each row of sub-pixels from the (m+1)-n-th row.

[0094] As can be seen from the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present invention, by setting the first sub-pixel driving circuit 11 to include a first capacitor storage unit 110, the second sub-pixel driving circuit 12 to include a second capacitor storage unit 120, and the third sub-pixel driving circuit 13 to include a third capacitor storage unit 130; and the capacitance value of the first capacitor storage unit 110 is smaller than the capacitance value of the second capacitor storage unit 120, and the capacitance value of the second capacitor storage unit 120 is smaller than the capacitance value of the third capacitor storage unit 130; the difference caused by the capacitor storage unit in V(1~i), V(i+1 / m), and V(m+1 / n) can be reduced, thereby effectively improving the phenomenon of dark actual brightness of the last few rows of sub-pixels on the display substrate and improving the virtual edge phenomenon of the display substrate.

[0095] It should be noted that V(1~i) refers to the gate voltage of the driving transistor T3 included in the driving circuit of each sub-pixel in the first to i-th rows. V(i+1 / m) refers to the gate voltage of the driving transistor T3 included in the driving circuit of each sub-pixel in the (i+1)-th and m-th rows. V(m+1 / n) refers to the gate voltage of the driving transistor T3 included in the driving circuit of each sub-pixel in the (m+1)-th and n-th rows.

[0096] In some embodiments, C3 = 3C1 and C2 = 1.5C1; wherein C3 is the capacitance value of the third capacitor storage unit 130, C2 is the capacitance value of the second capacitor storage unit 120, and C1 is the capacitance value of the first capacitor storage unit 110.

[0097] The above configuration ensures that V(1~i)=Q / (3C1+Cdata), V(i+1 / m)=Q / (2*1.5C1+Cdata), and V(m+1 / n)=Q / (3C1+Cdata), thereby minimizing the differences in V(1~i), V(i+1 / m), and V(m+1 / n) caused by the capacitor storage unit. This ensures that the loading of each row of sub-pixels on the entire display substrate is consistent during charging, effectively improving the phenomenon of dim brightness in the last few rows of sub-pixels on the display substrate and improving the virtual edge phenomenon on the display substrate.

[0098] like Figure 4 , Figures 9 to 13 As shown, in some embodiments, the display substrate further includes multiple power lines VDD; the first sub-pixel driving circuit 11 further includes a driving transistor T3:

[0099] The first capacitor storage unit 110 includes a first capacitor Cst1. The first plate Cst11 of the first capacitor Cst1 is coupled to the gate T3-g of the driving transistor T3, and the second plate Cst12 of the first capacitor Cst1 is coupled to the corresponding power line VDD.

[0100] like Figure 4 and Figure 5 As shown, exemplarily, the display substrate further includes: multiple reset signal lines Reset, multiple initialization signal lines Vint, multiple gate lines Gate, multiple data lines DA, multiple light emission control signal lines EM, and multiple power supply lines VDD.

[0101] For example, the first sub-pixel driving circuit 11 includes a 7T1C (i.e., 7 transistors and 1 capacitor) circuit structure, but is not limited thereto.

[0102] For example, the sub-pixel driving circuit includes: a driving transistor T3, a first reset transistor T1, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6, a second reset transistor T7, and a first capacitor Cst1.

[0103] The gate of the first reset transistor T1 is coupled to the corresponding reset signal line Reset, the first terminal of the first reset transistor T1 is coupled to the corresponding initialization signal line Vint, and the second terminal of the first reset transistor T1 is coupled to the gate of the driving transistor T3.

[0104] The gate of the compensation transistor T2 is coupled to the corresponding gate line, the first terminal of the compensation transistor T2 is coupled to the second terminal of the driving transistor T3, and the second terminal of the compensation transistor T2 is coupled to the gate of the driving transistor T3.

[0105] The gate of the data writing transistor T4 is coupled to the corresponding gate line, the first terminal of the data writing transistor T4 is coupled to the corresponding data line DA, and the second terminal of the data writing transistor T4 is coupled to the first terminal of the driving transistor T3.

[0106] The gate of the power control transistor T5 is coupled to the corresponding light emission control signal line EM, the first terminal of the power control transistor T5 is coupled to the corresponding positive power supply line VDD, and the second terminal of the power control transistor T5 is coupled to the first terminal of the driving transistor T3.

[0107] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM. The first terminal of the light-emitting control transistor T6 is coupled to the second terminal of the driving transistor T3. The second terminal of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element.

[0108] The gate of the second reset transistor T7 is coupled to the corresponding reset signal line Reset, the first terminal of the second reset transistor T7 is coupled to the initialization signal line Vint, and the second terminal of the second reset transistor T7 is coupled to the anode of the corresponding light-emitting element EL. The cathode of the light-emitting element EL receives the power supply signal VSS.

[0109] The first plate of the first capacitor Cst1 is coupled to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is coupled to the power supply line VDD.

[0110] The operation of the first pixel driving circuit is as follows:

[0111] During the reset period P1, the first reset transistor T1 is turned on, and the initialization signal transmitted by the initialization signal line Vint is written to the first plate of the first capacitor Cst1, charging the first capacitor Cst1; the driving transistor T3 is turned on, and the gate voltage of the driving transistor T3 is the voltage of the initialization signal; the second reset transistor T7 is turned on, and the initialization signal is written to the anode pattern 40 of the light-emitting element, releasing the residual charge; the compensation transistor T2, the data writing transistor T4, the power control transistor T5 and the light-emitting control transistor T6 are all turned off.

[0112] During pixel charging period P2, the first reset transistor T1 and the second reset transistor T7 are off, the power control transistor T5 and the light emission control transistor T6 are off, and the compensation transistor T2 and the data writing transistor T4 are on. The data signal transmitted by the data line DA is written into the circuit. The transmission path is as follows: data writing transistor T4, driving transistor T3 and compensation transistor T2, charging the first capacitor Cst1; driving transistor T3 gradually turns off. When Vgs = Vg - Vs = Vg - Vdata ≥ Vth, driving transistor T3 turns off, the first capacitor Cst1 is fully charged, and the gate voltage of driving transistor T3 is Vg = Vth + Vdata. It should be noted that Vgs is the gate-source voltage difference of driving transistor T3, Vg is the gate voltage value of driving transistor T3, Vs is the source voltage value of driving transistor T3, Vdata is the voltage value of the data signal, and Vth is the threshold voltage of driving transistor T3.

[0113] During the light-emitting period P3, the first reset transistor T1 and the second reset transistor T7 are off, the compensation transistor T2 and the data writing transistor T4 are off, and the power control transistor T5 and the light-emitting control transistor T6 are on. The power signal transmitted by the power line VDD is written into the circuit. At this time, the source voltage Vs of the driving transistor T3 is Vdd, where Vdd is the voltage value of the power signal; the gate voltage value of the driving transistor T3 is Vg = Vth + Vdata, and Vgs = Vth + Vdata - Vdd < Vth. Therefore, the driving transistor T3 is on, the screen is lit, and the 7T1C circuit eliminates the Vth difference, resulting in better brightness uniformity.

[0114]

[0115]

[0116] Where W / L is the aspect ratio of the driving transistor T3, Cox is the dielectric constant of the gate oxide layer, and μ is the electron mobility.

[0117] like Figure 6 , Figure 8 , Figures 14 to 19 , Figure 26 As shown, in some embodiments, the display substrate further includes multiple first control signal lines CT1; the second sub-pixel driving circuit 12 further includes a driving transistor T3 and a first control transistor T8; the second capacitor storage unit 120 includes a second capacitor Cst1_a1 and a third capacitor Cst1_b1;

[0118] The first plate Cst1_a11 of the second capacitor Cst1_a1 is coupled to the gate T3-g of the driving transistor T3, and the second plate Cst1_a12 of the second capacitor Cst1_a1 is coupled to the corresponding power supply line VDD; the first plate Cst1_b11 of the third capacitor Cst1_b1 is coupled to the gate T3-g of the driving transistor T3, and the second plate Cst1_b12 of the third capacitor Cst1_b1 is coupled to the first terminal of the first control transistor T8, the second terminal of the first control transistor T8 is coupled to the corresponding power supply line VDD, and the gate of the first control transistor T8 is coupled to the corresponding first control signal line CT1.

[0119] For example, the capacitance value of the second capacitor is equal to the capacitance value of the first capacitor, and the capacitance value of the third capacitor is half the capacitance value of the first capacitor. A first control transistor T8 is used to control whether the third capacitor is connected to the circuit.

[0120] For example, the second sub-pixel driving circuit 12 adopts an 8T2C circuit structure. Compared with the first sub-pixel driving circuit 11, the second sub-pixel driving circuit 12 adds a capacitor and a first control transistor.

[0121] For example, when the first control signal transmitted by the first control signal line CT1 is low, the first control transistor T8 is turned on, and the second plate Cst1_b12 of the third capacitor Cst1_b1 is electrically connected to the power line VDD. The second capacitor and the third capacitor are connected in parallel, and the storage capacitance of the second sub-pixel driving circuit 12 at this time is 1.5*C1. When the first control signal transmitted by the first control signal line CT1 is high, the first control transistor T8 is turned off, the second plate Cst1_b12 of the third capacitor Cst1_b1 is not electrically connected to the power line VDD, the third capacitor is ineffective, and the storage capacitance of the second sub-pixel driving circuit 12 at this time is C1.

[0122] In the display substrate provided in the above embodiment, by controlling whether the third capacitor is connected to the circuit through the first control transistor T8, the second capacitor and the third capacitor can be connected in parallel during the pixel charging period from the (i+1)th row sub-pixel to the mth row sub-pixel. This makes the storage capacitance of the second sub-pixel driving circuit 12 at this time 1.5*C1, thereby minimizing the difference caused by the capacitor storage unit and effectively improving the phenomenon of dark actual brightness of the (i+1)th row sub-pixel to the mth row sub-pixel of the display substrate, and improving the virtual edge phenomenon of the display substrate.

[0123] like Figure 7 , Figure 8 , Figures 20 to 26As shown, in some embodiments, the display substrate further includes at least two second control signal lines CT2; the third sub-pixel driving circuit 13 further includes a driving transistor T3, a first control transistor T8, and a second control transistor T9; the third capacitor storage unit 130 includes a fourth capacitor Cst1_a2, a fifth capacitor Cst1_b2, and a sixth capacitor Cst1_c2.

[0124] The first plate Cst1_a21 of the fourth capacitor Cst1_a2 is coupled to the gate T3-g of the driving transistor T3, and the second plate Cst1_a22 of the fourth capacitor Cst1_a2 is coupled to the corresponding power line VDD.

[0125] The first plate Cst1_b21 of the fifth capacitor Cst1_b2 is coupled to the gate T3-g of the driving transistor T3, the second plate Cst1_b22 of the fifth capacitor Cst1_b2 is coupled to the first terminal of the first control transistor T8, the second terminal of the first control transistor T8 is coupled to the corresponding power supply line VDD, and the gate of the first control transistor T8 is coupled to the corresponding first control signal line CT1.

[0126] The first plate Cst1_c21 of the sixth capacitor Cst1_c2 is coupled to the gate T3-g of the driving transistor T3, the second plate Cst1_c22 of the sixth capacitor Cst1_c2 is coupled to the first terminal of the second control transistor T9, the second terminal of the second control transistor T9 is coupled to the corresponding power supply line VDD, and the gate of the second control transistor T9 is coupled to the corresponding second control signal line CT2.

[0127] For example, the capacitance value of the fourth capacitor is equal to that of the first capacitor, the capacitance value of the fifth capacitor is half the capacitance value of the first capacitor, and the capacitance value of the sixth capacitor is 1.5 times the capacitance value of the first capacitor. A first control transistor T8 controls whether the fifth capacitor is connected to the circuit. A second control transistor T9 controls whether the sixth capacitor is connected to the circuit.

[0128] For example, the second sub-pixel driving circuit 12 adopts a 9T3C circuit structure. Compared with the first sub-pixel driving circuit 11, the third sub-pixel driving circuit 13 adds two capacitors, a first control transistor T8 and a second control transistor T9.

[0129] For example, when the first control signal transmitted by the first control signal line CT1 is low, the first control transistor T8 is turned on, and the second plate Cst1_b22 of the fifth capacitor Cst1_b2 is electrically connected to the power line VDD. When the second control signal transmitted by the second control signal line CT2 is low, the second control transistor T9 is turned on, and the second plate Cst1_c22 of the sixth capacitor Cst1_c2 is electrically connected to the power line VDD. The fourth, fifth, and sixth capacitors are connected in parallel, and the storage capacitance of the third sub-pixel driving circuit 13 at this time is (1+1.5+0.5)*C1. When the first control signal transmitted by the first control signal line CT1 is high, the first control transistor T8 is turned off, the second plate Cst1_b22 of the fifth capacitor Cst1_b2 is not electrically connected to the power line VDD, and the fifth capacitor is ineffective. When the second control signal transmitted by the second control signal line CT2 is high, the second control transistor T9 is turned off, the second plate Cst1_c22 of the sixth capacitor Cst1_c2 is not electrically connected to the power line VDD, and the sixth capacitor is ineffective. The storage capacitance of the third sub-pixel driving circuit 13 at this time is C1.

[0130] For example, the first control signal line CT1 and the second control signal line CT2 are connected to the GPIO port of the DDIC to receive the corresponding first control signal and second control signal.

[0131] The above configuration ensures that V(1~i)=Q / (3C1+Cdata), V(i+1 / m)=Q / (2*1.5C1+Cdata), and V(m+1 / n)=Q / (3C1+Cdata), thereby minimizing the differences in V(1~i), V(i+1 / m), and V(m+1 / n) caused by the capacitor storage unit. This ensures that the loading of each row of sub-pixels on the entire display substrate is consistent during charging, effectively improving the phenomenon of dim brightness in the last few rows of sub-pixels on the display substrate and improving the virtual edge phenomenon on the display substrate.

[0132] like Figure 16 As shown, in some embodiments, the first plate Cst1_a11 of the second capacitor Cst1_a1 and the first plate Cst1_b11 of the third capacitor Cst1_b1 are formed as an integral structure; the second plate Cst1_a12 of the second capacitor Cst1_a1 and the second plate Cst1_b12 of the third capacitor Cst1_b1 are disposed in the same layer, and the second plates Cst1_a12 of the second capacitor Cst1_a1 and the second plate Cst1_b12 of the third capacitor Cst1_b1 are arranged along a first direction.

[0133] For example, the gate T3-g of the driving transistor T3 is multiplexed as the first plate Cst1_a11 of the second capacitor Cst1_a1 and the first plate Cst1_b11 of the third capacitor Cst1_b1.

[0134] For example, the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first planarization layer, an anode layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, sequentially stacked on the substrate along a direction away from the substrate. For example, the display substrate may further include a passivation layer, which may be disposed between the first source / drain metal layer and the first planarization layer.

[0135] It is worth noting that, for example Figure 20 As shown in the figure, the first reset active pattern 21, the compensation active pattern 22, the data writing active pattern 24, the power control active pattern 25, the light emission control active pattern 26, and the second reset active pattern 27 are illustrated. Figure 23 The diagram illustrates the third conductive connection portion 33, the fourth conductive connection portion 34, and the fifth conductive connection portion 35.

[0136] For example, the second plate Cst1_a12 of the second capacitor Cst1_a1 and the second plate Cst1_b12 of the third capacitor Cst1_b1 are both made using the second gate metal layer.

[0137] For example, the second plate Cst1_a12 of the second capacitor Cst1_a1 and the second plate Cst1_b12 of the third capacitor Cst1_b1 are spaced apart and insulated from each other.

[0138] The above configuration rationally allocates the layout space of the sub-pixel driving circuit, which not only ensures the working stability and reliability of the sub-pixel driving circuit, but also facilitates the development of narrow bezels in the display substrate.

[0139] like Figures 14 to 19 As shown, in some embodiments, the driving transistor T3 includes a driving active pattern 23; the orthographic projection of the second plate Cst1_b12 of the third capacitor Cst1_b1 on the substrate overlaps at least partially with the orthographic projection of the driving active pattern 23 on the substrate.

[0140] like Figures 20 to 25As shown, in some embodiments, the first plate Cst1_a21 of the fourth capacitor Cst1_a2, the first plate Cst1_b21 of the fifth capacitor Cst1_b2, and the first plate Cst1_c21 of the sixth capacitor Cst1_c2 are formed as an integral structure.

[0141] The second plates Cst1_a22 of the fourth capacitor Cst1_a2, Cst1_b22 of the fifth capacitor Cst1_b2, and Cst1_c22 of the sixth capacitor Cst1_c2 are disposed in the same layer. The second plates Cst1_a22 of the fourth capacitor Cst1_a2 and Cst1_b22 of the fifth capacitor Cst1_b2 are arranged along a first direction. The second plates Cst1_a22 of the fourth capacitor Cst1_a2 and Cst1_c22 of the sixth capacitor Cst1_c2 are arranged along the first direction. The second plates Cst1_b22 of the fifth capacitor Cst1_b2 and Cst1_c22 of the sixth capacitor Cst1_c2 are arranged along a second direction, which intersects the first direction.

[0142] For example, the gate T3-g of the driving transistor T3 is multiplexed to the first plate Cst1_a21 of the fourth capacitor Cst1_a2, the first plate Cst1_b21 of the fifth capacitor Cst1_b2, and the first plate Cst1_c21 of the sixth capacitor Cst1_c2.

[0143] For example, the second plate Cst1_a22 of the fourth capacitor Cst1_a2, the second plate Cst1_b22 of the fifth capacitor Cst1_b2, and the second plate Cst1_c22 of the sixth capacitor Cst1_c2 are all made of the second gate metal layer.

[0144] For example, the second plates Cst1_a22 of the fourth capacitor Cst1_a2, Cst1_b22 of the fifth capacitor Cst1_b2, and Cst1_c22 of the sixth capacitor Cst1_c2 are all spaced apart and insulated from each other.

[0145] The above configuration rationally allocates the layout space of the sub-pixel driving circuit, which not only ensures the working stability and reliability of the sub-pixel driving circuit, but also facilitates the development of narrow bezels in the display substrate.

[0146] like Figures 20 to 25As shown, in some embodiments, the driving transistor T3 includes a driving active pattern 23; the orthographic projection of the second plate Cst1_b22 of the fifth capacitor Cst1_b2 on the substrate at least partially overlaps with the orthographic projection of the driving active pattern on the substrate; and / or, the orthographic projection of the second plate Cst1_c22 of the sixth capacitor Cst1_c2 on the substrate at least partially overlaps with the orthographic projection of the driving active pattern on the substrate.

[0147] like Figures 14 to 25 As shown, in some embodiments, the second sub-pixel driving circuit 12 and the third sub-pixel driving circuit 13 further include a first conductive connection portion 31; the first control transistor T8 includes a first control active pattern 28, the first control active pattern 28 includes a first active portion 281 and a second active portion 282 coupled together, the first active portion 281 extends along a first direction, the second active portion 282 extends along a second direction, and the first direction intersects with the second direction;

[0148] The end of the first active portion 281 away from the second active portion 282 serves as the second electrode of the first control transistor T8, and the end of the second active portion 282 away from the first active portion 281 serves as the first electrode of the first control transistor T8. The end of the second active portion 282 away from the first active portion 281 is coupled to the second electrode plate Cst1_b12 of the third capacitor Cst1_b1 or the second electrode plate Cst1_b22 of the fifth capacitor Cst1_b2 through the first conductive connection portion 31.

[0149] For example, the first conductive connection portion 31 is made of a first source / drain metal layer.

[0150] For example, the first control active graphic 28 includes a first active part 281 and a second active part 282 of an integral structure.

[0151] For example, the first direction is horizontal and the second direction is vertical, but it is not limited to this.

[0152] For example, the end of the first active portion 281 away from the second active portion 282 is coupled to the corresponding power line VDD through a via. The end of the second active portion 282 away from the first active portion 281 is coupled to the first conductive connection portion 31 through a via. The first conductive connection portion 31 is coupled to the second plate Cst1_b12 of the third capacitor Cst1_b1 or the second plate Cst1_b22 of the fifth capacitor Cst1_b2 through a via.

[0153] like Figures 14 to 25As shown, in some embodiments, the first conductive connection portion 31 includes a first sub-connection portion 310 and a second sub-connection portion 311 coupled together, the first sub-connection portion 310 extending along the first direction and the second sub-connection portion 311 extending along the second direction.

[0154] The first sub-connection portion 310 is coupled to the second active portion 282, and the second sub-connection portion 311 is coupled to the second plate Cst1_b12 of the third capacitor Cst1_b1 or the second plate Cst1_b22 of the fifth capacitor Cst1_b2.

[0155] For example, the first conductive connection portion 31 includes a first sub-connection portion 310 and a second sub-connection portion 311 with an integral structure.

[0156] like Figures 14 to 25 As shown, in some embodiments, the display substrate further includes a plurality of light emission control signal lines EM, at least a portion of which extend along the first direction;

[0157] The orthographic projection of the first sub-connection portion 310 on the substrate does not overlap with the orthographic projection of the light-emitting control signal line EM on the substrate, while the orthographic projection of the second sub-connection portion 311 on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate.

[0158] The above configuration can reduce the impact of the light emission control signal transmitted by the light emission control signal line EM on the second plate Cst1_b12 of the third capacitor Cst1_b1 or the second plate Cst1_b22 of the fifth capacitor Cst1_b2 when the signal changes.

[0159] like Figures 14 to 25 As shown, in some embodiments, the first control signal line CT1 includes at least a portion extending along the first direction; the orthographic projection of the first sub-connection portion 310 on the substrate is located between the orthographic projection of the light emission control signal line EM on the substrate and the orthographic projection of the first control signal line CT1 on the substrate.

[0160] For example, both the first control signal line CT1 and the light emission control signal line EM are made using the first gate metal layer.

[0161] For example, the first control signal line CT1 and the light emission control signal line EM are arranged along the second direction.

[0162] The above configuration rationally allocates the layout space of the sub-pixel driving circuit, which not only ensures the working stability and reliability of the sub-pixel driving circuit, but also facilitates the development of narrow bezels in the display substrate.

[0163] like Figure 25 and Figure 26 As shown, in some embodiments, the sub-pixels in the display substrate further include light-emitting elements, the light-emitting elements including an anode pattern 40; the orthographic projection of the first sub-connection portion 310 on the substrate overlaps at least partially with the orthographic projection of the anode pattern 40 belonging to the same sub-pixel on the substrate.

[0164] For example, the anode pattern 40 includes an anode body portion 41 and an anode connecting portion 42 coupled together. The orthographic projection of the first sub-connecting portion 310 on the substrate at least partially overlaps with the orthographic projection of the anode connecting portion 42 belonging to the same sub-pixel on the substrate.

[0165] like Figures 20 to 26 As shown, in some embodiments, the third sub-pixel driving circuit 13 further includes a second conductive connection portion 32; the second control transistor T9 further includes a second control active pattern 29, the second control active pattern 29 including at least a portion extending along a first direction, the first end of the second control active pattern 29 serving as the first electrode of the second control transistor T9, the first end of the second control active pattern 29 being coupled to the second electrode plate Cst1_c22 of the sixth capacitor Cst1_c2 through the second conductive connection portion 32, and the second end of the second control active pattern 29 serving as the second electrode of the second control transistor T9.

[0166] For example, the second conductive connection portion 32 is made of a first source / drain metal layer.

[0167] For example, the second conductive connection portion 32 extends along a third direction, which intersects both the first direction and the second direction.

[0168] For example, the first end of the second control active pattern 29 is coupled to the second conductive connection portion 32 through a via, the second conductive connection portion 32 is coupled to the second plate Cst1_c22 of the sixth capacitor Cst1_c2 through a via, and the second end of the second control active pattern 29 is coupled to the power line VDD through a via.

[0169] like Figures 20 to 26 As shown, in some embodiments, the display substrate further includes a plurality of gate lines, each gate line including at least a portion extending along the first direction;

[0170] The orthographic projection of the second conductive connection portion 32 on the substrate overlaps at least partially with the orthographic projection of the gate line Gate on the substrate.

[0171] For example, the orthographic projection of the second conductive connection portion 32 on the substrate is located between the orthographic projection of the second control signal line CT2 on the substrate and the orthographic projection of the second plate Cst1_b22 of the fifth capacitor Cst1_b2 on the substrate.

[0172] like Figures 20 to 26 As shown, in some embodiments, the second control signal line CT2 includes a control body portion CT21 and a control protrusion CT22 coupled together. The control body portion CT21 includes at least a portion extending along the first direction. The orthographic projection of the control protrusion CT22 on the substrate is located between the orthographic projection of the control body portion CT21 on the substrate and the orthographic projection of the gate line Gate on the substrate. The control protrusion CT22 is coupled to the gate of the second control transistor T9.

[0173] For example, the second control signal line CT2 includes a control body CT21 and a control protrusion CT22, which are integrally structured.

[0174] For example, the control protrusion CT22 is multiplexed as the gate of the second control transistor T9.

[0175] For example, the second control signal line CT2 is made using a first gate metal layer.

[0176] The above configuration rationally allocates the layout space of the sub-pixel driving circuit, which not only ensures the working stability and reliability of the sub-pixel driving circuit, but also facilitates the development of narrow bezels in the display substrate.

[0177] like Figure 26 As shown, in some embodiments, the distance between two adjacent first sub-pixel driving circuits 11 in the same row, the distance between two adjacent second sub-pixel driving circuits 12 in the same row, and the distance between two adjacent third sub-pixel driving circuits 13 in the same row are all the same.

[0178] On the same side of the center line extending along the second direction of the display substrate, the first boundary of the first sub-pixel driving circuit 11 closest to the center line, the first boundary of the second sub-pixel driving circuit 12 closest to the center line, and the first boundary of the third sub-pixel driving circuit 13 closest to the center line are aligned.

[0179] The first boundary is the boundary facing the center line.

[0180] For example, along the first direction, the first sub-pixel driving circuit 11, the second sub-pixel driving circuit 12, and the third sub-pixel driving circuit 13 are all arranged at equal intervals with the same spacing.

[0181] For example, on the left side of the center line extending along the second direction of the display substrate, the first boundary of the first sub-pixel driving circuit 11 closest to the center line, the first boundary of the second sub-pixel driving circuit 12 closest to the center line, and the first boundary of the third sub-pixel driving circuit 13 closest to the center line are aligned.

[0182] For example, on the right side of the center line extending along the second direction of the display substrate, the first boundary of the first sub-pixel driving circuit 11 closest to the center line, the first boundary of the second sub-pixel driving circuit 12 closest to the center line, and the first boundary of the third sub-pixel driving circuit 13 closest to the center line are aligned.

[0183] It is worth noting that the first boundary can be the first boundary of the same reference object in the sub-pixel driving circuit. For example, the boundary of the anode body 41 toward the center line, but not limited to this.

[0184] It should be noted that the widths of the second sub-pixel driving circuit 12 and the third sub-pixel driving circuit 13 in the first direction are greater than the width of the first sub-pixel driving circuit 11. In this application, the first boundaries of the second sub-pixel driving circuit 12, which is adjacent to the center line in the second region, are aligned with the first boundaries of the first sub-pixel driving circuit 11, which is adjacent to the center line in the first region, on both the left and right sides of the center line. Similarly, in this application, the first boundaries of the third sub-pixel driving circuit 13, which is adjacent to the center line in the third region, are aligned with the first boundaries of the first sub-pixel driving circuit 11, which is adjacent to the center line in the first region. This arrangement ensures the uniformity of the display substrate and improves the display effect.

[0185] like Figure 26 As shown, in some embodiments, the sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern 40, the anode pattern 40 includes an anode body portion 41 and an anode connection portion 42 coupled together, the anode connection portion being coupled to the sub-pixel driving circuit included in its sub-pixel;

[0186] The anode body portion 41 of the anode pattern 40 coupled to the first sub-pixel driving circuit 11, the anode body portion 41 of the anode pattern 40 coupled to the second sub-pixel driving circuit 12, and the anode body portion 41 of the anode pattern 40 coupled to the third sub-pixel driving circuit 13 are arranged in an array.

[0187] For example, the anode body portion 41 and the anode connection portion 42 are formed as an integral structure.

[0188] For example, the anode body portion 41 of the anode pattern 40 coupled to the third sub-pixel driving circuit 13, the anode body portion 41 of the anode pattern 40 coupled to the second sub-pixel driving circuit 12, and the anode body portion 41 of the anode pattern 40 coupled to the first sub-pixel driving circuit 11 can be located in the same column extending along the second direction.

[0189] The above configuration allows the anode pattern 40 of each sub-pixel to be evenly distributed, which helps to improve the display uniformity of the display substrate.

[0190] This invention also provides a display device, including the display substrate provided in the above embodiments.

[0191] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0192] In the display substrate provided in the above embodiments, by setting the first sub-pixel driving circuit 11 to include a first capacitor storage unit 110, the second sub-pixel driving circuit 12 to include a second capacitor storage unit 120, and the third sub-pixel driving circuit 13 to include a third capacitor storage unit 130; and by setting the capacitance value of the first capacitor storage unit 110 to be smaller than the capacitance value of the second capacitor storage unit 120, and the capacitance value of the second capacitor storage unit 120 to be smaller than the capacitance value of the third capacitor storage unit 130; the difference caused by the capacitor storage unit in V(1~i), V(i+1 / m), and V(m+1 / n) can be reduced, thereby effectively improving the phenomenon of dark actual brightness of the last few rows of sub-pixels on the display substrate and improving the virtual edge phenomenon of the display substrate.

[0193] Therefore, the display device provided in the embodiments of the present invention, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0194] This invention also provides a driving method for a display substrate, used to drive the display substrate provided in the above embodiments, the driving method comprising:

[0195] When charging the sub-pixels from row i+1 to row m, the first control signal line controls the first control transistor T8 to be turned on.

[0196] When charging sub-pixels from row (m+1) to row (n), the first control signal line controls the first control transistor T8 to turn on, and the second control signal line controls the second control transistor T9 to turn on.

[0197] When the display substrate is driven using the driving method provided in this embodiment of the invention, V(1~i)=Q / (3C1+Cdata), V(i+1 / m)=Q / (2*1.5C1+Cdata), and V(m+1 / n)=Q / (3C1+Cdata) are made so that the differences in V(1~i), V(i+1 / m), and V(m+1 / n) caused by the capacitor storage unit are minimized, so that the loading of each row of sub-pixels on the entire screen of the display substrate is consistent during charging, effectively improving the phenomenon that the actual brightness of the last few rows of sub-pixels on the display substrate is dark, and improving the virtual edge phenomenon of the display substrate.

[0198] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0199] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0200] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0201] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0202] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0203] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0204] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0205] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, include: A substrate and n rows of sub-pixels disposed on the substrate, wherein each sub-pixel in the first row to the i-th row includes a first sub-pixel driving circuit, each sub-pixel in the (i+1)-m-th row includes a second sub-pixel driving circuit, and each sub-pixel in the (m+1)-n-th row includes a third sub-pixel driving circuit; 1 < i < m, m < n; The first sub-pixel driving circuit includes a first capacitor storage unit, the second sub-pixel driving circuit includes a second capacitor storage unit, and the third sub-pixel driving circuit includes a third capacitor storage unit. The capacitance of the first capacitor storage unit is less than the capacitance of the second capacitor storage unit, and the capacitance of the second capacitor storage unit is less than the capacitance of the third capacitor storage unit. The display substrate also includes multiple power lines; The display substrate further includes multiple first control signal lines; the second sub-pixel driving circuit further includes a driving transistor and a first control transistor; the second capacitor storage unit includes a second capacitor and a third capacitor; the third capacitor storage unit includes a fifth capacitor; The first plate of the second capacitor is coupled to the gate of the driving transistor, and the second plate of the second capacitor is coupled to the corresponding power supply line; the first plate of the third capacitor is coupled to the gate of the driving transistor, the second plate of the third capacitor is coupled to the first terminal of the first control transistor, the second terminal of the first control transistor is coupled to the corresponding power supply line, and the gate of the first control transistor is coupled to the corresponding first control signal line. The second sub-pixel driving circuit and the third sub-pixel driving circuit further include a first conductive connection portion; the first control transistor includes a first control active pattern, the first control active pattern includes a first active portion and a second active portion coupled together, the first active portion extends along a first direction, the second active portion extends along a second direction, and the first direction intersects with the second direction; The end of the first active portion away from the second active portion serves as the second electrode of the first control transistor, and the end of the second active portion away from the first active portion serves as the first electrode of the first control transistor. The end of the second active portion away from the first active portion is coupled to the second electrode of the third capacitor or the second electrode of the fifth capacitor through the first conductive connection portion.

2. The display substrate according to claim 1, characterized in that, C3 = 3C1, C2 = 1.5C1; where, C3 is the capacitance value of the third capacitor storage unit, C2 is the capacitance value of the second capacitor storage unit, and C1 is the capacitance value of the first capacitor storage unit.

3. The display substrate according to claim 1, characterized in that, The first sub-pixel driving circuit also includes a driving transistor: The first capacitor storage unit includes a first capacitor, the first plate of the first capacitor is coupled to the gate of the driving transistor, and the second plate of the first capacitor is coupled to the corresponding power line.

4. The display substrate according to claim 3, characterized in that, The display substrate further includes at least two second control signal lines; the third sub-pixel driving circuit further includes a driving transistor, a first control transistor, and a second control transistor; the third capacitor storage unit includes a fourth capacitor and a sixth capacitor. The first plate of the fourth capacitor is coupled to the gate of the driving transistor, and the second plate of the fourth capacitor is coupled to the corresponding power line. The first plate of the fifth capacitor is coupled to the gate of the driving transistor, the second plate of the fifth capacitor is coupled to the first electrode of the first control transistor, the second electrode of the first control transistor is coupled to the corresponding power supply line, and the gate of the first control transistor is coupled to the corresponding first control signal line. The first plate of the sixth capacitor is coupled to the gate of the driving transistor, the second plate of the sixth capacitor is coupled to the first plate of the second control transistor, the second plate of the second control transistor is coupled to the corresponding power supply line, and the gate of the second control transistor is coupled to the corresponding second control signal line.

5. The display substrate according to claim 3, characterized in that, The capacitance value of the second capacitor is equal to the capacitance value of the first capacitor, and the capacitance value of the third capacitor is half of the capacitance value of the first capacitor.

6. The display substrate according to claim 3, characterized in that, The first plate of the second capacitor and the first plate of the third capacitor are formed as an integral structure; the second plate of the second capacitor and the second plate of the third capacitor are disposed in the same layer, and the second plates of the second capacitor and the second plates of the third capacitor are arranged along a first direction.

7. The display substrate according to claim 3, characterized in that, The driving transistor includes a driving active pattern; the orthographic projection of the second plate of the third capacitor on the substrate overlaps at least partially with the orthographic projection of the driving active pattern on the substrate.

8. The display substrate according to claim 4, characterized in that, The capacitance value of the fourth capacitor is equal to that of the first capacitor, the capacitance value of the fifth capacitor is half the capacitance value of the first capacitor, and the capacitance value of the sixth capacitor is 1.5 times the capacitance value of the first capacitor.

9. The display substrate according to claim 4, characterized in that, The first plate of the fourth capacitor, the first plate of the fifth capacitor, and the first plate of the sixth capacitor are formed as an integral structure; The second plates of the fourth capacitor, the fifth capacitor, and the sixth capacitor are disposed on the same layer. The second plates of the fourth capacitor and the fifth capacitor are arranged along a first direction. The second plates of the fourth capacitor and the sixth capacitor are arranged along the first direction. The second plates of the fifth capacitor and the sixth capacitor are arranged along a second direction, which intersects with the first direction.

10. The display substrate according to claim 4, characterized in that, The driving transistor includes a driving active pattern; the orthographic projection of the second plate of the fifth capacitor on the substrate overlaps at least partially with the orthographic projection of the driving active pattern on the substrate. And / or, the orthographic projection of the second plate of the sixth capacitor onto the substrate overlaps at least partially with the orthographic projection of the driving active pattern onto the substrate.

11. The display substrate according to claim 3 or 4, characterized in that, The first conductive connection portion includes a first sub-connection portion and a second sub-connection portion coupled together, the first sub-connection portion extending along the first direction and the second sub-connection portion extending along the second direction; The first sub-connection portion is coupled to the second active portion, and the second sub-connection portion is coupled to the second plate of the third capacitor or the second plate of the fifth capacitor.

12. The display substrate according to claim 11, characterized in that, The display substrate further includes a plurality of light-emitting control signal lines, at least a portion of which extend along the first direction; The orthographic projection of the first sub-connection portion on the substrate does not overlap with the orthographic projection of the light-emitting control signal line on the substrate, while the orthographic projection of the second sub-connection portion on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate.

13. The display substrate according to claim 12, characterized in that, The first control signal line includes at least a portion extending along the first direction; The orthographic projection of the first sub-connection portion on the substrate is located between the orthographic projection of the light emission control signal line on the substrate and the orthographic projection of the first control signal line on the substrate.

14. The display substrate according to claim 11, characterized in that, The sub-pixels in the display substrate also include light-emitting elements, and the light-emitting elements include an anode pattern; the orthographic projection of the first sub-connection portion on the substrate overlaps at least partially with the orthographic projection of the anode pattern belonging to the same sub-pixel on the substrate.

15. The display substrate according to claim 4, characterized in that, The third sub-pixel driving circuit further includes a second conductive connection portion; the second control transistor further includes a second control active pattern, the second control active pattern including at least a portion extending along a first direction, the first end of the second control active pattern serving as the first electrode of the second control transistor, the first end of the second control active pattern being coupled to the second electrode plate of the sixth capacitor through the second conductive connection portion, and the second end of the second control active pattern serving as the second electrode of the second control transistor.

16. The display substrate according to claim 15, characterized in that, The display substrate further includes a plurality of gate lines, the gate lines including at least a portion extending along the first direction; The orthographic projection of the second conductive connection portion on the substrate overlaps at least partially with the orthographic projection of the gate line on the substrate.

17. The display substrate according to claim 15, characterized in that, The second control signal line includes a control body portion and a control protrusion coupled together. The control body portion includes at least a portion extending along the first direction. The orthographic projection of the control protrusion on the substrate is located between the orthographic projection of the control body portion on the substrate and the orthographic projection of the gate line on the substrate. The control protrusion is coupled to the gate of the second control transistor.

18. The display substrate according to claim 1, characterized in that, The distance between two adjacent first sub-pixel driving circuits in the same row, the distance between two adjacent second sub-pixel driving circuits in the same row, and the distance between two adjacent third sub-pixel driving circuits in the same row are all the same. On the same side of the center line extending along the second direction of the display substrate, the first boundary of the first sub-pixel driving circuit closest to the center line, the first boundary of the second sub-pixel driving circuit closest to the center line, and the first boundary of the third sub-pixel driving circuit closest to the center line are aligned. The first boundary is the boundary facing the center line.

19. The display substrate according to claim 18, characterized in that, The sub-pixel also includes a light-emitting element, which includes an anode pattern. The anode pattern includes an anode body and an anode connection portion coupled together. The anode connection portion is coupled to the sub-pixel driving circuit included in its sub-pixel. The anode body portion of the anode pattern coupled to the first sub-pixel driving circuit, the anode body portion of the anode pattern coupled to the second sub-pixel driving circuit, and the anode body portion of the anode pattern coupled to the third sub-pixel driving circuit are arranged in an array.

20. The display substrate according to claim 1, characterized in that, i = n - 4, m = n - 2.

21. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 20.

22. A driving method for a display substrate, characterized in that, For driving a display substrate as described in any one of claims 1 to 20, the display substrate includes at least two second control signal lines; the third sub-pixel driving circuit further includes a driving transistor, a first control transistor, and a second control transistor; the third capacitor storage unit includes a fourth capacitor and a sixth capacitor; the first plate of the fourth capacitor is coupled to the gate of the driving transistor, and the second plate of the fourth capacitor is coupled to a corresponding power supply line; the first plate of the fifth capacitor is coupled to the gate of the driving transistor, the second plate of the fifth capacitor is coupled to the first electrode of the first control transistor, the second electrode of the first control transistor is coupled to a corresponding power supply line, and the gate of the first control transistor is coupled to a corresponding first control signal line; the first plate of the sixth capacitor is coupled to the gate of the driving transistor, the second plate of the sixth capacitor is coupled to the first electrode of the second control transistor, the second electrode of the second control transistor is coupled to a corresponding power supply line, and the gate of the second control transistor is coupled to a corresponding second control signal line; the driving method includes: When charging sub-pixels from row i+1 to row m, the first control signal line controls the first control transistor to turn on. When charging sub-pixels from row (m+1) to row (n), the first control signal line controls the first control transistor to turn on, and the second control signal line controls the second control transistor to turn on.

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