A data transmission system and signal generator that enables high-speed and low-power bidirectional read / write.

Abstract

This application provides a data transmission system and signal generator that realizes high-speed and low-power bidirectional read / write operations. Based on MIPI D-PHY, it realizes bidirectional read / write operations between the signal generator and the display module in low-power mode, and write operations to the display module in high-speed mode. The data transmission system of this application not only implements the functionality of a bidirectional LP interface, but also reduces the complexity of hardware and software design, increases reliability, and saves costs.

Description

Technical Field

[0001] This application relates to the field of image transmission, and in particular to a data transmission system and signal generator that enables high-speed and low-power bidirectional read / write. Background Technology

[0002] The purpose of MIPI (Mobile Industry Processor Interface) is to standardize interfaces on the back of mobile phones, such as camera and display interfaces. Currently, the more mature MIPI interface applications are DSI (Display Interface) and CSI (Camera Interface).

[0003] Currently, the commonly used MIPI display solution on the market uses a dedicated MIPI bridge chip, with the video stream input being a DPI interface. However, the bandwidth of the data input interface is limited and cannot meet the data throughput requirements of high-resolution screens. Furthermore, when it is necessary to implement HS (high-speed) video transmission and LP (low-power) bidirectional read / write, since existing FPGAs do not have bidirectional LP interfaces or LP-CD (low-power contention detector) functionality, it is necessary to separate the reception and transmission of HS and LP signals in MIPI using MIPI level conversion chips and switching circuits, and implement this using multiple I / O (input-output) ports. This results in high complexity and low reliability in hardware and software design. Moreover, the use of level conversion chips requires more complex circuit structures, which also increases the cost. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a data transmission system and signal generator that realizes high-speed and low-power bidirectional read and write, in order to solve the problems of the inability to realize the function of bidirectional LP bidirectional interface in the prior art, as well as the high complexity, low reliability and high cost of hardware and software design.

[0005] To achieve the above and other related objectives, this application provides a transmission system for high-speed and low-power bidirectional read / write using MIPI D-PHY, comprising: a host computer module, a signal generator, and a display module; wherein, the host computer module is used to send first image information and a first control command; the signal generator, connected to the host computer module, is used to, in low-power mode, write display configuration information obtained based on the first control command to the display module in the form of MIPI signals and send corresponding display status information read from the display module to the host computer module; in high-speed mode, it writes second image information obtained by processing the first image information based on the first control command to the display module in the form of MIPI signals, for the display module to display accordingly.

[0006] In some embodiments of this application, the signal generator includes: a main control module, an FPGA-based signal interface module, and a power supply module for supplying power to the display module; wherein, the main control module is connected to the host computer module and is used to send the first image information in LVDS signal form and send a second control command generated based on the first control command; the FPGA-based signal interface module is connected to the main control module and is used, based on MIPI D-PHY, in low-power mode, to write display configuration information obtained based on the second control command to the display module in MIPI signal form and to read corresponding display status information from the display module for sending to the host computer module; in high-speed mode, to write second image information obtained by processing the first image information sent in LVDS signal form based on the second control command to the display module in MIPI signal form, for the display module to perform corresponding display.

[0007] In some embodiments of this application, the FPGA-based signal interface module includes: a control state module, a processing module, and a DSI controller module; wherein, the control state module is used to issue image configuration control signals and display configuration control signals obtained based on a second control command obtained from the main control module; the processing module is connected to the main control module and is used to process the first image information based on the image configuration control signals to obtain and store the second image information; the DSI controller module is connected to the control state module and the processing module respectively, and is used to write display configuration information obtained based on the display configuration control signals to the display module in the form of MIPI signals in low-power mode and read the corresponding display state information from the display module; and to write the second image information obtained from the processing module to the display module in the form of MIPI signals in high-speed mode for the display module to perform corresponding display.

[0008] In some embodiments of this application, the DSI controller module includes: a low-power read / write mode module, a high-speed write mode module, a configuration interface, and a DSI transmission submodule; wherein, the DSI transmission submodule is connected to the low-power read / write mode module, the high-speed write mode module, and the configuration interface, and is used to receive a display configuration signal transmitted by the control state module through the low-power read / write mode module, and, in conjunction with the configuration interface, write the display configuration information to the display module in the form of a MIPI signal in low-power mode; read the corresponding display status information from the display module in low-power mode, and transmit the display status information to the main control module through the low-power read / write mode module; the DSI transmission submodule is also used to receive second image information transmitted by the processing module through the high-speed write mode module, and, in conjunction with the configuration interface, write the second image information to the display module in the form of a MIPI signal in high-speed mode, so that the display module can perform corresponding display.

[0009] In some embodiments of this application, the FPGA-based signal interface module further includes a double-rate synchronous dynamic random access memory connected to the processing module, for providing additional image caching functionality.

[0010] In some embodiments of this application, the FPGA-based signal interface module further includes: an RGB interface connecting the processing module and the DSI transmission submodule, used to transmit second image information obtained from the processing module to the DSI transmission submodule.

[0011] In some embodiments of this application, the FPGA-based signal interface module further includes: a first interface selector, connected between the control state module and the low-power read / write mode module, for expanding interfaces of different signal transmission types to output corresponding signals according to the corresponding signal transmission methods, so as to test the configuration interfaces of different signal transmission types of the display module.

[0012] In some embodiments of this application, the FPGA-based signal interface module further includes: a second interface selector, connected between the processing module and the RGB interface, for extending the RGB interface to transmit RGB signals for testing the image interface of the display module.

[0013] In some embodiments of this application, the display module is a high-resolution display screen.

[0014] To achieve the above and other related objectives, this application also provides a signal generator for implementing a high-speed and low-power bidirectional read / write data transmission system. The system includes a host computer module, a signal generator, and a display module. The signal generator includes a main control module, an FPGA-based signal interface module, and a power supply module for supplying power to the display module. The main control module, connected to the host computer module, is used to send first image information acquired from the host computer module in LVDS signal form and to send a second control instruction generated based on a first control instruction acquired from the host computer module. The FPGA-based signal interface module, connected to the main control module, is used to write display configuration information acquired based on the second control instruction to the display module in MIPI signal form in low-power mode, and to read corresponding display status information from the display module for transmission to the host computer module. In high-speed mode, it writes second image information obtained by processing the first image information sent in LVDS signal form based on the second control instruction to the display module in MIPI signal form, for the display module to display accordingly.

[0015] As described above, the data transmission system and signal generator of this application, which realizes high-speed and low-power bidirectional read / write, have the following advantages: Based on MIPI D-PHY, this application realizes bidirectional read / write operations between the signal generator and the display module in low-power mode and write operations to the display module in high-speed mode. The data transmission system of this application not only realizes the function of a bidirectional LP interface, but also reduces the complexity of hardware and software design, increases reliability, and saves costs. Attached Figure Description

[0016] Figure 1 The diagram shown is a schematic of a transmission system structure that implements high-speed and low-power bidirectional read / write in one embodiment of this application.

[0017] Figure 2 The diagram shown is a schematic diagram of a signal generator structure in one embodiment of this application.

[0018] Figure 3 The diagram shown is a schematic diagram of the FPGA-based signal interface module structure in one embodiment of this application.

[0019] Figure 4 The diagram shown is a schematic representation of the processing module and the DSI controller module in one embodiment of this application.

[0020] Figure 5 The diagram shown is a schematic of the FPGA-based signal interface module structure for extending the IIC / SPI interface in an embodiment of this application.

[0021] Figure 6 The diagram shown is a schematic of the FPGA-based signal interface module structure for extending the RGB interface in an embodiment of this application. Detailed Implementation

[0022] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0023] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0024] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising,” “including,” indicate the presence of the stated features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. It should be further understood that the terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, or operations is inherently mutually exclusive in some way.

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the invention.

[0027] MIPI (Mobile Industry Processor Interface) is a standard developed for mobile application processors. FPGAs contain a hard-core D-PHY IP. MIPI D-PHY is the physical layer of MIPI, comprising two protocol layers: CSI (Camera Serial Interface) and DSI (Display Serial Interface). CSI is primarily used in devices such as cameras, while DSI is primarily used in devices such as displays. Through MIPI D-PHY, write commands at a single lane rate of 2.5Gbps can be achieved in high-speed (HS) mode. In low-power (LP) mode, the signal generator's I / O (Input-Output) can be set to bidirectional, allowing the signal generator to be configured as the master and the MIPI interface display as the slave, or vice versa, thus enabling bidirectional read and write of command signals.

[0028] This invention provides a data transmission system based on MIPI D-PHY that achieves high-speed and low-power bidirectional read / write, such as... Figure 1 As shown, the system includes: a host computer module 1, a signal generator 2, and a display module 3;

[0029] The host computer module 1 is used to send out the first image information and the first control command. The host computer module 1 refers to a computer or microcontroller that can directly send operation commands. Devices that can serve as host computers include computers, mobile phones, tablets, panels, touch screens, etc., which will not be listed here.

[0030] Signal generator 2, connected to the host computer module 1, receives first image information and first control commands from the host computer module 1. Based on MIPI D-PHY, in low-power mode, it writes display configuration information obtained based on the first control commands to the display module 3 in MIPI signal form and reads corresponding display status information from the display module 3 and sends it to the host computer module 1. In high-speed mode, it writes second image information obtained by processing the first image information based on the first control commands to the display module 3 in MIPI signal form, for the display module 3 to perform corresponding display. The host computer module 1 is connected to the network port of signal generator 2 via a network cable.

[0031] Display module 3 is connected to signal generator 2 and is used to display second image information sent in the form of MIPI signal; wherein, display module 3 is a display screen with MIPI interface and is composed of a high-resolution screen.

[0032] In some embodiments of the present invention, the first image information is video image information; the host computer module 1 sends the video image information and a first control command to the signal generator 2; the signal generator 2 obtains display configuration information from the first control command; wherein, the display configuration information includes: initialization information for initializing the display module 3 based on the pixel format of the second image information sent to the display module 3 so that the display module 3 can display the second image information accordingly.

[0033] In some embodiments of the present invention, the signal generator 2 and the display module 3 have the following two transmission modes:

[0034] Low power mode: In low power mode, bidirectional read and write operations are performed between signal generator 2 and display module 3; specifically, signal generator 2 is set as the master and display module 3 is the slave, and signal generator 2 performs write operations on display module 3; alternatively, signal generator 2 can be set as the slave and display module 3 as the master, and signal generator 2 performs read operations on display module 3; bidirectional read and write operations between signal generator 2 and display module 3 are completed through the above write and read operations.

[0035] Specifically, signal generator 2 receives a first control command sent from host computer module 1, obtains display configuration information based on the first control command, and writes the display configuration information to display module 3 for corresponding configuration. Signal generator 2 reads corresponding display status information from display module 3 and sends the display status information to host computer module 1 to obtain information about the status of display module 3. The display status information includes: display module status information, data packet format, etc. Signal generator 2 can check whether errors occurred during the transmission of the second image information to display module 3 by reading the display status information.

[0036] High-speed mode: In high-speed mode, signal generator 2 writes image information to display module 3 at high speed so that display module 3 can display the image information.

[0037] Specifically, the host computer module 1 sends the first image information to the signal generator 2. The signal generator 2 processes the first image information based on the first control command to obtain the second image information and sends the second image information to the display module 3 for display.

[0038] It should be noted that display configuration information needs to be sent to display module 3 first for display module 3 to perform initial configuration before display module 3 can display the second image information accordingly; bidirectional read and write in low power mode and write in high speed mode cannot be performed simultaneously; image information, display configuration information and display status information transmitted between signal generator 2 and display module 3 are all transmitted in the form of MIPI signals.

[0039] In some embodiments of the present invention, the signal generator 2, such as Figure 2 As shown, it includes: a main control module 21, an FPGA-based signal interface module 22, and a power supply module 23 for supplying power to the display module;

[0040] The main control module 21 is connected to the host computer module 1 and is used to send the first image information and the second control command generated based on the first control command to the FPGA-based signal interface module 22 in the form of LVDS signal. The main control module 21 is composed of a microprocessor, which generates the second control command for configuring the display module 3 based on the first control command sent by the host computer module 1 and sends the second control command to the FPGA-based signal interface module 22.

[0041] It should be noted that LVDS (Low-Voltage Differential Signaling) signals are signals with advantages such as low power consumption, low bit error rate, low crosstalk and low radiation, and are often used in high-speed data transmission scenarios.

[0042] The FPGA-based signal interface module 22 consists of a 2-port FPGA with a line rate of 2.5Gbps. It is connected to the main control module 21 and the display module 3, respectively. It obtains display configuration information from the second control command. Based on MIPI D-PHY, in low power mode, it writes the display configuration information to the display module 3 in the form of MIPI signals for configuration of the display module 3. It also sends the corresponding display status information read from the display module 3 to the host computer module 1 through the main control module 21.

[0043] In high-speed mode, the FPGA-based signal interface module 22 writes a second control command to the display module 3 in the form of a MIPI signal to process the first image information sent in the form of an LVDS signal, and obtains the second image information for the display module 3 to display accordingly.

[0044] It should be noted that by configuring the resources inside the FPGA, the level conversion chip can be omitted in the hardware circuit, and the FPGA-based signal interface module 22 can directly output the MIPI signal required by the display module.

[0045] The power supply module 23, which supplies power to the display module, is connected to the main control module 21 and the display module 3, and is used to control the voltage output, power-on sequence, and power monitoring of the display module 3.

[0046] In some embodiments of the present invention, the power supply module 23 that supplies power to the display module is composed of a microcontroller and peripheral circuits.

[0047] In some embodiments of the present invention, the FPGA-based signal interface module 22, such as Figure 3 As shown, it includes: a control status module 221, a processing module 222, and a DSI controller module 223;

[0048] Among them, the control status module 221 is connected to the main control module 21 and the DSI controller module 223 respectively, and is used to issue image configuration control signals and display configuration control signals based on the second control command obtained from the main control module 21;

[0049] Processing module 222 is connected to the main control module 21 and the DSI controller module 223 respectively, and is used to process the first image information based on the image configuration control signal to obtain and store the second image information;

[0050] Specifically, processing module 222, such as Figure 4As shown, the system includes: a video data decoder, a write controller, a read controller, and a timing controller. The video data decoder is connected to the main control module 21 and is used to decode the first image information received from the main control module 21 in LVDS signal form to obtain decoded image information, which is then sent to the write controller. The write controller, read controller, and timing controller are all connected to the control state module 221. The control state module 221 configures the parameters of the write controller, read controller, and timing controller based on the image configuration control signal obtained from the second control command received from the main control module 21. The processing module 222 processes the first image information based on the configured parameters to obtain second image information and sends it to the DSI controller module 223. The processing module 222 can also implement image caching and timing control functions. Furthermore, due to the image caching function of the processing module 222, the display module 3 can display high-resolution image information.

[0051] In some embodiments of the present invention, such as Figure 4 As shown, a Double Rate Synchronous Dynamic Random Access Memory (DDR) controller is connected between the write controller and the read controller. The DDR controller is connected to the DDR to provide additional caching functionality. When image information is transmitted to the processing module 222, if the currently transmitted image information does not need to be displayed in the display module 3 at this moment, the currently transmitted image information will be temporarily stored in the DDR.

[0052] For example, when image data is transmitted from signal generator 2 to display module 3, the image data is divided into multiple data packets for transmission. When a data packet is transmitted to processing module 222, the image corresponding to the data packet does not need to be displayed on display module 3. The data packet is temporarily stored in double rate synchronous dynamic random access memory (DDR). When the image corresponding to the data packet needs to be displayed on display module 3, the data packet is sent to DSI controller module 223.

[0053] In some preferred embodiments of the present invention, the double data rate synchronous dynamic random access memory (DDR) is DDR3.

[0054] DSI controller module 223, such as Figure 4As shown, it is connected to the control state module 221 and the processing module 222 respectively. It is used to write the display configuration information to the display module in the form of MIPI signal in low power mode and read the corresponding display status information from the display module. It is sent to the main control module 21 through the control state module 221, and the main control module 21 sends the display status information to the host computer module. In high speed mode, it writes the second image information obtained from the processing module 221 to the display module in the form of MIPI signal for the display module to perform corresponding display.

[0055] In some embodiments of the present invention, such as Figure 4 As shown, the DSI controller module 223 includes: a low-power read / write mode module, a high-speed write mode module, a configuration interface, and a DSI transmission submodule; wherein, the DSI transmission submodule is connected to the low-power read / write mode module, the high-speed write mode module, and the configuration interface.

[0056] The two transmission modes can be implemented through the DSI controller module 223 as follows:

[0057] (1) Low power mode: The DSI transmission submodule is used to receive the display configuration signal transmitted by the control status module through the low power read / write mode module, and in conjunction with the configuration interface, write the display configuration information to the display module in the form of MIPI signal in low power mode; read the corresponding display status information from the display module in low power mode, and transmit the display status information to the main control module through the low power read / write mode module, and the main control module then sends the display status information to the host computer module;

[0058] (2) High-speed mode: DSI transmission submodule, used to receive the second image information transmitted by the processing module through the high-speed write mode module and, in conjunction with the configuration interface, write the second image information to the display module in the form of MIPI signal in high-speed mode so that the display module can perform corresponding display.

[0059] It should be noted that the configuration interface is used to configure the DSI controller module 223, enabling the DSI controller module 223 to support multiple pixel formats and image transmission modes.

[0060] In some embodiments of the present invention, such as Figure 4As shown, the FPGA-based signal interface module also includes an RGB interface between the access processing module and the DSI transmission submodule, used to transmit the second image information obtained from the processing module to the DSI transmission submodule; specifically, the RGB interface is connected between the timing controller and the DSI transmission submodule, and the RGB interface includes various signals, such as HS, VS, DEN, Pixel_data, etc., which are adapted to the display requirements of display modules with different resolutions through the timing control module.

[0061] In some embodiments of the present invention, such as Figure 5 As shown, the FPGA-based signal interface module includes: a first interface selector, connected between the control state module and the low-power read / write mode module, used to expand interfaces for different signal transmission types to output corresponding signals according to the corresponding signal transmission methods, for testing the configuration interfaces of different signal transmission types of the display module; wherein, the expanded interface can be an IIC (Inter-Integrated Circuit) interface or an SPI (Serial Peripheral Interface) interface. When it is necessary to test the IIC signal interface, the IO ports and configuration module of the FPGA-based signal interface module are configured to output IIC signals accordingly for testing the IIC interface of the display module; when it is necessary to test the SPI signal interface, the IO ports and configuration module of the FPGA-based signal interface module are configured to output SPI signals accordingly for testing the SPI interface of the display module.

[0062] In some embodiments of the present invention, such as Figure 6 As shown, the FPGA-based signal interface module includes a second interface selector, connected between the processing module and the RGB interface, used to expand the RGB interface to transmit RGB signals for testing the image interface of the display module. Specifically, by configuring the I / O ports and configuration module of the FPGA-based signal interface module, RGB signals can be output to meet the testing requirements of the display module's image interface.

[0063] The present invention also provides a signal generator, which is applied to a data transmission system for realizing high-speed and low-power bidirectional read and write. The system includes: a host computer module, a signal generator, and a display module. The signal generator includes: a main control module, an FPGA-based signal interface module, and a power supply module for supplying power to the display module.

[0064] The main control module is connected to the host computer module and is used to send the first image information obtained from the host computer module in the form of LVDS signal and to send the second control command generated based on the first control command obtained from the host computer module.

[0065] The FPGA-based signal interface module is connected to the main control module. It is used to write display configuration information obtained based on the second control command to the display module in low-power mode via MIPI signals, and to read corresponding display status information from the display module for transmission to the host computer module. In high-speed mode, it writes second image information obtained by processing the first image information sent in LVDS signal form based on the second control command to the MIPI module via MIPI signals, for the display module to display accordingly.

[0066] Since the signal generator in this embodiment can perform all the functions of the signal generator in the above embodiments, it will not be repeated here.

[0067] In summary, this application provides a data transmission system and signal generator that achieves high-speed and low-power bidirectional read / write operations. Based on MIPI D-PHY, it realizes bidirectional read / write operations between the signal generator and the display module in low-power mode, and write operations to the display module in high-speed mode. The data transmission system of this application not only implements the functionality of a bidirectional LP interface, but also reduces the complexity of hardware and software design, increases reliability, and saves costs. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0068] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A data transmission system for achieving high-speed and low-power bidirectional read / write, characterized in that, include: The host computer module, signal generator, and display module; The host computer module is used to send out the first image information and the first control command; The signal generator, connected to the host computer module, is used to write display configuration information obtained based on the first control command to the display module in the form of a MIPI signal in low-power mode, and to read corresponding display status information from the display module and send it to the host computer module; in high-speed mode, it writes second image information obtained by processing the first image information based on the first control command to the display module in the form of a MIPI signal, so that the display module can perform corresponding display. The signal generator includes: a main control module, an FPGA-based signal interface module, and a power supply module for supplying power to the display module; Furthermore, the main control module, connected to the host computer module, is used to send the first image information and the second control command generated based on the first control command to the FPGA-based signal interface module in the form of LVDS signal; the main control module is composed of a microprocessor, which generates the second control command for configuring the display module based on the first control command sent by the host computer module and sends the second control command to the FPGA-based signal interface module. The FPGA-based signal interface module consists of a 2-port FPGA with a line rate of 2.5Gbps, connected to the main control module and the display module respectively. It is used to obtain display configuration information from the second control command. Based on MIPI D-PHY, in low-power mode, it writes display configuration information to the display module in MIPI signal form for configuration, and sends the corresponding display status information read from the display module to the host computer module through the main control module. In high-speed mode, it writes second image information based on the second control command to the display module in MIPI signal form, processes the first image information sent in LVDS signal form, and obtains the second image information for the display module to display accordingly.

2. The system according to claim 1, characterized in that, The FPGA-based signal interface module includes: a control status module, a processing module, and a DSI controller module; The control status module is used to issue image configuration control signals and display configuration control signals based on the second control command obtained from the main control module. The processing module is connected to the main control module and is used to process the first image information based on the image configuration control signal to obtain and store the second image information; The DSI controller module is connected to the control state module and the processing module respectively. In low power mode, it writes the display configuration information obtained based on the display configuration control signal to the display module in the form of a MIPI signal and reads the corresponding display state information from the display module. In high speed mode, it writes the second image information obtained from the processing module to the display module in the form of a MIPI signal for the display module to perform corresponding display.

3. The system according to claim 2, characterized in that, The DSI controller module includes: a low-power read / write mode module, a high-speed write mode module, a configuration interface, and a DSI transmission submodule. The DSI transmission submodule, connected to the low-power read / write mode module, the high-speed write mode module, and the configuration interface, is used to receive the display configuration signal transmitted by the control status module through the low-power read / write mode module, and, in conjunction with the configuration interface, write the display configuration information to the display module in the form of a MIPI signal in low-power mode; and, in low-power mode, read the corresponding display status information from the display module and transmit the display status information to the main control module through the low-power read / write mode module. The DSI transmission submodule is also used to receive the second image information transmitted by the processing module through the high-speed write mode module, and in conjunction with the configuration interface, write the second image information to the display module in the form of a MIPI signal in high-speed mode so that the display module can perform corresponding display.

4. The system according to claim 3, characterized in that, The FPGA-based signal interface module further includes a double-rate synchronous dynamic random access memory connected to the processing module, used to provide additional image caching functionality.

5. The system according to claim 4, characterized in that, The FPGA-based signal interface module further includes an RGB interface connecting the processing module and the DSI transmission submodule, used to transmit the second image information obtained from the processing module to the DSI transmission submodule.

6. The system according to claim 5, characterized in that, The FPGA-based signal interface module further includes: a first interface selector, connected between the control state module and the low-power read / write mode module, used to expand the interface for different signal transmission types to output corresponding signals according to the corresponding signal transmission method, so as to test the configuration interface of different signal transmission types of the display module.

7. The system according to claim 5, characterized in that, The FPGA-based signal interface module further includes a second interface selector, which is connected between the processing module and the RGB interface to extend the RGB interface to transmit RGB signals for testing the image interface of the display module.

8. The system according to claim 1, characterized in that, The display module is a high-resolution display screen.

9. A signal generator, characterized in that, A data transmission system for achieving high-speed and low-power bidirectional read / write is provided. The system includes: a host computer module, a signal generator, and a display module. The signal generator includes: a main control module, an FPGA-based signal interface module, and a power supply module for supplying power to the display module. The main control module is connected to the host computer module and is used to send the first image information obtained from the host computer module in the form of LVDS signal and to send the second control command generated based on the first control command obtained from the host computer module. The main control module is composed of a microprocessor and generates the second control command for configuring the display module based on the first control command sent by the host computer module and sends the second control command to the FPGA-based signal interface module. The FPGA-based signal interface module consists of a 2-port FPGA with a line rate of 2.5Gbps, connected to the main control module and the display module respectively. It is used to write display configuration information obtained based on the second control command to the display module in MIPI signal form in low-power mode, based on MIPI D-PHY, for configuring the display module. It also sends the corresponding display status information read from the display module to the host computer module through the main control module. In high-speed mode, it writes second image information obtained by processing the first image information sent in LVDS signal form based on the second control command to the display module in MIPI signal form, for the display module to display accordingly.

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