Solid-state imaging device and electronic apparatus

Abstract

This invention proposes an advantageous layout of circuit structure and light-receiving elements. A solid-state imaging device according to an embodiment includes: a plurality of unit pixels (110) arranged in a two-dimensional grid; an arbitrator (104) arbitrating the readout of the plurality of unit pixels; and a first signal processing circuit (103) processing a first signal output from each unit pixel. Each unit pixel includes: a plurality of photoelectric conversion units (PDs) arranged in a two-dimensional grid; and a plurality of detection circuits (210) detecting brightness changes of light entering the photoelectric conversion unit based on photocurrent flowing from each photoelectric conversion unit and outputting the first signal. The plurality of photoelectric conversion units are disposed on a first chip (140). At least a portion of each detection circuit, the arbitrator, and the first signal processing circuit are disposed on a second chip (150) stacked on the first chip. A first region of the first chip, in which the plurality of photoelectric conversion units are arranged, and a second region of the second chip, in which at least a portion of each detection circuit is arranged, at least partially overlap each other in the stacking direction of the first chip and the second chip. Logic circuitry including the arbitrator and the first signal processing circuit is disposed in a third region of the second chip, at least a portion of which is adjacent to the second region.

Description

Technical Field

[0001] This disclosure relates to solid-state imaging devices and electronic devices. Background Technology

[0002] In solid-state imaging devices using complementary metal-oxide-semiconductor (CMOS) and the like, asynchronous solid-state imaging elements that detect brightness changes in each pixel as events in real time have been proposed (e.g., Patent Document 1). As described above, solid-state imaging elements that detect events in each pixel are also referred to as event-based vision sensors (EVS) or dynamic vision sensors (DVS).

[0003] List of citations

[0004] Patent documents

[0005] Patent Document 1: JP2017-535999A Summary of the Invention

[0006] Technical issues

[0007] However, in addition to the circuitry required to convert the photocurrent flowing from each pixel into a voltage signal, EVS also requires circuitry to detect events based on the voltage signal. However, traditionally, a suitable layout has not been proposed for these circuitry configurations and the mounting of the light-receiving elements on a single chip.

[0008] Therefore, this disclosure proposes a solid-state imaging device and electronic device in which circuit configuration and light receiving elements are appropriately arranged.

[0009] Solution to the problem

[0010] To address the aforementioned problems, a solid-state imaging apparatus according to an embodiment of the present disclosure includes: a plurality of unit pixels arranged in a two-dimensional grid pattern; an arbitrator that arbitrates readouts from the plurality of unit pixels; and a first signal processing circuit that processes a first signal output from each unit pixel, wherein each unit pixel includes: a plurality of photoelectric conversion units arranged in a two-dimensional grid pattern; and a plurality of detection circuits that detect brightness changes of incident light toward the photoelectric conversion units based on photocurrent flowing from each photoelectric conversion unit and output the first signal. The plurality of photoelectric conversion units are arranged on a first chip, at least a portion of each detection circuit, the arbitrator, and the first signal processing circuit are arranged on a second chip stacked on the first chip, a first region in the first chip in which the plurality of photoelectric conversion units are arranged, and a second region in the second chip in which at least a portion of each detection circuit is arranged, at least partially overlapping in the stacking direction of the first chip and the second chip, and a logic circuit including the arbitrator and the first signal processing circuit is arranged in a third region in the second chip that is at least partially adjacent to the second region. Attached Figure Description

[0011] Figure 1 It is a schematic diagram depicting an example of an electronic device on which a solid-state imaging apparatus according to the first embodiment is mounted.

[0012] Figure 2 It is a block diagram depicting a system configuration example of an electronic device according to the first embodiment.

[0013] Figure 3 This is a block diagram illustrating a schematic configuration example of a solid-state imaging apparatus according to a first embodiment.

[0014] Figure 4 This is a diagram illustrating an example of a stacked structure of a solid-state imaging apparatus according to a first embodiment.

[0015] Figure 5 This is a circuit diagram illustrating a schematic configuration example of a unit pixel according to the first embodiment.

[0016] Figure 6 This is a circuit diagram illustrating a schematic configuration example of the address event detection circuit according to the first embodiment.

[0017] Figure 7 This is a circuit diagram illustrating a schematic configuration example of a current-to-voltage conversion circuit according to the first embodiment.

[0018] Figure 8 This is a circuit diagram illustrating another schematic configuration example of the current-to-voltage conversion circuit according to the first embodiment.

[0019] Figure 9 This is a circuit diagram illustrating a schematic configuration example of a unit pixel according to a variation of the first embodiment.

[0020] Figure 10 This is a plan view showing a layout example of a circuit chip according to a first layout example of a first embodiment.

[0021] Figure 11 It is a plan view describing a layout example of a pixel chip according to a first layout example of a first embodiment.

[0022] Figure 12 This is a plan view showing a layout example of a circuit chip according to a second layout example of the first embodiment.

[0023] Figure 13 This is a plan view showing a layout example of a circuit chip according to a third layout example of the first embodiment.

[0024] Figure 14 This is a plan view illustrating a layout example of a circuit chip according to a fourth layout example of the first embodiment.

[0025] Figure 15 This is a plan view illustrating a layout example of a circuit chip according to a fifth layout example of the first embodiment.

[0026] Figure 16 This is a diagram illustrating an example of a stacked structure of a solid-state imaging apparatus according to a variation of the first embodiment.

[0027] Figure 17 This is a plan view illustrating a layout example of a pixel chip according to a variation of the first embodiment.

[0028] Figure 18 This is a plan view illustrating a layout example of the first circuit chip according to a variation of the first embodiment.

[0029] Figure 19 This is a plan view illustrating a layout example of the second circuit chip according to a variation of the first embodiment.

[0030] Figure 20 It is a plan view describing a layout example of a circuit chip according to a first layout example of the second embodiment.

[0031] Figure 21 This is a plan view illustrating a layout example of a circuit chip according to a second layout example of a second embodiment.

[0032] Figure 22 This is a front exterior view of a smartphone, a specific example of an electronic device according to the present disclosure.

[0033] Figure 23 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0034] Figure 24 This diagram illustrates an example of the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0035] In the following description, embodiments of the present disclosure will be presented in detail based on the accompanying drawings. Furthermore, in the following embodiments, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted.

[0036] Furthermore, this disclosure will be described in the following order.

[0037] 1. First Embodiment

[0038] 1.1 System Configuration Example

[0039] 1.2 Configuration Examples of Solid-State Imaging Devices

[0040] 1.3 Examples of Stacked Structures for Solid-State Imaging Devices

[0041] 1.4 Circuit configuration example per unit pixel

[0042] 1.4.1 Luminance Pixels

[0043] 1.4.2 Event Pixels

[0044] 1.4.2.1 Configuration Example of Address Event Detection Circuit

[0045] 1.4.2.2 Configuration Example of Optical Receiver Circuit

[0046] 1.4.2.3 Modifications to the optical receiving circuit

[0047] 1.4.3 Variations related to pixel sharing

[0048] 1.5 Chip Layout Example

[0049] 1.5.1 First Layout Example

[0050] 1.5.2 Example of the second layout

[0051] 1.5.3 Example of the third layout

[0052] 1.5.4 Example of the fourth layout

[0053] 1.5.5 Fifth Layout Example

[0054] 1.6 Conclusion

[0055] 1.7 Variation Example

[0056] 1.7.1 Example of a stacked structure for a solid-state imaging device

[0057] 1.7.2 Chip Layout Example

[0058] 2. Second Embodiment

[0059] 2.1 Chip Layout Example

[0060] 2.1.1 Example of the first layout

[0061] 2.1.2 Example of the second layout

[0062] 2.2 Conclusion

[0063] 3. Specific examples of electronic devices

[0064] 4. Examples of applications to moving bodies

[0065] 1. First Embodiment

[0066] First, the solid-state imaging apparatus and electronic device according to the first embodiment will be described in detail with reference to the accompanying drawings. In this embodiment, a solid-state imaging apparatus and electronic device having a hybrid structure in which an EVS based on a brightness change detection event and an image sensor that detects brightness and generates image data are integrated into a single chip will be described as an example. Note that in the following description, a complementary metal-oxide-semiconductor (CMOS) image sensor (hereinafter simply referred to as an image sensor) will be described as an example of an image sensor. However, this is not limiting, and various sensors including photoelectric conversion elements, such as charge-coupled device (CCD) image sensors and time-of-flight (ToF) sensors, can be employed.

[0067] 1.1 System Configuration Example

[0068] Figure 1 This is a schematic diagram illustrating an example configuration of an electronic device on which a solid-state imaging apparatus according to the first embodiment is mounted. Figure 2 This is a block diagram illustrating a system configuration example of an electronic device according to a first embodiment.

[0069] like Figure 1 As shown, the electronic device 1 according to this embodiment includes a laser light source 1010, an illumination lens 1030, an imaging lens 1040, a solid-state imaging device 100, and a system control unit 1050.

[0070] like Figure 2 As shown, the laser source 1010 includes, for example, a vertical-cavity surface-emitting laser (VCSEL) 1012 and a light source driving unit 1011 for driving the VCSEL 1012. However, the VCSEL 1012 is not limiting, and various light sources, such as light-emitting diodes (LEDs), can be used. Furthermore, the laser source 1010 can be any of a point source, a surface source, and a line source. In the case of a surface source or a line source, the laser source 1010 may have, for example, a configuration of one-dimensional or two-dimensional arrangement of multiple point sources (such as VCSELs). It should be noted that, in this embodiment, for example, the laser source 1010 may emit light in a wavelength band different from the wavelength band of visible light (such as infrared (IR) light).

[0071] An illumination lens 1030 is arranged on the emitting surface side of the laser source 1010 and converts the light emitted from the laser source 1010 into illumination light with a predetermined divergence angle.

[0072] An imaging lens 1040 is disposed on the light-receiving surface side of the solid-state imaging device 100 and forms an image by incident light on the light-receiving surface of the solid-state imaging device 100. The incident light may also include reflected light emitted from the laser source 1010 and reflected onto the object 901.

[0073] Although details will be described later, such as Figure 2 As shown, the solid-state imaging device 100 includes, for example, a light receiving unit 1022 and a sensor control unit 1021. In the light receiving unit 1022, pixels for detecting brightness (hereinafter referred to as brightness pixels) and pixels for detecting events (hereinafter referred to as event pixels) are arranged in a two-dimensional grid pattern. The sensor control unit 1021 generates image data by driving the light receiving unit 1022 based on the brightness signal detected by each brightness pixel (hereinafter referred to as image frame data) and the event data detected by each event pixel (hereinafter referred to as event frame data).

[0074] The system control unit 1050 includes, for example, a processor (CPU) and drives the VCSEL 1012 via the light source driving unit 1011. Furthermore, the system control unit 1050 acquires image frame data by controlling the solid-state imaging device 100, and acquires event data based on the emission / extinction detection of the laser light source 1010 by controlling the solid-state imaging device 100 in synchronization with the control of the laser light source 1010.

[0075] For example, illumination light emitted from laser source 1010 is projected onto object (also called measurement target or object) 901 through illumination lens 1030. The projected light is reflected on object 901. The light reflected from object 901 then passes through imaging lens 1040 and is incident on solid-state imaging device 100. EVS in solid-state imaging element 100 receives the reflected light from object 901, generates event data, and generates event frame data as an image based on the generated event data. On the other hand, image sensor in solid-state imaging device 100 receives, for example, visible light in the incident light and generates image frame data. The image frame data and event frame data generated by solid-state imaging device 100 are provided to application processor 1100 of electronic device 1. Application processor 1100 performs predetermined processing, such as image processing and recognition processing, on the image frame data and event frame data input from solid-state imaging device 100.

[0076] 1.2 Configuration Examples of Solid-State Imaging Devices

[0077] Figure 3 This is a block diagram illustrating a schematic configuration example of a solid-state imaging apparatus according to a first embodiment. (As shown...) Figure 3 As shown, the solid-state imaging apparatus 100 according to this embodiment includes, for example, a pixel array unit 101, a vertical driving circuit 102A, a horizontal driving circuit 102B, an X arbiter 104A, a Y arbiter 104B, a luminance signal processing circuit 103A, an event signal processing circuit 103B, a system control circuit 105, a luminance data processing unit 108A, and an event data processing unit 108B.

[0078] The pixel array section 101 has a configuration in which unit pixels 110, which are repeating units in the pixel layout, are arranged in the row direction and the column direction (i.e., a two-dimensional grid pattern (also called a matrix pattern)). Here, the row direction (also called row direction) refers to the array direction of pixels in a pixel row (the horizontal direction in the figure), and the column direction (also called column direction) refers to the array direction of pixels in a pixel column (the vertical direction in the figure). It should be noted that the repeating unit described herein is different from the repeating unit in a color filter array such as a Bayer array or a quad Bayer array, and can be a repeating configuration unit in the device design.

[0079] Each unit pixel 110 includes one or more luminance pixels 10 and one or more event pixels 20. In this specification, each of the luminance pixels 10 and event pixels 20 may be simply referred to as a pixel. Although details of the specific circuit configuration and pixel structure of each unit pixel 110 will be described later, the luminance pixel 10 includes a photoelectric conversion element that generates and accumulates a charge corresponding to the luminance of the incident light, and generates a luminance signal of voltage based on the luminance. On the other hand, each of the event pixels 20 includes a photoelectric conversion element to generate a charge corresponding to the luminance of the incident light, and, upon detecting a change in the luminance of the incident light based on the photocurrent flowing from the photoelectric conversion element, outputs a readout request to the X arbitrator 104A and Y arbitrator 104B according to the arbitration of the X arbitrator 104A and Y arbitrator 104B, and outputs event data indicating that an event was detected.

[0080] In the pixel array section 101, for the pixel array in matrix mode, pixel driving lines LD1 and LD2 are routed in the row direction of each pixel row, and vertical signal lines VSL1 and VSL2 are routed in the column direction of each pixel column. For example, pixel driving line LD1 is connected to the luminance pixel 10 in each row, and pixel driving line LD2 is connected to the event pixel 20 in each row. On the other hand, for example, vertical signal line VSL1 is connected to the luminance pixel 10 in each column, and vertical signal line VSL2 is connected to the event pixel 20 in each column. However, this is not limiting, and pixel driving lines LD1 and LD2 can be routed orthogonally to each other. Similarly, vertical signal lines VSL1 and VSL2 can be routed orthogonally to each other. For example, pixel driving line LD1 can be routed in the row direction, pixel driving line LD2 can be routed in the column direction, vertical signal line VSL1 can be routed in the column direction, and vertical signal line VSL2 can be routed in the row direction.

[0081] Pixel drive line LD1 transmits control signals to execute driving when reading luminance signals from each luminance pixel 10. Pixel drive line LD2 transmits control signals to cause each of the event pixels 20 to enter a valid state where an event can be detected. Although each of pixel drive lines LD1 and LD2... Figure 3 The image is shown as a single wiring, but the number of such wirings is not limited to one. One end of each of the pixel drive lines LD1 and LD2 is connected to the output terminal corresponding to each row of the vertical drive circuit 102A.

[0082] (Driver configuration for luminance pixels)

[0083] As will be described in detail later, each brightness pixel 10 includes a photoelectric conversion unit and a pixel circuit. The photoelectric conversion unit photoelectrically converts incident light and generates an electric charge. The pixel circuit generates a brightness signal having a voltage value corresponding to the amount of charge generated in the photoelectric conversion unit, and under the control of the vertical drive circuit 102A, the brightness signal appears in the vertical signal line VSL1.

[0084] The vertical drive circuit 102A includes a shift register, an address decoder, etc., and drives the luminance pixels 10 of the pixel array 101 simultaneously with respect to all pixels or on a row-by-row basis. That is, the vertical drive circuit 102A and the system control circuit 105 that controls the vertical drive circuit 102A are included in the drive unit that controls the operation of each luminance pixel 10 of the pixel array 101. The vertical drive circuit 102A typically includes two scanning systems: a readout scanning system and a scan scanning system, although their specific configurations are not illustrated.

[0085] The readout scanning system selectively scans the pixels of the pixel array 101 sequentially, row by row, to read out a signal from each pixel. The brightness signal read from each pixel is an analog signal. Before the readout scanning exposure, the check scan system performs a check scan on the readout rows that have been read out by the readout scanning system.

[0086] By scanning with a scanning system, unwanted charges are removed from the photoelectric conversion elements of each pixel in the readout line, thereby resetting the photoelectric conversion elements. Then, by removing (resetting) unwanted charges through the scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the process of discarding the charge from the photoelectric conversion elements and starting a new exposure (initiating the accumulation of charge).

[0087] The signal read out by the readout scanning system corresponds to the amount of light received immediately following the preceding readout operation or electronic shutter operation. Then, the time period from the readout timing of the preceding readout operation or the scan timing of the electronic shutter operation to the readout timing of the current readout operation is the charge accumulation period (also known as the exposure period) in each pixel.

[0088] The luminance signal output from each luminance pixel 10 in the pixel row selectively scanned by the vertical drive circuit 102A is input to the luminance signal processing circuit 103A through each vertical signal line VSL1 for each pixel column. For each pixel column of the pixel array section 101, the luminance signal processing circuit 103A performs predetermined signal processing on the luminance signal output from each luminance pixel 10 in the selected row through the vertical signal line VSL1, and temporarily holds the luminance signal after the signal processing.

[0089] Specifically, as signal processing, the luminance signal processing circuit 103A performs at least noise removal processing, such as correlated double sampling (CDS) processing or dual data sampling (DDS) processing. For example, CDS processing removes pixel-specific fixed-pattern noise, such as reset noise and threshold variations of the amplifying transistors in the pixel. The luminance signal processing circuit 103A also has, for example, an analog-to-digital (AD) conversion function, which converts the analog luminance signal read from the photoelectric conversion element into a digital signal and outputs the digital signal.

[0090] The horizontal drive circuit 102B includes a shift register, an address decoder, etc., and sequentially selects the readout circuits (hereinafter referred to as pixel circuits) corresponding to the pixel columns of the luminance signal processing circuit 103A. Through selective scanning by the horizontal drive circuit 102B, the luminance signals processed in each pixel circuit of the luminance signal processing circuit 103A are sequentially output.

[0091] (Driver configuration for event pixels)

[0092] Each event pixel 20 detects the presence or absence of an event based on whether a change exceeding a predetermined threshold occurs in the photocurrent corresponding to the brightness of the incident light. For example, each event pixel 20 detects events where the brightness change exceeds or falls below the predetermined threshold as events.

[0093] When an event is detected, each event pixel 20 requests permission from each of the X arbitrator 104A and Y arbitrator 104B to output event data indicating the generation of the event. Then, upon receiving a response from each of the X arbitrator 104A and Y arbitrator 104B indicating permission to output event data, each event pixel 20 outputs the event data to the vertical drive circuit 102A and the event signal processing circuit 103B.

[0094] Furthermore, the event pixel 20 that detects the event outputs an analog luminance signal generated by photoelectric conversion to the luminance signal processing circuit 103A. That is, as a result of the arbitration performed by the X arbitrator 104A and the Y arbitrator 104B, the event pixel 20 that is allowed to perform readout requests its own drive from the vertical drive circuit 102A. On the other hand, by driving the luminance pixel 10 that is paired with the arbitrated event pixel 20, the vertical drive circuit 102A reads the luminance signal from the luminance pixel 10.

[0095] The X arbitrator 104A arbitrates requests for output of event data from each of the multiple event pixels 20, and transmits a response (allow / disallow output of event data) based on the arbitration result and a reset signal to reset the event detection to each of the event pixels 20 that made the output request.

[0096] The event signal processing circuit 103B performs predetermined signal processing on each input event data from the event pixel 20 and outputs the processed event data.

[0097] As described above, the change in photocurrent generated in each event pixel 20 can also be considered as a change in the amount of light (brightness change) incident on the photoelectric conversion unit of the event pixel 20. Therefore, it can also be said that the event is a change in the amount of light (brightness change) in the event pixel 20 that exceeds a predetermined threshold. Event data indicating the occurrence of an event includes at least location information, such as coordinates indicating the position of the event pixel 20 where the amount of light changes due to the event. In addition to location information, event data may also include the polarity of the light change.

[0098] For a series of event data output from event pixel 20 at the time of event generation, as long as the interval between the event data at the time of event generation is maintained as is, it can be said that the event data implicitly includes time information indicating the relative time of event generation.

[0099] However, when the interval between multiple event data entries is not maintained at the interval when the event was generated due to storing event data in a memory or the like, the time information implicitly included in the event data is lost. Therefore, before the interval between the event data at the time of the event is no longer maintained, the event signal processing circuit 103B may include time information representing the relative time of the event generation, such as a timestamp in the event data.

[0100] (Other configurations)

[0101] The system control circuit 105 includes a timing generator that generates various timing signals, and performs drive control of the vertical drive circuit 102A, horizontal drive circuit 102B, X arbiter 104A, Y arbiter 104B, luminance signal processing circuit 103A, event signal processing circuit 103B, etc., based on the various timing signals generated by the timing generator.

[0102] Each of the luminance data processing unit 108A and the event data processing unit 108B has at least one arithmetic processing function, performing various signal processing such as arithmetic processing on the image data (image frame data and event frame data) output from the luminance signal processing circuit 103A or the event signal processing circuit 103B.

[0103] For example, the image data output from the brightness data processing unit 108A or the event data processing unit 108B can be processed in a predetermined manner in the application processor 1100 or the like in the electronic device 1 on which the solid-state imaging device 100 is installed, or can be transmitted to the outside via a predetermined network.

[0104] It should be noted that the solid-state imaging device 100 may include a storage unit to temporarily store data required for signal processing in the luminance data processing unit 108A and the event data processing unit 108B, as well as data processed by any one or more of the luminance signal processing circuit 103A, the event signal processing circuit 103B, the luminance data processing unit 108A, and the event data processing unit 108B.

[0105] 1.3 Examples of Stacked Structures for Solid-State Imaging Devices

[0106] Figure 4 This is a diagram illustrating an example of a stacked structure of a solid-state imaging apparatus according to a first embodiment. (See diagram for example.) Figure 4 As shown, the solid-state imaging device 100 has a structure in which pixel chips 140 and circuit chips 150 are vertically stacked. Pixel chip 140 is, for example, a semiconductor chip including a photoelectric conversion unit of each of luminance pixels 10 and event pixels 20 and a part of the circuit structure in luminance pixels 10 and event pixels 20, and circuit chip 150 is a semiconductor chip including structures other than those arranged in pixel chip 140.

[0107] For the bonding of pixel chip 140 and circuit chip 150, for example, a so-called direct bonding can be used, in which their bonding surfaces are planarized and bonded to each other by forces between electrons. However, this is not limiting, and for example, so-called Cu-Cu bonding, bump bonding, etc., in which copper (Cu) electrode pads formed on the bonding surfaces are bonded to each other can also be used.

[0108] Furthermore, for example, the pixel chip 140 and the circuit chip 150 are electrically connected via a connection such as a through-contact via (TCV) penetrating the semiconductor substrate. For connections using TCVs, for example, a so-called dual TCV method can be employed, wherein two TCVs providing the TCV in the pixel chip 140 and a TCV provided from the pixel chip 140 to the circuit chip 150 are connected on the outer surface of the chip; a so-called shared TCV method can be employed, wherein the two are connected by a TCV penetrating from the pixel chip 140 to the circuit chip 150, and so on.

[0109] However, in the case of Cu-Cu bonding or bump bonding for bonding pixel chip 140 and circuit chip 150, the two can be electrically connected via Cu-Cu bonding or bump bonding.

[0110] 1.4 Circuit configuration example per unit pixel

[0111] Next, we will describe an example of the circuit configuration for each unit pixel 110. Figure 5 This is a circuit diagram illustrating a schematic configuration example of a unit pixel according to the first embodiment. (e.g.) Figure 5 As shown, unit pixel 110 includes a luminance pixel 10 and an event pixel 20.

[0112] 1.4.1 Luminance Pixels

[0113] The brightness pixel 10 includes, for example, a photoelectric conversion unit PD, a transmission transistor 11, a floating diffusion region FD, a reset transistor 12, an amplification transistor 13, and a selection transistor 14.

[0114] For example, the photoelectric conversion unit PD and the transmission transistor 11 in the brightness pixel 10 can be arranged on the pixel chip 140. On the other hand, the reset transistor 12, the amplification transistor 13, and the selection transistor 14 can be arranged on the pixel chip 140 or on the circuit chip 150.

[0115] The selection control line included in the pixel driving line LD1 is connected to the gate of the selection transistor 14, the reset control line included in the pixel driving line LD1 is connected to the gate of the reset transistor 12, and the transfer control line included in the pixel driving line LD1 is connected to the gate of the transfer transistor 11. Furthermore, the vertical signal line VSL1, one end of which is connected to the luminance signal processing circuit 103A, is connected to the drain of the amplification transistor 13 via the selection transistor 14.

[0116] In this specification, the reset transistor 12, the amplification transistor 13, and the selection transistor 14 are also collectively referred to as pixel circuit 111. The pixel circuit 111 may include a floating diffusion region FD and / or a transfer transistor 11.

[0117] For example, the photoelectric conversion unit PD photoelectrically converts incident light and generates a charge corresponding to the amount of light (brightness). The transfer transistor 11 transfers the charge generated in the photoelectric conversion unit PD. The floating diffusion region FD accumulates the charge transferred by the transfer transistor 11. The amplification transistor 13 causes a brightness signal corresponding to the voltage value of the charge accumulated in the floating diffusion region FD to appear on the vertical signal line VSL1. The reset transistor 12 releases the charge accumulated in the floating diffusion region FD. The selection transistor 14 selects the brightness pixel 10 as the readout target.

[0118] The anode of the photoelectric conversion unit PD is grounded, and its cathode is connected to the transfer transistor 11. The charge flowing out through the transfer transistor 11 is accumulated in the floating diffusion region FD, which has a wiring structure connecting the source of the reset transistor 12 and the gate of the amplification transistor 13. Note that the drain of the reset transistor 12 can be connected to, for example, the power supply voltage VDD or a power supply line that provides a reset voltage lower than the power supply voltage VDD.

[0119] The source of amplifying transistor 13 can be connected to a power supply line via, for example, a constant current circuit (not shown). The drain of amplifying transistor 13 is connected to the source of select transistor 14, and the drain of select transistor 14 is connected to the vertical signal line VSL1.

[0120] The floating diffusion region FD converts the accumulated charge into a voltage corresponding to the amount of charge. Note that the floating diffusion region FD can be, for example, a capacitance to ground. However, the floating diffusion region FD is not limited to the above, and can also be a capacitance added intentionally through a capacitor or other means, such as a capacitor, to connect the nodes of the drain of transistor 11, the source of reset transistor 12, and the gate of amplifying transistor 13.

[0121] The vertical signal line VSL1 is connected to an analog-to-digital (AD) conversion circuit 103a in the luminance signal processing circuit 103A, which is provided for each column (i.e., each vertical signal line VSL1). The AD conversion circuit 103a includes, for example, a comparator and a counter, and converts the analog luminance signal into a digital luminance signal by comparing a reference voltage with a single slope, ramp shape, etc., of the voltage input from an external reference voltage generation circuit (digital-to-analog converter (DAC)) with the luminance signal appearing in the vertical signal line VSL1. It should be noted that the AD conversion circuit 103a may include, for example, a correlated double sampling (CDS) circuit, and may be configured to reduce kTC noise, etc.

[0122] 1.4.2 Event Pixels

[0123] Event pixel 20 includes, for example, a photoelectric conversion unit PD, a discharge transistor 21, and an address event detection circuit 210. The photoelectric conversion unit PD may be the same as the photoelectric conversion unit PD of the luminance pixel 10. That is, in this embodiment, one photoelectric conversion unit PD may be shared by the luminance pixel 10 and the event pixel 20. However, this is not limiting, and the luminance pixel 10 and the event pixel 20 may include separate photoelectric conversion units. In this case, the discharge transistor 21 may be omitted.

[0124] For example, the photoelectric conversion unit PD and the discharge transistor 21 in the event pixel 20 can be arranged on the pixel chip 140. On the other hand, the address event detection circuit 210 can be arranged on the circuit chip 150.

[0125] The discharge transistor 21 causes the photocurrent flowing from the photoelectric conversion unit PD to flow into the address event detection circuit 210.

[0126] As will be described in detail later, the address event detection circuit 210 detects the presence or absence of an event based on changes in the photocurrent flowing from the photoelectric conversion unit PD, and when an event is detected as described above, it sends a request to each of the X arbitrator 104A and Y arbitrator 104B to allow the output of event data indicating the generation of the event. Then, upon receiving a response from each of the X arbitrator 104A and Y arbitrator 104B indicating permission to output event data, the address event detection circuit 210 outputs the event data to the vertical drive circuit 102A and the event signal processing circuit 103B. At this time, the address event detection circuit 210 may include time information indicating the relative time of the event generation, such as a timestamp in the event data.

[0127] The vertical signal line VSL2 is connected to the signal processing circuit 103b, for example, which is set in each column (i.e., each vertical signal line VSL2) of the event signal processing circuit 103B.

[0128] 1.4.2.1 Configuration Example of Address Event Detection Circuit

[0129] Next, a configuration example of the address event detection circuit 210 in event pixel 20 will be described. Event pixel 20 detects whether an event has occurred based on whether the change in photocurrent exceeds a predetermined threshold. This event includes, for example, an "On" event indicating that the change in photocurrent exceeds an upper threshold and an "Off" event indicating that the change is below a lower threshold. Furthermore, event data (event information) indicating the occurrence of an event includes, for example, one bit indicating the detection result of an "On" event and one bit indicating the detection result of an "Off" event. Note that event pixel 20 may be configured to detect only "On" events or only "Off" events.

[0130] Figure 6 This is a circuit diagram illustrating a schematic configuration example of the address event detection circuit according to this embodiment. It should be noted that... Figure 6 The document describes a configuration example of a comparator that performs the detection of turn-on events and turn-off events in a time-division manner.

[0131] like Figure 6 As shown, the address event detection circuit 210 includes an optical receiving circuit 212, a memory capacitor 213, a comparator 214, a reset circuit 215, an inverter 216, and an output circuit 217.

[0132] Although details will be described later, the optical receiving circuit 212 is... Figure 7 or Figure 8 The method described includes, for example, a current-to-voltage conversion circuit, and the photocurrent I flowing from the photoelectric conversion unit PD. photo Converted to voltage V pr Here, the voltage V pr The relationship with light intensity (brightness) is usually logarithmic. That is, the light receiving circuit 212 generates a photocurrent I corresponding to the intensity of the light emitted to the light receiving surface of the photoelectric conversion unit PD. photo Voltage V converted into a logarithmic function pr However, the photocurrent I photo and voltage V pr The relationships between them are not limited to logarithmic relationships.

[0133] Corresponding to photocurrent I photo and the voltage V output from the light receiving circuit 212 pr Through memory capacitor 213, it then becomes the inverting (-) input (first input) of comparator 214 as voltage V. diff Comparator 214 typically includes a differential pair transistor. Comparator 214 uses a threshold voltage V provided from the sensor control unit 1021. b It serves as a non-inverting (+) input (second input) and performs turn-on and turn-off event detection in a time-division manner. Furthermore, after a turn-on / turn-off event is detected, the reset circuit 215 resets the event pixel 20.

[0134] The sensor control unit 1021 will control the voltage V during the detection of the on-event phase. on As the threshold voltage V b Output voltage V during the disconnection event detection phase. off And during the time-division reset phase, the output voltage V reset Voltage V reset Set as voltage V on and voltage V offThe value between, preferably voltage V on and voltage V off The intermediate value between. Here, "intermediate value" means not only including cases that are strictly intermediate values, but also cases that are essentially intermediate values, and allows for various variations caused by design or manufacturing.

[0135] Furthermore, the sensor control unit 1021 outputs an on selection signal to the event pixel 20 during the on-event detection phase, an off-event detection phase, and a global reset signal during the reset phase. The on selection signal is provided as a control signal to the selection switch SW provided between the inverter 216 and the output circuit 217. on The disconnect selection signal is provided as a control signal to the selection switch SW provided between comparator 214 and output circuit 217. off .

[0136] During the event detection phase, comparator 214 converts voltage V... on With voltage V diff Compare, and as a result of the comparison, when voltage V diff Exceeding voltage V on At that time, the output indicates the photocurrent I. photo The change in the signal exceeds the upper limit threshold, triggering an on event. The on event is inverted by inverter 216 and then transmitted via selector switch SW. on It is provided to the output circuit 217.

[0137] During the disconnection event detection phase, comparator 214 will convert the voltage V off With voltage V diff Compare, and as a result of the comparison, when voltage V diff Becomes lower than voltage V off Time output indicating photocurrent I photo The change in the amount of the event occurs when the disconnection event information (Off) falls below the lower threshold. The disconnection event information (Off) is transmitted via the selector switch SW. off It is provided to the output circuit 217.

[0138] The reset circuit 215 includes a reset switch SW. RS Configuration of the 2-input OR circuit 2151 and the 2-input AND circuit 2152. Reset switch SW. RS It is connected between the inverting (-) input terminal and the output terminal of comparator 214, and selectively performs a short circuit between the inverting input terminal and the output terminal by changing to the ON (OFF) state.

[0139] In OR circuit 2151, via selector switch SW onOn event information and via selector switch SW off The off event information Off has two inputs. With the output signal of the OR circuit 2151 as one input and the global reset signal provided from the sensor control unit 1021 as the other input, when the on event information On or the off event information Off is detected and the global reset signal is active, the AND circuit 2152 turns on (closes) the reset switch SW. RS .

[0140] As described above, when the output signal of the AND circuit 2152 becomes active, the reset switch SW... RS A short circuit is applied between the inverting input terminal and the output terminal of comparator 214, and a global reset is performed on event pixel 20. As a result, the reset operation is performed only on event pixel 20 that detected the event.

[0141] Output circuit 217 has a configuration including a disconnect event output transistor NM1, a turn-on event output transistor NM2, and a current source transistor NM3. Disconnect event output transistor NM1 has a memory (not shown) to retain disconnect event information Off at its gate. This memory includes the gate parasitic capacitance of disconnect event output transistor NM1.

[0142] Similar to the off event output transistor NM1, the on event output transistor NM2 has a memory (not shown) to retain the on event information On at its gate. This memory includes the gate parasitic capacitance of the on event output transistor NM2.

[0143] During the readout phase, when a row selection signal is provided from the sensor control unit 1021 to the gate electrode of the current source transistor NM3, the disconnection event information Off, stored in the memory of the disconnection event output transistor NM1, and the on-event information On, stored in the memory of the on-event event output transistor NM2, are transmitted to the readout circuit 130 via the output lines nRxOff and nRxOn of each pixel row of the pixel array unit 101. The readout circuit 130 is, for example, a circuit provided in the event signal processing circuit 103B (see...). Figure 3 ).

[0144] As described above, the event pixel 20 according to the first circuit configuration example has an event detection function: under the control of the sensor control unit 1021, it detects on-time events and off-time events by using a comparator 214 in a time-division manner.

[0145] 1.4.2.2 Configuration Example of Optical Receiver Circuit

[0146] Figure 7This is a circuit diagram illustrating a basic configuration example of the optical receiving circuit according to this embodiment. For example... Figure 7 As shown, the light receiving circuit 212 includes n-channel metal-oxide-semiconductor (nMOS) transistors 312 and 313 and a p-channel MOS (pMOS) transistor 314. For example, the two nMOS transistors 312 and 313 are included in a logarithmic converter circuit that converts the photocurrent flowing from the photoelectric conversion unit PD into a voltage signal corresponding to its logarithmic value. Wiring connected to the gate of the nMOS transistor 313 and wiring into which the photocurrent from the photoelectric conversion unit PD flows serve as a sensing node SN when an event is detected. The nMOS transistor 313 may correspond to, for example, the second transistor as claimed in the claim, and the nMOS transistor 312 may correspond to, for example, the third transistor as claimed in the claim.

[0147] Furthermore, in the logarithmic conversion circuit including two nMOS transistors 312 and 313, the pMOS transistor 314 operates as a load MOS transistor. Note that the photoelectric conversion unit PD and the nMOS transistors 312 and 313 can be arranged, for example, on the pixel chip 140, and the pMOS transistor 314 can be arranged on the circuit chip 150.

[0148] The source of nMOS transistor 312 is connected to the cathode of the photoelectric conversion unit PD, and its drain is connected to the power supply terminal. PMOS transistor 314 and nMOS transistor 313 are connected in series between the power supply terminal and the ground terminal. Furthermore, the connection point of pMOS transistor 314 and nMOS transistor 313 is connected to the gate of nMOS transistor 312 and the input terminal of logic circuit 211, and is used to output a voltage signal V to logic circuit 211. pr The output node. In addition, a predetermined bias voltage Vbias1 is applied to the gate of the pMOS transistor 314.

[0149] The drains of nMOS transistors 312 and 313 are connected to the power supply side, and such a circuit is called a source follower. The photocurrent from the photoelectric conversion unit PD is converted into a voltage signal V corresponding to its logarithm by two source followers connected in a loop. pr In addition, pMOS transistor 314 supplies a constant current to nMOS transistor 313.

[0150] It should be noted that the grounding of pixel chip 140 and the grounding of circuit chip 150 can be separated from each other to combat interference.

[0151] 1.4.2.3 Modifications to the optical receiving circuit

[0152] Although Figure 7 The source follower type optical receiver circuit 212 has been described, but such a configuration is not limiting. Figure 8 This is a circuit diagram illustrating a basic configuration example of the optical receiving circuit according to a modified embodiment of this invention. For example... Figure 8 As shown, the optical receiving circuit 212A according to a modified example includes, for example, a so-called gain boost circuit configuration, wherein an nMOS transistor 315 connected in series between an nMOS transistor 312 and a power supply line and an nMOS transistor 316 connected in series between an nMOS transistor 313 and a pMOS transistor 314 are added. Figure 7 The source follower type photoreceiver circuit 212 is shown. For example, four nMOS transistors 312, 313, 315, and 316 are included in a logarithmic converter circuit that converts the photocurrent flowing out of the photoconversion unit PD into a voltage signal V corresponding to its logarithmic value. pr .

[0153] As described above, even when using the gain boost type optical receiver circuit 212A, it is possible to convert the photocurrent from the photoelectric conversion unit PD into a voltage signal V having a logarithmic value corresponding to its charge quantity. pr .

[0154] 1.4.3 Variations related to pixel sharing

[0155] Figure 9 This is a circuit diagram illustrating a schematic configuration example of a unit pixel according to a variation of the first embodiment. For example... Figure 9 As shown, according to the modified example, unit pixel 110-1 includes multiple ( Figure 9 The four luminance pixels in the image are 10⁻⁰ to 10⁻³ and multiple (…). Figure 9 The four event pixels 20-0 to 20-3 in the pixel array section 101. For example, the multiple luminance pixels 10-0 to 10-3 and the multiple event pixels 20-0 to 20-3 can be arranged into an M×N matrix pattern (M and N are integers 1 or larger) in the pixel array section 101.

[0156] In this configuration, multiple luminance pixels 10-1 to 10-4 included in a unit pixel 110-1 can share a single pixel circuit 111. Therefore, switching can be performed between an operating mode in which a pixel includes one photoelectric conversion unit PD and an operating mode in which a luminance pixel includes multiple photoelectric conversion units PD (such as high dynamic range (HDR)).

[0157] 1.5 Chip Layout Example

[0158] Next, the layout of each of the pixel chip 140 and circuit chip 150 according to this embodiment will be described with some examples.

[0159] 1.5.1 First Layout Example

[0160] Figure 10 and Figure 11 This is a plan view illustrating an example of a chip layout according to a first layout example of this embodiment. Figure 10 The layout example of circuit chip 150A is depicted, and Figure 11 The layout example of pixel chip 140A is depicted in the figure.

[0161] (Circuit chip)

[0162] like Figure 10 As shown, the circuit chip 150A according to the first layout example includes, for example, an EVS analog front-end circuit (hereinafter referred to as EVS_AFE) 151, a logic circuit (LOGIC) 152, a vertical drive circuit (VSCANNER) 153, a successive approximation analog-to-digital converter circuit (hereinafter referred to as SARADC) 155, an interface section (I / F) 157, peripheral circuits 158, and connection sections (via contact vias (TCVs)) 154 and 156.

[0163] EVS_AFE 151, for example, includes a portion of the address event detection circuit 210 within the aforementioned event pixel 20 (e.g., see reference 210). Figure 9 The logic circuit (EVS_AFE) 211 and pMOS transistor 314 (refer to) Figure 7 or Figure 8 Arranged in a two-dimensional grid pattern and included in a portion of the aforementioned pixel array 101 (see reference). Figure 3 The structure of ).

[0164] Logic circuit 152 includes, for example Figure 3 The configuration shown includes a horizontal drive circuit 102B, an event signal processing circuit 103B, an X arbiter 104A, a Y arbiter 104B, a luminance data processing unit 108A, and an event data processing unit 108B, which control the luminance pixel 10 and the event pixel 20, and process the signals read from the luminance pixel 10 and the event pixel 20. This logic circuit 152 can be arranged adjacent to EVS_AFE 151. Furthermore, the logic circuit 152 may include a storage section such as static random access memory (SRAM).

[0165] Vertical drive circuit 153 corresponds to, for example Figure 3The vertical drive circuit 102A is shown. The connection portion 154, arranged adjacent to the vertical drive circuit 153, can be a through electrode that routes pixel drive lines LD1 and LD2 from the vertical drive circuit 153 to the pixel chip 140A. The vertical drive circuit 153 can be arranged in a direction perpendicular to the column direction of the pixel array portion 101 in the pixel chip 140A (horizontal direction (lateral direction in the figure)).

[0166] SARADC 155 is, for example Figure 3 The luminance signal processing circuit 103A, or a portion thereof (AD conversion function), shown converts the analog luminance signal read from the luminance pixel 10 into a digital signal. Note that the AD conversion function of the luminance signal processing circuit 103A is not necessarily a SARADC and can be modified in various ways. It can be an ADC that converts the analog luminance signal into a digital signal by comparing a reference voltage with a single slope or ramp shape with the luminance signal. The connection portion 156 arranged adjacent to the SARADC 155 can be a through electrode that routes the vertical signal lines VSL1 and VSL2 in the pixel chip 140A to the circuit chip 150A. Furthermore, the SARADC 155 can be arranged in the column direction (vertical direction (longitudinal direction in the figure)) of the pixel array portion 101 in the pixel chip 140A.

[0167] Apart from Figure 3 In addition to the system control circuit 105 shown, the peripheral circuit 158 ​​may also include, for example, various peripheral circuits such as a thermometer.

[0168] The interface section 157 can be, for example, an interface conforming to standards such as MIPI, and outputs various data (such as image frame data and event frame data) processed by the logic circuit 152 and / or peripheral circuit 158 ​​to the outside. This interface section 157 can also be configured near the main pad P1, described later. In this case, by arranging the functional blocks of the logic circuit 152 in such a way that the output terminals of the logic circuit 152 are located near the interface section 157, effects such as increasing the speed of signal output and reducing propagation loss can be achieved.

[0169] (Pixel chip)

[0170] like Figure 11 As shown, for example, the pixel chip 140A according to the first layout example includes a pixel array section 101 (excluding EVS_AFE 151), connection sections 144 and 146, and wiring sections 143 and 145.

[0171] Pixel array section 101 is, for example, Figure 3 The pixel array section 101 shown (excluding a portion of the address event detection circuit 210 (see example)) Figure 9It includes an effective pixel area (PIXEL_ARRAY) 141 and a light-shielding pixel area (Optical Black (OPB)) 142. The effective pixel area 141 is at least an area where the photoelectric conversion units (PDs) in the luminance pixel 10 and the event pixel 20 are arranged in a two-dimensional grid pattern. The light-shielding pixel area 142 can be, for example, an area where pixels with light-shielding photoelectric conversion units (PDs) are arranged in the same configuration as the luminance pixel 10 and the event pixel 20. This light-shielding pixel area 142 can be arranged in the column direction relative to the effective pixel area 141 (column direction...). Figure 11 The head or end in the longitudinal direction of the middle.

[0172] Furthermore, the effective pixel region 141 can be arranged in the substrate thickness direction corresponding to... Figure 10 In the area of ​​EVS_AFE151 depicted in the diagram. As a result, in the stacked structure where pixel chip 140A and circuit chip 150A are vertically stacked, each event pixel 20 in pixel chip 140A and each address event detection circuit 210 in EVS_AFE 151 of circuit chip 150A can be aligned.

[0173] For example, connection portion 144 is configured to be continuous with or connected to connection portion 154 in circuit chip 150A. Connection portion 146 is configured to be continuous with or connected to connection portion 156 in circuit chip 150A. Furthermore, wiring portion 143 may be part of pixel driving lines LD1 and LD2, and wiring portion 145 may be part of vertical signal lines VSL1 and VSL2.

[0174] In the above configuration, in the first layout example, the pad (hereinafter also referred to as the main pad) P1 for external connection is arranged near one of the four chip ends L1 to L4, chip end L1. As a result, the connection configuration for connecting external devices and solid-state imaging devices 100, such as flexible cables, can be simplified. This improves the efficiency of connection structure design, assembly operations, etc. It should be noted that, for example, chip end L1 may be substantially perpendicular to each of chip ends L2 and L3, and chip ends L2 and L3, as well as chip ends L1 and L4, may be substantially parallel to each other. That is, the pixel chip 140 and the circuit chip 150 may have rectangular shapes of the same size.

[0175] In addition, test pads (hereinafter also referred to as test pads) P2, and spare or auxiliary power pads (hereinafter also referred to as spare power pads) P3a, P3b, and P4 can be placed at other chip terminals L2 to L4 of the circuit chip 150A. For example, spare power pad P3b can be used as an auxiliary power pad to control the power drop of the SARADC 155.

[0176] Note that the main pad P1 includes signal pads for controlling the solid-state imaging device 100 (image sensor and EVS), power pads for supplying power to each part, etc. By arranging the main pad P1 near a chip end L1, in the first layout example, the pixel array section 101 (including EVS_AFE 151) is arranged near the chip end L3 on the opposite side of the chip end L1. Furthermore, in the circuit chip 150A, the vertical drive circuit 153 and the connection section 154 are arranged between the main pad P1 and the EVS_AFE 151, and the SARADC 155 and the connection section 156 are arranged on a chip end orthogonal to the chip end L1 near which the main pad P1 is arranged (chip end L4 in this example).

[0177] By adopting this layout, the wiring lengths of the vertical signal lines VSL1 and VSL2 can be shortened to transmit the luminance signal and event data read from the luminance pixel 10 and the event pixel 20, while the wiring lengths of the pixel drive lines LD1 and LD2 can be shortened to drive the luminance pixel 10 and the event pixel 20. This allows control over the reduction in the signal-to-noise ratio (SN ratio) due to propagation losses, etc. Furthermore, by arranging the backup power pad P3b near the SARADC 155, the drop in the reference voltage can be controlled, thereby generating a more accurate digital value for the luminance signal. Additionally, by arranging the backup power pad P2a near the logic circuit 152, the power supply to the logic circuit 152 can be strengthened. Note that the test pad P2 is not limited to operational testing of the solid-state imaging device 100, and can be used as a backup or auxiliary pad.

[0178] Furthermore, in the first layout example, since a layout in which the center O2 of the effective pixel area 141 is offset relative to the chip center O1 only in the horizontal direction (X direction (horizontal direction in the figure)) can be adopted, it also has the following advantages: with the imaging lens 1040 arranged to face the light receiving surface of the solid-state imaging device 100 (see Figure 1 Alignment is easy.

[0179] 1.5.2 Example of the second layout

[0180] Figure 12 This is a plan view illustrating an example of the chip layout of the second layout example according to this embodiment, and a diagram illustrating an example of the layout of the circuit chip 150B. Note that since the layout example of the pixel chip 140 according to the second layout example can be easily conceived from the layout example of the circuit chip 150B (described later) and the first layout example described above, its description will be omitted here.

[0181] (Circuit chip)

[0182] like Figure 12As shown, the circuit chip 150B according to the second layout example has a configuration in which the test pad P2 is omitted, the backup power pad P3 is placed together at the chip end L3 opposite to the chip end L1 where the main pad P1 is arranged, and the EVS_AFE 151, logic circuit 152, vertical drive circuit 153, SARADC 155, connectors 154 and 156, interface 157 and peripheral circuit 158 ​​are arranged in accordance with the second layout example. Figure 10 The circuit chip 150A of the first layout example shown is further optimized in a similar configuration.

[0183] By adopting this layout, the wiring lengths of the vertical signal lines VSL1 and VSL2 can be shortened to transmit the luminance signal and event data read from the luminance pixel 10 and the event pixel 20, while the wiring lengths of the pixel drive lines LD1 and LD2 can be shortened to drive the luminance pixel 10 and the event pixel 20. This allows control over the reduction in the signal-to-noise ratio (SN ratio) due to propagation losses, etc. Furthermore, by arranging the backup power pad P3b near the SARADC 155, the drop in the reference voltage can be controlled, thereby generating a more accurate digital value for the luminance signal. Additionally, by arranging the backup power pad P2a near the logic circuit 152, the power supply to the logic circuit 152 can be strengthened. Note that the test pad P2 is not limited to operational testing of the solid-state imaging device 100, and can be used as a backup or auxiliary pad.

[0184] 1.5.3 Example of the third layout

[0185] Figure 13 This is a plan view illustrating an example of the chip layout according to the third layout example of this embodiment, and a diagram illustrating an example of the layout of the circuit chip 150C. Note that since the layout example of the pixel chip 140 according to the third layout example can be easily conceived from the layout example of the circuit chip 150C (described later) and the first layout example described above, its description will be omitted here.

[0186] (Circuit chip)

[0187] like Figure 13 As shown, in the circuit chip 150C according to the third layout example, the following configuration is included: the interface section 157 is divided into an interface section 157a for outputting image frame data and an interface section 157b for outputting event frame data, and the interface section 157a and the main pad P1c (a part of the main pad P1) connected thereto are configured to interact with the circuit chip 150C according to the third layout example. Figure 12 The circuit chip 150B in the second layout example shown is arranged in a similar configuration to the chip end L1 where the main pad P1 is arranged (chip end L2 in this example). However, in the third layout example, a portion of the backup power pad P2b may be arranged at chip end L2.

[0188] According to this layout, although the restriction of clustering the main pad P1 at one chip end L1 is lifted, the degree of freedom in the arrangement of each part can be increased. Therefore, for example, while controlling the increase in chip size, it is possible to achieve a layout in which the center O2 of the effective pixel area 141 is offset relative to the chip center O1 only in the horizontal direction.

[0189] 1.5.4 Example of the fourth layout

[0190] Figure 14 This is a plan view illustrating an example of the chip layout according to the fourth layout example of this embodiment, and a diagram illustrating an example of the layout of the circuit chip 150D. It should be noted that since the layout example of the pixel chip 140 according to the fourth layout example can be easily conceived from the layout example of the circuit chip 150D (described later) and the first layout example described above, its description will be omitted here.

[0191] (Circuit chip)

[0192] like Figure 14 As shown, in the circuit chip 150D according to the fourth layout example, the following configuration is included: the interface section 157 is arranged to face a chip end (in this example, chip end L2) that is different from the chip end L1 on which the main pad P1 is arranged, and the output pad P2c of the main pad P1 is arranged to... Figure 10 The circuit chip 150A in the first layout example shown is arranged in a similar configuration at the chip end L2 facing the interface section 157.

[0193] This layout further relaxes the restriction that the main pads P1 are clustered at one chip end L1, and increases the degree of freedom in the arrangement of each portion. Therefore, for example, while controlling the increase in chip size, it is possible to achieve a layout in which the center O2 of the effective pixel area 141 is offset relative to the chip center O1 only in the horizontal direction.

[0194] 1.5.5 Fifth Layout Example

[0195] Figure 15 This is a plan view illustrating an example of the chip layout according to the fifth layout example of this embodiment, and a diagram illustrating an example of the layout of the circuit chip 150E. It should be noted that since the layout example of the pixel chip 140 according to the fifth layout example can be readily conceived from the layout example of the circuit chip 150E (described later) and the first layout example described above, its description will be omitted here.

[0196] (Circuit chip)

[0197] like Figure 15As shown, in the circuit chip 150E according to the fifth layout example, the following configuration is included: test pad P2 is omitted, main pad P1 is divided into main pad P1a arranged on chip end L1 and main pad P1b arranged on a chip end different from chip end L1 (chip end L3 in this example), and in accordance with the... Figure 14 The fourth layout example shown further optimizes the EVS_AFE 151, logic circuit 152, vertical drive circuit 153, SARADC 155, connectors 154 and 156, interface 157, and peripheral circuit 158 ​​in a similar configuration to the circuit chip 150D. However, in the third layout example, the backup power pad P2b can be clustered at the chip end L2.

[0198] The main pad P1a disposed near chip end L1 may be, for example, a pad (including signal pad and power pad) connected to a portion of the EVS included in the solid-state imaging device 100, and the main pad P1b disposed near chip end L3 may be, for example, a pad (including signal pad and power pad) connected to each portion of the image sensor included in the solid-state imaging device 100.

[0199] Alternatively, the main pad P1a may be, for example, a signal pad that inputs a signal to each part of the solid-state imaging device 100 or outputs a signal from each part to it, and the main pad P1b may be, for example, a power pad that supplies power to each part of the solid-state imaging device 100.

[0200] Alternatively, for example, the main pad P1a may be a pad (including a signal pad and a power pad) connected to analog circuitry in the solid-state imaging device 100, and for example, the main pad P1b may be a pad (including a signal pad and a power pad) connected to logic circuitry in the solid-state imaging device 100.

[0201] As mentioned above, the combination of the main pads P1a and P1b can be changed in various ways.

[0202] This layout further relaxes the restriction that the main pads P1 are clustered at a single chip end L1, and increases the degree of freedom in the arrangement of each portion. Thus, for example, it is possible to achieve a layout where the center O2 of the effective pixel area 141 is closer to the chip center O1, while controlling the increase in chip size.

[0203] 1.6 Conclusion

[0204] As described above, according to this embodiment, the circuit structure and optical receiving elements can be appropriately arranged.

[0205] For example, the main pad P1 for external connection is clustered at a chip end L1, thereby simplifying connection configurations, such as connecting the external device and the flexible cable of the solid-state imaging device 100, and improving the efficiency of connection configuration design and assembly. At this time, by arranging the functional blocks of the logic circuit 152 such that the output of the logic circuit 152 is located near the interface section 157, effects such as increasing signal output speed and reducing propagation loss can be achieved.

[0206] Furthermore, by configuring the logic circuit 152 to surround EVS_AFE 151 in a region adjacent to it, and further arranging the vertical drive circuit 153 outside it, the wiring lengths of the vertical signal lines VSL1 and VSL2 that transmit the luminance signal and event data read from the luminance pixel 10 and the event pixel 20 can be shortened, while the wiring lengths of the pixel drive lines LD1 and LD2 can be shortened to drive the luminance pixel 10 and the event pixel 20. Therefore, the reduction in the SN ratio due to propagation loss, etc., can be controlled. Furthermore, by arranging the backup power pad P3b near the SARADC 155, the drop in the reference voltage can also be controlled, thereby generating a more accurate digital value of the luminance signal. Furthermore, by arranging the backup power pad P2a near the logic circuit 152, the power supply to the logic circuit 152 can be strengthened.

[0207] Furthermore, by removing the constraint that the main pads are clustered on one chip end L1, the degree of freedom in the arrangement of each portion becomes greater. Therefore, for example, it is possible to appropriately adjust the center O2 of the effective pixel area 141 and the chip center O1 while controlling the increase in chip size.

[0208] 1.7 Variation Example

[0209] In the above description, as referenced Figure 4 The solid-state imaging device 100 described herein has been illustrated as an example of a two-layer stacked structure. However, the stacked structure of the solid-state imaging device 100 is not limited to two layers and may have three or more layers.

[0210] 1.7.1 Example of a stacked structure for a solid-state imaging device

[0211] Figure 16 This is a diagram illustrating an example of a stacked structure of a solid-state imaging apparatus according to a variation of the first embodiment. For example... Figure 16 As shown, the solid-state imaging device 100A according to the modified example has a three-layer structure, wherein the pixel chip 140F, the first circuit chip 150F, and the second circuit chip 160F are stacked vertically. That is, in the solid-state imaging element 100A, the circuit chip 150 in the solid-state imaging element 100 is further divided into the first circuit chip 150F and the second circuit chip 160F.

[0212] The bonding and electrical connection between pixel chip 140F and first circuit chip 150F can be similar to the bonding and electrical connection between pixel chip 140 and circuit chip 150 described above. Similarly, for example, direct bonding, Cu-Cu bonding, bump bonding, etc., can be used for bonding between first circuit chip 150F and second circuit chip 160F, and for example, connection portions such as TCV, Cu-Cu bonding portions, bump bonding portions, etc., can be used for electrical connection.

[0213] 1.7.2 Chip Layout Example

[0214] Figures 17 to 19 This is a plan view illustrating an example of a modified chip layout according to this embodiment. Figure 17 The image depicts a layout example of the 140F pixel chip. Figure 18 The layout example of the first circuit chip 15F is depicted in the figure, and in Figure 19 The layout example of the second circuit chip 160F is depicted in the figure.

[0215] like Figures 17 to 19 As shown, in a variant example, the following configuration is included: to match Figure 10 and Figure 11 In the first layout example shown, a similar configuration is arranged on circuit chip 150. The EVS_AFE 151 and peripheral circuitry 158 are arranged on the first circuit chip 150F, and, for example, the logic circuitry 152, vertical drive circuitry 153, SARADC 155, interface section 157, and connection sections (via contact vias (TCVs)) 154 and 156 are arranged on the second circuit chip 160F. Furthermore, connection sections 159 and 169 are respectively provided on the first circuit chip 150F and the second circuit chip 160F for inputting signals processed by the EVS_AFE 151 to the logic circuitry 152 on the second circuit chip 160F.

[0216] As described above, when the solid-state imaging device 100 is formed as a stacked structure with three or more layers, portions can be distributed in each layer, thereby allowing for further reduction in chip size. Furthermore, by reducing the chip size, the center O2 of the effective pixel region 141 can be brought closer to the chip center O1.

[0217] Since other configurations, operations, and effects may be similar to those in the first embodiment described above, detailed descriptions thereof are omitted here.

[0218] 2. Second Embodiment

[0219] Next, the solid-state imaging apparatus and electronic device according to the second embodiment will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, configurations similar to those of the first embodiment or its variations are referenced, and redundant descriptions will be omitted.

[0220] In the first embodiment, a case where the solid-state imaging device 100 includes different types of sensors (such as image sensors and EVS) is described as an example. On the other hand, as an example in the second embodiment, a case where the solid-state imaging device is a single EVS will be described.

[0221] It should be noted that the illustrative configuration examples and system configuration examples of the electronic device according to this embodiment can be compared with, for example, those referred to in the first embodiment. Figure 1 and Figure 2 The illustrative configuration examples and system configuration examples described are similar. However, in this embodiment, a solid-state imaging device 200 is used instead of a solid-state imaging device 100. Furthermore, the solid-state imaging device 200 according to this embodiment may have, for example, a luminance pixel 10, a vertical driving circuit 102A, a horizontal driving circuit 102B, a luminance signal processing circuit 103A, a luminance data processing unit 108A, a pixel driving line LD1, and a vertical signal line VSL1 from a reference. Figure 3 The configuration of the solid-state imaging device 100 described is omitted, and its stacked structure example may be similar to the reference. Figure 4 The stacked structure described. However, in this embodiment, pixel chip 140 is replaced by pixel chip 240, and circuit chip 150 is replaced by circuit chip 250. Furthermore, the unit pixel 110 according to this embodiment can be similar to, for example, from a reference... Figure 5 The circuit configuration example for unit pixel 110 described omits the configuration of luminance pixel 10 and vertical signal line VSL1.

[0222] 2.1 Chip Layout Example

[0223] Next, the layout of each of the pixel chip 240 and circuit chip 250 according to this embodiment will be described by way of some examples.

[0224] 2.1.1 Example of the first layout

[0225] Figure 20 This is a plan view illustrating an example of a chip layout according to the first layout example of this embodiment, and a diagram illustrating an example of a layout of circuit chip 250A. It should be noted that since the layout example of pixel chip 240 according to the first layout example can be readily conceived from the layout example of circuit chip 250A (described later) and the first layout example according to the first embodiment described above, its description will be omitted here.

[0226] like Figure 20 As shown, for example, the circuit chip 250A according to the first layout example has the following configuration, wherein the vertical drive circuit 153, its connection portion 154, SARADC 155, its connection portion 156, test pad P2, and backup power pads P3b and P4 are omitted from the configuration similar to that of the circuit chip 150A according to the first layout example of the first embodiment. Furthermore, in the first layout example, EVS_AFE 151 is located near a corner of the circuit chip 250A (in this example, the corner where chip ends L3 and L4 intersect).

[0227] By adopting this layout, the wiring length of the vertical signal line VSL2, which transmits event data read from event pixel 20, can be shortened, while the wiring length of the pixel drive line LD2, used to drive event pixel 20, can be shortened, thereby controlling the decrease in the SN ratio due to propagation loss, etc. Furthermore, by arranging a backup power pad P2a near the logic circuit 152, the power supply to the logic circuit 152 can be enhanced. Note that although omitted in this example, the test pad P2 can, for example, be arranged at the chip end L2.

[0228] 2.1.2 Example of the second layout

[0229] Figure 21 This is a plan view illustrating an example of the chip layout according to the second layout example of this embodiment, and a diagram illustrating an example of the layout of the circuit chip 250B. It should be noted that since the layout example of the pixel chip 240 according to the second layout example can be readily conceived from the layout example of the circuit chip 250B (described later) and the first layout example according to the first embodiment described above, its description will be omitted here.

[0230] like Figure 21 As shown, for example, circuit chip 250B according to the second layout example has a configuration in which main pads P1a and P1b are arranged at two opposite chip ends (chip ends L2 and L4 in this example), similar to the configuration of circuit chip 250A according to the first layout example. Note that main pads P1a and P1b may include backup power pads, test pads, etc.

[0231] As described above, by separately arranging main pads P1a and P1b at two opposite chip ends L2 and L4 (chip ends L1 and L3 can also be used), the pixel array section 101 and EVS_AFE 151 can be arranged close to the center of each chip. This allows for a layout where the center O2 of the effective pixel area 141 is closer to the chip center O1, and a layout where the center O2 of the effective pixel area 141 is offset relative to the chip center O1 in only one direction (vertical in this example).

[0232] 2.2 Conclusion

[0233] As described above, according to this embodiment, the circuit structure and optical receiving elements can be appropriately arranged.

[0234] For example, the main pad P1 for external connection is clustered at a chip end L1, thereby simplifying the connection configuration between the external device and the solid-state imaging device 200, such as a flexible cable, and improving the efficiency of connection configuration design and assembly. At this time, by arranging the functional blocks of the logic circuit 152 such that the output of the logic circuit 152 is located near the interface section 157, effects such as increasing signal output speed and reducing propagation loss can be achieved.

[0235] Furthermore, by configuring the logic circuit 152 to surround EVS_AFE 151 in a region adjacent to it, the wiring length of the vertical signal line VSL2, which transmits event data read from the event pixel 20, can be shortened, as can the wiring length of the pixel driving line LD2, used to drive the event pixel 20, also be shortened. Therefore, the reduction in the SN ratio due to propagation loss, etc., can be controlled. Furthermore, by arranging a backup power supply pad P2a near the logic circuit 152, the power supply to the logic circuit 152 can be enhanced.

[0236] Furthermore, by removing the constraint that the main pads are clustered on one chip end L1, the degree of freedom in the arrangement of each portion becomes greater. Thus, for example, it is possible to appropriately adjust the center O2 of the effective pixel area 141 and the chip center O1 while controlling the increase in chip size, and it is possible to provide a layout in which the center O2 of the effective pixel area 141 is offset relative to the chip center O1 in only one direction.

[0237] Since other configurations, operations, and effects may be similar to those in the first embodiment described above, detailed descriptions thereof are omitted here.

[0238] 3. Specific examples of electronic devices

[0239] Here, a smartphone will be described as a specific example of an electronic device to which the identification system disclosed herein can be applied. Figure 22 The image depicts a front exterior view of a smartphone, a specific example of an electronic device according to this disclosure.

[0240] The smartphone 300 according to this specific example includes a display unit 320 on the front side of the housing 310. Furthermore, the smartphone 300 includes a light-emitting unit 330 and a light-receiving unit 340 in the upper part of the front side of the housing 310. It should be noted that... Figure 22 The example of the arrangement of the light-emitting part 330 and the light-receiving part 340 described herein is an example, and this example is not a limitation.

[0241] In the smartphone 300, which is an example of a mobile device having the above configuration, the laser light source 1010 (VCSEL 1012) in the electronic device 1 according to the above embodiment can be used as a light-emitting unit 330, and the solid-state imaging device 100 can be used as a light-receiving unit 340. That is, the smartphone 300 according to this specific embodiment is manufactured by utilizing the electronic device 1 according to the above embodiment as a three-dimensional image acquisition system.

[0242] The electronic device 1 according to the above embodiment can increase the resolution of the distance image without increasing the number of light sources in the array of light source points. Therefore, by using the electronic device 1 according to the above embodiment as a three-dimensional image acquisition system (face authentication system), the smartphone 300 according to this particular example can have a highly accurate face recognition function (face authentication function).

[0243] 4. Examples of applications to moving bodies

[0244] The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein can be implemented as a device mounted on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0245] Figure 23 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which serves as an example of a mobile body control system to which the techniques according to embodiments of this disclosure can be applied.

[0246] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 23 In the example depicted, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 1205. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0247] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: drive force generating devices for generating drive force for the vehicle, such as internal combustion engines, drive motors, etc.; drive force transmission mechanisms for transmitting drive force to the wheels; steering mechanisms for adjusting the vehicle's steering angle; braking devices for generating braking force for the vehicle, etc.

[0248] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0249] The external information detection unit 12030 detects external information, including information from outside the vehicle, which is part of the vehicle control system 12000. For example, the external information detection unit 12030 is connected to an imaging unit 12031. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the external environment and receives these images. Based on the received images, the external information detection unit 12030 can perform processing such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0250] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0251] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0252] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained from the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0253] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0254] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the outside of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030.

[0255] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 23 In this example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0256] Figure 24 This is an illustration showing an example of the mounting position of the imaging unit 12031.

[0257] exist Figure 24 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0258] Imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose inside the vehicle and imaging unit 12105 on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0259] Incidentally, Figure 24An example of the imaging range of imaging units 12101 to 12104 is described. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by imaging units 12101 to 12104.

[0260] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0261] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. It can then extract the nearest three-dimensional object as the vehicle ahead, specifically one that exists on the driving path of the vehicle 12100 and is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to maintain in front of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, coordinated control for automated driving can be performed without relying on driver operation.

[0262] For example, the microcomputer 12051 can classify the three-dimensional object data of three-dimensional objects into categories such as two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, and utility poles based on distance information obtained from imaging units 12101 to 12104. It then extracts the classified three-dimensional object data and uses this data to automatically avoid obstacles. For instance, the microcomputer 12051 identifies obstacles around vehicle 12100 as those that the driver of vehicle 12100 can visually recognize and those that are difficult for the driver to visually recognize. Then, the microcomputer 12051 determines the collision risk, representing the risk of colliding with each obstacle. If the collision risk exceeds a set value and a collision is possible, the microcomputer 12051 outputs a warning to the driver via an audio speaker 12061 or a display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0263] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the imaging images of the imaging units 12101 to 12104 as a process of an infrared camera and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired location.

[0264] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, it can be installed on vehicle 12100 as… Figure 24 The imaging units 12101, 12102, 12103, 12104, 12105, etc., described herein. By applying the technology according to this disclosure to the imaging units 12101, 12102, 12103, 12104, 12105, etc., the accuracy of the results obtained by integrating information (such as color images and monochrome images) obtained from different sensors can be improved.

[0265] While embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the embodiments described above, and various modifications can be made within the spirit and scope of the present disclosure. Furthermore, components of different embodiments and variations can be combined arbitrarily.

[0266] Furthermore, the effects of each embodiment described in this specification are merely examples and not limitations, and may have different effects.

[0267] It should be noted that this technology may also have the following configurations. (1)

[0269] A solid-state imaging device, comprising:

[0270] Multiple unit pixels arranged in a two-dimensional grid pattern;

[0271] An arbitrator that arbitrates the readout of the plurality of unit pixels; and

[0272] A first signal processing circuit processes a first signal output from each of the unit pixels, wherein...

[0273] Each unit pixel includes:

[0274] Multiple photoelectric conversion units are arranged in a two-dimensional grid pattern, and

[0275] Multiple detection circuits detect changes in the brightness of the incident light from each photoelectric conversion unit based on the photocurrent flowing out of each photoelectric conversion unit and output a first signal.

[0276] Multiple photoelectric conversion units are arranged on the first chip.

[0277] At least a portion of each of the detection circuit, the arbitrator, and the first signal processing circuit is arranged on a second chip stacked on the first chip.

[0278] A first region in the first chip, in which the plurality of photoelectric conversion units are arranged, and a second region in the second chip, in which at least a portion of each of the detection circuits is arranged, at least partially overlap in the stacking direction of the first chip and the second chip.

[0279] The logic circuitry, including the arbitrator and the first signal processing circuit, is arranged in a third region of the second chip that is at least partially adjacent to the second region. (2)

[0281] According to the solid-state imaging device described in (1), wherein

[0282] One or more first pads connecting the logic circuit to the outside are arranged near the first chip end of the second chip. (3)

[0284] According to the solid-state imaging device described in (1), wherein

[0285] Two or more first pads connecting the logic circuit to the outside are arranged separately on the first chip end of the second chip and on the opposite side of the second chip end near the first chip end. (4)

[0287] According to the solid-state imaging device described in (1), wherein

[0288] Each unit pixel includes:

[0289] The first pixel, including the photoelectric conversion unit and the detection circuit, detects the brightness change of the incident light and outputs the first signal.

[0290] The second pixel detects the brightness of the incident light and outputs a second signal.

[0291] The second signal processing circuit processes the second signal output from the second pixel, and

[0292] It further includes a driving circuit for driving the second pixel and reading the second signal.

[0293] The second signal processing circuit is included in the logic circuit, and

[0294] In the second chip, the driving circuit is arranged on the side of the second region opposite to the third region. (5)

[0296] According to the solid-state imaging device described in (4), wherein

[0297] The second pixel includes:

[0298] The photoelectric conversion unit, and

[0299] The pixel circuit detects the brightness of the incident light to the photoelectric conversion unit based on the charge accumulated in the photoelectric conversion unit, and outputs the second signal. (6)

[0301] According to the solid-state imaging device described in (4) or (5), wherein

[0302] One or more first pads, which connect logic circuits and drive circuits to the outside, are arranged near the first chip end of the second chip. (7)

[0304] According to the solid-state imaging device described in (6), wherein

[0305] The second pad outputs a signal based on the second signal, and the second pad is arranged near a third chip terminal that is different from the first chip terminal. (8)

[0307] According to the solid-state imaging device described in (7), wherein

[0308] A third pad that outputs a signal based on the first signal in the first pad is arranged near the third chip end. (9)

[0310] According to the solid-state imaging device described in (4) or (5), wherein

[0311] One or more first pads, which connect logic circuits and drive circuits to the outside, are separately arranged near the first chip end of the second chip and near the second chip end on the opposite side of the first chip end. (10)

[0313] The solid-state imaging apparatus according to any one of (4) to (9) further comprises:

[0314] The conversion circuit converts the second signal output from the second pixel into a digital signal, wherein...

[0315] The conversion circuit is arranged in a fourth region located between the fifth chip end and the second region, the fifth chip end being located on the opposite side of the second region across the third region in the second chip and substantially perpendicular to the fourth chip end closest to the driving circuit. (11)

[0317] The solid-state imaging apparatus according to any one of (6) to (9) further comprises:

[0318] The conversion circuit converts the second signal output from the second pixel into a digital signal; and

[0319] A fourth pad is disposed on the second chip, and the fourth pad provides auxiliary power to the conversion circuit;

[0320] The conversion circuit is arranged in a fourth region located between the fifth chip terminal and the second region, the fifth chip terminal spanning the third region in the second chip, situated on the opposite side of the second region and substantially perpendicular to the fourth chip terminal closest to the driving circuit.

[0321] The first pad includes a fifth pad that supplies power to the conversion circuit, and

[0322] The fourth pad is positioned near the sixth chip end, which is located near the conversion circuit in the second chip. (12)

[0324] The solid-state imaging apparatus according to any one of (6) to (9) further comprises:

[0325] Multiple test pads are used for operational testing, and the test pads are arranged near a seventh chip end that is different from the first chip end. (13)

[0327] According to the solid-state imaging device described in (2) or (6), wherein

[0328] The center of the second chip is offset from the center of the second region in a direction parallel or perpendicular to the end of the first chip. (14)

[0330] A solid-state imaging device, comprising:

[0331] Multiple unit pixels, each unit pixel including: a first pixel, which detects the brightness change of the incident light and outputs a first signal; and a second pixel, which detects the brightness of the incident light and outputs a second signal, the multiple unit pixels being arranged in a two-dimensional grid pattern;

[0332] Arbitrator, arbitrating the readout of the first pixel;

[0333] A first signal processing circuit processes the first signal output from each first pixel;

[0334] The driving circuit drives the second pixel and reads the second signal; and

[0335] The second signal processing circuit processes the second signal output from the second pixel, wherein...

[0336] Each unit pixel includes:

[0337] Multiple photoelectric conversion units are arranged in a two-dimensional grid pattern, and

[0338] Multiple detection circuits detect changes in the brightness of incident light directed to each photoelectric conversion unit based on the photocurrent flowing from each unit, and output the first signal.

[0339] Multiple photoelectric conversion units are arranged on the first chip.

[0340] At least a portion of each of the detection circuits is arranged on a second chip stacked on the first chip.

[0341] The arbitrator, the first signal processing circuit, the driving circuit, and the second signal processing circuit are disposed on a third chip stacked on the opposite side of the first chip relative to the second chip, and

[0342] The first region, in which the plurality of photoelectric conversion units are arranged in the first chip, and the second region, in which at least a portion of each of the detection circuits are arranged in the second chip, at least partially overlap in the stacking direction of the first chip and the second chip. (15)

[0344] An electronic device, comprising:

[0345] Solid-state imaging apparatus according to any one of (1) to (14);

[0346] The system control unit controls the solid-state imaging device; and

[0347] The processor processes the data output from the solid-state imaging device.

[0348] Reference Symbol List

[0349] 1. Electronic equipment

[0350] 10, 10-0 to 10-3 brightness pixels

[0351] 11 Transmission transistors

[0352] 12 Reset Transistors

[0353] 13 Amplifying Transistors

[0354] 14 Selecting Transistors

[0355] 20, 20-0 to 20-3 event pixels

[0356] 21 Discharge transistor

[0357] 100, 100A, 200 Solid-State Imaging Device

[0358] 101 pixel array

[0359] 102A, 153 Vertical Drive Circuit

[0360] 102B Horizontal Drive Circuit

[0361] 103A Luminance Signal Processing Circuit

[0362] 103a AD conversion circuit

[0363] 103B Event Signal Processing Circuit

[0364] 103b signal processing circuit

[0365] 104 AX Arbitrator

[0366] 104 BY Arbitrator

[0367] 105 System Control Circuit

[0368] 108A Luminance Data Processing Unit

[0369] 108B Event Data Processing Department

[0370] 110, 110-1 unit pixel

[0371] 111 pixel circuit

[0372] 140, 140A, 140F pixel chips

[0373] 141 effective pixel area

[0374] 142 light-shielding pixel area

[0375] 143, 145 Cabling Department

[0376] Connection parts 144, 146, 154, 156, 169

[0377] Circuit chips 150, 150A to 150E, 250A, 250B

[0378] 150F First Circuit Chip

[0379] 151 EVS_AFE

[0380] 152 Logic Circuits

[0381] 155 SARAD

[0382] 157 Interface Section

[0383] 158 Peripheral Circuits

[0384] 160F Second Circuit Chip

[0385] 210 Address Event Detection Circuit

[0386] 211 Logic Circuits

[0387] 212, 212A Optical Receiver Circuit

[0388] 1010 laser source

[0389] 1011 Light Source Driver Unit

[0390] 1012 VCSEL

[0391] 1021 Sensor Control Unit

[0392] 1022 Optical Receiver

[0393] 1030 Illumination Lens

[0394] 1040 Imaging Lens

[0395] 1050 System Control Department

[0396] 1100 Application Processor

[0397] FD floating diffusion region

[0398] L1 to L4 chip side

[0399] LD1 and LD2 pixel drive lines

[0400] P1, P1a, P1b and P1c main pads

[0401] P2 Test Pad

[0402] P2a, P2b, P3a, P3b, P4 Backup power pads

[0403] P2c output pad

[0404] PD photoelectric conversion unit

[0405] VSL1 and VSL2 are vertical signal lines.

Claims

1. A solid-state imaging device, comprising: Multiple unit pixels arranged in a two-dimensional grid pattern; An arbitrator that arbitrates readouts of multiple said unit pixels; as well as A first signal processing circuit processes a first signal output from each of the unit pixels, wherein... Each unit pixel includes: Multiple photoelectric conversion units are arranged in a two-dimensional grid pattern, and Multiple detection circuits detect changes in the brightness of incident light directed to each photoelectric conversion unit based on the photocurrent flowing from each of the photoelectric conversion units and output the first signal. Multiple photoelectric conversion units are arranged on the first chip. At least a portion of each of the detection circuits, the arbitrator, and the first signal processing circuit are arranged on a second chip stacked on the first chip. The first region in the first chip, in which the plurality of photoelectric conversion units are arranged, and the second region in the second chip, in which at least a portion of each of the detection circuits is arranged, at least partially overlap in the stacking direction of the first chip and the second chip. The logic circuitry, including the arbitrator and the first signal processing circuit, is arranged in a third region of the second chip that is at least partially adjacent to the second region.

2. The solid-state imaging device according to claim 1, wherein... One or more first pads are arranged close to the first chip end of the second chip, connecting the logic circuit to the outside.

3. The solid-state imaging device according to claim 1, wherein... Two or more first pads connecting the logic circuit to the outside are arranged separately near the first chip end of the second chip and near the second chip end on the opposite side from the first chip end.

4. The solid-state imaging device according to claim 1, wherein... Each unit pixel includes: The first pixel includes the photoelectric conversion unit and the detection circuit. The first pixel detects the brightness change of the incident light and outputs the first signal. The second pixel detects the brightness of the incident light and outputs a second signal. The solid-state imaging device further includes: The second signal processing circuit processes the second signal output from the second pixel, and The driving circuit drives the second pixel and reads the second signal. The second signal processing circuit is included in the logic circuit, and The driving circuit is arranged in the second chip on the opposite side of the second region, separated by the third region.

5. The solid-state imaging device according to claim 4, wherein... The second pixel includes: The photoelectric conversion unit, and The pixel circuit detects the brightness of the incident light directed to the photoelectric conversion unit based on the charge accumulated in the photoelectric conversion unit, and outputs the second signal.

6. The solid-state imaging device according to claim 4, wherein... The logic circuit and the driving circuit are connected to one or more external first pads arranged close to the first chip end of the second chip.

7. The solid-state imaging apparatus according to claim 6, wherein... The second pad, which outputs a signal based on the second signal in the first pad, is arranged close to a third chip end that is different from the first chip end.

8. The solid-state imaging apparatus according to claim 7, wherein The third pads, which output signals based on the first signal, are arranged close to the third chip end in the first pad.

9. The solid-state imaging device according to claim 4, wherein... One or more first pads, which connect the logic circuit and the driving circuit to the outside, are arranged separately near the first chip end of the second chip and near the second chip end on the opposite side of the first chip end.

10. The solid-state imaging apparatus according to claim 4, further comprising: The conversion circuit converts the second signal output from the second pixel into a digital signal, wherein... The conversion circuit is arranged in a fourth region located between the fifth chip end and the second region. The fifth chip end is on the opposite side of the second chip, separated from the third region, and is in a roughly right-angle relationship with the fourth chip end closest to the driving circuit.

11. The solid-state imaging apparatus according to claim 6, further comprising: The conversion circuit converts the second signal output from the second pixel into a digital signal. as well as A fourth pad is disposed on the second chip, and the fourth pad provides auxiliary power to the conversion circuit; in, The conversion circuit is arranged in a fourth region located between the fifth chip terminal and the second region. The fifth chip terminal is on the opposite side of the second chip, separated by the third region, and is approximately perpendicular to the fourth chip terminal closest to the driving circuit. The first pad includes a fifth pad that supplies power to the conversion circuit, and The fourth pad is positioned close to the sixth chip end, which is located near the conversion circuit in the second chip.

12. The solid-state imaging apparatus according to claim 6, further comprising: Multiple test pads are used for operational testing, and the test pads are arranged close to a seventh chip end that is different from the first chip end.

13. The solid-state imaging device according to claim 2, wherein... The center of the second chip is offset from the center of the second region in a direction parallel or perpendicular to the end of the first chip.

14. A solid-state imaging device, comprising: Multiple unit pixels, each unit pixel including: a first pixel, which detects the brightness change of the incident light and outputs a first signal; and a second pixel, which detects the brightness of the incident light and outputs a second signal, the multiple unit pixels being arranged in a two-dimensional grid pattern; Arbitrator, arbitrating the readout of the first pixel; A first signal processing circuit processes the first signal output from each of the first pixels; The driving circuit drives the second pixel and reads the second signal; and The second signal processing circuit processes the second signal output from the second pixel, wherein... Each unit pixel includes: Multiple photoelectric conversion units are arranged in a two-dimensional grid pattern, and Multiple detection circuits detect changes in the brightness of incident light directed to each photoelectric conversion unit based on the photocurrent flowing from each unit, and output the first signal. Multiple photoelectric conversion units are arranged on the first chip. At least a portion of each of the detection circuits is arranged on a second chip stacked on the first chip. The arbitrator, the first signal processing circuit, the driving circuit, and the second signal processing circuit are arranged on a third chip stacked on the opposite side of the first chip relative to the second chip, and The first region in the first chip, in which the plurality of photoelectric conversion units are arranged, and the second region in the second chip, in which at least a portion of each of the detection circuits are arranged, at least partially overlap in the stacking direction of the first chip and the second chip.

15. An electronic device comprising: The solid-state imaging device according to claim 1; The system control unit controls the solid-state imaging device; as well as The processor processes the data output from the solid-state imaging device.

Images