Semiconductor structure and method of making the same, package structure
By setting a filling layer on the capacitor layer and forming an electrostatic discharge (ESD) protection device with alternating N-type and P-type doped regions, the problem of ESD damage in the silicon interposer is solved, and the ESD protection performance of the semiconductor structure and packaging structure is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-06-14
- Publication Date
- 2026-06-23
AI Technical Summary
In the existing technology, in the semiconductor field, the problem that the existing technology cannot effectively solve is that there is a problem of electrostatic discharge damage in the semiconductor structure of silicon interposers and deep trench capacitors.
By setting a filling layer on the capacitor layer that fills the gap area surrounded by deep trench capacitors and covers the top surface of the capacitor layer, and forming an electrostatic protection device with alternating N-type doped regions and P-type doped regions in the filling layer, electrostatic discharge can be prevented from damaging the semiconductor structure.
It improves the electrostatic discharge (ESD) protection performance of semiconductor structures, prevents damage to semiconductor structures and their electrical connections from electrostatic discharge, and enhances the ESD protection performance of packaging structures.
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Figure CN116544230B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure, its fabrication method, and its packaging structure. Background Technology
[0002] With the rapid development of artificial intelligence, big data, and cloud computing, the requirements for chips are becoming increasingly stringent, demanding high processing speeds, high bandwidth, low cost, and low power consumption. 2.5D packaging can meet these requirements. 2.5D packaging integrates the chip, silicon interposer, packaging substrate, and circuit board into a single package structure to achieve better performance and lower power consumption. The silicon interposer acts as an interconnect between the chip, packaging substrate, and circuit board. Deep trench capacitors are incorporated within the silicon interposer, which help stabilize the signal-to-noise ratio. However, static electricity exists within the semiconductor structure, including the silicon interposer and deep trench capacitors. When this static electricity is released, it can easily damage the semiconductor structure and devices electrically connected to it. Summary of the Invention
[0003] To overcome the problems existing in related technologies, this disclosure provides a semiconductor structure, its fabrication method, and its packaging structure.
[0004] According to some embodiments, the semiconductor structure provided in the first aspect of this disclosure includes:
[0005] A silicon interposer layer having multiple trenches;
[0006] A capacitor layer is disposed on the silicon interposer layer. The capacitor layer includes a plurality of deep trench capacitors, each deep trench capacitor being located in a corresponding trench, and each deep trench capacitor forming a void region.
[0007] A filling layer is disposed on the capacitor layer, the filling layer fills the gap area and covers the top surface of the capacitor layer;
[0008] Multiple conductive plugs, each of which is inserted into the filling layer;
[0009] The filling layer includes at least one N-type doped region and at least one P-type doped region, which together form an electrostatic discharge protection device, and the N-type doped region and the P-type doped region are arranged alternately.
[0010] In some embodiments of this disclosure, the electrostatic discharge protection device includes a clamping diode and / or a silicon controlled rectifier;
[0011] The clamping diode is at least one of the following: a PNPN type diode including two P-type doped regions and two N-type doped regions; an NPNP type diode including two N-type doped regions and two P-type doped regions; a PNP type diode including two P-type doped regions and one N-type doped region; an NPN type diode including two N-type doped regions and one P-type doped region; an NP type diode including one P-type doped region and one N-type doped region; or a PN type diode including one N-type doped region and one P-type doped region.
[0012] The thyristor rectifier is a PNPN type diode comprising two N-type doped regions and two P-type doped regions.
[0013] In some embodiments of this disclosure, the thickness of the filling layer covering the top surface of the capacitor layer along the thickness direction of the silicon interposer is greater than or equal to 240 nm; and / or,
[0014] The distance between adjacent deep trench capacitors is 1.5–3.5 μm; and / or,
[0015] Along the thickness direction of the silicon interposer, the height of the deep trench capacitor is 20–40 μm; and / or,
[0016] The top diameter of the deep trench capacitor is greater than or equal to 2 μm; and / or,
[0017] The breakdown voltage of the clamping diode, which includes one P-type doped region and one N-type doped region, is 3-4V.
[0018] In some embodiments of this disclosure, there are multiple clamping diodes connected in series, and the multiple clamping diodes connected in series are electrically connected to the multiple conductive plugs.
[0019] In some embodiments of this disclosure, one of the adjacent conductive plugs is electrically connected to a power supply terminal, and the other conductive plug is electrically connected to a ground terminal.
[0020] In some embodiments of this disclosure, the deep trench capacitor includes multiple dielectric layers stacked sequentially on the inner surface of the trench and electrode layers located between adjacent dielectric layers.
[0021] In some embodiments of this disclosure, the doping concentration of the N-type doped region is 1*e 18 / cm 3 -1*e 21 / cm 3 ; and / or,
[0022] The doping concentration of the P-type doped region is 1*e 18 / cm 3 -1*e 21 / cm 3 .
[0023] According to some embodiments, a packaging structure provided in the second aspect of this disclosure includes a circuit board, a packaging substrate disposed on the circuit board, a semiconductor structure as described in the first aspect disposed on the packaging substrate, and a chip layer disposed on the semiconductor structure, wherein the chip layer, the semiconductor structure, the packaging substrate and the circuit board are electrically interconnected.
[0024] According to some embodiments, a method for fabricating a semiconductor structure provided in the third aspect of this disclosure includes:
[0025] A silicon interposer is provided, wherein a plurality of trenches are formed in the silicon interposer;
[0026] A capacitor layer is formed on the silicon interposer, the capacitor layer including a plurality of deep trench capacitors, each deep trench capacitor being located in a corresponding trench, and each deep trench capacitor surrounding a void region.
[0027] A filling layer is formed on the capacitor layer, the filling layer fills the void region and covers the top surface of the capacitor layer; the filling layer includes at least one N-type doped region and at least one P-type doped region, the at least one N-type doped region and the at least one P-type doped region form an electrostatic discharge protection device, and the N-type doped region and the P-type doped region are arranged alternately.
[0028] Multiple conductive plugs are formed, and each conductive plug is inserted into the filling layer.
[0029] In some embodiments of this disclosure, the step of forming a filling layer on the capacitor layer includes:
[0030] An N-type polysilicon layer or a P-type polysilicon layer is formed on the capacitor layer, wherein the N-type polysilicon layer or the P-type polysilicon layer fills the void region and covers the top surface of the capacitor layer.
[0031] A photomask is formed on the N-type polysilicon layer or the P-type polysilicon layer;
[0032] Using the mask as a mask, the N-type polysilicon layer or the P-type polysilicon layer is doped with P-type or N-type doping to form at least one P-type doped region and at least one N-type doped region in the filling layer, with the N-type doped region and the P-type doped region arranged alternately.
[0033] The embodiments disclosed herein have at least the following beneficial effects: by providing a filling layer on the capacitor layer that fills the gap region surrounded by each deep trench capacitor and covers the top surface of the capacitor layer, and forming an electrostatic discharge protection device including at least one N-type doped region and at least one P-type doped region in the filling layer, electrostatic discharge damages the semiconductor structure and the device electrically connected to the semiconductor structure is prevented, thereby improving the electrostatic discharge protection performance of the semiconductor structure and the subsequently formed packaging structure.
[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0036] Figure 1 This is a partial schematic diagram of a semiconductor structure shown in an exemplary embodiment of the present disclosure.
[0037] Figure 2 This is a partial schematic diagram of a semiconductor structure shown for another exemplary embodiment of the present disclosure.
[0038] Figure 3 This is a partial schematic diagram of a silicon interposer shown in an exemplary embodiment of the present disclosure.
[0039] Figure 4 This is a partial schematic diagram of a silicon interposer and a capacitor layer shown in an exemplary embodiment of the present disclosure.
[0040] Figure 5 This is a partial schematic diagram illustrating a silicon interposer, capacitor layer, and filler layer as an exemplary embodiment of the present disclosure.
[0041] Figure 6 This is a schematic diagram illustrating the connection of a clamping diode to a power supply terminal and a ground terminal, as shown in an exemplary embodiment of this disclosure.
[0042] Figure 7 An exemplary embodiment of this disclosure is shown Figure 1 Equivalent circuit diagram of electrostatic discharge protection devices.
[0043] Figure 8 This is a partial schematic diagram of a semiconductor structure, including deep trench capacitors, in related technologies.
[0044] Figure 9 This is a schematic diagram illustrating an exemplary embodiment of the present disclosure of the packaging structure.
[0045] Figure 10 This is a flowchart illustrating a method for a semiconductor structure as an exemplary embodiment of the present disclosure.
[0046] Figure 11 This is a schematic diagram illustrating an N-type polysilicon layer formed on a capacitor layer, as shown in an exemplary embodiment of the present disclosure.
[0047] Figure 12 This is a schematic diagram illustrating the formation of a mask on an N-type polysilicon layer, as shown in an exemplary embodiment of the present disclosure.
[0048] Figure 13 This is a schematic diagram illustrating, as an exemplary embodiment of the present disclosure, the p-type doping of an N-type polysilicon layer using a mask as a mask.
[0049] Explanation of reference numerals in the attached figures:
[0050] 10-Silicon interposer; 11-Trench;
[0051] 20 - Capacitor layer; 21 - Deep trench capacitor;
[0052] 22 - Void region; 23 - Electrode layer;
[0053] 24 - Dielectric layer; 30 - Filler layer;
[0054] 31-N-type doped region; 32-P-type doped region;
[0055] 40 - Electrostatic discharge protection device; 50 - Clamping diode;
[0056] 60 - Conductive plug; 70 - Circuit board;
[0057] 80 - Packaging substrate; 90 - Semiconductor structure;
[0058] 100 - Chip layer; 101 - Chip;
[0059] 110 - N-type polysilicon layer; 120 - photomask;
[0060] VDD - Power supply terminal; VSS - Ground terminal. Detailed Implementation
[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0062] In related technologies, 2.5D packaging technology, used to meet the requirements of high computing speed, high bandwidth, low cost, and low power consumption, integrates a chip, silicon interposer, packaging substrate, and circuit board into a single package structure. The silicon interposer acts as an interconnect between the chip, substrate, and circuit board. In package structure design, placing deep trench capacitors within the silicon interposer is a crucial factor in improving package structure performance and stabilizing the signal-to-noise ratio. However, static electricity exists in semiconductor structures including silicon interposers and deep trench capacitors. Electrostatic discharge (ESD) generated under three modes—Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM)—can damage the semiconductor structure and devices electrically connected to it.
[0063] Based on this, an exemplary embodiment of the present disclosure provides a semiconductor structure that, by providing a filling layer on a capacitor layer that fills the gap region surrounded by each deep trench capacitor and covers the top surface of the capacitor layer, and forming an electrostatic discharge protection device including at least one N-type doped region and at least one P-type doped region in the filling layer, prevents electrostatic discharge from damaging the semiconductor structure and the device electrically connected to the semiconductor structure, thereby improving the electrostatic discharge protection performance of the semiconductor structure and the subsequently formed packaging structure.
[0064] In one exemplary embodiment, such as Figure 1 and Figure 2 As shown, the semiconductor structure 90 provided in this embodiment includes a silicon interposer 10, a capacitor layer 20, a filler layer 30, and a plurality of conductive plugs 60. The silicon interposer 10 has a plurality of trenches 11. The capacitor layer 20 is disposed on the silicon interposer 10, and the capacitor layer 20 includes a plurality of deep trench capacitors 21. Each deep trench capacitor 21 is located in a corresponding trench 11, and each deep trench capacitor 21 surrounds a void region 22. The filler layer 30 is disposed on the capacitor layer 20, filling the void region 22 and covering the top surface of the capacitor layer 20. Each conductive plug 60 is inserted into the filler layer 30. The filler layer 30 includes at least one N-type doped region 31 and at least one P-type doped region 32. The at least one N-type doped region 31 and at least one P-type doped region 32 form an electrostatic discharge (ESD) protection device 40, and the N-type doped regions 31 and P-type doped regions 32 are arranged alternately.
[0065] Semiconductor structure 90 includes a silicon interposer 10, which is typically disposed between the package substrate 80 and the chip 101 in 2.5D packaging technology to achieve high-density interconnection and communication between chips, between chips and the package substrate and circuit board. For example... Figure 3 As shown, the silicon interposer 10 is provided with a plurality of trenches 11, the opening of each trench 11 being located on the top surface of the silicon interposer 10, and the plurality of trenches 11 being used to accommodate a plurality of deep trench capacitors 21 subsequently formed.
[0066] like Figure 4 As shown, a capacitor layer 20 is disposed on the silicon interposer 10. A portion of the capacitor layer 20 is located on the top surface of the silicon interposer 10, and another portion of the capacitor layer 20 is located in each trench 11. The capacitor layer 20 located in the trench 11 forms a deep trench capacitor 21. The deep trench capacitor 21 has a void region 22 in the middle.
[0067] like Figure 5 As shown, a filling layer 30 is disposed on the capacitor layer 20. The filling layer 30 is made of a semiconductor material, such as polysilicon. A portion of the filling layer 30 fills the gap regions 22 of each deep trench capacitor 21, and another portion of the filling layer 30 covers the top surface of the capacitor layer 20. That is, the filling layer 30 includes the portion that fills the gap regions 22 of the deep trench capacitor 21 and the portion located on the top surface of the capacitor layer 20. By using the filling layer 30 to fill each gap region 22, the strength of the semiconductor structure 90 can be increased, and it is easier to form other structures or devices in the semiconductor structure 90 subsequently.
[0068] The filling layer 30 includes at least one N-type doped region 31 and at least one P-type doped region 32. The N-type doped region 31 can be formed by N-type doping of the polycrystalline silicon filling layer 30, and the P-type doped region 32 can be formed by P-type doping of the polycrystalline silicon filling layer 30. As an example, when forming the N-type doped region, pentavalent impurities can be doped into the filling layer 30. The pentavalent impurities can be elements such as phosphorus, arsenic, and antimony. When forming the P-type doped region, trivalent impurities can be doped into the filling layer 30. The trivalent impurities can be elements such as boron, aluminum, gallium, or indium.
[0069] like Figure 1 and Figure 2 As shown, a plurality of conductive plugs 60 are inserted in the filling layer 30. The conductive plugs 60 can be, for example, tungsten (W) plugs. The conductive plugs 60 can be inserted in the portion of the filling layer 30 that fills the gap region 22, and can also be inserted in the portion of the filling layer 30 that covers the top surface of the capacitor layer 20.
[0070] When there are multiple N-type doped regions 31 and P-type doped regions 32 in the filling layer 30, the N-type doped regions 31 and P-type doped regions 32 are arranged alternately, for example... Figure 1 and Figure 2 These represent two different arrangements of alternating N-type doped regions 31 and P-type doped regions 32 between two adjacent deep trench capacitors 21. Figure 1 The arrangement of N-type doped regions 31 and P-type doped regions 32 is also shown. These N-type doped regions 31 and P-type doped regions 32 can form an electrostatic discharge (ESD) protection device 40. Using this ESD protection device 40, the discharge current of electrostatic discharge can be discharged to the ground terminal, preventing ESD from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90.
[0071] It should be noted that the specific locations of the N-type doped region 31 and the P-type doped region 32 in the filled layer 30 can vary. For example, the N-type doped region 31 and the P-type doped region 32 may be located between adjacent conductive plugs 60 and arranged alternately between adjacent conductive plugs 60. As an example, ... Figure 2 As shown, three N-type doped regions 31 and two P-type doped regions 32 are disposed between the two conductive plugs 60, and the three N-type doped regions 31 and two P-type doped regions 32 are arranged alternately between the two conductive plugs 60.
[0072] In this embodiment, by providing a filling layer 30 on the capacitor layer 20, the filling layer 30 can fill the gap region 22 in the middle of each deep trench capacitor 21. The filling layer 30 contains alternately arranged N-type doped regions 31 and P-type doped regions 32, which can constitute an electrostatic discharge (ESD) protection device 40. Using the ESD protection device 40, damage to the semiconductor structure 90 and devices electrically connected to the semiconductor structure 90 can be prevented from being caused by electrostatic discharge, thus improving the ESD protection performance of the semiconductor structure 90 and the subsequently formed packaging structure. Furthermore, by forming the ESD protection device 40 in the filling layer 30, the ESD protection device 40 does not require additional space, thereby preventing the semiconductor structure 90 from increasing in size due to the inclusion of the ESD protection device 40.
[0073] In some embodiments, the electrostatic discharge protection device 40 includes a clamping diode 50 and / or a silicon controlled rectifier; the clamping diode 50 is at least one of the following: a PNPN diode including two P-type doped regions 32 and two N-type doped regions 31, an NPNP diode including two N-type doped regions 31 and two P-type doped regions 32, a PNP diode including two P-type doped regions 32 and one N-type doped region 31, an NPN diode including two N-type doped regions 31 and one P-type doped region 32, an NP diode including one P-type doped region 32 and one N-type doped region 31, or a PN diode including one N-type doped region 31 and one P-type doped region 32; the silicon controlled rectifier is a PNPN diode including two N-type doped regions 31 and two P-type doped regions 32.
[0074] The electrostatic discharge (ESD) protection device 40 includes a clamp diode 50, which is a semiconductor device made of a PN junction. The forward characteristic of the clamp diode 50 is the same as that of a regular diode, meaning it conducts current when the voltage is greater than the cutoff voltage. The reverse characteristic of the clamp diode 50 is that when the voltage is below the breakdown voltage, the resistance is extremely high and the leakage current is extremely low; when the voltage reaches the breakdown voltage, the reverse resistance drops sharply to a very small value, and current flows.
[0075] As an example, such as Figure 6 As shown, the negative terminal of clamping diode 50 is connected to the power supply terminal VDD, and the positive terminal of clamping diode 50 is connected to the ground terminal VSS. At this time, clamping diode 50 is in a reverse bias state. When no electrostatic discharge occurs, i.e., the power supply terminal voltage is small, clamping diode 50 does not conduct. When electrostatic discharge occurs and the power supply terminal voltage exceeds the breakdown voltage of clamping diode 50, clamping diode 50 conducts and releases the electrostatic current to the ground terminal. In this example, clamping diode 50 acts as an electrostatic discharge protection device 40 to prevent electrostatic discharge from damaging semiconductor structure 90 and devices electrically connected to semiconductor structure 90.
[0076] The clamping diode 50 can be at least one of the following: a PNPN diode including two P-type doped regions 32 and two N-type doped regions 31; an NPNP diode including two N-type doped regions 31 and two P-type doped regions 32; a PNP diode including two P-type doped regions 32 and one N-type doped region 31; an NPN diode including two N-type doped regions 31 and one P-type doped region 32; an NP diode including one P-type doped region 32 and one N-type doped region 31; or a PN diode including one N-type doped region 31 and one P-type doped region 32. For example, when the clamping diode 50 is an NP diode including one P-type doped region 32 and one N-type doped region 31, or a PN diode including one N-type doped region 31 and one P-type doped region 32, the clamping diode 50 is a Zener diode.
[0077] A PNPN diode can be considered as two PN diodes connected in series, and an NPNP diode can be considered as two NP diodes connected in series. A PNP or NPN diode can be considered as having one P-type doped region 32 or N-type doped region 31 inactive, providing the same electrostatic discharge protection as an NP or PN diode. PNPN and NPNP diodes, and PN and NP diodes, are essentially the same, differing only in the spacing arrangement of the P-type doped region 32 and N-type doped region 31 in the filling layer 30.
[0078] The electrostatic discharge protection device 40 also includes a silicon controlled rectifier (SCR). The SCR is a PNPN diode consisting of two N-type doped regions 31 and two P-type doped regions 32. The structure of the SCR also includes an N-well and a P-well. When the power supply reaches the breakdown voltage, the PN junction formed by the N-well and the P-well undergoes avalanche breakdown. The electron current and hole current generated by the breakdown turn on the PNP and NPN parts, causing a strong conductivity modulation effect in both the N-well and the P-well, thereby reducing the voltage across the device.
[0079] In this embodiment, by designing different numbers of N-type doped regions 31 and P-type doped regions 32, and adopting different arrangement methods, the electrostatic discharge protection device 40 can include different numbers of PN junctions to adapt to different electrostatic discharge protection requirements. This not only prevents electrostatic discharge from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90, but also improves the applicability of the semiconductor structure 90.
[0080] In some embodiments, the thickness of the filling layer 30 is greater than or equal to 240 nm along the thickness direction of the silicon interposer 10; the distance between adjacent deep trench capacitors 21 is 1.5 to 3.5 μm; the height of the deep trench capacitor 21 is 20 to 40 μm along the thickness direction of the silicon interposer 10; the top diameter of the deep trench capacitor 21 is greater than or equal to 2 μm; and the breakdown voltage of the PNP diode, NPN diode, NP diode, and PN diode is 3-4 V.
[0081] As an example, the thickness of the filling layer 30 along the thickness direction of the silicon interposer 10 is 240 nm, the height of the deep trench capacitor 21 is 30 μm, the distance between adjacent deep trench capacitors 21 is set to 2.5 μm, and the top diameter of each deep trench capacitor 21 is 2 μm.
[0082] In this embodiment, setting the thickness of the filling layer 30 covering the top surface of the capacitor layer 20 to be greater than or equal to 240 nm ensures that the filling layer 30 fully fills the void region 22 in the middle of the deep trench capacitor 21, preventing air gaps in the deep trench capacitor 21 from affecting its performance. Setting the top diameter of each deep trench capacitor 21 to be greater than or equal to 2 μm increases the top diameter compared to conventional deep trench capacitors. Furthermore, setting the height of the deep trench capacitor 21 to 20–40 μm not only increases the capacitance of the deep trench capacitor but also improves the electrostatic discharge (ESD) protection effect of the ESD protection device 40 formed in the filling layer 30.
[0083] In some embodiments, there are multiple clamping diodes 50, which are connected in series and electrically connected to multiple conductive plugs 60.
[0084] The filling layer 30 includes multiple N-type doped regions 31 and multiple P-type doped regions 32 arranged alternately. These N-type doped regions 31 and P-type doped regions 32 can form multiple clamping diodes 50 connected in series. As an example, such as Figure 1 As shown, three N-type doped regions 31 and two P-type doped regions 32 are formed in the filling layer 30 of the local semiconductor structure 90. The three N-type doped regions 31 and two P-type doped regions 32 can form two clamping diodes 50 connected in series. The two clamping diodes 50 are electrically connected to two conductive plugs 60, which can be regarded as an NP-type clamping diode 50 and an NPN-type clamping diode 50 connected in series. Figure 2 As shown, four N-type doped regions 31 and three N-type doped regions 32 are formed in the filling layer 30, which can be regarded as two NP-type clamping diodes 50 connected in series with one NPN-type clamping diode 50.
[0085] When multiple clamping diodes 50 are connected in series, the total breakdown voltage of the electrostatic discharge (ESD) protection device 40 is the sum of the breakdown voltages of each clamping diode 50. For example, when the filler layer 30 is formed with... Figure 1 The three N-type doped regions 31 and three P-type doped regions 32 arranged at intervals shown can be considered equivalent to the filling layer 30 as follows: Figure 7 The three clamping diodes 50 connected in series shown have a breakdown voltage of 3-4V for each of them. Therefore, the breakdown voltage of the electrostatic discharge protection device 40 formed by the three clamping diodes 50 is 9-12V.
[0086] In this embodiment, multiple clamping diodes 50 are connected in series and electrically connected to multiple conductive plugs 60, resulting in an electrostatic discharge (ESD) protection device 40 formed by the series-connected clamping diodes 50 having a higher breakdown voltage. The total breakdown voltage of the ESD protection device 40 can be adjusted according to the number of series-connected clamping diodes 50, enabling the ESD protection device 40 to meet different ESD protection requirements and improving the applicability of the semiconductor structure 90.
[0087] In some embodiments, one of the adjacent conductive plugs 60 is electrically connected to the power supply terminal, and the other conductive plug 60 is electrically connected to the ground terminal.
[0088] It should be noted that, as Figure 8 In the related technology shown, the semiconductor structure of the deep trench capacitor 21 includes a conductive plug 60 electrically connected to the deep trench capacitor 21 for supplying power to the deep trench capacitor 21. In this embodiment, the conductive plug 60 is inserted into the filling layer 30. One of the adjacent conductive plugs 60 is electrically connected to the power supply terminal VDD, and the other conductive plug 60 is electrically connected to the ground terminal VSS. In other words, the N-type doped region 31 and the P-type doped region 32 form a clamping diode 50. The negative terminal of the clamping diode 50 is connected to the power supply terminal VDD, and the positive terminal of the clamping diode 50 is connected to the ground terminal VSS. That is, the clamping diode 50 is in a reverse bias state. When the electrostatic discharge voltage is less than the breakdown voltage, the clamping diode 50 is cut off. When the electrostatic discharge voltage exceeds the breakdown voltage of the clamping diode, the clamping diode 50 is turned on and releases the electrostatic current to the ground terminal.
[0089] In this embodiment, by electrically connecting one of the adjacent conductive plugs 60 to the power supply terminal and the other conductive plug 60 to the ground terminal, the negative terminal of the clamping diode 50 formed by the N-type doped region 31 and the P-type doped region 32 in the filling layer 30 is connected to the power supply terminal, and the positive terminal is connected to the ground terminal, i.e., the clamping diode 50 is in a reverse bias state. When the electrostatic discharge voltage applied to the power supply terminal exceeds the breakdown voltage of the clamping diode 50, the clamping diode 50 conducts and releases the electrostatic current to the ground terminal, thereby achieving the electrostatic protection effect of the electrostatic discharge protection device 40, preventing electrostatic discharge from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90, and improving the electrostatic protection performance of the semiconductor structure 90 and the subsequently formed packaging structure.
[0090] In some embodiments, such as Figure 4 As shown, the deep trench capacitor 21 includes multiple dielectric layers 24 stacked sequentially on the inner surface of the trench 11 and electrode layers 23 located between adjacent dielectric layers 24.
[0091] like Figure 4 As shown, the deep trench capacitor 21 includes multiple electrode layers 23. Two adjacent electrode layers 23 can be considered as one-sided capacitors. The deep trench capacitor 21 formed by multiple electrode layers 23 is a multi-sided capacitor, which can increase the capacitor surface area and improve the effective capacitance of the deep trench capacitor 21. Dielectric layers 24 are provided between adjacent electrode layers 23, between electrode layers 23 and the surface of the trench 11 of the silicon interposer 10, and on the topmost electrode layer 23 along the thickness direction of the silicon interposer 10. The dielectric layers 24 serve as isolation and energy storage medium.
[0092] The electrode layer 23 is made of materials such as titanium nitride (TiN), tantalum, tantalum nitride, or a combination thereof. The electrode layer 23 can be formed by methods such as plating, physical vapor deposition (PVD), atomic layer deposition, or chemical vapor deposition. The dielectric layer 24 is made of a high-dielectric material with a dielectric constant (K) in the range of 10-30, such as aluminum oxide, zirconium oxide, or a laminate of aluminum oxide and zirconium oxide (AZAZ).
[0093] In this embodiment, a deep trench capacitor 21 is formed in the trench 11 by sequentially stacking dielectric layer 24 and electrode layer 23. The deep trench capacitor 21 bypasses high-frequency noise in the semiconductor structure 90 and can stabilize power integrity (PI) and signal integrity (SI). In addition, by setting the number of electrode layers 23 and dielectric layers 24 to multiple, the capacitor surface area can be increased to improve the effective capacitance of the deep trench capacitor 21.
[0094] In some embodiments, the doping concentration of the N-type doped region 31 is 1*e 18 / cm 3 -1*e 21 / cm 3 ; and / or,
[0095] The doping concentration of the P-type doped region is 1*e 18 / cm 3 -1*e 21 / cm 3 .
[0096] In this embodiment, the doping concentration of the N-type doped region 31 and the P-type doped region 32 is set to 1*e 18 -1*e 21 / cm 3 This allows the clamping diode 50 formed by the N-type doped region 31 and the P-type doped region 32 to have a breakdown voltage of 3-4V. This ensures that when the power supply voltage exceeds 3-4V during electrostatic discharge, the clamping diode 50 conducts and releases the electrostatic current to the ground terminal. This achieves the electrostatic protection effect of the electrostatic protection device 40, preventing electrostatic discharge from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90, and improving the electrostatic protection performance of the semiconductor structure 90 and the subsequently formed packaging structure.
[0097] In one exemplary embodiment, such as Figure 9 As shown, the packaging structure provided in this embodiment includes a circuit board 70, a packaging substrate 80 disposed on the circuit board 70, a semiconductor structure 90 disposed on the packaging substrate 80, and a chip layer 100 disposed on the semiconductor structure 90, and the chip layer 100, the semiconductor structure 90, the packaging substrate 80 and the circuit board 70 are electrically interconnected.
[0098] like Figure 10As shown, the package structure includes a circuit board 70, which serves as the support for the package structure and can be manufactured using electronic printing technology. A package substrate 80 is disposed above the circuit board 70, providing electrical connection, protection, support, and assembly for the chip 101, thereby achieving the goals of multi-pin configuration, reduced package size, improved electrical performance, and better heat dissipation.
[0099] A semiconductor structure 90 is disposed above the packaging substrate 80. The specific structure of the semiconductor structure 90 can be found in the relevant descriptions in the above embodiments, and will not be repeated here. A chip layer 100 is disposed on the semiconductor structure 90. The chip layer 100 includes various chips 101, such as logic chips and memory chips. The silicon interposer 10 in the semiconductor structure 90 enables interconnection between the various chips 101 in the chip layer 100. Electrical interconnection between the chip layer 100, the semiconductor structure 90, the packaging substrate 80, and the circuit board 70 can be achieved through structures such as through-silicon vias (TSVs), bumps, and package balls.
[0100] In this embodiment, the packaging structure includes the semiconductor structure 90 described in the above embodiments. An electrostatic discharge protection device 40 is provided in the filling layer 30 of the semiconductor structure 90. The electrostatic discharge protection device 40 is used to prevent electrostatic discharge from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90, thereby improving the electrostatic discharge protection performance of the packaging structure.
[0101] In one exemplary embodiment, such as Figure 11 As shown, the method for fabricating the semiconductor structure 90 provided in this embodiment includes:
[0102] Step S100: Provide a silicon interposer layer, wherein a plurality of trenches are formed in the silicon interposer layer;
[0103] Step S200: A capacitor layer is formed on the silicon interposer. The capacitor layer includes a plurality of deep trench capacitors, each deep trench capacitor is located in a corresponding trench, and each deep trench capacitor surrounds a void region.
[0104] Step S300: A filling layer is formed on the capacitor layer. The filling layer fills the void area and covers the top surface of the capacitor layer. The filling layer includes at least one N-type doped region and at least one P-type doped region. The at least one N-type doped region and at least one P-type doped region form an electrostatic discharge protection device. The N-type doped region and the P-type doped region are arranged alternately.
[0105] In step S400, multiple conductive plugs are formed, and each conductive plug is inserted into the filler layer.
[0106] In step S100, for example, as follows Figure 3 As shown, the silicon interposer 10 is used to realize high-density interconnection and communication between chips, between chips and packaging substrates and circuit boards. The silicon interposer 10 is provided with a plurality of trenches 11, the opening of each trench 11 being located on the top surface of the silicon interposer 10, and the plurality of trenches 11 being used to accommodate a plurality of deep trench capacitors 21 subsequently formed.
[0107] In step S200, for example, as follows Figure 4 As shown, a capacitor layer 20 is formed on a silicon interposer 10. A portion of the capacitor layer 20 is located on the top surface of the silicon interposer 10, and another portion of the capacitor layer 20 is located in each trench 11. The capacitor layer 20 located in the trench 11 forms a deep trench capacitor 21. The deep trench capacitor 21 has a void region 22 in the middle.
[0108] In step S300, for example, as follows Figure 5 As shown, a portion of the filling layer 30 fills the void region 22 formed by the deep trench capacitors 21 in each trench 11, and another portion of the filling layer 30 covers the top surface of the capacitor layer 20.
[0109] like Figure 1 and Figure 2 As shown, the filling layer 30 includes at least one N-type doped region 31 and at least one P-type doped region 32. The N-type doped region 31 and the P-type doped region 32 can be formed by N-type doping and P-type doping of the polycrystalline material filling layer 30, respectively. When there are multiple N-type doped regions 31 and P-type doped regions 32 in the filling layer 30, the N-type doped regions 31 and P-type doped regions 32 are arranged alternately. These N-type doped regions 31 and these P-type doped regions 32 form an electrostatic discharge (ESD) protection device 40. Using the ESD protection device 40, the discharge current of electrostatic discharge can be discharged to the ground terminal, preventing ESD from damaging the semiconductor structure 90 and the devices electrically connected to the semiconductor structure 90.
[0110] In step S400, for example, as follows Figure 1 and Figure 2 As shown, a plurality of conductive plugs 60 are formed and inserted into the filling layer 30. The conductive plugs 60 can be, for example, tungsten (W) plugs. The conductive plugs 60 can be inserted into the portion of the filling layer 30 that fills the void region 22, and can also be inserted into the portion of the filling layer 30 that covers the top surface of the capacitor layer 20.
[0111] In this embodiment, by providing a filling layer 30 on the capacitor layer 20, the filling layer 30 can fill the gap region 22 in the middle of each deep trench capacitor 21. The filling layer 30 contains alternately arranged N-type doped regions 31 and P-type doped regions 32, which can constitute an electrostatic discharge (ESD) protection device 40. Using the ESD protection device 40, damage to the semiconductor structure 90 and devices electrically connected to the semiconductor structure 90 can be prevented from being caused by electrostatic discharge, thus improving the ESD protection performance of the semiconductor structure 90 and the subsequently formed packaging structure. Furthermore, by forming the ESD protection device 40 in the filling layer 30, the ESD protection device 40 does not require additional space, thereby preventing the semiconductor structure 90 from increasing in size due to the inclusion of the ESD protection device 40.
[0112] In some embodiments, the step of forming a filling layer 30 on the capacitor layer 20 includes:
[0113] Step S310: An N-type polysilicon layer or a P-type polysilicon layer is formed on the capacitor layer. The N-type polysilicon layer or the P-type polysilicon layer fills the void area and covers the top surface of the capacitor layer.
[0114] Step S320: A photomask is formed on an N-type polysilicon layer or a P-type polysilicon layer;
[0115] Step S330: Using a mask as a mask, P-type doping or N-type doping is performed on the N-type polysilicon layer or the P-type polysilicon layer to form at least one P-type doped region and at least one N-type doped region in the filling layer, with the N-type doped region and the P-type doped region arranged alternately.
[0116] In step S310, exemplarily, an N-type polysilicon layer 110 or a P-type polysilicon layer is formed on the capacitor layer 20, such as... Figure 11 As shown, taking the formation of an N-type polysilicon layer 110 on the capacitor layer 20 as an example, the N-type polysilicon layer 110 fills the void region 22 and covers the top surface of the capacitor layer 20. The N-type polysilicon layer 110 can serve as a filler layer 30.
[0117] In step S320, as Figure 12 As shown, a mask 120 is formed on the N-type polysilicon layer 110. The mask 120 has a preset pattern, that is, part of the top surface of the N-type polysilicon layer 110 is covered by the mask 120, and another part of the top surface of the N-type polysilicon layer 110 is exposed through the mask opening on the mask 120. The preset pattern of the mask 120 is determined according to the preset arrangement of the N-type doped region 31 and the P-type doped region 32 to be formed.
[0118] In step S330, exemplarily, using mask 120 as a mask, P-type doping is performed on the N-type polysilicon layer 110 or the P-type polysilicon layer, such as... Figure 13 As shown, mask 120 blocks the portion of the N-type polysilicon layer 110 covered by P-type doped ions. This portion of the N-type polysilicon layer 110 remains unchanged after the doping process, still being N-type polysilicon, forming the final N-type doped region 31. P-type doped ions are implanted into the portion of the N-type polysilicon layer 110 not covered by mask 120. This portion of the N-type polysilicon layer 110 becomes P-type polysilicon after doping, forming the final P-type doped region 32, resulting in... Figure 5 The filling layer 30 shown has N-type doped regions 31 and P-type doped regions 32 arranged alternately.
[0119] It is understandable that when a P-type polysilicon layer is formed on the capacitor layer 20, the P-type polysilicon layer fills the void region 22 and covers the top surface of the capacitor layer 20, a mask 120 is formed on the P-type polysilicon layer, and the P-type polysilicon layer is N-type doped using the mask 120 as a mask.
[0120] In this embodiment, by forming an N-type polysilicon layer 110 or a P-type polysilicon layer as a filler layer 30 on the capacitor layer 20, not only can the void region 22 surrounded by each deep trench capacitor 21 be filled, but also when forming the N-type doped region 31 and the P-type doped region 32 in the filler layer 30, only one doping is required for the filler layer 30, reducing the number of doping operations on the filler layer 30, simplifying the fabrication process of the electrostatic discharge device in the semiconductor structure, and reducing the production cost when forming the electrostatic protection device 40 in the semiconductor structure 90.
[0121] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of this disclosure. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0122] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: A silicon interposer layer having multiple trenches; A capacitor layer is disposed on the silicon interposer layer. The capacitor layer includes a plurality of deep trench capacitors, each deep trench capacitor being located in a corresponding trench, and each deep trench capacitor forming a void region. A filling layer is disposed on the capacitor layer, the filling layer fills the gap area and covers the top surface of the capacitor layer; Multiple conductive plugs, each of which is inserted into the filling layer; The filling layer includes at least one N-type doped region and at least one P-type doped region, which together form an electrostatic discharge protection device, and the N-type doped region and the P-type doped region are arranged alternately.
2. The semiconductor structure according to claim 1, characterized in that, The electrostatic discharge protection device includes a clamping diode and / or a silicon controlled rectifier; The clamping diode is at least one of the following: a PNPN type diode including two P-type doped regions and two N-type doped regions; an NPNP type diode including two N-type doped regions and two P-type doped regions; a PNP type diode including two P-type doped regions and one N-type doped region; an NPN type diode including two N-type doped regions and one P-type doped region; an NP type diode including one P-type doped region and one N-type doped region; or a PN type diode including one N-type doped region and one P-type doped region. The thyristor rectifier is a PNPN type diode comprising two N-type doped regions and two P-type doped regions.
3. The semiconductor structure according to claim 2, characterized in that, Along the thickness direction of the silicon interposer, the thickness of the filling layer covering the top surface of the capacitor layer is greater than or equal to 240 nm; and / or, The distance between adjacent deep trench capacitors is 1.5–3.5 μm; and / or, Along the thickness direction of the silicon interposer, the height of the deep trench capacitor is 20–40 μm; and / or, The top diameter of the deep trench capacitor is greater than or equal to 2 μm; and / or, The breakdown voltage of the clamping diode, which includes one P-type doped region and one N-type doped region, is 3-4V.
4. The semiconductor structure according to claim 2, characterized in that, The clamping diodes are multiple, and the multiple clamping diodes are connected in series, and the multiple clamping diodes connected in series are electrically connected to the multiple conductive plugs.
5. The semiconductor structure according to any one of claims 1-4, characterized in that, One of the adjacent conductive plugs is electrically connected to the power supply terminal, and the other conductive plug is electrically connected to the ground terminal.
6. The semiconductor structure according to any one of claims 1-4, characterized in that, The deep trench capacitor includes multiple dielectric layers stacked sequentially on the inner surface of the trench and electrode layers located between adjacent dielectric layers.
7. The semiconductor structure according to any one of claims 1-4, characterized in that, The doping concentration of the N-type doped region is 1*e 18 / cm 3 -1*e 21 / cm 3 ; and / or, The doping concentration of the P-type doped region is 1*e 18 / cm 3 -1*e 21 / cm 3 .
8. A packaging structure, characterized in that, The device includes a circuit board, a packaging substrate disposed on the circuit board, a semiconductor structure as described in any one of claims 1-7 disposed on the packaging substrate, and a chip layer disposed on the semiconductor structure, wherein the chip layer, the semiconductor structure, the packaging substrate and the circuit board are electrically interconnected.
9. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A silicon interposer is provided, wherein a plurality of trenches are formed in the silicon interposer; A capacitor layer is formed on the silicon interposer, the capacitor layer including a plurality of deep trench capacitors, each deep trench capacitor being located in a corresponding trench, and each deep trench capacitor surrounding a void region. A filling layer is formed on the capacitor layer, the filling layer fills the void region and covers the top surface of the capacitor layer; the filling layer includes at least one N-type doped region and at least one P-type doped region, the at least one N-type doped region and the at least one P-type doped region form an electrostatic discharge protection device, and the N-type doped region and the P-type doped region are arranged alternately. Multiple conductive plugs are formed, and each conductive plug is inserted into the filling layer.
10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The step of forming a filling layer on the capacitor layer includes: An N-type polysilicon layer or a P-type polysilicon layer is formed on the capacitor layer, wherein the N-type polysilicon layer or the P-type polysilicon layer fills the void region and covers the top surface of the capacitor layer. A photomask is formed on the N-type polysilicon layer or the P-type polysilicon layer; Using the mask as a mask, the N-type polysilicon layer or the P-type polysilicon layer is doped with P-type or N-type doping to form at least one P-type doped region and at least one N-type doped region in the filling layer, with the N-type doped region and the P-type doped region arranged alternately.