Electronic devices

Abstract

This disclosure provides an electronic device. The electronic device includes a substrate, a first signal line, a second signal line, a third signal line, a first level shifter, and a second level shifter. The first, second, and third signal lines are disposed on the substrate. Each of the first, second, and third signal lines has two endpoints. The second signal line is disposed between the first and third signal lines. The first level shifter is coupled to the first and third signal lines. The second level shifter is coupled to the second signal line. The first level shifter is coupled to both endpoints of the first and third signal lines. The second level shifter is coupled to both endpoints of the second signal line.

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] In existing electronic devices, such as display devices, level shifters are used to drive the gate circuit. As the resolution of display devices increases, the number of frequency signals required to drive the gate circuit also increases. As the number of frequency signals continues to increase, multiple level shifters are connected in series to sequentially output the required number of frequency signals and control costs. However, this architecture can easily cause the level shifters to accumulate a large amount of heat in a short period of time, resulting in problems that affect the stability of the electronic device. Summary of the Invention

[0003] This disclosure provides an electronic device, particularly an electronic device having a display panel, which can avoid the display panel being overloaded, affecting operational stability and causing problems that affect the stability of the electronic device. In other words, the temperature rise during continuous operation of the electronic device can be mitigated.

[0004] The electronic device disclosed herein includes a substrate, a first signal line, a second signal line, a third signal line, a first level shifter, and a second level shifter. The first, second, and third signal lines are disposed on the substrate. Each of the first, second, and third signal lines has two endpoints. The second signal line is disposed between the first and third signal lines. The first level shifter is coupled to the first and third signal lines. The second level shifter is coupled to the second signal line. The first level shifter is coupled to both endpoints of the first and third signal lines. The second level shifter is coupled to both endpoints of the second signal line.

[0005] In embodiments of this disclosure, a first level converter outputs a plurality of first frequency signals, and a second level converter outputs a plurality of second frequency signals. The first first frequency signal of the plurality of first frequency signals and the first second frequency signal of the plurality of second frequency signals partially overlap in time.

[0006] In embodiments of this disclosure, the plurality of first frequency signals do not overlap with each other in time.

[0007] In embodiments of this disclosure, the plurality of second frequency signals do not overlap with each other in time.

[0008] In embodiments of this disclosure, a first level converter outputs a plurality of first frequency signals, and a second level converter outputs a plurality of second frequency signals. The first first frequency signal of the plurality of first frequency signals and the first second frequency signal of the plurality of second frequency signals completely overlap.

[0009] In embodiments of this disclosure, a plurality of first frequency signals partially overlap each other in time.

[0010] In embodiments of this disclosure, multiple second frequency signals partially overlap with each other in time.

[0011] In embodiments of this disclosure, a first level converter outputs a plurality of first frequency signals, and a second level converter outputs a plurality of second frequency signals. The plurality of first frequency signals and the plurality of second frequency signals are input from opposite sides of the substrate.

[0012] In embodiments of this disclosure, the plurality of first frequency signals and the plurality of second frequency signals are input from the opposite sides of the substrate in the same order.

[0013] In embodiments of this disclosure, the plurality of first frequency signals and the plurality of second frequency signals are input from opposite sides of the substrate in reverse order.

[0014] To make the foregoing more understandable, several embodiments, accompanied by accompanying drawings, are described in detail below. Attached Figure Description

[0015] Figure 1 A block diagram showing an embodiment of an electronic device of the present disclosure;

[0016] Figure 2 A block diagram illustrating an electronic device according to another embodiment of the present disclosure;

[0017] Figure 3 A block diagram showing a first level converter and a second level converter according to an embodiment of the present disclosure;

[0018] Figure 4A A waveform diagram of a first frequency signal and a second frequency signal according to an embodiment of the present disclosure is shown.

[0019] Figure 4B A waveform diagram of a first frequency signal and a second frequency signal according to another embodiment of the present disclosure is shown. Detailed Implementation

[0020] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0021] In the following description and claims, the words “containing” and “including” are open-ended terms and should therefore be interpreted as “containing but not limited to…”.

[0022] It should be understood that although the terms first, second, third… can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by first, second, third… in the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0023] In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

[0024] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, sensing devices, light-emitting devices, or splicing devices. Electronic devices may include bendable or flexible electronic devices. Electronic devices may include electronic components. Electronic devices may include, for example, liquid crystal layers or light-emitting diodes (LEDs). Electronic components may include passive or active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, liquid crystal chips, controllers, etc., but are not limited to these. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), miniLEDs, microLEDs, quantum dot LEDs, fluorescent, phosphorescent, or other suitable materials, or combinations thereof, but are not limited to these. Sensors may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but are not limited thereto. Controllers may include, for example, timing controllers, but are not limited thereto. The following description uses a display device as an example of an electronic device to illustrate this disclosure, but this disclosure is not limited thereto.

[0025] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0026] Figure 1 A block diagram illustrating an embodiment of the electronic device of this disclosure is shown. Please refer to... Figure 1The electronic device 100 includes a substrate 110, multiple signal lines 112, a first level shifter 131, and a second level shifter 132. The signal lines 112 include a first signal line L1, a second signal line L2, and a third signal line L3, and are disposed on the substrate 110. The second signal line L2 is disposed between the first signal line L1 and the third signal line L3. The first level shifter 131 is coupled to the first signal line L1 and the third signal line L3. The second level shifter 132 is coupled to the second signal line L2.

[0027] Each of the first signal line L1, the second signal line L2, and the third signal line L3 has two endpoints. Specifically, the first signal line L1 has endpoints N11 and N12, the second signal line L2 has endpoints N21 and N22, and the third signal line L3 has endpoints N31 and N32. A first level shifter 131 is coupled to endpoints N11 and N12 of the first signal line L1 and endpoints N31 and N32 of the third signal line L3. A second level shifter 132 is coupled to endpoints N21 and N22 of the second signal line L2.

[0028] In this embodiment, the first level converter 131 is used to output multiple first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11, and applies these first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11 to a portion of the signal lines in signal line 112. For example, the first frequency signal CK1 is applied to the first signal line L1, and the first frequency signal CK3 is applied to the third signal line L3. The second level converter 132 is used to output multiple second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12, and applies these second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 to another portion of the signal lines in signal line 112. For example, the second frequency signal CK2 is applied to the second signal line L2. In other embodiments, the number of first frequency signals that the first level converter 131 can output may not be equal to 6, and the number of second frequency signals that the second level converter 132 can output may not be equal to 6, for example, 4 or 8 frequency signals, but is not limited thereto.

[0029] In this embodiment, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 can be input from the two opposite sides of the substrate 110 via corresponding coupled frequency signal lines. For example, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are input from the left side of the substrate 110 via frequency signal lines CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL9, CL10, CL11, CL12 arranged in a first order on the substrate 110. At the same time, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are also input to the substrate 110 from the right side of the substrate 110 through the frequency signal lines CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8, CR9, CR10, CR11, CR12 arranged in the first order on the substrate 110. In other words, in this embodiment, the frequency signal lines of the input first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the input second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are arranged in the same order on both opposite sides of the substrate 110, from left to right: the first order CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL9, CL10, CL11, CL12 and CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8, CR9, CR10, CR11, CR12.

[0030] In this embodiment, the substrate 110 is, for example, an active substrate in a display device, but is not limited thereto. The active substrate includes multiple pixel circuits. The signal line 112 is, for example, a gate line, connected to the corresponding active element in the pixel circuit, such as a transistor. The first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are, for example, gate signals used to control the conduction state of the transistors.

[0031] In this embodiment, the connecting line 113 is coupled to the frequency signal line on the substrate 110, for example, through circuit boards 120_1 and 120_2. Circuit boards 120_1 and 120_2 can be flexible circuit boards or rigid circuit boards, but are not limited thereto. Therefore, the signal line 112 can be coupled to the first level converter 131 or the second level converter 132 through the frequency signal line and the corresponding coupled connecting line 113. For example, the first signal line L1 can be coupled to the first level converter 131 through the frequency signal line CL1 and / or the frequency signal line CR1 and the corresponding coupled connecting line 113; the second signal line L2 can be coupled to the second level converter 132 through the frequency signal line CL2 and / or the frequency signal line CR2 and the corresponding coupled connecting line 113. The driving circuit board 130 may include a timing controller 133, but is not limited thereto. The first level converter 131 and the second level converter 132 are disposed on the driving circuit board 130, but are not limited thereto. The timing controller 133 can be used to control the operation of the first level converter 131 and the second level converter 132. The first level converter 131, the second level converter 132 and the timing controller 133 can be integrated into a single circuit chip or implemented as different circuit chips, but are not limited thereto.

[0032] In this embodiment, the first level converter 131 and the second level converter 132 can output the first frequency signal and the second frequency signal alternately. The first frequency signal and the second frequency signal can be input from the two opposite sides of the substrate 110 through the connecting line 113 and the corresponding coupled frequency signal line. In this embodiment, each signal line 112 can receive the frequency signal from the two opposite sides of the substrate 110 through the coupling of the frequency signal line at both ends. This can reduce the situation where the transistor switch coupled to the signal line 112 malfunctions due to excessive load caused by the excessive length of the signal line 112 on a large-size substrate 110, and can reduce the problem of the optical characteristics of the electronic device 100 not meeting the requirements.

[0033] Figure 2 A block diagram illustrating another embodiment of the electronic device of this disclosure is shown. Please refer to... Figure 1 and Figure 2 , Figure 2 The electronic device 200 of the embodiment is similar to Figure 1 The electronic device 100 of the embodiment differs from the other in that the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are input from frequency signal lines arranged in reverse order on opposite sides of the substrate 110.

[0034] In this embodiment, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are input to the substrate 110 from the left side via frequency signal lines CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL9, CL10, CL11, CL12 arranged in a first order on the substrate 110. Simultaneously, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are also input to the substrate 110 from the right side via frequency signal lines CR12, CR11, CR10, CR9, CR8, CR7, CR6, CR5, CR4, CR3, CR2, CR1 arranged in a second order on the substrate 110. In other words, in this embodiment, the frequency signal lines for inputting the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are arranged in different orders on opposite sides of the substrate 110. From left to right, they are the first order CL1, CL2, CL3, CL4, CL5, CL6, CL7, CL8, CL9, CL10, CL11, CL12 and the second order CR12, CR11, CR10, CR9, CR8, CR7, CR6, CR5, CR4, CR3, CR2, CR1. This can reduce the situation where the transistors coupled to the signal lines 112 malfunction due to excessive load caused by the excessive length of the signal lines 112 on the large-size substrate 110, thereby reducing the problem of the optical characteristics of the electronic device 100 not meeting the requirements.

[0035] Therefore, the first frequency signals CK1, CK3, CK5, CK7, CK9, CK11 and the second frequency signals CK2, CK4, CK6, CK8, CK10, CK12 are input from the double-opposite sides of the substrate 110 through frequency signal lines arranged in different sequences. This allows for corresponding adjustments to the trace layout on the circuit board 120_2 to ensure compatibility with... Figure 1 The routing layout on the circuit board 120_2 is different.

[0036] Figure 3 A block diagram illustrating a first level converter and a second level converter according to an embodiment of this disclosure is shown. Please refer to... Figure 3The first level converter 131 and the second level converter 132 are implemented as different circuit chips, for example. The first level converter 131 has eight pins. Pins 1 to 6 output first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11, respectively. The second level converter 132 has eight pins. Pins 1 to 6 output second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12, respectively. The number of pins and the number of frequency signals are not intended to limit this disclosure.

[0037] Figure 4A The diagram shows waveforms of a first frequency signal and a second frequency signal according to an embodiment of this disclosure. Please refer to... Figure 4A In this embodiment, the first first frequency signal CK1 of the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11, and the first second frequency signal CK2 of the second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 partially overlap in time, as shown in dashed box 410. Furthermore, the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11 do not overlap in time with each other; therefore, the heat generated by the first level converter 131 during operation can be evenly distributed over the operation period T1. Similarly, the second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 do not overlap in time with each other; therefore, the heat generated by the second level converter 132 during operation can be evenly distributed over the operation period T2.

[0038] In this embodiment, since the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11 do not overlap with each other in time, and the second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 also do not overlap with each other in time, the temperature rise is relatively mild even if the electronic devices 100 and 200 operate continuously, which can reduce the impact on the stability of the electronic devices 100 and 200.

[0039] Figure 4B A waveform diagram of a first frequency signal and a second frequency signal according to another embodiment of this disclosure is shown. Please refer to... Figure 4BIn this embodiment, the first first frequency signal CK1 of the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11, and the first second frequency signal CK2 of the second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12, completely overlap in time, as shown in dashed box 420. Furthermore, the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11 partially overlap in time with each other, as shown in dashed box 430. The first first frequency signal CK1 and the second first frequency signal CK3 partially overlap in time. Therefore, the heat generated by the first level converter 131 can be evenly distributed during operation period T3. The second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 also partially overlap in time with each other, as shown in dashed box 440. The first second second frequency signal CK2 and the second second second frequency signal CK4 partially overlap in time. Therefore, the heat generated by the second level converter 132 can be evenly distributed during operation period T4.

[0040] In this embodiment, since the first frequency signals CK1, CK3, CK5, CK7, CK9, and CK11 partially overlap in time, and the second frequency signals CK2, CK4, CK6, CK8, CK10, and CK12 also partially overlap in time, the temperature rise is relatively mild even if the electronic devices 100 and 200 operate continuously, which reduces the impact on the stability of the electronic devices 100 and 200.

[0041] In summary, in the embodiments of this disclosure, multiple first frequency signals and multiple second frequency signals are input from opposite sides of the substrate, which improves the convenience of wiring layout and reduces the possibility of malfunctions in transistor switches coupled to signal lines due to excessively long signal lines on large-size substrates caused by excessive load. This also reduces the problem of the optical characteristics of the electronic device not meeting requirements. Furthermore, since the multiple first frequency signals and the multiple second frequency signals may not overlap or may partially overlap in time, the temperature rise is more moderate even during continuous operation of the electronic device, reducing the impact on the stability of the electronic device.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, comprising: a substrate having a frequency signal line; a first signal line, a second signal line, and a third signal line disposed on the substrate, wherein each of the first, second, and third signal lines has two end points, and the second signal line is disposed between the first and third signal lines; a first level shifter coupled to the first and third signal lines; and a second level shifter coupled to the second signal line, wherein the first level shifter is coupled to the two end points of the first signal line and the two end points of the third signal line, and the second level shifter is coupled to the two end points of the second signal line, wherein the first level shifter outputs a plurality of first frequency signals, and the second level shifter outputs a plurality of second frequency signals, the first, second, and third signal lines are coupled to the first level shifter or the second level shifter through the frequency signal line and a corresponding coupled connection line, and the first and second level shifters input the plurality of first frequency signals and the plurality of second frequency signals from two opposite edges of the substrate through the connection line and the corresponding coupled frequency signal line.

2. The electronic device of claim 1, wherein a first one of the plurality of first frequency signals and a first one of the plurality of second frequency signals partially overlap in time.

3. The electronic device of claim 2, wherein the plurality of first frequency signals do not overlap in time with each other.

4. The electronic device of claim 2, wherein the plurality of second frequency signals do not overlap in time with each other.

5. The electronic device of claim 1, wherein a first one of the plurality of first frequency signals and a first one of the plurality of second frequency signals completely overlap in time.

6. The electronic device of claim 5, wherein the plurality of first frequency signals partially overlap in time with each other.

7. The electronic device of claim 5, wherein the plurality of second frequency signals partially overlap in time with each other.

8. The electronic device of claim 1, wherein the plurality of first frequency signals and the plurality of second frequency signals are input from the two opposite edges of the substrate in the same order.

9. The electronic device of claim 1, wherein the plurality of first frequency signals and the plurality of second frequency signals are input from the two opposite edges of the substrate in opposite orders. ​

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