Multi-channel high-speed data transmission synchronization method and system

Abstract

The present invention discloses a multi-channel high-speed data transmission synchronization method and system. The method comprises: at a transmitting end, detecting the validity of an externally input reference synchronization pulse and simultaneously generating a local synchronization pulse; delaying the local synchronization pulse by several system clocks; framing the high-speed data and the local synchronization pulse to complete time stamp printing and transmit the data to a receiving end; at a receiving end, detecting the validity of the externally input reference synchronization pulse and simultaneously generating a local synchronization pulse; delaying the local synchronization pulse by several system clocks to ensure that the receiving ends of multiple channels have completed time stamp detection and that a certain difference between the write address and the read address is maintained after synchronization. The method also assigns the stored write address to the read address according to the time of the delayed local synchronization pulse, and reads data from an array register at the next time, thereby achieving multi-channel high-speed data synchronization. The present invention facilitates multiplexing, detection, and cross-platform porting.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed digital signal transmission, and in particular to a multi-channel high-speed data transmission synchronization method and system. Background Art

[0002] With the advancement of high-speed and ultra-high-speed signal acquisition, transmission, and processing technologies, large-scale phased array digital beamforming has become a key technological trend. Digital beamforming technology is being applied to advanced radar system design and smart antennas for wireless communications. Digital beamforming involves multi-board, multi-channel, high-speed signal acquisition, transmission, convergence, synthesis, and distribution. Digital beamforming is implemented using large-scale field-programmable gate arrays (FPGAs). High-speed data transmission within and between digital beamforming boards utilizes high-speed serial I / O technologies, such as the Aurora and 204B protocols offered by Xilinx FPGAs.

[0003] The Aurora protocol is an open, free link layer protocol that can be used for point-to-point serial data transmission. It has the characteristics of high efficiency and ease of use in achieving high-performance data transmission systems.

[0004] When high-speed data is transmitted within and between digital beamforming boards using the Aurora protocol, multi-channel high-speed data within and between boards becomes asynchronous. Multi-channel data synchronization is essential for digital beamforming. Therefore, the technical solution must prioritize the synchronization of multi-channel high-speed data transmission within and between boards. Existing high-speed data synchronization technologies use a dual-port RAM IPcore within the FPGA for data caching, which hinders cross-platform program portability. Summary of the Invention

[0005] In view of this, the present invention provides a multi-channel high-speed data transmission synchronization method and system to solve the above technical problems.

[0006] The present invention discloses a multi-channel high-speed data transmission synchronization system, which is applicable to the same board or between boards, and includes multiple transmitting ends and multiple receiving ends; a single transmitting end corresponds to a single receiving end, and is used to process high-speed data; the high-speed data of all channels are processed simultaneously and in parallel;

[0007] The single sending end includes:

[0008] The data sending module is used to transmit the received high-speed data to the data framing and time stamping module;

[0009] A first local synchronization pulse module is used to detect the validity of an externally input reference synchronization pulse and generate a local synchronization pulse;

[0010] The first delay module is used to delay the local synchronization pulse by several system clocks;

[0011] Data framing and timestamping module, used to frame high-speed data with local synchronization pulses, complete timestamp printing and send it to the receiving end;

[0012] An Aurora protocol sending module is used to send the data with the timestamp printed to the Aurora protocol receiving module at the receiving end through the Aurora protocol;

[0013] The single receiving end includes:

[0014] The second local synchronization pulse module is used to detect the validity of the external input reference synchronization pulse and generate a local synchronization pulse;

[0015] The second delay module is used to delay the local synchronization pulse by several system clocks to ensure that each receiving end has completed the timestamp detection and that the write address and read address can always maintain a certain difference after synchronization;

[0016] Aurora protocol receiving module, used to realize serial-to-parallel conversion of high-speed data, output valid data, valid identifier, and associated user clock;

[0017] The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the accompanying user clock, and write the valid data into the array register according to the write address;

[0018] The timestamp detection logic module is used to detect in real time whether the timestamp bit in the data sent by the write address control logic module is at a high level. If a high level is detected, the current write address is stored.

[0019] The read address control logic module is used to assign the stored write address to the read address according to the delayed local synchronization pulse time, and read the data from the array register at the next moment, so as to realize the synchronization of multi-channel high-speed data within the same board and between boards;

[0020] Array register, used to store write address data and output synchronized data.

[0021] Furthermore, the transmitting end and the receiving end use the same system working clock; the first delay module and the second delay module are the same;

[0022] The first local synchronization pulse module and the second local synchronization pulse module are identical to generate the same local synchronization pulse, and the external reference synchronization pulses received by them are identical.

[0023] Furthermore, the first local synchronization pulse module is further configured to:

[0024] Continuously detect and judge whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold value; if consistent, it is judged that the reference synchronization pulse input is valid, and the local generated pulse counter is reset at the same time to start continuously generating local synchronization pulses;

[0025] After determining that the reference synchronization pulse input is valid, the validity of the input reference synchronization pulse is monitored in real time. If the system clock count values ​​between the rising edges of multiple consecutive reference synchronization pulses are inconsistent and inconsistent with the preset threshold, the previous synchronization is judged to be invalid, and the detection of the validity of the external input reference synchronization pulse is restarted.

[0026] Furthermore, the Aurora protocol receiving module is used to perform serial-to-parallel conversion on the received data and output valid data, valid identifier, and associated user clock;

[0027] The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the associated user clock, and write the valid data into the array register according to the write address;

[0028] The timestamp detection logic module is used to detect and determine in real time whether the timestamp bit in the received data is at a high level based on the valid identifier and the associated user clock, and if a high level is detected, store the current write address;

[0029] The read address control logic module is used to assign the stored write address to the read address according to the local synchronization pulse time after the delay, and read data from the array register at the next moment, thereby realizing the synchronization of multi-channel high-speed data within the board and between boards.

[0030] The present invention also discloses a multi-channel high-speed data transmission synchronization method, which is applicable to the multi-channel high-speed data transmission synchronization system described above. The method comprises:

[0031] For each channel of high-speed data, at the transmitting end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated. The local synchronization pulse is delayed by several system clocks. The high-speed data and the local synchronization pulse are framed to complete the timestamp printing and sent to the receiving end. The timestamp is inserted into a preset position in the high-speed data, occupying only one bit in the high-speed data.

[0032] For the high-speed data of each channel, at the receiving end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated at the same time. The local synchronization pulse is delayed by several system clocks to ensure that the receiving ends of multiple channels have completed time stamp detection and that the write address and read address can always maintain a certain difference after synchronization. According to the time of the delayed local synchronization pulse, the stored write address is assigned to the read address, and the data is read from the array register at the next moment, thus realizing the synchronization of multi-channel high-speed data.

[0033] Furthermore, on the transmitting end, the high-speed data of each channel is processed in parallel at the same time; on the receiving end, the high-speed data of each channel is processed in parallel at the same time;

[0034] For each channel of high-speed data, the sending end and the receiving end correspond one to one;

[0035] The reference synchronization pulse is distributed to each board through equal-length coaxial cables or equal-length optical fibers to ensure that the phase of the reference synchronization pulse input to each board is consistent; the frequency period of the synchronization pulse is set according to system requirements.

[0036] Furthermore, the detecting the validity of the externally input reference synchronization pulse and generating the local synchronization pulse at the same time includes:

[0037] Continuously detect multiple times whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold; if consistent, the reference synchronization pulse input is determined to be valid, and the local generated pulse counter is reset at the same time to start continuously generating local synchronization pulses.

[0038] Furthermore, after determining whether the reference synchronization pulse input is valid, the method further includes:

[0039] Monitor the validity of the input reference synchronization pulse in real time. If the system clock count value between the rising edges of multiple consecutive reference synchronization pulses is inconsistent and inconsistent with the preset threshold, it is judged that the previous synchronization has failed, and the detection of the validity of the external input reference synchronization pulse is restarted.

[0040] Furthermore, at the transmitting end, the high-speed data is framed with the local synchronization pulse, that is, the timestamp printing is completed, and finally the transmission is completed through the high-speed channel data Aurora protocol.

[0041] Furthermore, at the receiving end, the received data is serial-to-parallel converted and valid data, valid identifier, and associated user clock are output;

[0042] After synchronization, the write address and the read address can always maintain a certain difference, including:

[0043] According to the valid flag and the user clock, the write address is controlled to accumulate in a loop, and the valid data is written into the array register according to the write address;

[0044] Based on the valid identifier and the associated user clock, real-time detection is performed to determine whether the timestamp bit in the received data is at a high level. If a high level is detected, the current write address is stored. According to the delay of high-speed data transmission of different channels, the delay amount of the corresponding second delay module is set to ensure that the timestamp detection logic modules of all channels have completed the timestamp detection and when the timestamp detection logic module at the receiving end detects that the timestamp in the data is at a high level, the write address at that time is stored, and it is ensured that the read address and write address in the array register are different at the same time.

[0045] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0046] 1. Modular and parameterized design: The transmitter and receiver functions are modularly designed and implemented using Verilog language coding. The delay module has parameterized input for delay value, which is convenient for reuse and transplantation.

[0047] 2. Flexible insertion of timestamp and easy detection: The timestamp identifier of the present invention is flexibly inserted into a predetermined position of the data frame, occupying only one bit in the data frame; the receiving end detects a fixed bit, which is easy to implement detection and occupies little resources.

[0048] 3. Array register design: The present invention uses array register reading and writing to replace the FPGA's dual-port read-write RAM IPcore, which is easy to implement and cross-platform transplantation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments described in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0050] Figure 1 Schematic diagram of a single-channel implementation structure of a multi-channel high-speed data transmission synchronization system at the transmitting end according to an embodiment of the present invention;

[0051] Figure 2 The present invention is a schematic diagram of a single-channel implementation structure of a multi-channel high-speed data transmission synchronization system at the receiving end according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described with reference to the accompanying drawings and embodiments. Obviously, the embodiments described are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art should fall within the scope of protection of the embodiments of the present invention.

[0053] Figure 1 The local synchronization pulse output is used to timestamp the high-speed data at the sending end. Figure 2 The local synchronization pulse is used to start reading high-speed data in the array register at the same time according to the stored start read address, thereby realizing the synchronization of multi-channel high-speed data.

[0054] The present invention provides an embodiment of a multi-channel high-speed data transmission synchronization system, which is applicable to the same board or between multiple boards, and includes multiple transmitting ends and multiple receiving ends; a single transmitting end corresponds to a single receiving end, and is used to process high-speed data; the high-speed data of all channels is processed simultaneously and in parallel; each transmitting end is the same, see Figure 1 ; Each receiving end is the same, see Figure 2 Each transmitter and receiver is implemented in the on-board FPGA, processing the high-speed data in each channel. The synchronized data output by a receiver on one board undergoes algorithmic processing (such as beamforming) and then passes through the transmitter on that board before being transmitted to the Aurora protocol receiver module on the other board via high-speed cables, digital fiber, or other high-speed transmission media.

[0055] The high-speed data may come from a high-speed digital signal sampled by a high-speed ADC or a high-speed digital signal synthesized, aggregated, and distributed within a board.

[0056] Among them, a single sending end includes:

[0057] The data sending module is used to transmit the received high-speed data to the data framing and time stamping module;

[0058] A first local synchronization pulse module is used to detect the validity of an externally input reference synchronization pulse and generate a local synchronization pulse;

[0059] The first delay module is used to delay the local synchronization pulse by several system clocks;

[0060] Data framing and timestamping module, used to frame high-speed data with local synchronization pulses, complete timestamp printing and send it to the receiving end;

[0061] An Aurora protocol sending module is used to send the data with the timestamp printed to the Aurora protocol receiving module at the receiving end through the Aurora protocol;

[0062] A single receiver includes:

[0063] The second local synchronization pulse module is used to detect the validity of the external input reference synchronization pulse and generate a local synchronization pulse;

[0064] The second delay module is used to delay the local synchronization pulse by several system clocks to ensure that each receiving end has completed the timestamp detection and that the write address and read address can always maintain a certain difference after synchronization;

[0065] Aurora protocol receiving module, used to implement high-speed data serial-to-parallel conversion, output valid data, valid flag (valid), and user clock (userclk);

[0066] The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the accompanying user clock, and write the valid data into the array register according to the write address;

[0067] The timestamp detection logic module is used to detect in real time whether the timestamp bit in the data sent by the write address control logic module is at a high level. If a high level is detected, the current write address is stored.

[0068] The read address control logic module is used to assign the stored write address to the read address according to the delayed local synchronization pulse time, and read the data from the array register at the next moment, so as to realize the synchronization of multi-channel high-speed data within the same board and between boards;

[0069] Array register, used to store write address data and output synchronized data.

[0070] Preferably, the system working clocks used by the transmitting end and the receiving end are the same; the first delay module and the second delay module are the same; the delay amount of the first delay module and the second delay module are parameterized, and the input delay amount parameters are set according to needs;

[0071] The first local synchronization pulse module and the second local synchronization pulse module are identical to each other so as to generate the same local synchronization pulse, and the external reference synchronization pulses received by the modules are identical.

[0072] Preferably, the first local synchronization pulse module is further used for:

[0073] Continuously detect and determine whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold; if consistent, the reference synchronization pulse input is determined to be valid, and the local generated pulse counter is reset at the same time to start continuously generating local synchronization pulses; the width of the first local synchronization pulse module outputting a high level is set according to requirements;

[0074] After judging that the reference synchronization pulse input is valid, the validity of the input reference synchronization pulse is monitored in real time. If the system clock count value between the rising edges of multiple consecutive reference synchronization pulses is inconsistent and inconsistent with the preset threshold, the previous synchronization is judged to be invalid, and the validity of the external input reference synchronization pulse is restarted.

[0075] Preferably, the Aurora protocol receiving module is used to perform serial-to-parallel conversion on the received data and output valid data, valid identifier, and associated user clock;

[0076] The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the accompanying user clock, and write the valid data into the array register according to the write address;

[0077] The timestamp detection logic module is used to detect in real time whether the timestamp bit in the received data is high level according to the valid identifier and the associated user clock. If a high level is detected, the current write address is stored.

[0078] The read address control logic module is used to assign the stored write address to the read address according to the delayed local synchronization pulse time, and read data from the array register at the next moment, thereby realizing the synchronization of multi-channel high-speed data within the board and between boards.

[0079] The present invention also discloses a multi-channel high-speed data transmission synchronization method, which is applicable to the multi-channel high-speed data transmission synchronization system mentioned above. The method includes:

[0080] For each channel of high-speed data, at the transmitting end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated. The local synchronization pulse is delayed by several system clocks. The high-speed data and the local synchronization pulse are framed to complete the timestamp printing and sent to the receiving end. The timestamp is inserted into a preset position in the high-speed data, occupying only one bit in the high-speed data.

[0081] For the high-speed data of each channel, at the receiving end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated at the same time. The local synchronization pulse is delayed by several system clocks to ensure that the receiving ends of multiple channels have completed time stamp detection and that the write address and read address can always maintain a certain difference after synchronization. According to the time of the delayed local synchronization pulse, the stored write address is assigned to the read address, and the data is read from the array register at the next moment, thus realizing the synchronization of multi-channel high-speed data.

[0082] Preferably, at the transmitting end, the high-speed data of each channel is processed in parallel at the same time; at the receiving end, the high-speed data of each channel is processed in parallel at the same time;

[0083] For each channel of high-speed data, the sending end and the receiving end correspond one to one;

[0084] The reference synchronization pulse is distributed to each board through equal-length coaxial cables or equal-length optical fibers to ensure that the phase of the reference synchronization pulse input to each board is consistent; the frequency period of the synchronization pulse is set according to system requirements.

[0085] Preferably, detecting the validity of an externally input reference synchronization pulse and generating a local synchronization pulse at the same time comprises:

[0086] Continuously detect multiple times whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold; if consistent, the reference synchronization pulse input is determined to be valid, and the local generated pulse counter is reset at the same time to start continuously generating local synchronization pulses.

[0087] Preferably, after determining whether the reference synchronization pulse input is valid, the method further includes:

[0088] Monitor the validity of the input reference synchronization pulse in real time. If the system clock count value between the rising edges of multiple consecutive reference synchronization pulses is inconsistent and inconsistent with the preset threshold, it is judged that the previous synchronization has failed and the validity of the external input reference synchronization pulse is restarted.

[0089] Preferably, at the transmitting end, the high-speed data is framed with the local synchronization pulse, that is, the timestamp printing is completed, and finally the transmission is completed through the high-speed channel data Aurora protocol.

[0090] Preferably, at the receiving end, the received data is serial-to-parallel converted, and valid data, valid identification, and associated user clock are output;

[0091] After synchronization, the write address and read address can always maintain a certain difference, including:

[0092] According to the valid flag and the user clock, the write address is controlled to accumulate cyclically and the valid data is written into the array register according to the write address;

[0093] Based on the valid identifier and the associated user clock, real-time detection is performed to determine whether the timestamp bit in the received data is at a high level. If a high level is detected, the current write address is stored. According to the delay of high-speed data transmission of different channels, the delay amount of the corresponding second delay module is set to ensure that the timestamp detection logic modules of all channels have completed the timestamp detection and when the timestamp detection logic module at the receiving end detects that the timestamp in the data is at a high level, the write address at that time is stored, and it is ensured that the read address and write address in the array register are different at the same time.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A multi-channel high-speed data transmission synchronization system, suitable for use within the same board or between boards, characterized in that: including multiple sending ends and multiple receiving ends; A single transmitter corresponds to a single receiver, and is used to process high-speed data on a single channel. High-speed data from all channels are processed in parallel simultaneously; The single sending end includes: The data sending module is used to transmit the received high-speed data to the data framing and time stamping module; A first local synchronization pulse module is used to detect the validity of an externally input reference synchronization pulse and generate a local synchronization pulse; The first delay module is used to delay the local synchronization pulse by several system clocks; Data framing and timestamping module, used to frame high-speed data with local synchronization pulses, complete timestamp printing and send it to the receiving end; An Aurora protocol sending module is used to send the data with the timestamp printed to the Aurora protocol receiving module at the receiving end through the Aurora protocol; The single receiving end includes: The second local synchronization pulse module is used to detect the validity of the external input reference synchronization pulse and generate a local synchronization pulse; The second delay module is used to delay the local synchronization pulse by several system clocks to ensure that each receiving end has completed the timestamp detection and that the write address and read address can always maintain a certain difference after synchronization; Aurora protocol receiving module, used to realize serial-to-parallel conversion of high-speed data, output valid data, valid identifier, and associated user clock; The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the accompanying user clock, and write the valid data into the array register according to the write address; The timestamp detection logic module is used to detect in real time whether the timestamp bit in the data sent by the write address control logic module is at a high level. If a high level is detected, the current write address is stored. The read address control logic module is used to assign the stored write address to the read address according to the delayed local synchronization pulse time, and read the data from the array register at the next moment, so as to realize the synchronization of multi-channel high-speed data within the same board and between boards; Array register, used to store write address data and output synchronized data; The first local synchronization pulse module is also used to: continuously detect and determine whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold; if consistent, it is determined that the reference synchronization pulse input is valid, and the local generated pulse counter is reset at the same time, and local synchronization pulses are continuously generated, and the validity of the input reference synchronization pulse is monitored in real time. If the system clock count value between the rising edges of multiple consecutive reference synchronization pulses is inconsistent and inconsistent with the preset threshold, it is determined that the previous synchronization is invalid, and the detection of the validity of the external input reference synchronization pulse is restarted.

2. The system according to claim 1, wherein: The transmitting end and the receiving end use the same system working clock; the first delay module and the second delay module are the same; The first local synchronization pulse module and the second local synchronization pulse module are identical to generate the same local synchronization pulse, and the external reference synchronization pulses received by them are identical.

3. The system according to claim 1, wherein: The Aurora protocol receiving module is used to perform serial-to-parallel conversion on the received data and output valid data, valid identifier, and associated user clock; The write address control logic module is used to control the write address cyclic accumulation according to the valid identifier and the associated user clock, and write the valid data into the array register according to the write address; The timestamp detection logic module is used to detect and determine in real time whether the timestamp bit in the received data is at a high level based on the valid identifier and the associated user clock, and if a high level is detected, store the current write address; The read address control logic module is used to assign the stored write address to the read address according to the local synchronization pulse time after the delay, and read data from the array register at the next moment, thereby realizing the synchronization of multi-channel high-speed data within the board and between boards.

4. A multi-channel high-speed data transmission synchronization method, applicable to a multi-channel high-speed data transmission synchronization system according to any one of claims 1 to 3, characterized in that: The method comprises: For each channel of high-speed data, at the transmitting end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated. The local synchronization pulse is delayed by several system clocks. The high-speed data and the local synchronization pulse are framed to complete the timestamp printing and sent to the receiving end. The timestamp is inserted into a preset position in the high-speed data, occupying only one bit in the high-speed data. For the high-speed data of each channel, at the receiving end, the validity of the external input reference synchronization pulse is detected and a local synchronization pulse is generated at the same time. The local synchronization pulse is delayed by several system clocks to ensure that the receiving ends of multiple channels have completed time stamp detection and that the write address and read address can always maintain a certain difference after synchronization. According to the time of the delayed local synchronization pulse, the stored write address is assigned to the read address, and the data is read from the array register at the next moment, thus realizing the synchronization of multi-channel high-speed data.

5. The method according to claim 4, characterized in that On the transmitting end, the high-speed data of each channel is processed in parallel at the same time; on the receiving end, the high-speed data of each channel is processed in parallel at the same time; For each channel of high-speed data, the sending end and the receiving end correspond one to one; The reference synchronization pulse is distributed to each board through equal-length coaxial cables or equal-length optical fibers to ensure that the phase of the reference synchronization pulse input to each board is consistent; the frequency period of the synchronization pulse is set according to system requirements.

6. The method according to claim 4, characterized in that The detecting the validity of the externally input reference synchronization pulse and generating the local synchronization pulse at the same time includes: Continuously detect multiple times whether the system clock count value between the rising edges of the reference synchronization pulse is consistent with the preset threshold; if consistent, the reference synchronization pulse input is determined to be valid, and the local generated pulse counter is reset at the same time to start continuously generating local synchronization pulses.

7. The method according to claim 6, characterized in that After determining that the reference synchronization pulse input is valid, the method further comprises: Monitor the validity of the input reference synchronization pulse in real time. If the system clock count value between the rising edges of multiple consecutive reference synchronization pulses is inconsistent and inconsistent with the preset threshold, it is judged that the previous synchronization has failed, and the detection of the validity of the external input reference synchronization pulse is restarted.

8. The method according to claim 7, characterized in that At the transmitting end, the high-speed data is framed with the local synchronization pulse to complete the timestamp printing, and finally sent through the high-speed channel data Aurora protocol.

9. The method according to claim 4, characterized in that At the receiving end, the received data is converted from serial to parallel and valid data, valid identifier and associated user clock are output; After synchronization, the write address and the read address can always maintain a certain difference, including: According to the valid flag and the user clock, the write address is controlled to accumulate in a loop, and the valid data is written into the array register according to the write address; Based on the valid identifier and the associated user clock, real-time detection is performed to determine whether the timestamp bit in the received data is at a high level. If a high level is detected, the current write address is stored. According to the delay of high-speed data transmission of different channels, the delay amount of the corresponding second delay module is set to ensure that the timestamp detection logic modules of all channels have completed the timestamp detection and when the timestamp detection logic module at the receiving end detects that the timestamp in the data is at a high level, the write address at that time is stored, and it is ensured that the read address and write address in the array register are different at the same time.

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