Display substrate and display device

Abstract

A display substrate includes: a substrate, a plurality of first light-emitting units and a plurality of second light-emitting units located in a first display area, a plurality of first pixel circuits located in the first display area, and a plurality of second pixel circuits located in a second display area. Each first light-emitting unit includes at least one first light-emitting element, and each second light-emitting unit includes at least one second light-emitting element. At least one first light-emitting unit is adjacent to at least one second light-emitting unit. At least one first pixel circuit is electrically connected to at least one first light-emitting element and configured to drive at least one first light-emitting element to emit light. At least one second pixel circuit is electrically connected to at least one second light-emitting element and configured to drive at least one second light-emitting element to emit light.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate includes a first display area and a second display area located at least one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area; the first light-emitting unit includes at least one first light-emitting element, and the second light-emitting unit includes at least one second light-emitting element; the first light-emitting unit is adjacent to the at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area; at least one of the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and configured to drive the at least one first light-emitting element to emit light. The plurality of second pixel circuits are located in the second display area; at least one of the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and configured to drive the at least one second light-emitting element to emit light.

[0006] In some exemplary embodiments, the plurality of first light-emitting units and the plurality of second light-emitting units are spaced apart along at least one of a first direction and a second direction; the first direction intersects the second direction.

[0007] In some exemplary embodiments, in the first direction, a first light-emitting unit and a second light-emitting unit are arranged at intervals; in the second direction, a first light-emitting unit and a second light-emitting unit are arranged at intervals.

[0008] In some exemplary embodiments, the plurality of first light-emitting units includes: a plurality of columns of first light-emitting units; each column of first light-emitting units includes a plurality of first light-emitting units arranged sequentially along the second direction. The plurality of second light-emitting units includes: a plurality of columns of second light-emitting units, each column of second light-emitting units including a plurality of second light-emitting units arranged sequentially along the second direction. In the first direction, a column of first light-emitting units and a column of second light-emitting units are arranged alternately.

[0009] In some exemplary embodiments, the plurality of first light-emitting units includes multiple rows of first light-emitting units, each row of first light-emitting units including multiple first light-emitting units arranged sequentially along the first direction. The plurality of second light-emitting units includes multiple rows of second light-emitting units, each row of second light-emitting units including multiple second light-emitting units arranged sequentially along the first direction. In the second direction, a row of first light-emitting units and a row of second light-emitting units are arranged alternately.

[0010] In some exemplary embodiments, adjacent first light-emitting units and second light-emitting units in the first direction are aligned, and adjacent first light-emitting units and second light-emitting units in the second direction are aligned; or, adjacent first light-emitting units and second light-emitting units in the second direction are misaligned.

[0011] In some exemplary embodiments, the ratio of the luminous area of ​​the second light-emitting element and the first light-emitting element emitting light of the same color is less than 1.

[0012] In some exemplary embodiments, the number of first light-emitting elements included in at least one first light-emitting unit is the same as the number of second light-emitting elements included in at least one second light-emitting unit.

[0013] In some exemplary embodiments, the at least one first light-emitting unit includes the following four first light-emitting elements: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light. The at least one second light-emitting unit includes the following four second light-emitting elements: a second light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and two second light-emitting elements emitting a third color light.

[0014] In some exemplary embodiments, the plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns. In the at least one first light-emitting unit, the two first light-emitting elements emitting a third color light are arranged in the same column, the first light-emitting elements emitting a first color light and the first light-emitting elements emitting a second color light are arranged in the same column, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows. In the at least one second light-emitting unit, the two second light-emitting elements emitting a third color light are arranged in the same column, the second light-emitting elements emitting a first color light and the second light-emitting elements emitting a second color light are arranged in the same column, and the four second light-emitting elements of the second light-emitting unit are arranged in different rows.

[0015] In some exemplary embodiments, the plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns. In the at least one first light-emitting unit, the two first light-emitting elements emitting a third color light are arranged in the same row, the first light-emitting elements emitting a first color light and the first light-emitting elements emitting a second color light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different columns. In the at least one second light-emitting unit, the two second light-emitting elements emitting a third color light are arranged in the same row, the second light-emitting elements emitting a first color light and the second light-emitting elements emitting a second color light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

[0016] In some exemplary embodiments, the four first light-emitting elements in the first light-emitting unit are electrically connected to the four first pixel circuits one by one. The four first pixel circuits are arranged sequentially along a first direction, and the orthographic projection of each first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element on the substrate.

[0017] In some exemplary embodiments, the four first pixel circuits are symmetrically arranged about the first midline along the first direction, the first and second first pixel circuits are symmetrically arranged about the two first pixel circuits along the second midline along the first direction, and the third and fourth first pixel circuits are symmetrically arranged about the two first pixel circuits along the third midline along the first direction.

[0018] In some exemplary embodiments, the four first pixel circuits are electrically connected to first power lines, which are arranged in a grid pattern in the first display area.

[0019] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer located on the substrate; the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits includes: at least one first type transistor, at least one second type transistor, and a storage capacitor. The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of the first type transistor of the pixel circuit; the first conductive layer includes at least: a gate of the first type transistor of the pixel circuit and a first electrode of the storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of the second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of the second type transistor of the pixel circuit; the fourth conductive layer includes at least: a plurality of connection electrodes; the fifth conductive layer includes at least: a plurality of data lines; and the sixth conductive layer includes at least: a first power line.

[0020] In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one of the plurality of second sub-regions is provided with at least one second light-emitting unit. The second conductive layer further includes: a first scan line, a light-emitting control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light-emitting control line, the first reset control line, and the second reset control line extend along a first direction. In a second direction, the first scan line and the first reset control line bypass one side of the second sub-region, and the light-emitting control line and the second reset control line bypass the other side of the second sub-region; the second direction intersects the first direction.

[0021] In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one of the plurality of second sub-regions is provided with at least one second light-emitting unit. The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend along a first direction. In a second direction, the first initial signal line and the second scan line bypass one side of the second sub-region, and the second initial signal line and the third initial signal line bypass the other side of the second sub-region; the second direction intersects the first direction.

[0022] In some exemplary embodiments, the ratio of the number of the first light-emitting unit and the second light-emitting unit in the first display area is 0.8 to 1.2.

[0023] In some exemplary embodiments, the light transmittance of the first display area is greater than that of the second display area. The display substrate further includes: a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area. At least one of the plurality of third pixel circuits is electrically connected to at least one of the plurality of third light-emitting elements and configured to drive the at least one third light-emitting element to emit light. The plurality of second pixel circuits are spaced apart between the plurality of third pixel circuits.

[0024] In some exemplary embodiments, the orthographic projection of the at least one first pixel circuit on the substrate overlaps with the orthographic projection of the at least one first light-emitting element on the substrate. The at least one second pixel circuit is electrically connected to the at least one second light-emitting element via at least one conductive connection line; the orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element on the substrate.

[0025] In some exemplary embodiments, the orthographic projection of the at least one conductive connection line on the substrate overlaps with the orthographic projection of the at least one first pixel circuit on the substrate.

[0026] On the other hand, this embodiment provides a display device, including a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit;

[0032] Figure 4A and Figure 4B This is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0033] Figure 5 This is a schematic diagram showing the connection relationship between the light-emitting element and the pixel circuit in at least one embodiment of the present disclosure;

[0034] Figure 6 This is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0035] Figure 7A for Figure 6 A schematic diagram of the first display area after the first semiconductor layer is formed;

[0036] Figure 7B for Figure 7A A schematic diagram of the first sub-region in the diagram;

[0037] Figure 8A for Figure 6 A schematic diagram of the first display area after the formation of the first conductive layer;

[0038] Figure 8B for Figure 8A A schematic diagram of the first conductive layer in the middle;

[0039] Figure 8C for Figure 8A A schematic diagram of the first sub-region in the diagram;

[0040] Figure 9A for Figure 6 A schematic diagram of the first display area after the second conductive layer is formed;

[0041] Figure 9B for Figure 9A A schematic diagram of the second conductive layer in the middle;

[0042] Figure 9C for Figure 9A A schematic diagram of the first sub-region in the diagram;

[0043] Figure 10A for Figure 6 A schematic diagram of the first display area after the second semiconductor layer is formed;

[0044] Figure 10B for Figure 10A A schematic diagram of the second semiconductor layer in the process;

[0045] Figure 10C for Figure 10A A schematic diagram of the first sub-region in the diagram;

[0046] Figure 11A for Figure 6 A schematic diagram of the first display area after the third conductive layer is formed;

[0047] Figure 11B for Figure 11A A schematic diagram of the third conductive layer in the diagram;

[0048] Figure 11C for Figure 11A A schematic diagram of the first sub-region in the diagram;

[0049] Figure 12 for Figure 6 A schematic diagram of the first sub-region after the formation of the fifth insulating layer;

[0050] Figure 13A for Figure 6 A schematic diagram of the first display area after the fourth conductive layer is formed;

[0051] Figure 13B for Figure 13A A schematic diagram of the fourth conductive layer in the diagram;

[0052] Figure 13C for Figure 13A A schematic diagram of the first sub-region in the diagram;

[0053] Figure 14 for Figure 6 A schematic diagram of the first sub-region after the formation of the seventh insulating layer;

[0054] Figure 15A for Figure 6 A schematic diagram of the first display area after the fifth conductive layer is formed;

[0055] Figure 15B for Figure 15A A schematic diagram of the fifth conductive layer in the diagram;

[0056] Figure 15C for Figure 15AA schematic diagram of the first sub-region in the diagram;

[0057] Figure 16 for Figure 6 A schematic diagram of the first sub-region after the formation of the eighth insulating layer;

[0058] Figure 17A for Figure 6 A schematic diagram of the first display area after the formation of the sixth conductive layer;

[0059] Figure 17B for Figure 17A A schematic diagram of the sixth conductive layer in the diagram;

[0060] Figure 17C for Figure 17A A schematic diagram of the first sub-region in the diagram;

[0061] Figure 18 for Figure 6 A schematic diagram of the first display area after the formation of the ninth insulating layer;

[0062] Figure 19A for Figure 6 A schematic diagram of the first display area after the formation of the conductive connection layer;

[0063] Figure 19B for Figure 19A A schematic diagram of the conductive connection layer in the diagram;

[0064] Figure 20 for Figure 6 A schematic diagram of the first display area after the anode layer has been formed.

[0065] Figure 21 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0066] Figure 22 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0067] Figure 23 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0068] Figure 24 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0069] Figure 25 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0070] Figure 26 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0071] Figure 27This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0072] Figure 28 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0073] Figure 29 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0074] Figure 30 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0075] Figure 31 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0076] Figure 32 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0077] Figure 33 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0078] Figure 34 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0079] Figure 35 This is another example diagram of the first display area of ​​at least one embodiment of the present disclosure;

[0080] Figure 36 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0081] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0082] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0083] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0084] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0085] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0086] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0087] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0088] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0089] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0090] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0091] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0092] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0093] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0094] With the continuous development of display technology, cameras are typically installed on display devices to meet the needs of photography or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, waterdrop displays, and punch-hole displays have emerged. These technologies reduce the area occupied by the camera by creating a hole in a portion of the display area and placing the camera below the hole, thereby increasing the screen-to-body ratio. However, these technologies require removing part of the display area, resulting in some areas of the screen being undisplayed and preventing further increases in screen-to-body ratio. To avoid drilling holes in the display area and to make a true full-screen display possible while ensuring the practicality of the display substrate, the pixel circuitry in the under-display camera area is typically placed externally or internally.

[0095] The external pixel circuit method refers to placing the pixel circuit connected to the light-emitting element in the under-display camera area within the normal display area. This separate arrangement of the light-emitting element and pixel circuit improves the light transmittance of the under-display camera area. Since the under-display camera area lacks pixel circuitry and has no light-shielding layer other than the anode of the light-emitting element, it achieves high light transmittance. However, in this method, the pixel circuitry and light-emitting element need to be electrically connected via conductive wires. Limited by the space available for these conductive wires, the size (e.g., aperture) of the under-display camera area on the display substrate using this method is constrained. Increasing the aperture of the under-display camera area typically requires additional masking processes for the conductive wires, increasing costs. Furthermore, the conductive wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the high sheet resistance of ITO, the conductive wires experience a high load, which can easily affect the brightness of the light-emitting element in the under-display camera area, leading to reduced brightness and display defects, such as vertical display defects (Mura).

[0096] The built-in pixel circuit method refers to placing the light-emitting element and the pixel circuit connected to it in the under-display camera area. Compared to the external pixel circuit method, the electrical connection between the pixel circuit and the light-emitting element in the under-display camera area using the built-in method does not require long conductive wires, thus avoiding display defects in the under-display camera area caused by conductive wires. Furthermore, the built-in method is not limited by the size of the under-display camera area and can support large-aperture under-display cameras. However, in display substrates using the built-in pixel circuit method, the light transmittance of the under-display camera area is affected because the anode of the light-emitting element in the under-display camera area cannot completely block the pixel circuit.

[0097] This embodiment provides a display substrate and a display device that can support increasing the size of the under-display camera area while ensuring the light transmittance of the under-display camera area.

[0098] This embodiment provides a display substrate, including: a substrate, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate includes a first display area and a second display area located at least one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area; each first light-emitting unit includes at least one first light-emitting element, and each second light-emitting unit includes at least one second light-emitting element. The first light-emitting units are adjacent to at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area; at least one of the plurality of first pixel circuits is electrically connected to at least one first light-emitting element and configured to drive the at least one first light-emitting element to emit light. The plurality of second pixel circuits are located in the second display area; at least one of the plurality of second pixel circuits is electrically connected to at least one second light-emitting element and configured to drive the at least one second light-emitting element to emit light.

[0099] The display substrate provided in this embodiment adopts a combination of external and internal pixel circuits, which can ensure the light transmittance of the first display area and support increasing the size of the first display area.

[0100] In some exemplary embodiments, a plurality of first light-emitting units and a plurality of second light-emitting units may be spaced apart along at least one of a first direction and a second direction. The first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. In some examples, the plurality of first light-emitting units and a plurality of second light-emitting units may be spaced apart in both the first and second directions. For example, in the first direction, one first light-emitting unit and one second light-emitting unit are spaced apart; in the second direction, one first light-emitting unit and one second light-emitting unit are spaced apart. In other examples, the plurality of first light-emitting units and a plurality of second light-emitting units may be spaced apart only along the first or second direction. This example, by spaced apart the first and second light-emitting units, allows for a reasonable layout of the external light-emitting elements and the internal light-emitting elements of the pixel circuit, achieving an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Moreover, by spaced apart the first and second light-emitting units, brightness compensation between the first and second light-emitting elements is facilitated, thereby improving the brightness uniformity of the first display area.

[0101] In some exemplary embodiments, the ratio of the luminous area of ​​the second light-emitting element to that of the first light-emitting element, which emits light of the same color, can be less than 1. In some examples, the ratio of the luminous area of ​​the second light-emitting element to that of the first light-emitting element, which emits light of the same color, can be 0.4 to 0.8, for example, about 0.5. This example improves the dimness caused by the external pixel circuitry of the second light-emitting element by reducing its luminous area.

[0102] In some exemplary embodiments, the number of first light-emitting elements included in at least one first light-emitting unit may be the same as the number of second light-emitting elements included in at least one second light-emitting unit. In some examples, at least one first light-emitting unit may include the following four first light-emitting elements: one first light-emitting element emitting a first color light, one first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light. At least one second light-emitting unit may include the following four second light-emitting elements: one second light-emitting element emitting a first color light, one second light-emitting element emitting a second color light, and two second light-emitting elements emitting a third color light. However, this embodiment is not limited to this. For example, the first light-emitting unit and the second light-emitting unit may each include three light-emitting elements. Setting the number of light-emitting elements included in the first light-emitting unit and the second light-emitting unit to be the same in this example can facilitate brightness compensation between adjacent light-emitting elements emitting the same color light, which helps to improve the brightness uniformity of the first display area.

[0103] In some exemplary embodiments, the ratio of the number of first light-emitting units and the number of second light-emitting units in the first display area can be from 0.8 to 1.2, for example, it can be about 1. The ratio of the number of first light-emitting units and the number of second light-emitting units in this example can effectively reduce the number of conductive connection lines and wiring space connected to the external pixel circuit, and can support the increase in the size of the first display area.

[0104] In some exemplary embodiments, the light transmittance of the first display area may be greater than that of the second display area. The display substrate may further include: a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area. At least one third pixel circuit is electrically connected to at least one third light-emitting element and configured to drive the at least one third light-emitting element to emit light. The plurality of second pixel circuits may be spaced apart between the plurality of third pixel circuits. This example ensures the display effect of the display substrate by setting a second display area with a light transmittance lower than that of the first display area.

[0105] In some examples, the sum of the number of first and second light-emitting elements per unit area may be less than or equal to the number of third light-emitting elements per unit area. Alternatively, the density of first and second light-emitting elements in the first display area may be less than or equal to the density of third light-emitting elements in the second display area. Alternatively, the pixel density (PPI, Pixels Per Inch) of the first display area may be less than or equal to the pixel density of the second display area.

[0106] The following examples illustrate the solution of this embodiment.

[0107] Figure 1This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may include a display area AA and a peripheral area BB located around the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited in this respect.

[0108] In some examples, such as Figure 1 As shown, the first display area A1 can be a light-transmitting display area, or it can also be called the under-display camera (FDC) area. The second display area A2 can be called the normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the first display area A1 can be circular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0109] In some examples, such as Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited in this respect. For example, the first display area A1 can be located at other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0110] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0111] In some examples, the display area AA can be configured with multiple sub-pixels. At least one sub-pixel can include pixel circuitry and a light-emitting element. The pixel circuitry can be configured to drive the connected light-emitting element. For example, the pixel circuitry can be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuitry can include multiple transistors and at least one capacitor. For example, the pixel circuitry can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, in the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0112] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the emitted light can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0113] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described using an 8T1C structure. In some examples, such as... Figure 2 As shown, the pixel circuit in this example may include eight transistors (i.e., first transistor T1 to eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be called the first reset transistor, the second transistor T2 may also be called the threshold compensation transistor, the third transistor T3 may also be called the driving transistor, the fourth transistor T4 may also be called the data writing transistor, the fifth transistor T5 may also be called the first light-emitting control transistor, the sixth transistor T6 may also be called the second light-emitting control transistor, the seventh transistor T7 may also be called the second reset transistor, and the eighth transistor T8 may also be called the third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0114] In some examples, the first transistor T1, the third transistor T3 through the eighth transistor T8 can be first-type transistors, such as P-type transistors, and the second transistor T2 can be a second-type transistor, such as an N-type transistor. However, this embodiment is not limited to this. For example, the multiple transistors in the pixel circuit can all be P-type transistors, or they can all be N-type transistors.

[0115] In some examples, the first type of transistors in the pixel circuit (e.g., including the first transistor T1, the third transistor T3 through the eighth transistor T8) can be low-temperature polycrystalline silicon (LTPS) thin-film transistors, and the second type of transistors in the pixel circuit (e.g., including the second transistor T2) can be oxide (O2) thin-film transistors. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the O2 thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while O2 thin-film transistors have advantages such as low leakage current. Integrating LTPS and O2 thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0116] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1, and the second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, where the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0117] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0118] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0119] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit is shown below. Figure 3 right Figure 2 The operation of the pixel circuit shown is explained. The first transistor T1, the third transistor T3 through the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0120] In some examples, such as Figure 2 and Figure 3 As shown, during a single frame display period, the operation of the pixel circuit can include at least the following stages: first stage S1, second stage S2, third stage S3, and fourth stage S4.

[0121] The first stage, S1, is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is low, turning on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is high, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be provided to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is high, the first reset control signal RESET1 provided by the first reset control line RST1 is high, and the light emission control signal EM provided by the light emission control line EML is high, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0122] The second stage, S2, is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is low, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is high, turning on the second transistor T2. The turning on of the first transistor T1 and the second transistor T2 allows the first initial signal line INIT1 to be provided to the first node N1, initializing N1. The second reset control signal RESET2 provided by the second reset control line RST2 is high, the first scan signal SCAN1 provided by the first scan line GL1 is high, and the light emission control signal EM provided by the light emission control line EML is high, causing the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to turn off. During this stage, the light-emitting element EL does not emit light.

[0123] The third stage, S3, is called the data writing stage or threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The turn-on of the second transistor T2, the fourth transistor T4, and the third transistor T3 allows the data voltage Vdata output from the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, which disconnects the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6.

[0124] In the fourth stage (S4), the light-emitting control signal EM provided by the light-emitting control line EML can switch from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are all high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power supply line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the conducting fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0125] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0126] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth]2 =K×[VDD-Vdata] 2 ;

[0127] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0128] As can be seen from the above formula, the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided in this embodiment can improve display defects caused by low frequencies and enhance the display effect of the light-emitting element.

[0129] In some examples, such as Figure 1 As shown, the first display area A1 of the display substrate may be provided with a plurality of first light-emitting elements 21, a plurality of second light-emitting elements 22, and a plurality of first pixel circuits 11. At least one first pixel circuit 11 is electrically connected to at least one first light-emitting element 21 and configured to drive at least one first light-emitting element 21 to emit light. The second display area A2 may be provided with a plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light-emitting elements 23. In this example, the circuit structures of the first pixel circuits 11, second pixel circuits 12, and third pixel circuits 13 may be identical, for example, the 8T1C structure described above. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 22 through at least one conductive connection line 15 and configured to drive at least one second light-emitting element 22 to emit light. The conductive connection line 15 may extend from the first display area A1 to the second display area A2. At least one third pixel circuit 13 is electrically connected to at least one third light-emitting element 23 and configured to drive at least one third light-emitting element 23 to emit light.

[0130] For example, multiple first pixel circuits 11 and multiple first light-emitting elements 21 are electrically connected in a one-to-one correspondence, and one first pixel circuit 11 can be configured to drive one first light-emitting element 21. The orthographic projection of the first light-emitting element 21 on the substrate at least partially overlaps with the orthographic projection of the connected first pixel circuit 11 on the substrate. Multiple second pixel circuits 12 and multiple second light-emitting elements 22 are electrically connected in a one-to-one correspondence, and one second pixel circuit 12 can be configured to drive one second light-emitting element 22. The orthographic projection of the second light-emitting element 22 on the substrate may not overlap with the orthographic projection of the connected second pixel circuit 12 on the substrate. Multiple third pixel circuits 13 and multiple third light-emitting elements 23 are electrically connected in a one-to-one correspondence, and one third pixel circuit 13 can be configured to drive one third light-emitting element 23. The orthographic projection of the third light-emitting element 23 on the substrate at least partially overlaps with the orthographic projection of the connected third pixel circuit 13 on the substrate. However, this embodiment is not limited in this respect. In other examples, multiple first pixel circuits can be configured to drive one first light-emitting element; or, one first pixel circuit can be configured to drive multiple first light-emitting elements. For example, multiple second pixel circuits can be configured to drive one second light-emitting element; or, one second pixel circuit can be configured to drive multiple second light-emitting elements. Similarly, multiple third pixel circuits can be configured to drive one third light-emitting element; or, one third pixel circuit can be configured to drive multiple third light-emitting elements.

[0131] Figure 4A and Figure 4B This is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 4A As shown, the first display area may include a plurality of first sub-regions A11 and a plurality of second sub-regions A12. At least one first sub-region A11 is adjacent to at least one second sub-region A12. For example, the first sub-region A11 is adjacent to two second sub-regions A12 in the first direction X and is located in the middle of these two second sub-regions A12; the first sub-region A11 is also adjacent to two second sub-regions A12 in the second direction Y and is located in the middle of these two second sub-regions A12. The first direction X intersects the second direction Y; for example, the first direction X may be perpendicular to the second direction Y.

[0132] In some examples, such as Figure 4AAs shown, a first sub-region A11 can be provided with a first light-emitting unit 2a, and a second sub-region A12 can be provided with a second light-emitting unit 2b. Multiple first light-emitting units 2a and multiple second light-emitting units 2b in the first display area can be arrayed into multiple rows and columns. A row of light-emitting units can include multiple first light-emitting units 2a and multiple second light-emitting units 2b spaced apart along a first direction X, and a column of light-emitting units can include multiple first light-emitting units 2a and multiple second light-emitting units 2b spaced apart along a second direction Y. In the first direction X, the first light-emitting units 2a and second light-emitting units 2b are spaced apart; in the second direction Y, the first light-emitting units 2a and second light-emitting units 2b are spaced apart. For example, one first light-emitting unit 2a can be adjacent to four second light-emitting units 2b. In this example, "A and B are adjacent" means that A and B are close to each other, and there are no other objects of the same type between A and B. This example demonstrates how setting the first light-emitting unit and the second light-emitting unit to be spaced apart in both the first and second directions can not only ensure the light transmittance of the first display area, but also facilitate the realization of a larger first display area, and improve the brightness uniformity of the first display area through brightness compensation.

[0133] In some examples, such as Figure 4A and Figure 4B As shown, in the first direction X, adjacent first light-emitting units 2a and second light-emitting units 2b are aligned, and in the second direction Y, adjacent first light-emitting units 2a and second light-emitting units 2b are aligned. In this example, "aligned in direction C" means that the line connecting the center positions of A and B in direction C is approximately parallel to direction C.

[0134] In some examples, such as Figure 4A As shown, the first light-emitting unit 2a may include at least one first light-emitting element, such as four first light-emitting elements; the second light-emitting unit 2b may include at least one second light-emitting element, such as four second light-emitting elements. The number of first light-emitting elements included in the first light-emitting unit 2a and the number of second light-emitting elements included in the second light-emitting unit 2b may be the same. However, this embodiment is not limited to this. In other examples, the number of first light-emitting elements included in the first light-emitting unit may be greater than the number of second light-emitting elements included in the second light-emitting unit, or the number of first light-emitting elements included in the first light-emitting unit may be less than the number of second light-emitting elements included in the second light-emitting unit. By setting the number of first light-emitting elements included in the first light-emitting unit and the number of second light-emitting elements included in the second light-emitting unit to be the same, this example facilitates the control of the ratio of the first light-emitting elements to the second light-emitting elements, thereby facilitating the design of brightness compensation between the first light-emitting elements and the second light-emitting elements.

[0135] In some examples, such as Figure 4A and Figure 4B As shown, the multiple light-emitting elements (including multiple first light-emitting elements and multiple second light-emitting elements) in the first display area can be arranged in multiple rows and columns. A row of light-emitting elements can include multiple first light-emitting elements and multiple second light-emitting elements arranged along a first direction X, and a column of light-emitting elements can include multiple first light-emitting elements and multiple second light-emitting elements arranged along a second direction Y. A column of light-emitting units can include four columns of light-emitting elements, and a row of light-emitting units can include two rows of light-emitting elements. For example, the a-th column of light-emitting units can include the light-emitting elements in the d-th, d+1-th, d+2-th, and d+3-th columns, and the b-th row of light-emitting units can include the light-emitting elements in the c-th and c+1-th rows, where a, b, c, and d are all integers greater than 0.

[0136] In some examples, such as Figure 4A and Figure 4B As shown, a first light-emitting unit 2a may include the following four first light-emitting elements: a first light-emitting element 21a emitting a first color light, a first light-emitting element 21b emitting a second color light, and two first light-emitting elements 21c and 21d emitting a third color light. The four first light-emitting elements of the first light-emitting unit 2a may be arranged in two rows of light-emitting elements. The first light-emitting element 21a emitting the first color light and the first light-emitting element 21b emitting the second color light may be arranged in the same row of light-emitting elements, and the two first light-emitting elements 21c and 21d emitting the third color light may be arranged in the same row of light-emitting elements. The four first light-emitting elements may be arranged in different columns of light-emitting elements.

[0137] In some examples, such as Figure 4A and Figure 4B As shown, a second light-emitting unit 2b may include the following four second light-emitting elements: a second light-emitting element 22a emitting a first color light, a second light-emitting element 22b emitting a second color light, and two second light-emitting elements 22c and 22d emitting a third color light. The four second light-emitting elements in a second light-emitting unit 2b can be arranged in two rows of light-emitting elements. The second light-emitting elements 22a and 22b emitting the first color light can be arranged in the same row, and the two second light-emitting elements 22c and 22d emitting the third color light can be arranged in the same row. The four second light-emitting elements can be arranged in different columns of light-emitting elements. The arrangement of the four second light-emitting elements in the second light-emitting unit of this example is roughly the same as the arrangement of the four first light-emitting elements in the first light-emitting unit. The arrangement of the light-emitting elements in this example can facilitate the design of brightness compensation between the first and second light-emitting elements.

[0138] In some examples, such as Figure 4BAs shown, in the c-th row of light-emitting elements, two second light-emitting elements 22c and 22d that emit third-color light and two first light-emitting elements 21c and 21d that emit third-color light can be arranged periodically along the first direction X; in the c+1-th row of light-emitting elements, a second light-emitting element 22a that emits first-color light, a second light-emitting element 22b that emits second-color light, a first light-emitting element 21a that emits first-color light and a first light-emitting element 21b that emits second-color light can be arranged periodically along the first direction X. In the d-th column of light-emitting elements, the second light-emitting element 22a emitting a first color light and the first light-emitting element 21b emitting a second color light can be spaced apart along the second direction X; in the d+1-th column of light-emitting elements, the second light-emitting element 22c (or 22d) emitting a second color light and the first light-emitting element 21c (or 21d) emitting a third color light can be spaced apart along the second direction Y; in the d+2-th column of light-emitting elements, the second light-emitting element 22b emitting a second color light and the first light-emitting element 21a emitting a first color light can be spaced apart along the second direction Y; in the d+3-th column of light-emitting elements, the second light-emitting element 22d emitting a second color light and the first light-emitting element 21d emitting a third color light can be spaced apart along the second direction Y.

[0139] In some examples, such as Figure 4A As shown, in different first light-emitting units located in adjacent rows of light-emitting units, the first light-emitting element 21a emitting a first color light and the first light-emitting element 21b emitting a second color light are arranged in reverse order. For example, in the first light-emitting unit located in row b, the first light-emitting element 21a emitting a first color light and the first light-emitting element 21b emitting a second color light can be arranged sequentially along the first direction X. In the first light-emitting unit located in row b+1, the first light-emitting element 21b emitting a second color light and the first light-emitting element 21a emitting a first color light can be arranged sequentially along the first direction X.

[0140] In some examples, such as Figure 4A As shown, in different first light-emitting units located in adjacent light-emitting unit columns, the arrangement order of the first light-emitting element 21a emitting first-color light and the first light-emitting element 21b emitting second-color light is reversed. For example, in the first light-emitting unit located in column a, the first light-emitting element 21b emitting second-color light and the first light-emitting element 21a emitting first-color light can be arranged sequentially along the first direction X. In the first light-emitting unit located in column (a+1), the first light-emitting element 21a emitting first-color light and the first light-emitting element 21b emitting second-color light can be arranged sequentially along the first direction X.

[0141] In some examples, such as Figure 4AAs shown, in different second light-emitting units located in adjacent rows of light-emitting units, the second light-emitting element 22a emitting the first color light and the second light-emitting element 22b emitting the second color light are arranged in opposite order; in different second light-emitting units located in adjacent columns of light-emitting units, the second light-emitting element 22a emitting the first color light and the second light-emitting element 22b emitting the second color light are arranged in opposite order. The arrangement of the second light-emitting elements within a second light-emitting unit is similar to the arrangement of the first light-emitting elements within a first light-emitting unit, and therefore will not be described further here.

[0142] In some examples, the first color light can be red light (R), the second color light can be blue light (B), and the third color light can be green light (G). However, this embodiment is not limited to this.

[0143] In some examples, the first light-emitting element of the first light-emitting unit 2a in the first display area can be configured to provide brightness compensation for the second light-emitting element emitting the same color light in the adjacent second light-emitting unit 2b. For example, the first light-emitting element 21b emitting blue light in the first light-emitting unit 2a in column a, row b+1 and row a, can provide brightness compensation for the second light-emitting element 22b emitting blue light in the second light-emitting unit 2b in column a, row b+2. Similarly, the first light-emitting element 21a emitting red light in the first light-emitting unit 2a in column a, row b+1 and row a, row b+3 can provide brightness compensation for the second light-emitting element 22a emitting red light in the second light-emitting unit 2b in column a, row b+2. The first light-emitting element 21c, the first light-emitting element 21d, and the first light-emitting element 21c emitting green light from the first light-emitting unit 2a in column a+1, row b, and the first light-emitting element 21c emitting green light from the first light-emitting unit 2a in column a+1, row b+1, can compensate for the brightness of the second light-emitting element 22c emitting green light from the second light-emitting unit 2b in column a+1, row b+1. This example uses the first light-emitting elements in the first light-emitting unit to compensate for the brightness of the second light-emitting elements emitting the same color light in adjacent second light-emitting units, effectively improving the situation where the brightness of the second light-emitting elements is too dim.

[0144] Figure 5 This is a schematic diagram illustrating the connection relationship between the light-emitting element and the pixel circuitry in at least one embodiment of this disclosure. In some examples, such as... Figure 5As shown, the first display area A1 may include: multiple first pixel circuits (e.g., first pixel circuits 11a, 11b, 11c, and 11d), multiple first light-emitting elements, and multiple second light-emitting elements. The second display area A2 may include multiple second pixel circuits 12, multiple third pixel circuits 13, and multiple third light-emitting elements (not shown). The first pixel circuits and first light-emitting elements may be located in the first sub-region A11, and the second light-emitting elements may be located in the second sub-region A12. The light transmittance of the second sub-region A12 may be greater than that of the first sub-region A11. For example, the first sub-region A11 may be a non-transparent area, and the second sub-region A12 may include both non-transparent and transparent areas. The positions of the anodes and traces of the second light-emitting elements within the second sub-region A12 may be non-transparent areas, and the areas between the anodes of adjacent second light-emitting elements where no metal traces are provided may be transparent areas.

[0145] In some examples, such as Figure 5 As shown, the four first pixel circuits in each first sub-region A11 can be arranged sequentially along the first direction X. For example, the first pixel circuits 11a, 11b, 11c, and 11d can be arranged sequentially along the first direction X. The four first light-emitting elements of the first light-emitting unit can be electrically connected to the four first pixel circuits in a one-to-one correspondence. For example, a first light-emitting element emitting a first color light (e.g., a red first light-emitting element) can be electrically connected to the first pixel circuit 11a, a first light-emitting element emitting a third color light (e.g., a green first light-emitting element) can be electrically connected to the first pixel circuit 11b, a first light-emitting element emitting a second color light (e.g., a blue first light-emitting element) can be electrically connected to the first pixel circuit 11c, and another first light-emitting element emitting a third color light (e.g., a green first light-emitting element) can be electrically connected to the first pixel circuit 11d.

[0146] In some examples, such as Figure 5 As shown, the second sub-region A12 does not have pixel circuits. The four second light-emitting elements in the second sub-region A12 can be electrically connected to the second pixel circuit 12 in the second display area A2 through conductive connecting lines 15. In the second sub-region A12, the light-transmitting areas between adjacent second light-emitting elements can be connected to each other to form a continuous light-transmitting area, thereby improving the light transmittance of the first display area.

[0147] In some examples, such as Figure 5 As shown, within the second display area A2, multiple second pixel circuits 12 can be spaced apart between multiple third pixel circuits 13. Within the second display area A2, the area where the second pixel circuits 12 are disposed can be obtained by reducing the size of the third pixel circuits 13 in the first direction X. For example, the size of the third pixel circuit 13 in the first direction X can be smaller than the size of the third light-emitting element in the first direction X.

[0148] In some examples, the original f columns of third pixel circuits can be compressed along the first direction X, thereby adding space for one or two columns of second pixel circuits. The space occupied by the f columns of pixel circuits before compression and the f+1 or f+2 columns of pixel circuits after compression can be the same. Here, f can be an integer greater than 1. In this example, f can be 4, adding space for two columns of second pixel circuits by compressing four columns of third pixel circuits. However, this embodiment is not limited to this.

[0149] In some examples, such as Figure 5 As shown, a second pixel circuit 12 can be disposed in a second display area A2 located on both sides (e.g., left and right sides) of the first display area A1 along the first direction X. In the second display area located on both sides (e.g., top and bottom sides) of the first display area A1 along the second direction Y, a second pixel circuit may not be disposed, or an invalid pixel circuit may be disposed, to maintain the uniformity of components in multiple film layers within the second display area during the etching process. The invalid pixel circuit can have a structure substantially the same as the second pixel circuit in the same row or column, except that it is not electrically connected to any light-emitting element. This embodiment is not limited in this respect.

[0150] In some examples, such as Figure 5 As shown, the second light-emitting element near the center of the first display area A1 can be electrically connected to the second pixel circuit 12 near the first display area A1 in the second display area A2. The second light-emitting element near the edge of the first display area A1 can be electrically connected to the second pixel circuit away from the first display area A1. This embodiment does not limit the connection relationship between the second pixel circuit and the second light-emitting element.

[0151] Figure 6 This is a partial top view of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 The diagram illustrates the first and second light-emitting units in columns a to a+2 and rows b to b+3. In some examples, such as... Figure 6As shown, on a plane parallel to the display substrate, the first display area of ​​the display substrate includes a plurality of first sub-regions and a plurality of second sub-regions arranged at intervals along a first direction X and a second direction Y. A first sub-region may include a first light-emitting unit (including four first light-emitting elements 21a, 21b, 21c, and 21d) and four first pixel circuits. A second sub-region may include a second light-emitting unit (including four second light-emitting elements 22a, 22b, 22c, and 22d). The second sub-region where the second light-emitting unit in column (a+1) and row (b+1) is located may be surrounded by the first sub-region where the first light-emitting unit in column (a+1) and row (b), the first sub-region where the first light-emitting unit in column (a) and row (b+1), the first sub-region where the first light-emitting unit in column (a+2) and row (b+1), and the first sub-region where the first light-emitting unit in column (a+1) and row (b+2). The first sub-region containing the first light-emitting unit in column a+1, row b, the first sub-region containing the first light-emitting unit in column a, row b+1, the first sub-region containing the first light-emitting unit in column a+2, row b+1, and the first sub-region containing the first light-emitting unit in column a+1, row b+2 can be interconnected.

[0152] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer, a conductive connection layer, and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on the side of the circuit structure layer away from the substrate, and the conductive connection layer may be located between the circuit structure layer and the light-emitting structure layer. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include: a plurality of first light-emitting elements and a plurality of second light-emitting elements.

[0153] In some examples, the circuit structure layers may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer; a second insulating layer may be disposed between the first and second conductive layers; a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer; a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer; a fifth insulating layer may be disposed between the third and fourth conductive layers; a sixth and a seventh insulating layer may be disposed between the fourth and fifth conductive layers; an eighth insulating layer may be disposed between the fifth and sixth conductive layers; and a ninth insulating layer may be disposed on the side of the sixth conductive layer away from the substrate. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. This embodiment is not limited in this respect.

[0154] In some examples, the conductive connection layer may include multiple conductive connection lines that can extend from the first display area to the second display area to realize the electrical connection between the second light-emitting element and the second pixel circuit.

[0155] In some examples, the light-emitting structure layer may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer sequentially disposed on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of the corresponding color under the drive of the anode layer and the cathode layer.

[0156] In some examples, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0157] The structure of a display substrate is illustrated below using an example of the fabrication process. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern."

[0158] The phrase "A and B are arranged in the same layer" as used in this disclosure means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is its dimension in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The phrase "the shape of A" as used in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0159] In some examples, the fabrication process of the display substrate may include the following operations. The circuit structure layer is described below using two first pixel circuits within the first sub-region of the first display area as an example. This example uses the aforementioned 8T1C structure as an example for the first pixel circuit. The first first pixel circuit (i.e., first pixel circuit 11a) may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the second first pixel circuit (i.e., first pixel circuit 11b) may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The connection relationship of the eight transistors and the storage capacitor in each first pixel circuit can be referred to... Figure 2 The equivalent circuit diagram is shown.

[0160] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0161] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc.

[0162] Figure 7A for Figure 6 A schematic diagram of the first display area after the first semiconductor layer is formed. Figure 7B for Figure 7A A schematic diagram of the first sub-region in the diagram.

[0163] In some examples, such as Figure 7A and Figure 7B As shown, the first semiconductor layer of the first display area may include at least: an active layer of a plurality of first type transistors of a plurality of first pixel circuits (e.g., including: the first active layer 310a of the first transistor of the first pixel circuit 11a in the first sub-region, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor and the eighth active layer 380a of the eighth transistor, and the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor and the eighth active layer 380b of the eighth transistor).

[0164] In some examples, within the first sub-region, the first semiconductor layer patterns of the four first pixel circuits can be approximately symmetrical about the first center line O1, the first semiconductor layer patterns of first pixel circuits 11a and 11b can be approximately symmetrical about the second center line O2, and the first semiconductor layer patterns of first pixel circuits 11c and 11d can be approximately symmetrical about the third center line O3. The first semiconductor layer patterns within different first sub-regions can be independent of each other.

[0165] In some examples, within the first sub-region, the first, third, fourth, fifth, sixth, and seventh active layers of the four first pixel circuits can be an interconnected integral structure. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b can be interconnected. The fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c can be interconnected. The seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d can be interconnected. The first active layer of each first pixel circuit can be located on one side of the third active layer along the second direction Y, and the eighth active layer can be located on the opposite side of the third active layer along the second direction Y.

[0166] In some examples, the third active layers 330a and 330b may be approximately U-shaped, the fourth active layers 340a and 340b and the fifth active layers 350a and 350b may be approximately I-shaped, and the first active layers 310a and 310b, the sixth active layers 360a and 360b, the seventh active layers 370a and 370b, and the eighth active layers 380a and 380b may be approximately L-shaped. However, this embodiment is not limited to these shapes.

[0167] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The material of the first semiconductor layer may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0168] (2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

[0169] Figure 8A for Figure 6 A schematic diagram of the first display area after the first conductive layer is formed. Figure 8B for Figure 8A A schematic diagram of the first conductive layer in the image. Figure 8C for Figure 8A A schematic diagram of the first sub-region in the diagram.

[0170] In some examples, such as Figures 8A to 8C As shown, the first conductive layer of the first display area may include at least: multiple first scan lines (e.g., first scan lines GL1(i), GL1(i+1), GL1(i+2), GL1(i+3)), multiple light emission control lines (e.g., light emission control lines EML(i), EML(i+1), EML(i+2), EML(i+3)), multiple first reset control lines (e.g., first reset control lines RST1(i), RST1(i+1), RST1(i+2), RST1(i+3)), multiple second reset control lines (e.g., second reset control lines RST2(i), RST2(i+1), RST2(i+2), RST2(i+3)), and first electrodes (e.g., first electrodes 391a, 391b) of the storage capacitors of multiple first pixel circuits.

[0171] In some examples, within the first sub-region, the first scan line GL1(i) may be located on one side of the storage capacitor of the first pixel circuit (e.g., 391a and 391b) in the second direction Y, and the first reset control line RST1(i) may be located on one side of the first scan line GL1(i) in the second direction Y. The light emission control line EML(i) may be located on the opposite side of the storage capacitor of the first pixel circuit (e.g., 391a and 391b), and the second reset control line RST2(i) may be located on the opposite side of the light emission control line EML(i) in the second direction Y.

[0172] In some examples, the first reset control line RST1(i), the first scan line GL1(i), the second reset control line RST2(i), and the emission control line EML(i) can be bent around the second sub-region adjacent to the first sub-region along the first direction X. For example, the first reset control line RST1(i) and the first scan line GL1(i) can be bent around the second sub-region along the second direction Y, and the second reset control line RST2(i) and the emission control line EML(i) can be bent around the second sub-region along the opposite direction of the second direction Y. In this example, by setting the traces of the first conductive layer to bend around the second sub-region, it is beneficial to improve the light transmittance of the second sub-region.

[0173] In some examples, the shape of the first reset control line RST1(i) can be approximately a broken line extending along the first direction X. Within the first sub-region, the overlapping region of the first reset control line RST1(i) and the first active layer of the four first pixel circuits can serve as the gate of the first transistor of the four first pixel circuits (e.g., including the gate of the first transistor 31a and the gate of the first transistor 31b).

[0174] In some examples, the shape of the first scan line GL1(i) can be approximately a broken line extending along the first direction X. Within the first sub-region, the overlapping region of the first scan line GL1(i) and the fourth active layer of the four first pixel circuits can serve as the gate of the fourth transistor of the four first pixel circuits (e.g., including the gate of the fourth transistor 34a and the gate of the fourth transistor 34b).

[0175] In some examples, the shape of the light emission control line EML(i) can be approximately a broken line extending along the first direction X. Within the first sub-region, the overlapping region of the light emission control line EML(i) with the fifth active layer of the four first pixel circuits can serve as the gate of the fifth transistor of the four first pixel circuits (e.g., including the gates of the fifth transistors 35a and 35b), and the overlapping region of the light emission control line EML(i) with the sixth active layer of the four first pixel circuits can serve as the gate of the sixth transistor of the four first pixel circuits (e.g., including the gates of the sixth transistors 36a and 36b).

[0176] In some examples, the shape of the second reset control line RST2(i) can be approximately a broken line extending along the first direction X. Within the first sub-region, the overlapping region of the second reset control line RST2(i) with the seventh active layer of the four first pixel circuits can serve as the gate of the seventh transistor of the four first pixel circuits (e.g., including the gates of the seventh transistors 37a and 37b), and the overlapping region of the second reset control line RST2(i) with the eighth active layer of the four first pixel circuits can serve as the gate of the eighth transistor of the four first pixel circuits (e.g., including the gates of the eighth transistors 38a and 38b).

[0177] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can simultaneously serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can simultaneously serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b onto the substrate can be approximately rectangular. This embodiment is not limited in this respect.

[0178] (3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned using a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

[0179] Figure 9A for Figure 6 A schematic diagram of the first display area after the second conductive layer is formed. Figure 9B for Figure 9A A schematic diagram of the second conductive layer in the image. Figure 9Cfor Figure 9A A schematic diagram of the first sub-region in the diagram.

[0180] In some examples, such as Figures 9A to 9C As shown, the second conductive layer of the first display area may include at least: multiple second scan auxiliary lines (e.g., second scan auxiliary lines GL2b(i), GL2b(i+1), GL2b(i+2), GL2b(i+3)) and the second electrodes of the storage capacitors of multiple first pixel circuits (e.g., second electrodes 392a, 392b).

[0181] In some examples, the shape of the second scan auxiliary line GL2b(i) can be approximately a broken line extending along the first direction X. Within the first sub-region, the second scan auxiliary line GL2b(i) can be located on one side of the second direction Y of the storage capacitor of the first pixel circuit (e.g., 392a and 392b). The second scan auxiliary line GL2b(i) can bypass the second sub-region from the side of the second direction Y and be located on the side of the first scan line GL1(i) opposite to the second direction Y.

[0182] In some examples, within the first sub-region, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit onto the substrate can be approximately a rectangular structure with a cutout area. This cutout area can be approximately rectangular, and the rectangle can have rounded or chamfered corners. The second electrodes 392a and 392b of the storage capacitors of the first pixel circuit 11a and 11b can be electrically connected via a first electrode plate connecting block 392-1. The second electrodes 392b and 392b of the storage capacitors of the first pixel circuit 11b and 11c can be electrically connected via a second electrode plate connecting block 392-2. The second electrodes of the storage capacitors of the first pixel circuit 11c and 11d can be electrically connected via another first electrode plate connecting block 392-1. The side of the second electrodes of the storage capacitors of the first pixel circuits 11a and 11d furthest from the remaining first pixel circuits can be electrically connected to a second electrode plate connecting block 392-2. The length L1 of the first electrode connecting block 392-1 along the second direction Y can be less than the length L2 of the second electrode connecting block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line via the second electrode connecting block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first sub-region can be an interconnected integral structure, which helps to ensure the uniform transmission of the first voltage signal along the first direction X.

[0183] (4) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0184] Figure 10A for Figure 6 A schematic diagram of the first display area after the second semiconductor layer is formed. Figure 10B for Figure 10A A schematic diagram of the second semiconductor layer. Figure 10C for Figure 10A A schematic diagram of the first sub-region in the diagram.

[0185] In some examples, such as Figures 10A to 10C As shown, the second semiconductor layer of the first display area may include at least: an active layer of second type transistors of a plurality of first pixel circuits (e.g., including: a second active layer 320a of the second transistor 32a of the first pixel circuit 11a in the first sub-region, and a second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0186] In some examples, within the first sub-region, the second semiconductor layer patterns of the four first pixel circuits can be approximately symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11a and 11b can be approximately symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d can be approximately symmetrical about the third center line O3.

[0187] In some examples, the shapes of the second active layers 320a and 320b can be approximately L-shaped. The overlapping area of ​​the second scan auxiliary line GL2b(i) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping area of ​​the second scan auxiliary line GL2b(i) and the second active layer 320b can serve as the bottom gate of the second transistor 32b.

[0188] (5) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is then patterned using a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer.

[0189] Figure 11A for Figure 6 A schematic diagram of the first display area after the third conductive layer is formed. Figure 11B for Figure 11A A schematic diagram of the third conductive layer in the image. Figure 11C for Figure 11A A schematic diagram of the first sub-region in the diagram.

[0190] In some examples, such as Figures 11A to 11C As shown, the third conductive layer of the first display area may include at least: multiple second scan lines (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), GL2(i+3)), multiple first initial signal lines (e.g., first initial signal lines INIT1(i), INIT1(i+1), INIT1(i+2), INIT1(i+3)), multiple second initial signal lines (e.g., second initial signal lines INIT2(i), INIT2(i+1), INIT2(i+2), INIT2(i+3)), and multiple third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), INIT3(i+3)). The shapes of the first initial signal lines, second scan lines, second initial signal lines, and third initial signal lines may each be approximately a broken line extending along the first direction X.

[0191] In some examples, within the first sub-region, the first initial signal line INIT1(i) and the second scan line GL2(i) can be located on one side of the storage capacitor along the second direction Y, and the second initial signal line INIT2(i) and the third initial signal line INIT3(i) can be located on the opposite side of the storage capacitor along the second direction Y. The first initial signal line INIT1(i) can be located on one side of the second scan line GL2(i) along the second direction Y. The second initial signal line INIT2(i) can be located on the opposite side of the third initial signal line INIT3(i) along the second direction Y.

[0192] In some examples, the first initial signal line INIT1(i), the second scan line GL2(i), the second initial signal line INIT2(i), and the third initial signal line INIT3(i) can be bent around the second sub-region adjacent to the first sub-region along the first direction X. For example, the first initial signal line INIT1(i) and the second scan line GL2(i) can be bent around the second sub-region along the second direction Y, and the second initial signal line INIT2(i) and the third initial signal line INIT3(i) can be bent around the second sub-region along the opposite direction of the second direction Y. In this example, by setting the traces of the third conductive layer to bend around the second sub-region, it is beneficial to improve the light transmittance of the second sub-region.

[0193] In some examples, the orthographic projection of the first initial signal line INIT1(i) onto the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i) onto the substrate; the orthographic projection of the second scan line GL2(i) onto the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) onto the substrate; the orthographic projection of the third initial signal line INIT3(i) onto the substrate may at least partially overlap with the orthographic projection of the light emission control line EML(i) onto the substrate; and the orthographic projection of the second initial signal line INIT2(i) onto the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i) onto the substrate. This example, by using a stacked design for the traces of different conductive layers, avoids occupying excessive trace space, which helps save wiring space and thus improves the light transmittance of the first display area.

[0194] (6) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer.

[0195] Figure 12 for Figure 6 A schematic diagram of a first sub-region after the formation of the fifth insulating layer. In some examples, such as... Figure 12 As shown, the fifth insulating layer of the first display area may have multiple vias, such as the first via V1 to the nineteenth via V19, the twenty-first via V21 to the twenty-second via V22, the twenty-third via V23 to the twenty-fourth via V24, the twenty-fifth via V25 to the twenty-ninth via V29, and the thirty-first via V31 to the thirty-fourth via V34.

[0196] In some examples, the fifth, fourth, third, second, and first insulating layers within the first via V1 to the nineteenth via V19 can be removed, exposing a portion of the surface of the first semiconductor layer. The fifth, fourth, third, and second insulating layers within the twenty-first via V21 and the twenty-second via V22 can be removed, exposing a portion of the surface of the first conductive layer. The fifth, fourth, and third insulating layers within the twenty-third via V23 and the twenty-fourth via V24 can be removed, exposing a portion of the surface of the second conductive layer. The fifth insulating layer within the twenty-fifth via V25 to the twenty-ninth via V29 can be removed, exposing a portion of the surface of the third conductive layer. The fifth and fourth insulating layers within the thirty-first via V31 to the thirty-fourth via V34 can be removed, exposing the surface of the second semiconductor layer.

[0197] (7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0198] Figure 13A for Figure 6 A schematic diagram of the first display area after the fourth conductive layer is formed. Figure 13B for Figure 13A A schematic diagram of the fourth conductive layer in the image. Figure 13C for Figure 13A A schematic diagram of the first sub-region in the diagram.

[0199] In some examples, such as Figures 13A to 13C As shown, the fourth conductive layer of the first display area may include at least a plurality of connecting electrodes (e.g., the first connecting electrode 401 to the ninth connecting electrode 409, and the eleventh connecting electrode 411 to the seventeenth connecting electrode 417).

[0200] In some examples, the first connection electrode 401 may be approximately rectangular in shape. The first connection electrode 401 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a via the third via V3.

[0201] In some examples, the second connection electrode 402 can be approximately strip-shaped, extending along the second direction Y. One end of the second connection electrode 402 can be electrically connected to the second active layer of the second transistor 32a of the first pixel circuit 11a through the thirty-first via V31, and the other end can be electrically connected to the first electrode 391a of the storage capacitor through the twenty-first via V21. The second connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a. The second connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0202] In some examples, the third connection electrode 403 may be generally strip-shaped, extending along the second direction Y. One end of the third connection electrode 403 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the second via V2, and the other end may be electrically connected to the second active layer of the second transistor 32a through the thirty-second via V32, and may also be electrically connected to the third active layer of the third transistor 33a through the sixth via V6.

[0203] In some examples, the fourth connection electrode 404 may be approximately shaped as a broken line extending along the second direction Y. The fourth connection electrode 404 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a via the fourth via V4, and may also be electrically connected to the eighth active layer of the eighth transistor 38a via the eighth via V8.

[0204] In some examples, the fifth connecting electrode 405 can be approximately strip-shaped, extending along the second direction Y. The fifth connecting electrode 405 can be electrically connected to the fifth active layer of the fifth transistor 35a of the first pixel circuit 11a through the fifth via V5, and can also be electrically connected to the second electrode connecting block 392-2 through the twenty-third via V23, thereby achieving electrical connection with the second electrode 392a of the storage capacitor.

[0205] In some examples, the sixth connection electrode 406 may be approximately rectangular in shape. The sixth connection electrode 406 may be electrically connected to the sixth active layer of the sixth transistor 36a of the first pixel circuit 11a via the seventh via V7.

[0206] In some examples, the seventh connection electrode 407 can be approximately L-shaped. The seventh connection electrode 407 can be electrically connected to the eighth active layer of the eighth transistor 38a of the first pixel circuit 11a through the ninth via V9, and can also be electrically connected to the third initial signal line INIT3(i) through the twenty-sixth via V26.

[0207] In some examples, the shape of the eighth connection electrode 408 may be approximately a strip extending along the second direction Y. The eighth connection electrode 408 can be electrically connected to the seventh active layer of the seventh transistor 37a of the first pixel circuit 11a through the tenth via V10, and can also be electrically connected to the second initial signal line INIT2(i) through the twenty-seventh via V27.

[0208] In some examples, the ninth connection electrode 409 may be approximately arched in shape extending along the second direction Y. One end of the ninth connection electrode 409 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the first via V1, and also electrically connected to the first initial signal line INIT1(i) through the twenty-fifth via V25. The other end may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b through the eleventh via V11, and also electrically connected to the first initial signal line INIT1(i) through the twenty-eighth via V28.

[0209] In some examples, the eleventh connection electrode 411 may be approximately rectangular in shape. The eleventh connection electrode 411 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b via the thirteenth via V13.

[0210] In some examples, the twelfth connecting electrode 412 can be approximately strip-shaped, extending along the second direction Y. One end of the twelfth connecting electrode 412 can be electrically connected to the second active layer of the second transistor 32b of the first pixel circuit 11b through the thirty-third via V31, and the other end can be electrically connected to the first electrode 391b of the storage capacitor through the twenty-second via V22. The twelfth connecting electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b. The twelfth connecting electrode 412 can serve as the first node of the first pixel circuit 11b.

[0211] In some examples, the thirteenth connecting electrode 413 may be approximately strip-shaped, extending along the second direction Y. One end of the thirteenth connecting electrode 413 may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b via the twelfth via V12, and the other end may be electrically connected to the second active layer of the second transistor 32b via the thirty-fourth via V34, and may also be electrically connected to the third active layer of the third transistor 33b via the sixteenth via V16.

[0212] In some examples, the fourteenth connection electrode 414 may be approximately zigzag-shaped, extending along the second direction Y. The fourteenth connection electrode 414 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b via the fourteenth via V14, and may also be electrically connected to the eighth active layer of the eighth transistor 38b via the eighteenth via V18.

[0213] In some examples, the fifteenth connecting electrode 415 can be approximately strip-shaped, extending along the second direction Y. The fifteenth connecting electrode 415 can be electrically connected to the fifth active layer of the fifth transistor 35b of the first pixel circuit 11b through the fifteenth via V15, and can also be electrically connected to another second electrode connecting block 392-2 through the twenty-fourth via V24, thereby achieving electrical connection with the second electrode 392b of the storage capacitor.

[0214] In some examples, the sixteenth connection electrode 416 may be approximately rectangular in shape. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer of the sixth transistor 36b of the first pixel circuit 11b via the seventeenth via V17.

[0215] In some examples, the seventeenth connection electrode 417 can be approximately L-shaped. The seventeenth connection electrode 417 can be electrically connected to the eighth active layer of the eighth transistor 38b of the first pixel circuit 11b through the nineteenth via V19, and can also be electrically connected to the third initial signal line INIT3(i) through the twenty-ninth via V29.

[0216] In some examples, within the first sub-region, the first pixel circuits 11a and 11b can be approximately symmetrical about the second center line O2, the first pixel circuits 11c and 11d can be approximately symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, and the first pixel circuits 11c and 11d can be approximately symmetrical about the first center line O1.

[0217] In some examples, the first pixel circuits in multiple first sub-regions arranged along the first direction X can be aligned in the first direction X, and the first pixel circuits in multiple first sub-regions arranged along the second direction Y can be aligned in the second direction Y. For example, four columns of first pixel circuits can be arranged in one column of first sub-regions.

[0218] (8) Forming the sixth and seventh insulating layers. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, followed by coating with a seventh insulating film. The seventh and sixth insulating films are then patterned using a patterning process to form the sixth and seventh insulating layers. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0219] Figure 14 for Figure 6 A schematic diagram of a first sub-region after the formation of the seventh insulating layer. In some examples, such as... Figure 14 As shown, the seventh insulating layer of the first display area may have multiple vias, such as vias V41 to V46. The seventh and sixth insulating layers within vias V41 to V46 may be removed, exposing a portion of the surface of the fourth conductive layer.

[0220] (9) Forming the fifth conductive layer. In some examples, a fifth conductive thin film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive thin film is patterned by a patterning process to form the fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as the second source / drain metal layer.

[0221] Figure 15A for Figure 6 A schematic diagram of the first display area after the fifth conductive layer is formed. Figure 15B for Figure 15A A schematic diagram of the fifth conductive layer. Figure 15C for Figure 15A A schematic diagram of the first sub-region in the diagram.

[0222] In some examples, such as Figures 15A to 15CAs shown, the fifth conductive layer of the first display area may include at least: multiple data lines (e.g., data lines DL(j-4), DL(j-3), DL(j-2), DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), multiple first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c and 422d), multiple first power connection electrodes (e.g., first power connection electrodes 423a, 423b and 423c), and multiple first shielding electrodes (e.g., first shielding electrodes 421a and 421b).

[0223] In some examples, the multiple data lines can be roughly zigzag-shaped extending along the second direction Y. Four first sub-pixels within each first sub-region are electrically connected to four data lines in a one-to-one correspondence. Data line DL(j) can be electrically connected to the first connection electrode 401 through the forty-first via V41, thereby connecting to the fourth transistor of the first pixel circuit 11a. Data line DL(j+1) can be electrically connected to the eleventh connection electrode 411 through the forty-fifth via V45, thereby connecting to the fourth transistor of the first pixel circuit 11b. Data line DL(j+2) can be electrically connected to the fourth transistor of the first pixel circuit 11c. Data line DL(j+3) can be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0224] In some examples, the four data lines electrically connected to the four first pixel circuits within the first sub-region can be divided into two groups to bypass the second sub-region adjacent to the first sub-region in the second direction Y. For example, data lines DL(j) connected to first pixel circuit 11a and DL(j+1) connected to first pixel circuit 11b can bypass the adjacent second sub-region in the second direction Y from the opposite side of the first direction X, and data lines DL(j+2) connected to first pixel circuit 11c and DL(j+2) connected to first pixel circuit 11d can bypass the adjacent second sub-region in the second direction Y from the side of the first direction X. This example, by setting the data lines to bend and bypass the second sub-region, helps to reduce the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0225] In some examples, the first anode connection electrodes 422a, 422b, 422c, and 422d may be approximately rectangular in shape. The first anode connection electrodes 422a and 422b may be located between data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d may be located between data lines DL(j+2) and DL(j+3).

[0226] In some examples, the first anode connection electrode 422a can be electrically connected to the sixth connection electrode 406 via the forty-third via V43, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b can be electrically connected to the sixteenth connection electrode 416 via the forty-sixth via V46, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0227] In some examples, the first power connection electrodes 423a, 423b, and 423c may be approximately rectangular in shape. The first power connection electrode 423a may be located on the side opposite to the first direction X of the data line DL(j), the first power connection electrode 423b may be located between the data lines DL(j+1) and DL(j+2), and the first power connection electrode 423c may be located on the side of the data line DL(j+3) of the first direction X.

[0228] In some examples, the first power connection electrode 423a can be electrically connected to the fifth connection electrode 405 through the forty-second via V42, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth connection electrode 415 through the forty-fourth via V44, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0229] In some examples, the shapes of the first shielding electrodes 421a and 421b can be approximately n-shaped. The first shielding electrode 421a can be located between data lines DL(j) and DL(j+1), and the first shielding electrode 421b can be located between data lines DL(j+2) and DL(j+3). The orthogonal projection of the first shielding electrode 421a onto the substrate can cover the orthogonal projections of the second connecting electrode 402 and the twelfth connecting electrode 412 onto the substrate, thereby shielding the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thus blocking the influence of other signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can shield the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11c and 11d.

[0230] (10) Forming the eighth insulating layer. In some examples, an eighth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the eighth insulating film is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as the second planarization layer.

[0231] Figure 16 for Figure 6 A schematic diagram of a first sub-region after the formation of the eighth insulating layer. In some examples, such as... Figure 16 As shown, the eighth insulating layer of the first display area may have multiple vias, such as vias V51 to V59. The eighth insulating layer within vias V51 to V59 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0232] (11) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0233] Figure 17A for Figure 6 A schematic diagram of the first display area after the formation of the sixth conductive layer. Figure 17B for Figure 17A A schematic diagram of the sixth conductive layer. Figure 17C for Figure 17A A schematic diagram of the first sub-region in the diagram.

[0234] In some examples, such as Figures 17A to 17C As shown, the sixth conductive layer of the first display area may include at least: a plurality of second anode connection electrodes (e.g., second anode connection electrodes 431a, 431b, 431c and 431d), a plurality of third anode connection electrodes (e.g., third anode connection electrodes 432a, 432b, 432c and 432d), and a first power line 44.

[0235] In some examples, the first power lines 44 of the first display area may be in a mesh structure. The first power lines 44 of the first sub-region may be substantially symmetrical about the first center line O1. The first power lines 44 of the first sub-region may include: first extensions 441a and 441b, second extensions 442a and 442b, third extensions 443a, 443b and 443c, and fourth extensions 444a and 444b. The first extensions 441a and 441b, the second extensions 442a and 442b, the third extensions 443a, 443b and 443c, and the fourth extensions 444a and 444b may be an interconnected integral structure. The second sub-region may be surrounded by the first extensions 441a and 441b in the first sub-region adjacent in the second direction Y, and the fourth extensions 444a and 444b in the first sub-region adjacent in the first direction X. The first extension, third extension, and fourth extension of the first power line 44 in different first sub-regions can be electrically connected to form a grid-like design within the entire first display area.

[0236] In some examples, the first extensions 441a and 441b may be generally strip-shaped extending along the first direction X. The first extension 441a may be located on the side opposite to the first shielding electrodes 421a and 421b along the second direction Y, and the first extension 441b may be located on the side of the first shielding electrodes 421a and 421b along the second direction Y.

[0237] In some examples, the second extensions 442a and 442b can be generally strip-shaped, extending along the second direction Y. The second extension 442a can be electrically connected to the first shielding electrode 421a via the fifty-first via V51, and the second extension 442b can be electrically connected to the first shielding electrode 421b via the fifty-second via V52. Both ends of the second extension 442a are electrically connected to the first extensions 441a and 441b, respectively, and both ends of the second extension 442b can be electrically connected to the first extensions 441a and 441b, respectively.

[0238] In some examples, the third extension segments 443a, 443b, and 443c can be generally strip-shaped, extending along the second direction Y. The third extension segment 443a can be electrically connected to the first power connection electrode 423a via the 53rd via V53, the third extension segment 443b can be electrically connected to the first power connection electrode 423b via the 54th via V54, and the third extension segment 443c can be electrically connected to the first power connection electrode 423c via the 55th via V55. The two ends of the third extension segment 443a can be electrically connected to the first extension segments 441a and 441b, respectively; the two ends of the third extension segment 443b can be electrically connected to the first extension segments 441a and 441b, respectively; and the two ends of the third extension segment 443c can be electrically connected to the first extension segments 441a and 441b, respectively. The three third extension segments and the two second extension segments can be spaced apart along the first direction X.

[0239] In some examples, the fourth extensions 444a and 444b may be generally strip-shaped, extending along the second direction Y. The two ends of the fourth extension 444a may be electrically connected to the first extensions 441a and 441b, respectively, and the two ends of the fourth extension 444b may be electrically connected to the first extensions 441a and 441b, respectively. The fourth extension 444a is located on the side opposite to the third extension 443a in the first direction X, and the fourth extension 444b is located on the side of the third extension 443c in the first direction X.

[0240] In some examples, in the first sub-region, two first extensions 441a and 441b, two second extensions 442a and 442b, and three third extensions 443a, 443b, and 443c of the first power line 44 can be connected to form four receiving areas. Each of the four receiving areas corresponds to one of the four first pixel circuits, and a second anode connection electrode can be disposed within each receiving area.

[0241] The mesh design of the first power line in this example within the first sub-region ensures a symmetrical design of the circuit structure layer, thereby avoiding display differences at different viewing angles (e.g., left-right viewing differences) caused by the circuit structure layer.

[0242] In some examples, the second anode connection electrode 431a may be located in the receiving area between the third extension 443a and the second extension 442a. The shape of the second anode connection electrode 431a may be generally dumbbell-shaped, extending along the second direction Y. The second anode connection electrode 431a may be electrically connected to the first anode connection electrode 422a through the fifty-sixth via V56, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a.

[0243] In some examples, the second anode connection electrode 431b may be located in the receiving area between the third extension 443b and the second extension 442a. The shape of the second anode connection electrode 431b may be generally dumbbell-shaped, extending along the second direction Y. The second anode connection electrode 431b may be electrically connected to the first anode connection electrode 422b through the fifty-seventh via V57, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b.

[0244] In some examples, the second anode connection electrode 431c may be located in the receiving area between the third extension 443b and the second extension 442b. The shape of the second anode connection electrode 431c may be generally dumbbell-shaped, extending along the second direction Y. The second anode connection electrode 431c may be electrically connected to the first anode connection electrode 422c through the fifty-eighth via V58, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11c.

[0245] In some examples, the second anode connection electrode 431d may be located in the receiving area between the third extension 443c and the second extension 442b. The shape of the second anode connection electrode 431d may be generally dumbbell-shaped, extending in a direction that intersects both the first and second directions. The second anode connection electrode 431d may be electrically connected to the first anode connection electrode 422d through the fifty-ninth via V59, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11d.

[0246] In some examples, the third anode connecting electrodes 432a, 432b, 432c, and 432d are generally rectangular in shape, with chamfered and rounded corners. The third anode connecting electrodes 432a, 432b, 432c, and 432d may be located within a region formed by first extensions 441a and 441b adjacent in the second direction Y, and fourth extensions 444a and 44b adjacent in the first direction X. The third anode connecting electrodes 432a and 432b are aligned along the first direction X and adjacent to a first extension 441a within a first sub-region in the second direction Y. The third anode connecting electrodes 432c and 432d may be aligned along the first direction X and adjacent to a first extension 441b within another first sub-region in the second direction Y.

[0247] (12) Forming the ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the ninth insulating film is patterned by a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as the third planarization layer.

[0248] Figure 18 for Figure 6 A schematic diagram of the first display area after the formation of the ninth insulating layer. In some examples, such as... Figure 18As shown, the ninth insulating layer of the first display area may have multiple vias, such as the sixty-first via V61 to the sixty-eighth via V68. The ninth insulating layer within the sixty-first via V61 to the sixty-eighth via V68 may be removed, exposing a portion of the surface of the sixth conductive layer.

[0249] At this point, the circuit structure layer can be completed. The film structure of the circuit structure layer in the second display area is similar to that in the first display area, so it will not be described again here.

[0250] (13) Forming a conductive connection layer. In some examples, a transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form a conductive connection layer. In this example, a single conductive connection layer is used as an example. However, this embodiment is not limited to this. In other examples, multiple conductive connection layers can be provided, and a planarization layer can be provided between adjacent conductive connection layers.

[0251] Figure 19A for Figure 6 A schematic diagram of the first display area after the formation of the conductive connection layer. Figure 19B for Figure 19A A schematic diagram of the conductive connection layer in the diagram.

[0252] In some examples, such as Figure 19A and Figure 19B As shown, the conductive connection layer of the first display area may include: multiple conductive connection lines (e.g., conductive connection lines 15a, 15b, 15c and 15d) and multiple fourth anode connection electrodes (e.g., fourth anode connection electrodes 461a, 461b, 461c and 461d).

[0253] In some examples, the fourth anode connecting electrodes 461a, 461b, 461c, and 461d can be generally rectangular in shape, and this rectangle can have rounded or chamfered corners. The fourth anode connecting electrode 461a can be electrically connected to the second anode connecting electrode 431a through the sixty-first via V61. The fourth anode connecting electrode 461b can be electrically connected to the second anode connecting electrode 431b through the sixty-second via V62. The fourth anode connecting electrode 461c can be electrically connected to the second anode connecting electrode 431c through the sixty-third via V63. The fourth anode connecting electrode 461d can be electrically connected to the second anode connecting electrode 431d through the sixty-fourth via V64.

[0254] In some examples, multiple conductive connection lines may extend at least along a first direction X, extending from a first display area to a second display area and electrically connected to the second pixel circuit of the second display area. Conductive connection line 15a may be electrically connected to the third anode connection electrode 432a via a sixty-fifth via V65, conductive connection line 15b may be electrically connected to the third anode connection electrode 432c via a sixty-sixth via V66, conductive connection line 15c may be electrically connected to the third anode connection electrode 432b via a sixty-seventh via V67, and conductive connection line 15d may be electrically connected to the third anode connection electrode 432d via a sixty-eighth via V68. The orthographic projection of the conductive connection lines onto the substrate may overlap with the orthographic projection of at least one first pixel circuit onto the substrate. For example, the orthographic projections of conductive connection lines 15a, 15b, 15c, and 15d onto the substrate may all overlap with the orthographic projections of the four first pixel circuits connected to the four first light-emitting elements of the first light-emitting unit in column a, row b+1.

[0255] In some examples, the conductive interconnect layer can be made of a transparent conductive material, such as ITO. Although the conductive interconnect lines pass through the second sub-region, they can avoid affecting the light transmittance of the second sub-region.

[0256] (14) Forming a light-emitting structure layer. In some examples, a tenth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the tenth insulating film is patterned by a patterning process to form a tenth insulating layer. The tenth insulating layer may have multiple vias, which can expose a portion of the surface of the conductive interconnect layer. Subsequently, an anode film is deposited on the substrate on which the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode layer.

[0257] Figure 20 for Figure 6 A schematic diagram of the first display area after the anode layer has been formed. In some examples, such as... Figure 20 As shown, the first display area may include: anodes of a plurality of first light-emitting elements (e.g., anode 211a of first light-emitting element 21a, anode 211b of first light-emitting element 21b, anode 211c of first light-emitting element 21c, anode 211d of first light-emitting element 21d), and anodes of a plurality of second light-emitting elements (e.g., anode 221a of second light-emitting element 22a, anode 221b of second light-emitting element 22b, anode 221c of second light-emitting element 22c, and anode 221d of second light-emitting element 22d).

[0258] In some examples, the anode 211a of the first light-emitting element 21a emitting the first color light can be electrically connected to the fourth anode connection electrode 461a through a via formed in the tenth insulating layer. The anode 211b of the first light-emitting element 21b emitting the second color light can be electrically connected to the fourth anode connection electrode 461c through a via formed in the tenth insulating layer. The anode 211c of the first light-emitting element 21c emitting the third color light can be electrically connected to the fourth anode connection electrode 461b through a via formed in the tenth insulating layer. The anode 211d of the first light-emitting element 21d emitting the third color light can be electrically connected to the fourth anode connection electrode 461d through a via formed in the tenth insulating layer.

[0259] In some examples, the anode 221a of the second light-emitting element 22a emitting the first color light can be electrically connected to the conductive connection line 15c through a via formed in the tenth insulating layer. The anode 221b of the second light-emitting element 22b emitting the second color light can be electrically connected to the conductive connection line 15a through a via formed in the tenth insulating layer. The anode 221c of the second light-emitting element 22c emitting the third color light can be electrically connected to the conductive connection line 15b through a via formed in the tenth insulating layer. The anode 221d of the second light-emitting element 22d emitting the third color light can be electrically connected to the conductive connection line 15d through a via formed in the tenth insulating layer.

[0260] In some examples, a pixel-defining film is coated on the substrate on which the aforementioned pattern is formed, and a pixel-defining layer is formed through masking, exposure, and development processes. The pixel-defining layer may have multiple pixel openings exposing the anode layer. An organic light-emitting layer is formed within the aforementioned pixel openings and is connected to the anode layer. Subsequently, a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern, which is then connected to the organic light-emitting layer.

[0261] In some examples, such as Figure 6 As shown, the pixel definition layer of the first display area can form multiple first pixel openings (e.g., first pixel openings 210a, 210b, 210c and 210d) and multiple second pixel openings (e.g., second pixel openings 220a, 220b, 220c and 220d). The shapes of the multiple first pixel openings and the multiple second pixel openings can be approximately circular.

[0262] In some examples, the first pixel opening 210a can expose a portion of the surface of the anode 211a, the first pixel opening 210b can expose a portion of the surface of the anode 211b, the first pixel opening 210c can expose a portion of the surface of the anode 211c, and the first pixel opening 210d can expose a portion of the surface of the anode 211d. The second pixel opening 220a can expose a portion of the surface of the anode 221a, the second pixel opening 220b can expose a portion of the surface of the anode 221b, the second pixel opening 220c can expose a portion of the surface of the anode 221c, and the second pixel opening 220d can expose a portion of the surface of the anode 221d.

[0263] In some examples, the luminous area of ​​the first light-emitting element 21b emitting the second color light can be larger than the luminous area of ​​the first light-emitting element 21a emitting the first color light. The luminous area of ​​the first light-emitting element 21a emitting the first color light can be larger than the luminous area of ​​the first light-emitting element 21c or 21d emitting the third color light. The luminous areas of the first light-emitting elements 21c and 21d emitting the third color light can be the same. In this example, the luminous area of ​​the light-emitting element can refer to the area of ​​the overlapping region of the anode, organic light-emitting layer, and cathode exposed by the pixel opening of the pixel definition layer.

[0264] In some examples, the luminous area of ​​the second light-emitting element 22b emitting the second color light can be larger than the luminous area of ​​the second light-emitting element 22a emitting the first color light. The luminous area of ​​the second light-emitting element 22a emitting the first color light can be larger than the luminous area of ​​the second light-emitting element 22c or 22d emitting the third color light. The luminous areas of the second light-emitting elements 22c and 22d emitting the third color light can be the same.

[0265] In some examples, the luminous area of ​​the first light-emitting element can be larger than the luminous area of ​​the second light-emitting element emitting the same color light. For example, the ratio of the luminous areas of the second light-emitting element emitting the same color light to that of the first light-emitting element can be 0.4 to 0.8, such as approximately 0.5. For example, the luminous area of ​​the second light-emitting element 22a emitting the first color light can be approximately half the luminous area of ​​the first light-emitting element 21a emitting the first color light. The luminous area of ​​the second light-emitting element 22b emitting the second color light can be approximately half the luminous area of ​​the first light-emitting element 21b emitting the second color light. The luminous area of ​​the second light-emitting element 22c (or 22d) emitting the third color light can be approximately half the luminous area of ​​the first light-emitting element 21c (or 21d) emitting the third color light.

[0266] This example reduces the light-emitting area of ​​the second light-emitting element, which can reduce the dimness of the second light-emitting element caused by the low current density due to the large load of the conductive connection wire, thus improving the brightness of the second light-emitting element.

[0267] In some examples, the pixel definition layer of the first sub-region may be made of a black material to block the first pixel circuitry and traces of the first sub-region, while the pixel definition layer of the second sub-region may be made of a transparent material to improve the light transmittance of the second sub-region. This embodiment is not limited in this respect.

[0268] In some examples, after the light-emitting structure layer is prepared, an encapsulation layer can be formed on the cathode, which may include a stacked structure of inorganic / organic / inorganic materials.

[0269] In some examples, the first, second, third, fourth, fifth, and sixth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The seventh, eighth, and ninth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode can be made of transparent conductive materials. However, this embodiment is not limited to this.

[0270] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0271] In some examples, the structures of the second and third pixel circuits in the second display area can be roughly the same as the structure of the first pixel circuit. The light-emitting areas of the third light-emitting element emitting the same color light and the first light-emitting element can be roughly the same. The structure of the third light-emitting element in the second display area can be roughly the same as the structure of the first light-emitting element, so it will not be described in detail here.

[0272] The display substrate provided in this example has a built-in first pixel circuit connected to the first light-emitting element of the first display area, and an external second pixel circuit connected to the second light-emitting element. This allows for a reasonable layout of the external light-emitting element and the built-in light-emitting element of the pixel circuit to achieve the optimal combination of light transmittance and size of the first display area, thereby improving the performance of the display substrate and the user experience.

[0273] Figure 21 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 21 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the second direction Y. The first sub-region A11 may include a row of first light-emitting units 2a (including multiple first light-emitting units 2a arranged sequentially along the first direction X), and the second sub-region A12 may include a row of second light-emitting units 2b (including multiple second light-emitting units 2b arranged sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0274] In some examples, such as Figure 21 As shown, the first light-emitting unit 2a may include: a first light-emitting element 21a emitting a first color light, a first light-emitting element 21b emitting a second color light, and two first light-emitting elements 21c and 21d emitting a third color light. The second light-emitting unit 2b may include: a second light-emitting element 22a emitting a first color light, a second light-emitting element 22b emitting a second color light, and two second light-emitting elements 22c and 22d emitting a third color light. The arrangement of the light-emitting elements in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0275] The display substrate of this example, by setting a row of first light-emitting units and a row of second light-emitting units spaced apart in a second direction, allows for a reasonable layout of the external light-emitting elements and the internal light-emitting elements of the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0276] Figure 22 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 22As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X. The first sub-region A11 may include a column of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the second direction Y), and the second sub-region A12 may include a column of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0277] The display substrate of this example, by setting a row of first light-emitting units and a row of second light-emitting units spaced apart in a first direction, allows for a reasonable layout of the external light-emitting elements and the internal light-emitting elements of the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0278] Figure 23 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 23 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart in both the first direction X and the second direction Y. The first sub-region A11 may include two first light-emitting units 2a arranged sequentially along the first direction X, and the second sub-region A12 may include two second light-emitting units 2b arranged sequentially along the first direction X. In the first direction X, the two first light-emitting units 2a and the two second light-emitting units 2b can be aligned and spaced apart. In the second direction Y, one first light-emitting unit 2a and one second light-emitting unit 2b can be aligned and spaced apart. However, this embodiment is not limited to this. In other examples, the two first light-emitting units and one second light-emitting unit can be spaced apart in the first direction, or the two first light-emitting units and one second light-emitting unit can be spaced apart in the second direction.

[0279] The display substrate of this example, by setting two first light-emitting units and two second light-emitting units spaced apart in a first direction and a second direction, allows for a reasonable layout of the external and internal light-emitting elements of the pixel circuit. This achieves an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0280] Figure 24 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 24As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X and the second direction Y. The first sub-region A11 may include a first light-emitting unit 2a, and the second sub-region A12 may include a second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart.

[0281] In some examples, such as Figure 24 As shown, the first light-emitting unit 2a may include: a first light-emitting element 21a emitting a first color light, a first light-emitting element 21b emitting a second color light, and two first light-emitting elements 21c and 21d emitting a third color light. The first light-emitting elements 21a and 21b may be arranged in the same column at intervals, the first light-emitting elements 21c and 21d may be arranged in the same column at intervals, and the first light-emitting elements 21a, 21b, 21c, and 21d may be arranged in different rows.

[0282] In some examples, such as Figure 24 As shown, the second light-emitting unit 2b may include: a second light-emitting element 22a emitting a first color light, a second light-emitting element 22b emitting a second color light, and two second light-emitting elements 22c and 22d emitting a third color light. The second light-emitting elements 22a and 22b may be arranged in the same column at intervals, the second light-emitting elements 22c and 22d may be arranged in the same column at intervals, and the second light-emitting elements 22a, 22b, 22c, and 22d may be arranged in different rows.

[0283] The display substrate of this example, by setting the first light-emitting unit (including four first light-emitting elements arranged in two vertical columns) and the second light-emitting unit (including four second light-emitting elements arranged in two vertical columns) at intervals in both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, so as to achieve the optimal combination of light transmittance and size of the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0284] Figure 25 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 25As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X. The first sub-region A11 may include a column of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the second direction Y), and the second sub-region A12 may include a column of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0285] The display substrate of this example, by setting a first light-emitting unit (including four first light-emitting elements arranged in two vertical columns) and a second light-emitting unit (including four second light-emitting elements arranged in two vertical columns) spaced apart in a first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0286] Figure 26 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 26 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the second direction Y. The first sub-region A11 may include a row of first light-emitting units 2a (including multiple first light-emitting units 2a arranged sequentially along the first direction X), and the second sub-region A12 may include a row of second light-emitting units 2b (including multiple second light-emitting units 2b arranged sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0287] The display substrate of this example, by setting a first light-emitting unit (including four first light-emitting elements arranged in two vertical columns) and a second light-emitting unit (including four second light-emitting elements arranged in two vertical columns) spaced apart in a second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0288] Figure 27 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 27As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X and the second direction Y. The first sub-region A11 may include a first light-emitting unit 2a, and the second sub-region A12 may include a second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart.

[0289] In some examples, such as Figure 27 As shown, the first light-emitting unit 2a may include: a first light-emitting element 21a emitting a first color light, a first light-emitting element 21b emitting a second color light, and a first light-emitting element 21c emitting a third color light. The first light-emitting elements 21a and 21b may be arranged alternately in the same column, the first light-emitting element 21c may be arranged in one column, and the first light-emitting elements 21a, 21b, and 21c may be arranged in different rows. The arrangement of the three first light-emitting elements in the first light-emitting unit 2a is approximately triangular.

[0290] In some examples, such as Figure 27 As shown, the second light-emitting unit 2b may include: a second light-emitting element 22a emitting a first color light, a second light-emitting element 22b emitting a second color light, and a second light-emitting element 22c emitting a third color light. The second light-emitting elements 22a and 22b may be arranged alternately in the same column, the second light-emitting element 22c may be arranged in one column, and the second light-emitting elements 22a, 22b, and 22c may be arranged in different rows. The arrangement of the three first light-emitting elements of the second light-emitting unit 2b is approximately triangular.

[0291] The display substrate of this example, by setting the first light-emitting unit (including three first light-emitting elements arranged in a triangle) and the second light-emitting unit (including three second light-emitting elements arranged in a triangle) at intervals in both the first and second directions, allows for a reasonable layout of the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit. This achieves an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0292] Figure 28 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 28As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the second direction Y. The first sub-region A11 may include a row of first light-emitting units 2a, and the second sub-region A12 may include a row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0293] The display substrate of this example, by setting the first light-emitting unit (including three first light-emitting elements arranged in a triangle) and the second light-emitting unit (including three second light-emitting elements arranged in a triangle) at intervals in the second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, so as to achieve an optimal combination of light transmittance and size, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0294] Figure 29 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 29 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X. The first sub-region A11 may include a column of first light-emitting units 2a, and the second sub-region A12 may include a column of second light-emitting units 2b. In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0295] The display substrate of this example, by setting a first light-emitting unit (including three first light-emitting elements arranged in a triangle) and a second light-emitting unit (including three second light-emitting elements arranged in a triangle) spaced apart in a first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0296] Figure 30 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 30 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the first direction X and the second direction Y. The first sub-region A11 may include a first light-emitting unit 2a, and the second sub-region A12 may include a second light-emitting unit 2b. The first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart along the first direction X and the second direction Y.

[0297] In some examples, such as Figure 30As shown, the first light-emitting unit 2a may include: a first light-emitting element 21a emitting a first color light, a first light-emitting element 21b emitting a second color light, and a first light-emitting element 21c emitting a third color light. The first light-emitting elements 21a, 21c, and 21b may be arranged sequentially along the first direction X. The second light-emitting unit 2b may include: a second light-emitting element 22a emitting a first color light, a second light-emitting element 22b emitting a second color light, and second light-emitting elements 22c and 22d emitting a third color light. The second light-emitting elements 22a, 22c, and 22b may be arranged sequentially along the first direction X. In this example, the light-emitting elements can be arranged periodically along the first direction X as a repeating unit, with the light-emitting element emitting the first color light, the light-emitting element emitting the third color light, and the light-emitting element emitting the second color light. In the second direction Y, light-emitting elements emitting the same color light can be aligned.

[0298] The display substrate of this example, by setting the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) at intervals in both the first and second directions, allows for a reasonable layout of the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit. This achieves an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0299] Figure 31 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 31 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart along the second direction Y. The first sub-region A11 may include a row of first light-emitting units 2a, and the second sub-region A12 may include a row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart. However, this embodiment is not limited to this. In other examples, the first and second sub-regions can be spaced apart along the first direction X. The first sub-region may include a column of first light-emitting units, and the second sub-region may include a column of second light-emitting units.

[0300] The display substrate of this example, by setting a first light-emitting unit (including three first light-emitting elements arranged along a first direction) and a second light-emitting unit (including three second light-emitting elements arranged along the first direction) spaced apart in a second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0301] Figure 32 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 32 As shown, the light-emitting elements in the first display area can be arranged periodically along the first direction X, with light-emitting elements emitting a second color light (e.g., blue light B), light-emitting elements emitting a first color light (e.g., red light R), and light-emitting elements emitting a third color light (e.g., green light G) forming a repeating unit. In the second direction Y, light-emitting elements emitting the same color light can be staggered. Specifically, the light-emitting elements emitting the second color light in one row of repeating units can be aligned with the light-emitting elements emitting the first color light in the previous row of repeating units in the second direction Y. Adjacent rows of light-emitting elements can be arranged with one light-emitting element offset in the second direction Y.

[0302] In some examples, such as Figure 32 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart on a fourth direction D4, which intersects both the first direction X and the second direction Y. The first sub-region A11 may include a plurality of first light-emitting units 2a arranged sequentially along the third direction D3, and the second sub-region A12 may include a plurality of second light-emitting units 2b arranged sequentially along the third direction D3. The third direction D3 and the fourth direction D4 may intersect, for example, they may be perpendicular to each other. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0303] The display substrate of this example, by setting the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) at intervals in a fourth direction that intersects both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size of the first display area, thus improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0304] Figure 33This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 33 As shown, the light-emitting elements in the first display area can be arranged periodically along the first direction X, with light-emitting elements emitting a first color light (e.g., red light R), light-emitting elements emitting a second color light (e.g., blue light B), and light-emitting elements emitting a third color light (e.g., green light G) forming a repeating unit. In the second direction Y, light-emitting elements emitting the same color light can be staggered. Specifically, the center lines of the light-emitting elements emitting the first color light in one row of repeating units can be aligned with the center lines of the light-emitting elements emitting the second color light and the light-emitting elements emitting the third color light in the previous row of repeating units in the second direction. Adjacent rows of light-emitting elements can be arranged with a stagger of 1.5 light-emitting elements in the second direction Y.

[0305] In some examples, such as Figure 33 As shown, the first sub-region A11 and the second sub-region A12 of the first display area can be spaced apart in the first direction X. The first sub-region A11 may include a plurality of first light-emitting units 2a arranged sequentially along the second direction Y, and adjacent first light-emitting units 2a may be misaligned. The second sub-region A12 may include a plurality of second light-emitting units 2b arranged sequentially along the second direction Y, and adjacent second light-emitting units 2b may be misaligned. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0306] The display substrate of this example, by setting a first light-emitting unit (including three first light-emitting elements arranged along a first direction) and a second light-emitting unit (including three second light-emitting elements arranged along the first direction) spaced apart in the first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, so as to achieve an optimal combination of light transmittance and size of the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0307] Figure 34 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 34As shown, multiple first light-emitting units 2a and multiple second light-emitting units 2b in the first display area can be arranged at intervals within multiple circumferential regions with the center of the first display area as the center. The first sub-region A11 and the second sub-region A12 can be arranged at intervals along a direction from the center to the edge. The first sub-region A11 may include at least one first light-emitting unit 2a, and the second sub-region A12 may include multiple second light-emitting units 2b. Along the direction from the center to the edge, the number of first light-emitting units 2a in different first sub-regions A11 can gradually increase, and the number of first light-emitting units 2b in different second sub-regions A12 can gradually increase. A first light-emitting unit 2a may include three or four first light-emitting elements, and a second light-emitting unit 2b may include three or four second light-emitting elements. This embodiment is not limited in this respect.

[0308] The display substrate of this example, by setting the first and second light-emitting units at intervals from the center to the edge, rationally arranges the external and internal light-emitting elements of the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0309] Figure 35 This is another example diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 35 As shown, the light-emitting elements in the first display area can be arranged in the following manner: multiple light-emitting elements emitting a third color light (e.g., green light G) are arranged in multiple rows and columns, and light-emitting elements emitting a first color light (e.g., red light R) and a second color light (e.g., blue light B) are arranged at intervals in the row and column directions, and the light-emitting elements emitting the first color light and the light-emitting elements emitting the third color light are arranged in different rows and different columns.

[0310] In some examples, such as Figure 35 As shown, the first light-emitting unit may include a first light-emitting element, and the second light-emitting unit may include a first second light-emitting element. In the first direction X, a first light-emitting unit and a second light-emitting unit are spaced apart. In a row of light-emitting elements, the first light-emitting element and the second light-emitting element are spaced apart. For example, the first light-emitting element emitting a third color light (G) and the second light-emitting element emitting a first color light (R) are spaced apart; the first light-emitting element emitting a first color light (R) and the second light-emitting element emitting a second color light (B) are spaced apart; or, the first light-emitting element emitting a second color light (B) and the second light-emitting element emitting a first color light (R) are spaced apart.

[0311] In some examples, in the second direction Y, a first light-emitting unit and a second light-emitting unit are spaced apart, or two first light-emitting units and two second light-emitting units are spaced apart. Specifically, in one column of light-emitting elements, first and second light-emitting elements emitting a third color light (G) are spaced apart; in another column of light-emitting elements, two first light-emitting elements (including a first light-emitting element emitting a first color light (R) and a first light-emitting element emitting a first color light (B)) and two second light-emitting elements (including a second light-emitting element emitting a first color light (R) and a second light-emitting element emitting a second color light (B)) are spaced apart.

[0312] The display substrate of this example, by setting a single first light-emitting element and a single second light-emitting element spaced apart in a first direction, and setting a single first light-emitting element and a single second light-emitting element, or two first light-emitting elements and two second light-emitting elements spaced apart in a second direction, rationally arranges the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, so as to achieve an optimal combination of light transmittance and size of the first display area, thereby improving the performance of the display substrate and the user experience. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0313] Figure 36 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 36 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0314] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following products: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, VR device or AR device containing a microdisplay, etc.

[0315] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to what is shown and described in detail herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized in that, include: The substrate includes a first display area and a second display area located at least one side of the first display area; A plurality of first light-emitting units and a plurality of second light-emitting units are located in the first display area; the first light-emitting unit includes at least one first light-emitting element, and the second light-emitting unit includes at least one second light-emitting element; the first light-emitting unit is adjacent to at least one second light-emitting unit. A plurality of first pixel circuits are located in the first display area; at least one of the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light. Multiple second pixel circuits are located in the second display area; At least one of the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and is configured to drive the at least one second light-emitting element to emit light. The plurality of first light-emitting units and the plurality of second light-emitting units are spaced apart along a first direction and a second direction; the first direction intersects the second direction. The ratio of the luminous area of ​​the second luminous element to that of the first luminous element, which emits light of the same color, is less than 1; The arrangement of the first light-emitting element in the first light-emitting unit is the same as the arrangement of the second light-emitting element in the second light-emitting unit.

2. The display substrate according to claim 1, characterized in that, In the first direction, a first light-emitting unit and a second light-emitting unit are arranged at intervals; in the second direction, a first light-emitting unit and a second light-emitting unit are arranged at intervals.

3. The display substrate according to claim 1, characterized in that, The first light-emitting unit and the second light-emitting unit that are adjacent to each other in the first direction are aligned and arranged, and the first light-emitting unit and the second light-emitting unit that are adjacent to each other in the second direction are aligned and arranged. Alternatively, there may be a misalignment between adjacent first and second light-emitting units in the second direction.

4. The display substrate according to any one of claims 1 to 3, characterized in that, The number of first light-emitting elements included in at least one first light-emitting unit is the same as the number of second light-emitting elements included in at least one second light-emitting unit.

5. The display substrate according to claim 4, characterized in that, The at least one first light-emitting unit includes the following four first light-emitting elements: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light; The at least one second light-emitting unit includes the following four second light-emitting elements: a second light-emitting element that emits a first color light, a second light-emitting element that emits a second color light, and two second light-emitting elements that emit a third color light.

6. The display substrate according to claim 5, characterized in that, The plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns; In the at least one first light-emitting unit, the two first light-emitting elements emitting a third color light are arranged in the same column, the first light-emitting elements emitting a first color light and the first light-emitting elements emitting a second color light are arranged in the same column, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows; In the at least one second light-emitting unit, the two second light-emitting elements emitting a third color light are arranged in the same column, the second light-emitting elements emitting a first color light and the second light-emitting elements emitting a second color light are arranged in the same column, and the four second light-emitting elements of the second light-emitting unit are arranged in different rows.

7. The display substrate according to claim 5, characterized in that, The plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns; In the at least one first light-emitting unit, the two first light-emitting elements emitting a third color light are arranged in the same row, the first light-emitting elements emitting a first color light and the first light-emitting elements emitting a second color light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different columns; In the at least one second light-emitting unit, the two second light-emitting elements emitting a third color light are arranged in the same row, the second light-emitting elements emitting a first color light and the second light-emitting elements emitting a second color light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

8. The display substrate according to claim 7, characterized in that, The four first light-emitting elements in the first light-emitting unit are electrically connected to the four first pixel circuits in a one-to-one correspondence. The four first pixel circuits are arranged sequentially along the first direction. The orthographic projection of each first pixel circuit on the substrate and the orthographic projection of the connected first light-emitting element on the substrate at least partially overlap.

9. The display substrate according to claim 8, characterized in that, The four first pixel circuits are symmetrically arranged about the first midline along the first direction. The first and second first pixel circuits are symmetrically arranged about the two first pixel circuits along the second midline along the first direction. The third and fourth first pixel circuits are symmetrically arranged about the two first pixel circuits along the third midline along the first direction.

10. The display substrate according to claim 8, characterized in that, The four first pixel circuits are electrically connected to the first power line, which is arranged in a grid pattern in the first display area.

11. The display substrate according to claim 8, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer located on the substrate; the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits includes: at least one first type transistor, at least one second type transistor, and a storage capacitor; The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate; the first semiconductor layer includes at least: an active layer of a first type transistor of the pixel circuit; the first conductive layer includes at least: a gate of the first type transistor of the pixel circuit and a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of a storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of a second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of the second type transistor of the pixel circuit; the fourth conductive layer includes at least: multiple connection electrodes; the fifth conductive layer includes at least: multiple data lines; and the sixth conductive layer includes at least: a first power line.

12. The display substrate according to claim 11, characterized in that, The first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one of the plurality of second sub-regions is provided with at least one second light-emitting unit; The second conductive layer further includes: a first scan line, a light emission control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend along a first direction; In the second direction, the first scan line and the first reset control line bypass one side of the second sub-region, and the light emission control line and the second reset control line bypass the other side of the second sub-region; the second direction intersects the first direction.

13. The display substrate according to claim 11, characterized in that, The first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one of the plurality of second sub-regions is provided with at least one second light-emitting unit; The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend along a first direction; In the second direction, the first initial signal line and the second scan line bypass one side of the second sub-region, and the second initial signal line and the third initial signal line bypass the other side of the second sub-region; the second direction intersects the first direction.

14. The display substrate according to claim 1, characterized in that, The ratio of the number of the first light-emitting unit and the second light-emitting unit in the first display area is 0.8 to 1.

2.

15. The display substrate according to claim 1, characterized in that, The light transmittance of the first display area is greater than that of the second display area; The display substrate further includes: a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area, wherein at least one of the plurality of third pixel circuits is electrically connected to at least one of the plurality of third light-emitting elements and is configured to drive the at least one third light-emitting element to emit light; The plurality of second pixel circuits are spaced apart between the plurality of third pixel circuits.

16. The display substrate according to claim 1, characterized in that, The orthographic projection of the at least one first pixel circuit on the substrate overlaps with the orthographic projection of the at least one first light-emitting element on the substrate; the at least one second pixel circuit and the at least one second light-emitting element are electrically connected through at least one conductive connection line; The orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element on the substrate.

17. The display substrate according to claim 16, characterized in that, The orthographic projection of the at least one conductive connection line on the substrate overlaps with the orthographic projection of the at least one first pixel circuit on the substrate.

18. A display device, characterized in that, The display substrate includes any one of claims 1 to 17, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate at least partially overlaps with the first display area of ​​the display substrate.

Images