Partitioned template matching and sign peephole optimization

Abstract

Systems and techniques are provided that facilitate partitioned template matching and / or symbol peephole optimization. In various embodiments, a system can include a template component that can perform template matching on a Clifford circuit associated with a set of qubits. In various aspects, the system can include a partition component that can partition the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage prior to template matching. In various instances, template matching can be performed on the computation stage.

Description

Background Technology

[0001] This disclosure relates to Clifford circuits, and more specifically, to partitioned template matching and symbolic peephole optimization for Clifford circuits.

[0002] A quantum circuit is a transformation that operates on a set of qubits. A quantum circuit can be represented by a unitary matrix (e.g., for any suitable positive integer n, a quantum circuit operating on n qubits can be represented by a 2^n unitary matrix). n x 2 n (Unitial matrix representation). The quantum state of a set of qubits can be represented by a quantum state vector (e.g., for n qubits, the quantum state vector can have 2n... n Quantum circuits can be applied to quantum state vectors via matrix multiplication. Quantum circuits can be combined in series via matrix multiplication and / or in parallel via tensor products (e.g., Kronecker products).

[0003] The long-term success of quantum computing depends on achieving at least partial fault tolerance. Clifford circuits are a specific type of quantum circuit that is inherent to fault-tolerant quantum computing (e.g., the encoding circuits used in many quantum error-correcting codes are Clifford circuits). Because Clifford circuits are very useful in quantum computing, it may be desirable to synthesize optimized Clifford circuits that implement a given Clifford operator. The goal of optimizing Clifford circuits is to reduce the single-qubit and / or two-qubit gate counts in the Clifford circuit, thereby reducing the computation time and / or computational resources required to implement the Clifford circuit.

[0004] Numerous studies have been conducted on the synthesis of asymptotically optimized Clifford circuits (e.g., Clifford circuits optimal up to a constant factor, but therefore not exactly optimal). Conventionally, the synthesis of exactly optimized Clifford circuits is extremely expensive even for small numbers of qubits (e.g., conventional techniques can generate exactly optimized Clifford circuits for only four qubits, and optimized Clifford circuits for up to five qubit input / output permutations). Conventional techniques for optimizing Clifford circuits include template matching and peephole optimization. Template matching involves using templates (e.g., strings of gates known to be equivalent in identity) to reduce the gate count in a given circuit. Conventional template matching is a general technique that works similarly with both Clifford and non-Clifford circuits. Therefore, conventional template matching cannot exploit and / or utilize the specific structural characteristics of Clifford circuits, which limits the extent to which the circuit can be optimized. Peephole optimization involves identifying sub-circuits within the entire Clifford circuit and optimizing these sub-circuits using a known library of optimal circuits. The technical problem with conventional peephole optimization is that it requires the subcircuit to be completely isolated from the rest of the Clifford circuit. In other words, conventional peephole optimization cannot be used if the subcircuit contains entangled gates that connect the subcircuit to the rest of the circuit.

[0005] It is expected that systems and / or technologies that can improve and / or resolve one or more of these technical problems can be improved. Summary of the Invention

[0006] The following is an overview to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatuses, and / or computer program products are described that can facilitate partition template matching and symbolic peephole optimization of Clifford circuits.

[0007] According to one or more embodiments, a system is provided. The system may include a memory capable of storing computer-executable components. The system may also include a processor operatively coupled to the memory and capable of executing the computer-executable components stored in the memory. In various embodiments, these computer-executable components may include a template component capable of performing template matching on a Clifford circuit associated with a set of qubits. In various aspects, the computer-executable components may also include a partitioning component capable of partitioning the Clifford circuit into a computational level, a Pauli level, and a SWAP level prior to template matching. In various instances, template matching may be performed at the computational level. In various embodiments, the computer-executable components may also include a symbol component capable of selecting a subset of qubits from the set of qubits, rewriting at least one entangled gate at the computational level such that the target of the at least one entangled gate is within the subset of qubits, and replacing at least one rewired entangled gate with a symbolic Pauli gate. In various cases, the symbolic Pauli gate may be a Pauli gate controlled by a symbolic variable. In various aspects, the computer-executable components may also include a peephole component capable of performing peephole optimization on a subset of qubits with symbolic Pauli gates by implementing a dynamic programming algorithm.

[0008] According to one or more embodiments, the above system can be implemented as a computer-implemented method and / or computer program product.

[0009] According to one or more embodiments, a system is provided. The system may include a memory capable of storing computer-executable components. The system may also include a processor operatively coupled to the memory and capable of executing the computer-executable components stored in the memory. In various embodiments, the computer-executable components may include a peephole component capable of performing peephole optimization on a Clifford circuit associated with a set of qubits. In various instances, the computer-executable components may also include a symbol component capable of selecting a subset of qubits from the set of qubits prior to peephole optimization, rewiring at least one entangled gate in the Clifford circuit such that the target of the at least one entangled gate is within the subset of qubits, and replacing the at least one rewiringed entangled gate with a symbolic Pauli gate. In various aspects, the computer-executable components may also include a partitioning component capable of partitioning the Clifford circuit into a computational level, a Pauli level, and a SWAP level. In various cases, the computer-executable components may also include a template component capable of performing template matching at the computational level prior to rewiring at least one entangled gate.

[0010] According to one or more embodiments, the above system can be implemented as a computer-implemented method and / or computer program product. Attached Figure Description

[0011] Figure 1 A block diagram of an example non-limiting system for facilitating partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0012] Figure 2-3 A flowchart illustrating an example non-limiting computer implementation of a method for facilitating partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0013] Figure 4 Example unrestricted tables and example unrestricted compilation algorithms are shown according to one or more embodiments described herein.

[0014] Figure 5 A block diagram of an example non-limiting system comprising compute-level, Pauli-level, and SWAP-level systems that facilitate partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0015] Figure 6 The method of pushing a Pauli gate to one end of a Clifford circuit is illustrated by way of example and non-limiting manner according to one or more embodiments described herein.

[0016] Figure 7 An example non-limiting Clifford circuit with partitioning is shown according to one or more embodiments described herein.

[0017] Figure 8 A block diagram of an example non-limiting system including a template library is shown, which facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein.

[0018] Figure 9 Example non-limiting templates that can be used for template matching according to one or more embodiments described herein are shown.

[0019] Figure 10 Example non-limiting templates are shown that can be used for Hadamard and / or Phase pushes during template matching, according to one or more embodiments described herein.

[0020] Figure 11 A block diagram of an example non-limiting system including floating gate conversion rules that facilitate partition template matching and / or symbol peephole optimization, according to one or more embodiments described herein, is shown.

[0021] Figure 12Example unrestricted rules for converting a Pauli operator back to a Hadamard and / or phase gate after a floating gate push, according to one or more embodiments described herein, are shown.

[0022] Figure 13 According to one or more embodiments described herein, the method of removing a blocking door from a template matching range is illustrated in an exemplary, non-limiting manner by means of a floating door push.

[0023] Figure 14 A block diagram of an example non-limiting system including SWAP equivalence relations that facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0024] Figure 15 According to one or more embodiments described herein, how to optimize a SWAP gate at the cost of an entanglement gate is illustrated by way of example and in a non-limiting manner.

[0025] Figure 16 A block diagram of an example non-limiting system including a symbolic Pauli gate that facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0026] Figure 17 According to one or more embodiments described herein, how to rewire a straddling gate is illustrated in an exemplary, non-limiting manner.

[0027] Figure 18 The invention illustrates, by way of example and non-limiting manner, how symbolic Pauli gates can be used to improve peephole optimization, based on one or more embodiments described herein.

[0028] Figure 19 A block diagram of an example non-limiting system comprising a library of optimal sub-circuits that facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0029] Figure 20-21 A flowchart illustrating an example non-limiting computer implementation of a method for facilitating partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown.

[0030] Figure 22 A block diagram is shown illustrating an example non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0031] Figure 23 An example non-limiting cloud computing environment is shown according to one or more embodiments described herein.

[0032] Figure 24An example non-limiting abstract model layer is shown according to one or more embodiments described herein. Detailed Implementation

[0033] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0034] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used to denote the same elements throughout. In the following description, numerous specific details are set forth for purposes of explanation and to provide a more thorough understanding of the one or more embodiments. However, it will be apparent in various circumstances that the one or more embodiments may be practiced without these specific details.

[0035] As mentioned above, a quantum circuit is a transformation that operates on a set of qubits. For any suitable positive integer n, a quantum circuit operating on n qubits can be derived from 2... n x2 n Unitary matrix representation. A quantum state of n qubits can be represented by a matrix with 2^n qubits. n A vector representation of elements. Quantum circuits can be applied to quantum state vectors via matrix multiplication. Furthermore, quantum circuits can be combined in series via matrix multiplication and / or can be combined in parallel via tensor products (e.g., Kronecker products).

[0036] As mentioned above, Clifford circuits are an important type of quantum circuit (e.g., important for achieving quantum fault tolerance). Therefore, it may be necessary to improve optimization techniques for Clifford circuits, where optimization involves reducing the gate count of a given Clifford circuit without changing the overall function / transformation implemented by the given Clifford circuit.

[0037] Clifford circuits (also known as stabilizer circuits) may include Hadamard gates (H), phase gates (S, also known as P), controlled NOT gates (CNOT), and Pauli gates (X, Y, and Z), where:

[0038] in, Clifford circuits can also include an identity matrix (I). Another frequently considered gate is the controlled Z-gate (CZ), which can be constructed as a combination of a Hadamard gate and a CNOT:

[0039]

[0040] Where * denotes matrix multiplication, and where, Represents the tensor product.

[0041] A key property of Clifford circuits is that Clifford gates H, S, and CNOT can be conjugated to themselves by mapping Pauli matrices (and / or tensor products of Pauli matrices). Equivalently, this can be written as the Pauli gates being “pushed” through the Clifford gates H, S, and CNOT. That is,

[0042] HX=ZH; HY=-YH; HZ=XH; SX=YS; SY=-XS; SZ=ZS

[0043] CNOT 1，2 X1=X1X2CNOT 1，2 CNOT 1，2 X2=X2CNOT 1，2 ;

[0044] CNOT 1，2 Z2=Z1Z2CNOT 1，2 GNOT 1，2 Z1=Z1CNOT 1，2

[0045] The index defines the control and target qubits. For ease of interpretation, these equations can be called Pauli-Push equations. As each of these Pauli-Push equations shows, a given Pauli gate implemented on the left side of a Clifford gate is equivalent to some potentially different Pauli gate implemented on the right side of the same Clifford gate. Thus, a Pauli can be “pushed” from one side of a Clifford gate to the other.

[0046] As mentioned above, optimization of Clifford circuits is typically performed via template matching and peephole optimization. These are briefly described below.

[0047] First, consider template matching. For any suitable positive integer m, a template of size m is a sequence of m gates that implement the identity function:

[0048] T = G0G1...G m-1 =I

[0049] Where T represents the template, and where G j Represents the gate for all non-negative integers j.

[0050] To see how templates can be used to reduce gate counts, observe some subsequences G of the template for some indices j and some 0≤p≤m. j ...G j+p-1(mod m)Whether it matches a gate in the circuit, and if the gates in the circuit can be moved together (e.g., made consecutive), then these gates in the circuit can be replaced by the inverses of the other mp gates of the template. Note that the larger the sequence length p, the more beneficial it is to perform the replacement, and for any The gate count is reduced. The precise criterion for applying the template can depend on the choice of the objective function (e.g., it can depend on how circuit cost is measured, such as by circuit depth, by 2-qubit gate count, or by total gate count). More formally, for the parameter p, where Template T can be applied in two directions as follows:

[0051] Forward:

[0052] Reverse:

[0053] in This represents the adjoint matrix (e.g., the conjugate transpose). Note that the adjoint matrix of a unitary matrix / gate is equal to the inverse of the unitary matrix / gate.

[0054] In various cases, a template T of size m can be independent of a smaller template (e.g., applying a smaller template does not reduce the number of gates in T or make it equal to another template). Circuit optimization using template matching is an iterative process in which, at each step, optimization begins with a given gate in the circuit and attempts to match the given template as backward and / or forward as possible. If the matched gates can move together and substitution is beneficial, the template can be applied as defined above. However, if the matched gates cannot move together and / or cannot otherwise be continuous, the template cannot be applied. If the matched gates are not continuous, it can be said that there is at least one blocking gate between the matched gates. Equivalently, it can be said that there is at least one blocking gate within the template matching range. In various cases, this step can be repeated for all templates and / or for all gates in the circuit until a predetermined convergence criterion (e.g., any suitable predefined convergence criterion) is met. The result can be a reduction (e.g., optimization) of the circuit gate count.

[0055] As described above, this conventional template matching is typically defined for quantum circuits. Therefore, while conventional template matching can be applied to Clifford circuits, it does not utilize the specific properties of Clifford circuits for optimization. As explained herein, the inventors of various embodiments of the invention have devised a technique for improving template matching (e.g., making template matching more efficient) by utilizing the specific structure of Clifford circuits.

[0056] Next, consider peephole optimization. Similar to template matching, peephole optimization is an iterative process that optimizes a circuit by considering subcircuits on a small subset of qubits (the small subset of qubits can be called A) and attempting to replace that subcircuit with an optimized version from a database / library of pre-computed optimized circuits. At each step, for a given gate, all subcircuits on a fixed small number of qubits (e.g., |A| = 4) including that gate are considered. For each subcircuit, its cost can be computed, and the optimal cost of its unitary implementation can be computed (e.g., this optimal cost can be obtained from a database of pre-computed optimal circuits). If the replacement is beneficial, the subcircuit is replaced with the optimal implementation. This step can be repeated for all gates until any suitable predetermined convergence criterion is met.

[0057] As described above, this conventional peephole optimization only works when the subcircuit is completely decoupled from the rest of the circuit (e.g., the subcircuit cannot include any bridging two-qubit gates that couple the subcircuit to the rest of the circuit). As explained herein, the inventors of various embodiments of the invention have devised a technique for performing peephole optimization on a subcircuit even when the subcircuit is not completely decoupled from the rest of the circuit.

[0058] Various embodiments of the present invention can solve one or more of these technical problems. Specifically, various embodiments of the present invention can provide systems and / or techniques capable of facilitating partition template matching and / or symbolic peephole optimization, which can optimize Clifford circuits more efficiently than conventional template matching and / or conventional peephole optimization. In various aspects, the teachings described herein can be equivalent to heuristic methods for Clifford circuit optimization, which can bridge the gap between non-scalable methods for synthesizing precisely optimized Clifford circuits and inexpensive synthesis techniques that are suboptimal (albeit asymptotically optimal). In various instances, embodiments of the present invention can be considered as computer-implemented tools (e.g., computer-implemented software programs) that can receive suboptimal Clifford circuits as input and can produce optimized versions of these suboptimal Clifford circuits as output more efficiently and / or more effectively than conventional systems and / or techniques.

[0059] In various respects, this computer-implemented tool can apply partitioned template matching to an input Clifford circuit, which can be considered an improved version of template matching that utilizes / uses the unique properties / structure of Clifford circuits. Specifically, partitioned template matching leverages the observation that in a Clifford circuit, Pauli gates can always be “pushed” to one end of the circuit (e.g., via the Pauli-Push equation explained above) without altering non-Pauli Clifford gates (e.g., H, S, CNOT). In various respects, partitioned template matching can include three steps. First, by “pushing” any Pauli gate and any SWAP gate in the Clifford circuit to one end of the circuit, the Clifford circuit can be partitioned into a computational stage, a Pauli stage, and a SWAP stage (it will be understood by those skilled in the art that SWAP gates can be “pushed” through a Clifford circuit in the same and / or similar manner as Pauli gates are “pushed” through the Clifford circuit). In various cases, the computational stage may consist only of H, S, and CNOT gates, the Pauli stage may consist only of Pauli gates, and the SWAP stage may consist only of SWAP gates. Secondly, template matching can be applied to the computational level to reduce gate count (e.g., templates are more easily applied because Pauli and SWAP are pushed to one end of the circuit during partitioning; in other words, Pauli and SWAP are excluded from the computational level). Thirdly, the SWAP level can be optimized by leveraging the fact that if a SWAP gate can be “aligned” with another two-qubit gate, a SWAP gate can be implemented at the cost of a single two-qubit gate. In some cases, if the application of templates or SWAP optimization produces any Pauli gates in the computational level, such Pauli gates can be pushed to the Pauli level (e.g., the circuit can be repartitioned). In some aspects, blocking gates can be used to prevent the application of templates to the computational level. As explained herein, the inventors have devised a novel floating gate technique that removes blocking gates, thus allowing the application of templates. In other words, the inventors have devised a process that enables the application of templates to sequences of discontinuous gates that cannot move directly together. The process attempts to remove (e.g., "float") the single-qubit gate that prevents template application by decomposing the single-qubit gate into a linear combination of Pauli operators and "pushing" the Pauli operators until they can be combined back into the single-qubit gate (which no longer prevents template application).

[0060] In other words, conventional template matching simply applies a template directly to a given Clifford circuit, while partitioned template matching may include: (1) partitioning a given Clifford circuit into three levels (e.g., computation, Pauli, and SWAP) by “pushing” any Pauli gates and / or SWAP gates in the given Clifford circuit to one end of the given Clifford circuit; (2) applying a template to one of the three partitions (e.g., the computation level); and (3) SWAP optimization by aligning SWAP with a two-qubit gate. Also as mentioned above, various embodiments of the invention may implement floating gate techniques that allow templates to be applied to sequences of discontinuous gates. As explained herein, floating gate techniques may involve rewriting blocking gates as linear combinations of Pauli gates and then “pushing” the Pauli gates out of the desired template matching range, thereby allowing the application of the desired template. Conventional template matching only excludes neither this partitioning nor this floating gate technique.

[0061] In various instances, computer-implemented tools according to various embodiments of the invention can apply symbolic peephole optimization to a given circuit, which can be considered an improved version of peephole optimization, even without complete subcircuit decoupling. Specifically, when considering a subcircuit coupled / entangled to the rest of the circuit via a bridging gate, the bridging gate can be rewritten such that the target of the bridging gate is in the subcircuit (e.g., this can typically be done by applying various Hadamard gates and / or phase gates), and the rewritten bridging gate can then be replaced and / or represented by a symbolic Pauli gate as defined herein. As described below, a symbolic Pauli gate is a Pauli gate controlled by a symbolic variable rather than by another qubit. It can be obtained from a two-qubit gate as needed by removing the control and replacing the target with a Pauli gate. Thus, a symbolic Pauli gate can be viewed as a single-qubit gate. Subcircuits with symbolic Pauli gates can then be optimized using dynamically programmed and / or pre-computed libraries of optimal circuits. In other words, when implementing a symbolic Pauli gate, although the subcircuit is not completely decoupled from the rest of the circuit, the subcircuit can be effectively treated as if it were completely decoupled from the rest of the circuit.

[0062] In other words, conventional peephole optimization only involves identifying fully decoupled subcircuits and replacing all or part of them with a pre-computed optimal circuit, while symbolic peephole optimization can include: (1) identifying any suitable subcircuits, whether fully decoupled or not; (2) rewriting any bridging gates such that the target of the bridging gate is in the subcircuit (e.g., such that the control of the rewritten bridging gate is in the rest of the circuit); (3) replacing each rewritten bridging gate in the subcircuit with a symbolic Pauli gate (e.g., a Pauli gate controlled by a symbolic variable); and (4) replacing all or part of the subcircuit with the symbolic Pauli gate with a pre-computed optimal circuit. Conventional peephole optimization cannot handle bridging gates at all.

[0063] In various cases, partition template matching and symbolic peephole optimization can be sequentially combined for the optimization of improved Clifford circuits (e.g., a computer-implemented tool as described herein can receive a Clifford circuit as input, apply partition template matching to the input Clifford circuit, and then apply symbolic peephole optimization to produce an optimized Clifford circuit as output).

[0064] Various embodiments of the present invention may be employed to solve inherently highly technical problems (e.g., to facilitate partition template matching and / or symbolic peephole optimization of Clifford circuits) using hardware and / or software, problems that are not abstract and cannot be performed as a set of mental actions by humans. Furthermore, some of the processes performed can be executed by a dedicated computer (e.g., by a device operatively coupled to a processor performing template matching on a Clifford circuit associated with a set of qubits; by that device dividing the Clifford circuit into computational, Pauli, and SWAP levels prior to template matching, wherein template matching is performed at the computational level; by that device pushing a blocking gate out of the template matching range at the computational level by replacing the blocking gate with a linear combination of Pauli operators; by that device selecting a subset of qubits from the set of qubits; by that device rewiring at least one entangled gate at the computational level such that the target of the at least one entangled gate is in the subset of qubits; by that device replacing at least one rewiring entangled gate with a symbolic Pauli gate, wherein the symbolic Pauli gate is a Pauli gate controlled by a symbolic variable; and by that device performing peephole optimization on a subset of qubits with a symbolic Pauli gate). Such defined tasks are typically not performed manually by humans. Furthermore, neither the human brain nor the use of pen and paper can electronically optimize a Clifford circuit by electronically dividing it into three distinct levels, by electronically applying template matching to one of these levels, and / or by electronically replacing bridging gates with symbolic Pauli gates. Instead, the various embodiments of the present invention are inherently and inevitably associated with computer technology and cannot be implemented outside of a quantum computing environment (e.g., the various embodiments of the present invention are directed to systems and / or computer-implemented methods that can more effectively optimize Clifford circuits of input; these systems and / or computer-implemented methods have great utility in the field of quantum computing and cannot be implemented in any practical way outside of a computing environment).

[0065] In various instances, embodiments of the invention can integrate the disclosed teachings regarding partitioned template matching and symbolic peephole optimization into practical applications. Indeed, as described herein, various embodiments of the invention, in the form of systems and / or computer-implemented methods, can be considered as computerized tools that can receive a Clifford circuit as input and generate an optimized version of the Clifford circuit (e.g., with a lower gate count) as output. More specifically, this computerized tool can facilitate optimization by implementing partitioned template matching (as opposed to conventional template matching) and by implementing symbolic peephole optimization (as opposed to conventional peephole optimization). The generation of electrons from optimized Clifford circuits is, of course, a useful and practical application for computers, especially considering how important Clifford circuits are for fault-tolerant quantum computing. Furthermore, as mentioned above, various embodiments of the invention can solve / address some of the technical problems experienced by conventional techniques. Specifically, conventional template matching is a general process, but partitioned template matching can be considered a Clifford-specific version of template matching that allows for more efficient optimization of the Clifford circuit than conventional template matching. Furthermore, conventional peephole optimization does not work if the subcircuit under consideration is not fully decoupled from the rest of the circuit (e.g., it does not work if a jumper gate is present), but symbolic peephole optimization can be considered an improved version of peephole optimization that works even without full decoupling. In summary, this system and / or technique clearly constitutes a concrete and tangible technical improvement in the field of Clifford circuit optimization.

[0066] Furthermore, various embodiments of the present invention can control real-world devices based on the disclosed teachings. For example, embodiments of the present invention can receive a real-world suboptimal Clifford circuit as input and generate a real-world optimized version of the suboptimal Clifford circuit as output by implementing partitioned template matching and symbolic peephole optimization. In some cases, embodiments of the present invention can execute such a real-world optimized version of the suboptimal Clifford circuit on a real-world quantum computing device.

[0067] It should be understood that the accompanying drawings and the disclosure herein are exemplary and not restrictive.

[0068] Figure 1A block diagram of an example non-limiting system 100 facilitating partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein is shown. As shown, the Clifford optimization system 102 can receive a suboptimal Clifford circuit 104 as input via any suitable wired and / or wireless electronic connection and can electronically generate an optimized Clifford circuit 106 as output. In various aspects, the optimized Clifford circuit 106 can be functionally equivalent to the suboptimal Clifford circuit 104 (e.g., can implement the same overall transformation as the suboptimal Clifford circuit 104), but can have a lower gate count than the suboptimal Clifford circuit 104. In various aspects, the suboptimal Clifford circuit 104 can operate on any suitable number of qubits. If the suboptimal Clifford circuit 104 operates on n qubits of any suitable positive integer n, then the optimized Clifford circuit 106 can also operate on n qubits.

[0069] In various embodiments, the Clifford optimization system 102 may include a processor 108 (e.g., a computer processing unit, a microprocessor) and a computer-readable storage 110 operatively connected to the processor 108. The storage 110 may store computer-executable instructions that, when executed by the processor 108, cause the processor 108 and / or other components of the Clifford optimization system 102 (e.g., partitioning component 112, template component 114, floating component 116, SWAP component 118, symbol component 120, peephole component 122) to perform one or more actions. In various embodiments, the storage 110 may store computer-executable components (e.g., partitioning component 112, template component 114, floating component 116, SWAP component 118, symbol component 120, peephole component 122), and the processor 108 may execute these computer-executable components.

[0070] In various embodiments, the Clifford optimization system 102 may include a partitioning component 112. In various aspects, the partitioning component 112 may divide (e.g., segment) the suboptimal Clifford circuit 104 into computational stages, Pauli stages, and SWAP stages. In various cases, the partitioning component 112 may “push” any Pauli gate (e.g., X, Y, and / or Z) to one end of the suboptimal Clifford circuit 104 via the aforementioned Pauli-Push equations. Similarly, the partitioning component 112 may “push” any SWAP gate in the suboptimal Clifford circuit 104 to one end via similar Push equations applied to SWAP gates. The result may be that all SWAP gates are now located in a portion of the suboptimal Clifford circuit 104 called the SWAP stage, all Pauli gates are now located in different portions of the suboptimal Clifford circuit 104 called the Pauli stage, and other Clifford gates (e.g., H, S, CNOT) are located in other different portions of the suboptimal Clifford circuit 104 called the computational stage. In other words, partitioning component 112 can move different operators / gates of suboptimal Clifford circuit 104 to different locations within suboptimal Clifford circuit 104 without functionally altering the overall transformation implemented by suboptimal Clifford circuit 104.

[0071] In various embodiments, the Clifford optimization system 102 may include a template component 114. In various aspects, the template component 114 may store, maintain, and / or otherwise have access to a template library in any suitable form. In various instances, the template may be any suitable quantum gate string that implements and / or is equivalent to an identifier transformation. In various cases, the template component 114 may facilitate template matching at the computational level of the suboptimal Clifford circuit 104 by utilizing the template library. In other words, the template component 114 may apply one or more templates from the template library to the computational level of the suboptimal Clifford circuit 104 to reduce the gate count of the suboptimal Clifford circuit 104. Note that in some cases, applying templates to the computational level may be easier and / or more effective / efficient than applying templates to an unpartitioned version of the suboptimal Clifford circuit 104. In other words, because all the Pauli gates and / or SWAP gates in the suboptimal Clifford circuit 104 are “pushed” to one end of the suboptimal Clifford circuit 104 by the partitioning component 112, these Pauli gates and / or SWAP gates no longer exist in the computational level and therefore cannot block and / or otherwise prevent the application of the template to the computational level (e.g., without partitioning, the Pauli gates and / or SWAP gates might be located in the middle of the template matching range, which could therefore block / prevent the application of the template).

[0072] In various embodiments, the Clifford optimization system 102 may include a floating component 116. In various aspects, the floating component 116 may store, maintain, and / or otherwise have access to any suitable form of various floating gate transformation rules. In various instances, as described above, gates in the computational level may block and / or hinder the application of a template (e.g., undesirable H-gates and / or undesirable S-gates may be within the template matching range). Conventionally, nothing is done, and different templates are tried. However, in various aspects, the floating component 116 can address this problem. Specifically, in various instances, the floating component 116 can utilize floating gate transformation rules to rewrite and / or transform blocking gates into linear combinations of Pauli gates (e.g., H can be represented as a linear combination of Pauli gates, and S can be represented as a linear combination of Pauli gates). The floating component 116 can then “push” the linear combination of Pauli gates outside the template matching range via Pauli-push equations. Thus, blocking gates are removed from the matching range, and the template can be applied. In some cases, the floating component 116 can utilize the floating gate transformation rule to transform a linear combination of the moved Pauli operators back into a single-qubit gate. In other words, the partitioning component 112 can move Pauli gates out of template-matching range, while the floating component 116 can move Hadamard and / or phase gates out of template-matching range.

[0073] In various embodiments, the Clifford optimization system 102 may include a SWAP component 118. In various aspects, the SWAP component 118 may store, maintain, and / or otherwise have access to any suitable form of various SWAP equivalence relations. In various aspects, SWAP gates can be implemented at a cost-effective cost of two-qubit gates (e.g., CNOT) by pushing / merging SWAP gates back into the computational stage and combining them with two-qubit gates according to known equations / formulas. SWAP equivalence relations can be these known equations / formulas. That is, SWAP equivalence relations can be various equations indicating the resulting circuits and / or resultant gate strings achieved when SWAP gates are implemented in series with CNOT gates and / or CZ gates. Thus, the SWAP component 118 can replace SWAP gates at the SWAP stage of the suboptimal Clifford circuit 104.

[0074] In various embodiments, the Clifford optimization system 102 may include a symbol component 120. In various aspects, the symbol component 120 may perform various actions that can prepare a partitioned and template-matched version of the suboptimal Clifford circuit 104 for peephole optimization. Specifically, the symbol component 120 may select any suitable subcircuit within the computational stage (e.g., a subcircuit operating on two and / or three qubits). In various instances, the symbol component 120 may then rewrite any bridging gates such that their target is in and / or operated by the subcircuit. In various cases, the bridging gate may be a two-qubit gate (e.g., CNOT and / or CZ) that has exactly one of the target qubit or control qubit in the subcircuit. If the target qubit of the bridging gate is in and / or operated by the subcircuit, then the control qubit of the bridging gate is in and / or operated by the rest of the circuit. On the other hand, if the control qubit of the bridging gate is in and / or operated by the sub-circuit, then the target qubit of the bridging gate is in and / or operated by the rest of the circuit. Therefore, the bridging gate couples the sub-circuit to the rest of the circuit. In various aspects, the symbol component 120 can redewire the bridging gate using any suitable mathematical equation / formula, such that the target qubit of the bridging gate is in the sub-circuit. In various cases, the symbol component 120 can replace the bridging gate redewired in the sub-circuit with a symbol Pauli gate. Similar to entangled gates (e.g., CNOT and / or CZ), the symbol Pauli gate can be a controlled Pauli gate (e.g., X, Y, and / or Z). However, unlike entangled gates, the symbol Pauli gate can be controlled by a symbol variable rather than by another qubit. In various aspects, the value of the symbol variable can be 0 or 1, and the symbol variable can be a power of the symbol Pauli gate. Therefore, if the symbol variable has a value of 1, the symbol Pauli gate can implement a basic Pauli. However, if the symbol variable has a value of 0, the symbol Pauli gate can instead implement a sign transformation. Thus, the symbolic Pauli gate can mimic the behavior of controlled Pauli (e.g., CNOT and / or CZ), but for the purpose of peephole optimization, it can be regarded as a single-qubit gate (e.g., it can be regarded as an entanglement-free gate).

[0075] In various embodiments, the Clifford optimization system 102 may include a peephole component 122. In various aspects, the peephole component 122 may store, maintain, and / or otherwise have any suitable form of access to an optimal circuit library. In various aspects, the peephole component 122 may utilize the optimal circuit library to perform peephole optimization on subcircuits with symbolic Pauli gates (e.g., pre-computed optimal circuits in the library may replace all and / or some of the gates in the subcircuit, thereby reducing the gate count). As mentioned above, conventional peephole optimization techniques cannot be simply performed on subcircuits that are not fully decoupled. However, due to symbolic Pauli gates, symbolic peephole optimization can be performed on subcircuits that are not fully decoupled.

[0076] In each respect, the Clifford optimization system 102 can iteratively execute all and / or some of the partitioning component 112, template component 114, floating component 116, SWAP component 118, symbol component 120 and / or peephole component 122 to generate an optimized Clifford circuit 106 as a result.

[0077] Figure 2-3 Flowcharts of example non-limiting computer-implemented methods 200 and 300 that facilitate partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein are shown. In some cases, system 100 may facilitate computer-implemented methods 200 and 300.

[0078] First, consider the computer-implemented method 200. In various embodiments, action 202 may include receiving a suboptimal Clifford circuit (e.g., 104) by a device operatively coupled to a processor. While in some embodiments the suboptimal Clifford circuit may be received and optimized directly, other embodiments may involve receiving a Clifford unit, compiling the Clifford unit via a technique based on Gaussian elimination of symplectic matrices (e.g., baseline compilation), and then optimizing the compiled circuit.

[0079] In various aspects, action 204 may include dividing the suboptimal Clifford circuit into a computational stage, a Pauli stage, and a SWAP stage by means of a device (e.g., 112) by “pushing” a Pauli gate and / or a SWAP gate to one end of the suboptimal Clifford circuit.

[0080] In various instances, action 206 may include the device performing a pass-through of template matching (e.g., via 114) and / or SWAP optimization (e.g., via 118) to the computational level until a convergence criterion is met. In some cases, this may include repartitioning the suboptimal Clifford circuit whenever the application of templates and / or the merging of SWAP gates produce Pauli gates and / or SWAP gates in the computational level.

[0081] In various cases, action 208 may include a symbolic peephole-optimized pass performed at the computational level by devices (e.g., 120 and 122) in a random order.

[0082] In some aspects, action 210 may include performing the template matching pass again by the device (e.g., 114) at the computation level to further reduce the single-qubit gate count.

[0083] In various instances, action 212 may include an optimized Clifford circuit (e.g., 106) that implements a suboptimal Clifford circuit by means of a device output.

[0084] Now, consider the computer-implemented method 300. In various embodiments, action 302 may include receiving a suboptimal Clifford circuit (e.g., 104) by a device operatively coupled to the processor.

[0085] In various aspects, action 304 may include the synthesis of a suboptimal Clifford circuit by the device using a baseline compiler (e.g., Gaussian elimination of the Singer matrix).

[0086] In various instances, action 306 may include actions 204-210 of the computer-implemented method 200 performed by the device.

[0087] In various cases, action 308 may include the device iteratively repeating actions 304-306 any appropriate number of times, and the device selecting the optimal result circuit.

[0088] In various aspects, action 310 may include an optimized Clifford circuit (e.g., 106) that implements a suboptimal Clifford circuit by means of a device output.

[0089] As explained herein, various embodiments of the present invention can facilitate partition template matching and symbolic peephole optimization, which can be considered two novel algorithms for Clifford circuit optimization. In some cases, these novel algorithms can be applied in at least two ways. First, if the input is a Clifford unit, it can be applied using a baseline compiler (see reference...). Figure 4(Discussion) Optimization can begin with synthesizing the circuit, and then optimization can include reducing the gate count by applying partitioned template matching and / or symbolic peephole optimization. Secondly, if the input is a Clifford circuit instead of a Clifford unit, optimization can begin by resynthesizing it or by directly applying partitioned template matching and / or symbolic peephole optimization. In some cases, these two approaches can be performed in parallel, and the best result can be selected. As mentioned above, in some cases, the gate count can be further reduced by iteratively repeating baseline compilation and optimization any suitable number of times and then selecting the best result.

[0090] Figure 4 Example non-limiting table 402 and example non-limiting compilation algorithm / circuit 404 are shown according to one or more embodiments described herein. In other words, Figure 4 This demonstrates how the baseline compiler works.

[0091] Let PL(n) denote the set of Pauli operators over n qubits, and CL(n) denote the set of Clifford operators over n qubits. It is said that the Clifford operator D∈CL(n) is a function of D... -1 OD = X1 and D -1 In the case of O′D=Z1, a pair of Pauli operators O, O′∈PL(n) can be decoupled. Note that this is only possible when OO′=-O′O. Then, the following holds: any pair of anti-commuting Pauli operators O, O′∈PL(n) can be decoupled by some Clifford operator D with a CNOT cost ≤ (3 / 2)n+O(1), where operator D can be computed in time O(n) (e.g., big-O notation). This can be called Lemma 1.

[0092] Suppose the goal is to compile a given Clifford operator C∈CL(n) using single-qubit gates and CNOT gates. For each qubit j∈[n], let O j =CX j C -1 and O′ j =CZ j C -1 Note O j and O′ j Anticommute. Let D j ∈CL(n) represents the O j and O′ j Decoupled Clifford operator. Select qubit j such that D... j It has a minimum number of CNOT gates, or, if using a randomized version of the compiled algorithm, selects random qubits. Definition

[0093]

[0094] Then, With X j and Z j Exchange. This is only possible when... It is only possible when acting trivially on the j-th qubit. Ignoring this insignificant action, we can... Consider it as an element in the smaller Clifford set CL(n-1). Performed inductively by reducing the number of qubits at each step, C can be decomposed into the product of SWAP gates and decoupling operators. Each decoupling operator can be compiled using single-qubit Clifford and CNOT gates as described above.

[0095] The proof of Lemma 1 is as follows. Specifically, as shown below, a decoupling operator D can be explicitly constructed such that D maps the anti-exchanges PauliO and O′ to X1 and Z1, respectively. The objective can be to minimize the CNOT cost of D.

[0096] Assuming the Pauli operators O and O' are in standard form, if their action on any qubit j falls into... Figure 4 One of the five cases shown in Table 402. Recall that the single-qubit Clifford set CL(1) is acted upon by permutations of the Pauli operators X, Y, Z. Therefore, any Pauli pair O and O' can be converted to standard form by applying a layer of single-qubit Clifford operators. This results in dividing the n qubits into five disjoint subsets [n] = ABCDE. Note that A has an odd size because otherwise O and O' would be swapped. Let A(j) be the j-th qubit of A. Next, apply Figure 4 The algorithm / circuit 404 is shown. Let D be an operator implemented by the compiled algorithm / circuit 404 combined with the initial layer of the single-qubit Clifford. Direct checks show that D has the desired decoupling properties up to the sign factor interpretation. The latter can be fixed by applying Pauli X1 or Y1 or Z1 as the last gate of D. The resulting circuit has a CNOT count of at most (3 / 2)|A|+|B|+|C|+|D|+O(1)≤(3 / 2)n+O(1).

[0097] Note that the above proof uses the symbol D in two separate meanings: as a way of representing a decoupled circuit (e.g., shown as algorithm / circuit 404), and also as a way of representing a subset of qubits (e.g., [n] = ABCDE). These separate uses of the symbol D will be understood by those skilled in the art.

[0098] Figure 5A block diagram of an example non-limiting system 500, which facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein, is shown. The system includes a compute level, a Pauli level, and a SWAP level. As shown, in some cases, system 500 may include the same components as system 100, and may also include a compute level 502, a Pauli level 504, and a SWAP level 506.

[0099] In various embodiments, partitioning component 112 can partition the suboptimal Clifford circuit 104 into computational stage 502, Pauli stage 504, and SWAP stage 506. As described above, Clifford gates can take the tensor product of Pauli matrices as the tensor product of Pauli matrices (e.g., via the Pauli-push equation). Partitioning component 112 can utilize this fact. Specifically, partitioning component 112 can use the Pauli-push equation to “push” and / or move any Pauli operator in the suboptimal Clifford circuit 104 to a specified location in the circuit, referred to as Pauli stage 504. In a similar manner, partitioning component 112 can “push” and / or move SWAP gates in the suboptimal Clifford circuit 104 to different specified locations in the circuit, referred to as SWAP stage 506 (e.g., as those skilled in the art will understand, SWAPs can be “push” and / or moved through the circuit via equations similar to the Pauli-Push equation). The result could be that Pauli stage 506 is a portion of the suboptimal Clifford circuit 104 containing only Pauli gates (e.g., X, Y, Z), SWAP stage 506 is a portion of the suboptimal Clifford circuit 104 containing only SWAP gates, and computation stage 502 is the remaining portion of the suboptimal Clifford circuit 104 containing other Clifford gates (e.g., H, S, CNOT). Figure 6-7 This helps to illustrate this division.

[0100] Figure 6 The illustration, by way of example and non-limiting manner, shows how a Pauli gate can be “pushed” to one end of a Clifford circuit according to one or more embodiments described herein. As shown in the figure, Figure 6 A two-qubit circuit 602 and its equivalent, 604, are depicted. As shown, the two-qubit circuit 602 includes two gates: a Clifford operator 608 (e.g., CNOT in the specific example shown), and a Pauli operator 606 applied to the left side of the Clifford operator 608 (e.g., in the specific example shown). And / or X0). By using the Pauli-push equation, the two-qubit circuit 602 can be transformed into a two-qubit circuit 604, which also includes two gates: the same Clifford operator 608 and a different Pauli operator 610 applied to the right side of the Clifford operator 608 (e.g., ...). (and / or X0X1). This non-limiting example shows how the Pauli operator can be “pushed” from one side of the Clifford operator to the other via the Pauli-Push equation.

[0101] Those skilled in the art will understand that the SWAP gate can be similarly "push".

[0102] Figure 7 An example non-limiting Clifford circuit 700 partitioned according to one or more embodiments described herein is shown. In other words, Figure 7 An example non-limiting result that can be obtained via partitioning by partitioning component 112 is shown. Circuit 700 can be considered as an example non-limiting partitioned version of the suboptimal Clifford circuit 104. As shown, the suboptimal Clifford circuit 104 can be partitioned into three distinct levels using Pauli-push equations (and similar SWAP-push equations). Specifically, all Pauli operators in the suboptimal Clifford circuit 104 can be “pushed” and / or repositioned to specific locations by partitioning component 112, referred to as Pauli level 504. Similarly, all SWAP gates in the suboptimal Clifford circuit 104 can be “pushed” and / or repositioned to different specific locations by partitioning component 112, referred to as SWAP level 506. In various respects, the remainder of the suboptimal Clifford circuit 104 can be referred to as computational level 502. As shown in the figure, in some cases, computation level 502 may only include H gates, S gates and / or CNOT gates; in some cases, Pauli level 504 may only include X gates, Y gates and Z gates; and in some cases, SWAP level 506 may only include SWAP gates.

[0103] Figure 8 A block diagram of an example non-limiting system 800 including a template library is shown, which facilitates partition template matching and / or symbol peephole optimization according to one or more embodiments described herein. As shown, in some cases, system 800 may include the same components as system 500, and may also include template library 802.

[0104] In various embodiments, template component 114 may electronically store, maintain, and / or otherwise access template library 802. As described above, a template may be a string of any suitable gates that implements the identifier transformation. In various aspects, template component 114 may perform template matching on computational stage 502 by utilizing template library 802. As described above, template matching may involve matching a subsequence of gates in a template with a corresponding subsequence of gates in a circuit. As long as the corresponding subsequence of gates in the circuit is consecutive (e.g., as long as there are no blocking gates within the template matching range), a subsequence of gates in the circuit can be replaced by the inverse of other gates in the template, which can therefore reduce the gate count of the circuit. Figure 9 Various exemplary and non-limiting templates are shown in the template library 802. In some cases, template component 114 can simplify template matching by converting all two-qubit gates in computation stage 502 into CZ gates (e.g., at the cost of introducing additional Hadamard) before performing template matching.

[0105] In various aspects, template component 114 can enable Hadamard push and / or phase push via two-qubit gates to further reduce single-qubit gate counts and increase opportunities for template application. Assume that computational stage 502 has already been optimized with templates. The idea is to "push" the Hadamard and phase gates to one side of the two-qubit gate as much as possible. This can be understood in the context of template applications where the fixed subsequences must match, where single-qubit gates are "push" via two-qubit gates. Figure 10 Exemplary and non-limiting templates that can be used for Hadamard and phase "push" are shown. Consider... Figure 10 Template (a) in the text. Figure 10 Template (a) can be used to "push" the H door to the right of the CNOT door. Here, it can be required that... Figure 10 The H and CNOT of template (a) must match in the circuit (indicated by a dash), and then use Figure 10 The other parts of the template (a) are replaced in reverse. In the above discussion of template matching tags, the dash can be understood as replacing the other parts of the template (a). Figure 10 The application of template (a) (e.g., which may be referred to as the "Hadamard push template") is restricted to i=0 and p=2. Note that if the circuit has already been optimized in terms of two-qubit gate counting, template matching can be applied specifically to reduce the single-qubit gate count by restricting the templates used to a subset that reduces the single-qubit gate count without reducing the two-qubit gate count. When applying a subset of the template to replace half of the entangled gates with the remainder, the subset of the template can include single-qubit templates and templates with an even number of two-qubit gates.

[0106] Figure 11A block diagram of an example non-limiting system 1100, comprising floating gate transition rules, is shown that facilitates partition template matching and / or symbol peephole optimization according to one or more embodiments described herein. As shown, in some cases, system 1100 may include the same components as system 800 and may further include floating gate transition rule 1102.

[0107] As described above, conventional template matching requires that matched gates in a circuit be continuous through commutation. If the matched gates are discontinuous, it can be said that a blocking gate is within the template matching range, which prevents the application of the intended template. In various aspects, the floating component 116 can address this problem. Specifically, if the template component 114 cannot directly apply a template from the template library 802 due to a blocking gate, the floating component 116 can take action. In various aspects, the floating component 116 can iteratively attempt to remove single-qubit gates within the template matching range (e.g., it can attempt to remove blocking gates). In various aspects, this may involve moving the blocking gate to the left of the leftmost matched gate in the circuit or to the right of the rightmost matched gate in the circuit, until all blocking gates are moved outside the template matching range or until the matched gates can be moved together.

[0108] In various aspects, the floating component 116 can electronically store, maintain, and / or otherwise access the floating gate transformation rule 1102. In various aspects, the floating gate transformation rule 1102 may include rules (e.g., equivalence relations, equations, and / or formulas) for converting phase gates and / or Hadamard gates into linear combinations of Pauli operators, and / or may include rules for converting linear combinations of Pauli operators back to single-qubit gates. Specifically, the floating gate transformation rule 1102 may include the following:

[0109]

[0110]

[0111] Operators O1 and O2 can be moved independently according to the Pauli-push equation until they are moved outside the template matching range, and until O1 and O2 are both single-qubit Pauli acting on the same qubit (e.g., the actual values ​​of O1 and O2 can change after each "push" and / or move). At this point, the floating component 116 can be... Figure 12The rules specified in Tables 1202 and 1204 convert O1 and O2 back to single-qubit gates. More specifically, Table 1202 can specify the rules for converting floating-phase gates into single-qubit gates based on the final values ​​of O1 and O2 (e.g., an S-gate can be converted into a linear combination of Pauli by the above equations, and a linear combination of Pauli can be "push" by the Pauli-push equation such that the linear combination of Pauli is outside the template matching range and acts on a single qubit, and then the linear combination of Pauli can be replaced with the result shown in Table 1202 depending on the value of the pushed linear combination of Pauli). Similarly, Table 1204 can specify rules for converting floating Hadamard gates into single-qubit gates based on the final values ​​of O1 and O2 (e.g., H gates can be converted into linear combinations of Pauli terms via the equations above, Pauli terms can be "push" via the Pauli-push equations such that the Pauli terms are outside the template-matching range and act on a single qubit, and then the pushed Pauli terms can be replaced with the results shown in Table 1204 depending on the value of the pushed Pauli terms). Note that the Pauli terms cannot be increased by pushing them through a Clifford gate to add a complex phase, and in the case of phase gates, the first term O1 will always remain the same. From these observations and since the conversion is defined only to the global phase, Tables 1202 and 1204 can be considered exhaustive. In various respects, floating gate conversion rules 1102 can include Tables 1202 and 1204, thereby allowing floating components 116 to convert floating phase gates and floating Hadamard gates back into single-qubit gates.

[0112] Figure 13 The example, in a non-limiting manner, illustrates how a blocking gate can be removed from a template matching range using a floating gate pushing method according to one or more embodiments described herein. In other words, Figure 13 An example of how the floating component 116 can work is depicted.

[0113] As shown in the figure Figure 13 Example non-limiting template 1302 and example non-limiting circuit 1304 are depicted. Note that template 1302 can be equivalent to... Figure 9 Template (e). As can be seen, the first three doors of template 1302 (e.g., CNOT) 2，1 CNOT 3，1 and CNOT 3，2 The qubits (ordered from top to bottom) are matched in circuit 1304 (e.g., circuit 1304 also has CNOTs in that order). 2，1 CNOT 3，1 and CNOT3，2 Therefore, circuit 1304 can potentially be optimized by template 1302. However, due to the S-gate in the CNOT of circuit 1304... 2，1 and CNOT 3，1 Between these conditions, template 1302 cannot be directly applied to circuit 1304. In this case, the S-gate can be considered a blocking gate (e.g., the S-gate lies between matched gates in circuit 1304, making the matched gates in circuit 1304 discontinuous; equivalently, it can be said that the S-gate is within the template matching range). Conventional template matching does not provide a solution to this problem; instead, different templates will be tried. However, the floating component 116 can solve this problem. Specifically, the floating component 116 can transform the S-gate (e.g., a non-limiting example of a blocking gate) into a linear combination of Pauli operators according to the above equation (e.g., according to the floating gate transformation rule 1102). Then, the floating component 116 can independently deduce the linear combination of Pauli operators from the template matching range via the Pauli-push equation (e.g., making the S-gate no longer within the CNOT range). 2，1 CNOT 3，1 and CNOT 3，2 (between), and this derivation can continue until the linear combination of the Pauli operators is a single-qubit gate acting on the same qubit. At this point, the floating component 116 can use the floating gate conversion rule 1102 (e.g., Table 1202, since the S-gate is floating in this example) to convert the shifted linear combination of the Pauli operators back to a single-qubit gate. Circuit 1306 can be the result of making the S-gate of circuit 1304 floating in this way. As shown, in circuit 1306, CNOT 2，1 CNOT 3，1 and CNOT 3，2 Now it's continuous, which allows template 1302 to be applied. Note that in this case, because only the S-gate floats through CNOT in this example... 3，1 and CNOT 3，2 This does not result in a qubit gate, so a floating S-gate may have to be moved through a fourth gate (e.g., CNOT). 1，3 (For example, those skilled in the art will understand how this floating is again performed via the Pauli-Push equations). In various aspects, due to the gates matched in circuit 1306 (e.g., CNOT) 2，1 CNOT 3，1 and CNOT 3，2 The gates are continuous, so template 1302 can be applied to reduce the gate count. That is, the matched gates in circuit 1306 (e.g., CNOT) are continuous. 2，1 CNOT 3，1 and CNOT 3，2This can be replaced by the inversion of other gates in template 1302. The result could be an optimized circuit 1308, which could have a lower gate count than the circuit 1304 shown.

[0114] Figure 14 A block diagram of an example non-limiting system 1400, including a SWAP equivalence relation, is shown, which can facilitate partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein. As shown, in some cases, system 1400 may include the same components as system 1100, and may also include a SWAP equivalence relation 1402.

[0115] In various embodiments, SWAP component 118 can optimize SWAP level 506 (e.g., after template component 114 and / or floating component 116 facilitate template matching on computational level 502). In various aspects, SWAP component 118 can electronically store, maintain, and / or otherwise access SWAP equivalence relation 1402, and SWAP equivalence relation 1402 can be used to facilitate SWAP optimization. Specifically, those skilled in the art will understand that a SWAP gate can be given by the following formula:

[0116]

[0117] If the SWAP gate is aligned and / or adjacent to a two-qubit gate, the SWAP gate can be implemented at the cost of an additional two-qubit gate. In other words, when the SWAP gate is implemented in series with some other two-qubit gate (e.g., CNOT and / or CZ), the resulting transformation can be equivalent to a series of other gates that do not include the SWAP gate but include a second two-qubit gate. In various aspects, the SWAP equivalence relation 1402 may include this equivalence relation, equation, and / or formula. Therefore, in various aspects, the SWAP component 118 can transfer the SWAP gate from the SWAP level 506.

[0118] "Pushing" and / or moving the SWAP gate into computational stage 502 (e.g., merging the SWAP gate back into computational stage 502 via a SWAP-push equation) aligns the SWAP gate with the biqubit gate in computational stage 502. At this point, SWAP component 118 can utilize SWAP equivalence relation 1402 to replace the moved SWAP gate and the biqubit gate aligned with a string of other gates including the biqubit gate. Figure 15 An unrestricted example of this SWAP optimization is described in the text.

[0119] Figure 15 The SWAP gate is illustrated by way of example and non-limiting manner in accordance with one or more embodiments described herein, and how a SWAP gate can be optimized at the cost of an entanglement gate. As shown in the figure, Figure 15Exemplary circuit 1502 and equivalent exemplary circuit 1504 are shown. In various aspects, circuit 1502 includes a CZ gate aligned with a SWAP gate (e.g., the CZ gate and SWAP gate are adjacent and operate on the same qubits). In various aspects, the application of equivalence relations related to the SWAP gate (e.g., the application of SWAP equivalence relation 1402) can transform circuit 1502 into circuit 1504. As shown, circuit 1504 does not have a SWAP gate, but has a second CZ gate (e.g., a second two-qubit gate). As another example, Figure 15 Exemplary circuit 1506 and equivalent exemplary circuit 1508 are depicted. In various aspects, circuit 1506 includes a CNOT gate aligned with a SWAP gate (e.g., the CNOT gate and SWAP gate are adjacent and operate on the same qubits). In various aspects, the application of equivalence relations related to the SWAP gate (e.g., the application of SWAP equivalence relation 1402) can transform circuit 1506 into circuit 1508. As shown, circuit 1508 does not have a SWAP gate, but has a second CNOT gate (e.g., a second two-qubit gate). Thus, the SWAP gate can be merged back from SWAP stage 506 to computation stage 502, and can be replaced at the cost of an additional two-qubit gate via SWAP equivalence relation 1402.

[0120] Figure 16 A block diagram of an example non-limiting system 1600 including a symbol Pauli gate, which facilitates partition template matching and / or symbol peephole optimization according to one or more embodiments described herein, is shown. As shown, in some cases, system 1600 may include the same components as system 1400 and may further include a symbol Pauli gate 1602.

[0121] As described above, conventional peephole optimization techniques rely on a database of optimal few-qubit Clifford circuits for optimizing larger Clifford circuits. However, such conventional peephole optimization techniques are limited to few-qubit sub-circuits that are completely decoupled from other qubits. In various embodiments, the symbol component 120 can address this problem (e.g., it can facilitate peephole optimization even for a small number of qubit sub-circuits that are not completely decoupled from other qubits). The symbol component 120 can do this by creating a symbolic Pauli gate 1602 in the suboptimal Clifford circuit 104 (e.g., in computational stage 502 after performing partition template matching).

[0122] Consider a Clifford circuit on n qubits expressed using standard gate sets:

[0123] C={I,X,Y,Z,H,S,CNOT}

[0124] Note that if the circuit includes a CZ gate, then as mentioned above, the CZ gate can be converted into a CNOT gate by introducing a Hadamard gate. Let C... n This represents a group of all n-qubit circuits represented by gate group C, where the cost of each gate can be defined as:

[0125] $(CNOT) = 1, and $(X) = $(Y) = $(Z) = $(H) = $(S) = 0

[0126] The cost of a circuit can be defined as the combined cost of all the gates appearing in the circuit. Symbolic peephole optimization can be considered an algorithm that takes a circuit U∈C as an example. n As input, and output the optimized circuit U′∈C n The optimized circuit implements the same Clifford operator as U (modulo the total phase) and makes $(U′A) = 1. Note that the symbolic peephole optimization can therefore focus on reducing the two-qubit gate count (e.g., as mentioned above, only CNOT gates have non-zero costs). This complements partitioned template matching well, which reduces the single-qubit gate count as described above.

[0127] Now, we will discuss more details of the symbolic peephole optimization. Consider the circuit U∈C. n and quantum bits A small subset of this makes a database of optimized Clifford circuits on |A| qubits available. The goal could be to meaningfully define and optimize the constraints of U on A, with an emphasis on settings where A is not fully decoupled from the rest of the circuit.

[0128] Let B = [n]\A be the complement of A. It is said that if a CNOT gate is coupled to A and B, then it is entangled and / or bridging. Assume, without loss of generality, that each entangled / bridging CNOT has its target qubit in A. If this is not the case, the entangled / bridging CNOT gates can be rewired and / or rewritten such that their control qubit and target qubit are switched by adding additional Hadamard gates. Figure 17 An exemplary, non-limiting illustration of this situation is shown in the figure.

[0129] like Figure 17As shown, exemplary circuit 1702 is equivalent to exemplary circuit 1704. Note that the CNOT gate in circuit 1702 has its control qubit in A and its target qubit in B. As shown, when Hadamard is implemented in parallel before and after the CNOT gate, the control qubit and target qubit can be switched. This produces circuit 1704, which may have a CNOT gate with its control qubit in B and its target qubit in A. Thus, symbol component 120 can rewrite / rewire any bridging gate by adding Hadamard such that the target qubit of the bridging gate is in A (e.g., the desired sub-circuit).

[0130] After all bridging gates have been rewired so that their targets are in A, symbol component 120 can partition the entangled / bridging CNOT gates into sets such that all CNOTs in the same set have the same control bit. Let k be the number of sets. Expand each entangled / bridging CNOT as... It can produce:

[0131]

[0132] Among them, U A (v) is achieved by preserving all gates acting on A and using the Pauli gate acting on the target qubit. The Clifford circuit obtained from U in place of each entangled / bridging CNOT gate in the i-th set. Similarly, U B (v) can be achieved by preserving all the gates acting on B and using the mapping |v| acting on the control qubit. i > <v i | Replaces each entangled / bridging CNOT from the i-th set with the (non-unitary) circuit obtained from U. In various respects, single-qubit gates can be used. and This is called a symbolic Pauli gate (e.g., symbolic Pauli gate 1602). A symbolic Pauli gate can be similar to a controlled Pauli gate, except that it is controlled by a symbolic variable v. i ∈{0,1} replaces the control qubit.

[0133] In all respects, symbol component 120 can enable the Clifford family of circuits U A ={U A (v)} v The optimization is as follows, which is a standard Clifford circuit on |A| qubits, explained below. First, U can be represented using a Clifford-plus-symbolic-Pauli-gate group. A The cost can be $(U) A ) is defined as UA The number of CNOTs plus U A The number of symbolic Pauli gates in the code. Secondly, optimization can consider U... A The symbolic Pauli gate in the time order. That is, if i < j, then it can be obtained by v. j Any symbol controlled by the Pauli gate before being applied by v i Control all symbolic Pauli gates. Third, optimization can preserve the U of each circuit. A (v) The total phase is expressed by the phase factor or For the modulus. The symbol component 120 can generate phase factors by applying single-qubit gates Z or S to control entangled / bridging CNOT qubits. These three conditions guarantee that the optimized circuit U′ can be optimized. A Upgraded to circuit U′∈C n Functionally equivalent to U. Furthermore, $(U′) = $(U) - $(U′) A )+$(U′ A ).

[0134] In various aspects, the symbol component 120 can select the subset A to be optimized. In some cases, the execution of symbol peephole optimization may be sensitive to the ordering of the qubit subset. From numerical experiments, the inventors of various embodiments of the invention have found that the most successful strategy is random subset allocation. Specifically, the symbol component 120 can generate all the qubits (For example, n is chosen to be 2, calculated via a binomial coefficient function) pairs and (For example, n is chosen as 3) A list of triples. Symbol component 120 can run passes until the optimal cost is reached (e.g., for a circuit with a known optimal cost) or until there is no improvement for two consecutive passes (e.g., the improvement drops below a predetermined threshold).

[0135] Figure 18 A simple example of how symbolic peephole optimization can be facilitated is shown. As shown in the figure, Figure 18An exemplary circuit 1802 for operating on n=2 qubits is depicted. Let A be a subset containing only the first qubit, and therefore B be the complement of A and containing only the second qubit. As shown, circuit 1802 may have two bridging CNOT gates coupling A and B. Also as shown, these two bridging CNOT gates can make their target qubits in A. As explained above, if this is not the case, the symbol component 120 can rewire / rewrite the bridging CNOT gates by applying Hadamard gates to make the target in A. In various respects, the symbol component 120 can replace each bridging CNOT gate with a symbolic Pauli gate, resulting in circuit 1804. As shown, circuit 1804 no longer has bridging CNOT gates. Instead, sub-circuit A of circuit 1804 has a symbolic Pauli-X gate (e.g., X...). v Each bridging CNOT gate was previously located at that position. Furthermore, other portions B of circuit 1804 may have non-unitary gates U. B (v) (For example, as mentioned above, this could include various mappings based on the symbolic variable v). As shown in the figure, sub-circuit U A ={X v HX v H} v It has one control bit (e.g., k=1) and contains two symbolic Pauli gates. Therefore, it is $(U A = 2. Using identifier 1806 (e.g., identifier 1806 can be obtained from any appropriate library / database of pre-calculated optimal circuits), symbol component 120 can represent subcircuit U A ={X v HX v H} v Converted to functionally equivalent to U A Sub-circuit U′ A ={HSX v i v ) v , so that $(U′ A ) = 1. Phase factor i v This can be implemented by the symbol component 120 via a single-qubit S-gate acting on B. The symbol component 120 can then boost U′. A (For example, replacing any symbolic Pauli gate with a crossover CNOT) thus produces an optimized circuit 1808.

[0136] Figure 19A block diagram of an example non-limiting system 1900, comprising a library of optimal subcircuits, is shown, which facilitates partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein. As shown, in some cases, system 1900 may include the same components as system 1600, and may also include a library 1902 of optimal circuits.

[0137] As described above, the symbol component 120 can prepare a suboptimal Clifford circuit 104 for peephole optimization by rewiring the jumper gates and / or implementing the symbol Pauli gate 1602. Then, in various aspects, the peephole component 122 can perform peephole optimization on the subcircuit containing the symbol Pauli gate 1602 by utilizing the library 1902 of the optimal circuit (e.g., the peephole component 122 can electronically store, maintain, and / or otherwise have any suitable form of access to the library 1902 of the optimal circuit).

[0138] In various aspects, the peephole assembly 122 and / or the symbol assembly 120 can be dynamically programmed to optimize the subcircuit including the symbol Pauli gate 1602. In various aspects, this dynamic programming can guarantee finding the maximum optimization for a given set of fixed qubits (e.g., for the subcircuit). This dynamic programming will now be described in detail.

[0139] Let PL(n) denote the set of Pauli operators over n qubits, and CL(n) denote the set of Clifford operators over n qubits. Consider the Clifford gate C and the symbolic Pauli gate P. v A quantum circuit is formed, where v∈{0,1} are formal variables, and P∈PL(n). A Clifford-plus-symbolic-Pauli-gate operator on n qubits containing k symbolic Pauli gates can be formed by n qubit Pauli operators P1, ... P... k The k-tuples of PL(n) and the Clifford operator R∈CL(n) are concisely specified such that:

[0140] Where, v∈{0,1} k .

[0141] The Clifford-plus-symbolic-Pauli-gate circuit that realizes U(v) has the following form:

[0142]

[0143] For some Clifford circuits, C0, ..., C k ∈CL(n) and some Pauli operators Q1, ..., Qk ∈PL(n), which satisfies:

[0144] C k ...C2C1C0=R

[0145] (C k ...C j )Q j (C k ...C j ) -1 =P j , where j = 1, ..., k.

[0146] The cost of the aforementioned Clifford-plus-symbolic-Pauli-gate circuit is defined as:

[0147]

[0148] It can be expected that the function $(C) is minimized, which pervades the Clifford operators C0, ..., C that satisfy the above conditions. k All tuples. To efficiently perform this minimization, the execution variable is changed as follows:

[0149] B j =C k ...C j , where 1≤j≤k.

[0150] Then also, And C k =B k The following conventions can be used:

[0151] B0≡R and B k+1 ≡I

[0152] Then, for all 1≤j≤k, Then implement the following:

[0153]

[0154] make Let F be a subset of the products of the Clifford set generated by a single-qubit Clifford gate. The function F can be easily checked in multiplication by B. j ←B j L j The following remains unchanged, where L j ∈LOC(n). Therefore, F depends only on the left coset B. j *LOC(n). Determine the canonical representation of each left coset, and let

[0155]

[0156] It is a set of canonical representations. By definition, the complete Clifford set is a disjoint union.

[0157]

[0158] The canonical representation of a coset can be the smallest element of the coset in lexicographical order. The following lemma gives an efficient algorithm for computing the canonical representation of a given Clifford operator: For a given Clifford operator C∈CL(n), the representation rep(C)=B∈REP(n) can be computed such that in time O(n... 3 In this case, C*LOC(n) = B*LOC(n). This can be referred to as Lemma 2.

[0159] Now, using dynamic programming methods and a pre-computed lookup table for the cost function $(B) for B∈REP(n), in B1, ..., B k Minimize the function F on ∈REP(n). That is, define intermediate objective functions f1, ..., f2. k : REP(n)→Z + Z + Represent a positive integer such that

[0160] as well as

[0161]

[0162] Finally, the following was obtained:

[0163]

[0164] The functions f1, ..., f can be calculated one by one. k The lookup table is constructed. Constructing each lookup table requires iterations over REP(n). This is feasible for n = 2, 3. Note that symbolic peephole optimization can be more resource-intensive than regular peephole optimization because it relies on a dynamic programming algorithm to ensure that all possible optimizations actually occur. That is, for each subcircuit considered, symbolic peephole optimization can perform |REP(n)| times more than one iteration in regular peephole optimization. 2 The lookup table size can be |REP(n)| = 6720, n = 3. However, the symbolic peephole optimization provides the benefit that the inspected subcircuit does not need to be completely decoupled.

[0165] Now, consider the following proof of Lemma 2. The algorithm described above for computing the minimum element of a coset in lexicographical order can be used for the selection of a specific order, as described below. A symplectic matrix C of size 2n can be formed by 4n elements of size int(C). 2 Bit parameterization. The following shows the bit order in an int(C) with n = 2, 3, and 4:

[0166]

[0167] This (along with the natural ordering of integers) defines the ordering of the Clifford operators used in various embodiments of the invention. The purpose may be to implement single-qubit Clifford gates V1, ..., V n The above makes int(C*V1V2...V n Minimize, where the single-qubit gate V q This is applied to qubit q. For each qubit q, the single-qubit Clifford operator G can be tracked. q A subset of V, from which to select V q , so that:

[0168] G q ={H, S, HSH} or G q ={HSH} or

[0169] Each step of the algorithm checks a pair of entries (C) i，q C i，q+n The single-qubit Pauli operator is parameterized according to the following formula:

[0170] I=(0,0), X=(1,0), Z=(0,1), Y=(1,1)

[0171] The selected order of the Clifford operator corresponds to the order of the single-qubit Pauli operator:

[0172] I < X < Z < Y

[0173] For each row of the symplectic matrix C and for each qubit, the algorithm attempts to map Y or Z to X by applying S or H respectively. If this is possible (e.g., the application of a gate will perform the desired transformation, and the corresponding gate is contained in G), the algorithm will map the transformation to X. q (in the middle), then the group G q Set to G q ←{HSH}. If this is not possible, the algorithm attempts to map Y to Z by applying HSH. If this is possible, the group is updated to... It can be easily verified that the algorithm does indeed return the smallest element of the coset C*LOC(n). Each multiplication C←CS q C←CHq and C←CH q S q H q The time required is O(n). Since the number of multiplications is O(n) 2 Therefore, the total running time is O(n^2). 3 ).

[0174] Figure 20-21 Flowcharts of example non-limiting computer implementations of methods 2000 and 2100 that facilitate partition template matching and / or symbolic peephole optimization according to one or more embodiments described herein are shown.

[0175] First, consider the computer-implemented method 2000. In different embodiments, action 2002 may include performing template matching on a Clifford circuit (e.g., 104) associated with a set of qubits via a device (e.g., 114) operatively coupled to a processor.

[0176] In various aspects, action 2004 may include dividing the Clifford circuitry into a computational level (e.g., 502), a Pauli level (e.g., 504), and a SWAP level (e.g., 506) by a device (e.g., 112) prior to template matching, wherein template matching can be performed at the computational level (e.g., Figure 7 (Example of the division shown).

[0177] In different instances, action 2006 may include selecting a subset (e.g., A) of qubits from the set of qubits by a device (e.g., 120).

[0178] In various cases, action 2008 may include rewiring at least one entangled gate (e.g., CNOT and / or CZ) in a computational stage by a device (e.g., 120) such that the target of at least one entangled gate is in that subset of qubits (e.g., via an application such as...). Figure 17 The image shows Hadamard.

[0179] In various aspects, action 2010 may include replacing at least one rewired entangled gate with a symbolic Pauli gate (e.g., 1602) by a device (e.g., 120), wherein the symbolic Pauli gate is a Pauli gate (e.g., controlled by a symbolic variable) that is controlled by a symbolic variable. Figure 18 (Example of the replacement shown).

[0180] In various instances, action 2012 may include peephole optimization performed by a device (e.g., 122) on a subset of qubits with sign Pauli gates by implementing a dynamic programming algorithm (e.g., by utilizing a library of optimal circuits 1902). For a fixed set of qubits undergoing peephole optimization, the optimization itself may be guided by the aforementioned dynamic programming algorithm.

[0181] although Figure 20 Not shown, but in some cases, the computer-implemented method 2000 may also include replacing the blocking gate (e.g., by a device (e.g., 116) with a linear combination of Pauli operators) by replacing the blocking gate. Figure 13 The S in the calculation level is used to derive the template matching range.

[0182] although Figure 20 Not shown, but in some cases, the computer-implemented method 2000 may also include repartitioning of the Clifford circuit by a device (e.g., 112) when template matching is performed in the computational level to generate Pauli gates or SWAP gates in the computational level.

[0183] Next, consider the computer-implemented method 2100. In different embodiments, action 2102 may include performing peephole optimization on a Clifford circuit (e.g., 104) associated with a set of qubits via a device (e.g., 122) operatively coupled to the processor.

[0184] In different aspects, action 2104 may include selecting a subset of qubits from the set of qubits by a device (e.g., 120).

[0185] In various instances, action 2106 may include rewiring at least one entangled gate (e.g., CNOT and / or CZ) in a Clifford circuit by a device (e.g., 120) such that the target of at least one entangled gate is in a subset of qubits (e.g., via an application such as...). Figure 17 The image shows Hadamard.

[0186] In various cases, action 2108 may include, by device (e.g., 120) and prior to peephole optimization, using a symbolic Pauli gate (e.g., Figure 18 The 1602 shown replaces at least one rewired entangled gate.

[0187] In various aspects, action 2110 may include dividing the Clifford circuitry into a computational level (e.g., 502), a Pauli level (e.g., 504), and a SWAP level (e.g., 506) by a device (e.g., 112).

[0188] In various instances, action 2112 may include template matching performed at the computational level by a device (e.g., 114) prior to rewiring at least one entangled gate.

[0189] Despite Figure 21 Not shown, but in some cases, the computer-implemented method 2100 may also include replacing the blocking gate (e.g., by a device (e.g., 116) with a linear combination of Pauli operators) by replacing the blocking gate (e.g., Figure 13 The S in the calculation level is used to derive the template matching range.

[0190] Despite Figure 21 Not shown, but in some cases, the computer-implemented method 2100 may also include repartitioning of the Clifford circuit by a device (e.g., 112) when template matching is performed in the computational level to generate Pauli gates or SWAP gates in the computational level.

[0191] The inventors of various embodiments of the present invention conducted various experiments and / or numerical simulations, the results of which confirmed that the embodiments of the present invention outperform conventional Clifford optimization techniques. The experiments / simulations involved generating 993 uniformly sampled randomized Clifford unitaries, where the CNOT cost was between 5 and 15. For costs from 5 to 14, the inventors considered 99 circuits for each cost value. For cost = 15, only 3 Clifford circuits existed (with modulo single-qubit Clifford on the left and right sides and modulo qubit swapping). For each Clifford unitary, the inventors synthesized it using the aforementioned baseline compiler and 9 randomized compilers, resulting in a total of 10 different initial circuits. Optimization (e.g., partitioned template matching and symbolic peephole optimization) was then performed on these 10 circuits, and the best result was selected. The inventors found that exact optimal cost was achieved for 90.2% of the circuits, while introducing only about 1% overhead in the CNOT cost on average.

[0192] The inventors also applied the described optimization techniques to the encoding circuitry of quantum error-correcting codes (QECC) to see how embodiments of the invention would work in practical, relevant circuitry. Encoding circuitry for QECC was obtained by starting with a stabilizer generator for the code and generating the corresponding circuitry using the Clifford circuit synthesis algorithm. These circuits were recompiled using a baseline compiler, and then optimizations (e.g., partition template matching and symbolic peephole optimization) were performed. The inventors found that the introduction of floating gates resulted in an average improvement of approximately 2.6% in the two-qubit gate count due to the application of additional templates implemented via floating gates. Furthermore, an average improvement of 64.5% was achieved relative to the reference circuitry and an average improvement of 35.4% relative to the circuit synthesized using the baseline compiler. The inventors also noted that the quality of the improvements produced by the various embodiments of the invention did not deteriorate with problem size (e.g., the improvement relative to the baseline compiler remained stable at approximately 35% even for a number of qubits greater than 12). The inventors also discovered that the combinatorial algorithm described in this paper may take only a few seconds for a small number of qubits (e.g., an average running time of 2.42 seconds for n=5), but may take up to tens of minutes for a large number of qubits.

[0193] In summary, various embodiments of the present invention can be considered as two novel algorithms for Clifford circuit optimization: (1) partitioned template matching; and (2) symbolic peephole optimization. Partitioned template matching can be considered as a Clifford-specific extension of conventional template matching, which utilizes the unique properties of Clifford to further reduce the gate count. Specifically, partitioned template matching may include dividing the Clifford circuit into three distinct stages (e.g., computation, Pauli, and SWAP), performing template matching on one of these distinct stages (e.g., computation), and eliminating SWAP gates via alignment with the other two qubit gates. Furthermore, various embodiments of the present invention may include floating gate techniques that can be used to remove blocking gates from the desired template matching range. Symbolic peephole optimization can be considered as an improved version of peephole optimization that does not require complete decoupling to function. Specifically, symbolic peephole optimization may include identifying the desired sub-circuit, rewiring any bridging gates such that their targets are in the sub-circuit, and then replacing the rewiring bridging gates with symbolic Pauli gates controlled by symbolic variables rather than by other qubits.

[0194] Throughout this disclosure, various variables, symbols, and / or mathematical notations are used to aid in describing embodiments of the invention. In some instances, the same variable / symbol may have different meanings when used in different parts of this specification (e.g., in some places, i is used to represent an imaginary number, and in others, i is used to represent an index; in some places, D is used to represent a particular algorithm and / or function, and in others, D is used to represent a subset of qubits; in some cases, C is used to represent various Clifford circuits and / or Clifford gate groups, and in others, C is used to represent a subset of qubits; etc.). Those skilled in the art will understand that the same variable / symbol may have different meanings when used in different contexts / modes.

[0195] To provide additional context for the various embodiments described herein, Figure 22 The following discussion is intended to provide a brief overview of a suitable computing environment 2200 in which various embodiments of the embodiments described herein can be implemented. The embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, and those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules and / or as a combination of hardware and software.

[0196] Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will understand that the methods of this invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframes, Internet of Things (IoT) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, each of which can be operatively coupled to one or more associated devices.

[0197] The embodiments illustrated herein can also be practiced in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0198] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, these two terms being used differently from each other herein. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium accessible by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium or a machine-readable storage medium may be implemented in conjunction with any method or technique used for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0199] Computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, optical disc read-only memory (CDROM), digital versatile disc (DVD), Blu-ray disc (BD) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, solid-state drives or other solid-state storage devices, or other tangible and / or non-transitory media that can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” as used herein with respect to storage devices, memories, or computer-readable media shall be understood to exclude only the propagation of transient signals themselves as a modifier, and shall not waive the rights to all standard storage devices, memories, or computer-readable media that do not only propagate transient signals themselves.

[0200] A computer-readable storage medium can be accessed by one or more local or remote computing devices, for example via access requests, queries or other data retrieval protocols, in order to perform various operations on the information stored on the medium.

[0201] Communication media typically embody computer-readable instructions, data structures, program modules, or other structured or unstructured data in the form of data signals such as modulated data signals, via carrier waves or other transmission mechanisms, and include any information transmission or delivery medium. The term "modulated data signal" or signal refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in one or more signals. By way of example and not limitation, communication media include wired media, such as wired networks or direct-wire connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0202] Refer again Figure 22An example environment 2200 for implementing the various embodiments of the aspects described herein includes a computer 2202, which includes a processing unit 2204, system memory 2206, and a system bus 2208. The system bus 2208 couples system components, including but not limited to system memory 2206, to the processing unit 2204. The processing unit 2204 can be any of a variety of commercially available processors. Dual-microprocessor and other multiprocessor architectures may also be used as the processing unit 2204.

[0203] System bus 2208 can be any of several bus architectures, which can also interconnect to memory buses (with or without memory controllers), peripheral buses, and local buses using any of the various commercially available bus architectures. System memory 2206 includes ROM 2210 and RAM 2212. The Basic Input / Output System (BIOS) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), EEPROM, etc., where the BIOS contains basic routines that help transfer information between components within computer 2202, such as during startup. RAM 2212 can also include high-speed RAM such as static RAM for caching data.

[0204] Computer 2202 also includes an internal hard disk drive (HDD) 2214 (e.g., EIDE, SATA), one or more external storage devices 2216 (e.g., floppy disk drive (FDD) 2216, memory stick or flash drive reader, memory card reader, etc.), and drives 2220, such as solid-state drives or optical disc drives, which can read from or write to disks 2222 such as CD-ROMs, DVDs, BDs, etc. Alternatively, disks 2222 may not be included where solid-state drives are involved, unless they are separate. Although the internal HDD 2214 is shown located within computer 2202, the internal HDD 2214 may also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in environment 2200, solid-state drives (SSDs) may be used in addition to or as a replacement for HDD 2214. HDD 2214, (multiple) external storage devices 2216, and drive 2220 can be connected to system bus 2208 via HDD interface 2224, external storage interface 2226, and drive interface 2228, respectively. Interface 2224 for the external drive implementation may include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the scope of the embodiments described herein.

[0205] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 2202, the drive and storage medium accommodate storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to a corresponding type of storage device, those skilled in the art will understand that other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the example operating environment, and furthermore, any such storage medium may include computer-executable instructions for performing the methods described herein.

[0206] Multiple program modules may be stored in the drive and RAM 2212, including an operating system 2230, one or more application programs 2232, other program modules 2234, and program data 2236. All or part of the operating system, applications, modules, and / or data may also be cached in RAM 2212. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0207] Computer 2202 may optionally include emulation technology. For example, a system management program (not shown) or other intermediary may emulate a hardware environment for operating system 2230, and the emulated hardware may optionally be compatible with... Figure 22 The hardware shown differs. In this example, operating system 2230 may include one of a plurality of virtual machines (VMs) hosted at computer 2202. Furthermore, operating system 2230 may provide a runtime environment, such as the Java Runtime Environment or the .NET Framework, for application 2232. A runtime environment is a consistent execution environment that allows application 2232 to run on any operating system that includes that runtime environment. Similarly, operating system 2230 may support containers, and application 2232 may be in the form of a container, which is a lightweight, standalone, executable package of software that includes, for example, code, runtime, system tools, system libraries, and application setup.

[0208] Furthermore, computer 2202 can be enabled using a security module such as a Trusted Processing Module (TPM). For example, using a TPM, the boot component hashes the next boot component in time and waits for the result to match a security value before loading the next boot component. This process can occur at any layer of the computer 2202's code execution stack, for example, at the application execution level or at the operating system (OS) kernel level, thereby allowing security at any code execution level.

[0209] Users can input commands and information to computer 2202 through one or more wired / wireless input devices, such as keyboard 2238, touchscreen 2240, and pointing devices such as mouse 2242. Other input devices (not shown) may include microphones, infrared (IR) remote controls, radio frequency (RF) remote controls, or other remote controls, joysticks, virtual reality controllers and / or virtual reality headsets, gaming pads, pointers, image input devices (e.g., cameras), gesture sensor input devices, visual motion sensor input devices, emotion or face detection devices, biometric input devices (e.g., fingerprint or iris scanners), etc. These and other input devices are typically connected to processing unit 2204 via input device interface 2244, which can be coupled to system bus 2208, but may also be connected via other interfaces, such as parallel ports, IEEE 1394 serial ports, gaming ports, USB ports, IR interfaces, Bluetooth, etc. Interfaces, etc.

[0210] Monitor 2246 or other types of display devices may also be connected to system bus 2208 via an interface such as video adapter 2248. In addition to monitor 2246, the computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

[0211] Computer 2202 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 2250) via wired and / or wireless communications. Remote computer 2250 can be a workstation, server computer, router, personal computer, laptop computer, microprocessor-based entertainment device, peer-to-peer device, or other common network node, and typically includes many or all of the elements described relative to computer 2202, although only memory / storage device 2252 is shown for simplicity. The depicted logical connections include wired / wireless connections to a local area network (LAN) 2254 and / or a larger network (e.g., a wide area network (WAN) 2256). This LAN and WAN networking environment is common in offices and companies and facilitates enterprise-wide computer networks such as intranets, all of which can connect to global communication networks such as the Internet.

[0212] When used in a LAN network environment, computer 2202 can connect to local network 2254 via a wired and / or wireless communication network interface or adapter 2258. Adapter 2258 facilitates wired or wireless communication to LAN 2254, which may also include a wireless access point (AP) configured thereon for communicating with adapter 2258 in wireless mode.

[0213] When used in a WAN network environment, computer 2202 may include modem 2260, or may be connected to a communication server on WAN 2256 via other means, to establish communication over WAN 2256 (such as via the Internet). Modem 2260 may be built-in or external, and may be a wired or wireless device, connected to system bus 2208 via input device interface 2244. In a networked environment, program modules described relative to computer 2202 or parts thereof may be stored in remote memory / storage device 2252. It is understood that the network connection shown is an example, and other means for establishing communication links between computers may be used.

[0214] When used in a LAN or WAN networking environment, computer 2202 can access cloud storage systems or other network-based storage systems as a supplement to or replacement for external storage device 2216 as described above, such as, but not limited to, network virtual machines that provide storage or processing of one or more aspects of information. Typically, the connection between computer 2202 and the cloud storage system can be established, for example, on LAN 2254 or WAN 2256 via adapter 2258 or modem 2260, respectively. When computer 2202 is connected to the associated cloud storage system, external storage interface 2226 can manage the storage provided by the cloud storage system with the help of adapter 2258 and / or modem 2260, just as it would manage other types of external storage. For example, external storage interface 2226 can be configured to provide access to cloud storage sources as if these sources were physically connected to computer 2202.

[0215] Computer 2202 can be used to communicate with any wireless device or entity operationally configured for wireless communication, such as printers, scanners, desktop and / or laptop computers, portable data assistants, communication satellites, any device or location associated with a wirelessly detectable tag (e.g., phone booths, newsstands, store shelves, etc.), and telephones. This can include Wi-Fi and Bluetooth. Wireless technology. Therefore, communication can be a predefined structure like a regular network, or simply self-organizing communication between at least two devices.

[0216] Now for reference Figure 23The diagram illustrates a schematic cloud computing environment 2300. As shown, the cloud computing environment 2300 includes one or more cloud computing nodes 2302 to which local computing devices used by cloud consumers (e.g., personal digital assistants (PDAs) or cellular phones 2304, desktop computers 2306, laptop computers 2308, and / or automotive computer systems 2310) can communicate. The nodes 2302 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 2300 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 23 The types of computing devices 2304-2310 shown are merely exemplary, and computing node 2302 and cloud computing environment 2300 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0217] Now for reference Figure 24 This demonstrates the 2300 cloud computing environment ( Figure 23 This provides a set of functional abstraction layers. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. It will be understood beforehand that... Figure 24 The components, layers, and functions shown are for illustrative purposes only, and embodiments of the invention are not limited thereto. As described, the following layers and corresponding functions are provided.

[0218] The hardware and software layer 2402 includes hardware and software components. Examples of hardware components include: a host 2404; a server 2406 based on a RISC (Reduced Instruction Set Computer) architecture; a server 2408; a blade server 2410; a storage device 2412; and a network and network components 2414. In some embodiments, software components include network application server software 2416 and database software 2418.

[0219] The virtualization layer 2420 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 2422; virtual storage 2424; virtual network 2426, including virtual private network; virtual application and operating system 2428; and virtual client 2430.

[0220] In one example, management layer 2432 can provide the functionality described below. Resource provisioning 2434 provides dynamic procurement of computing resources and other resources used to perform tasks in the cloud computing environment. Metering and pricing 2436 provides cost tracking when utilizing resources in the cloud computing environment, as well as billing or invoicing for consuming these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 2438 provides access to the cloud computing environment for consumers and system administrators. Service level management 2440 provides cloud resource allocation and management to ensure that required service levels are met. Service level agreement (SLA) planning and fulfillment 2442 provides pre-scheduling and procurement of cloud resources, where future needs are anticipated according to the SLA.

[0221] Workload layer 2444 provides examples of functionalities that can leverage a cloud computing environment. Examples of workloads and functionalities that can be provided from this layer include: map creation and navigation 2446; software development and lifecycle management 2448; virtual classroom education delivery 2450; data analysis and processing 2452; transaction processing 2454; and differential private federated learning processing 2456. Various embodiments of the invention can be found using references. Figure 23 and 24 The cloud computing environment described herein is used to execute one or more differential private federated learning processes according to the various embodiments described herein.

[0222] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0223] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of the invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of the computer-readable program instructions.

[0224] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of manufacture comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational actions to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0225] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a non-consecutive order as shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0226] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure can also be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some, if not all, aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0227] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities related to an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, an application running on a server and the server itself may both be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another example, a corresponding component may be executable from various computer-readable media on which various data structures are stored. Components may communicate via local and / or remote processes, for example, based on signals having one or more data packets (e.g., data from a component via which it interacts with a local system, another component in a distributed system, and / or with other systems via a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical components operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a device that provides specific functions through electronic components rather than mechanical components, wherein the electronic components can include a processor or other device to execute software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example within a cloud computing system.

[0228] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to indicate any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it imply exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0229] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can employ nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "database," and substantially any other information storage component, in relation to the operation and function of a component, are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may be used as external cache memory. For example, by way of illustration and not limitation, RAM may be available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the computer-implemented methods or systems disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0230] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components or computer-implemented methods in order to describe this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term “comprising” is interpreted when used as a transitional word in the claims.

[0231] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system comprising: A processor that executes a computer-executable component stored in a computer-readable storage memory, the computer-executable component comprising: Template components that perform template matching on a Clifford circuit associated with a set of qubits; and A partitioning component that divides the Clifford circuit into a computational level, a Pauli level, and a SWAP level prior to the template matching, wherein the template matching is performed at the computational level, and The computational stage includes all Hadamard gates, all phase gates, and all controlled NOT gates of the Clifford circuit, but does not include any Pauli gates or any SWAP gates of the Clifford circuit. The Pauli stage includes all Pauli gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any SWAP gates of the Clifford circuit; and The SWAP stage includes all SWAP gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any Pauli gates of the Clifford circuit.

2. The system according to claim 1, further comprising: A floating component that pushes the blocking gate outside the template matching range in the computation level by replacing the blocking gate with a linear combination of Pauli gates.

3. The system according to claim 1, wherein, When the template matching is performed in the computation level to generate a Pauli gate or a SWAP gate in the computation level, the partitioning component repartitions the Clifford circuit.

4. The system according to any one of claims 1 to 3, further comprising: A symbolic component selects a subset of qubits from the set of qubits, rewires at least one entangled gate in the computational stage such that the target of the at least one entangled gate is in the subset of qubits, and replaces the at least one rewired entangled gate with a symbolic Pauli gate, wherein the symbolic Pauli gate is a Pauli gate controlled by a symbolic variable.

5. The system according to claim 4, further comprising: A peephole assembly that performs peephole optimization on a subset of the qubits having the symbolic Pauli gate by implementing a dynamic programming algorithm.

6. A computer-implemented method, comprising: Template matching is performed on a Clifford circuit associated with a set of qubits via a device operatively coupled to the processor. as well as The device divides the Clifford circuit into a computational level, a Pauli level, and a SWAP level prior to the template matching, wherein the template matching is performed at the computational level. The computational stage includes all Hadamard gates, all phase gates, and all controlled NOT gates of the Clifford circuit, but does not include any Pauli gates or any SWAP gates of the Clifford circuit. The Pauli stage includes all Pauli gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any SWAP gates of the Clifford circuit; and The SWAP stage includes all SWAP gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any Pauli gates of the Clifford circuit.

7. The computer-implemented method according to claim 6, further comprising: The device pushes the blocking gate outside the template matching range in the computation level by replacing the blocking gate with a linear combination of Pauli gates.

8. The computer-implemented method according to claim 6, further comprising: When the template matching is performed in the computing level and a Pauli gate or a SWAP gate is generated in the computing level, the Clifford circuit is repartitioned by the device.

9. The computer-implemented method according to any one of claims 6 to 8, further comprising: The device selects a subset of qubits from the set of qubits; The device rewires at least one entangled gate in the computing stage such that the target of the at least one entangled gate is a subset of the qubits; as well as The device replaces the at least one rewired entangled gate with a symbolic Pauli gate, wherein the symbolic Pauli gate is a Pauli gate controlled by a symbolic variable.

10. The computer-implemented method according to claim 9, further comprising: The device performs peephole optimization on a subset of the qubits with the symbol Pauli gate by implementing a dynamic programming algorithm.

11. A computer program product for facilitating partition template matching and symbolic peephole optimization, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to cause the processor to: The processor performs template matching on the Clifford circuit associated with a set of qubits; and The processor, prior to template matching, divides the Clifford circuit into a computational level, a Pauli level, and a SWAP level, wherein... Perform the template matching at the computational level, and The computational stage includes all Hadamard gates, all phase gates, and all controlled NOT gates of the Clifford circuit, but does not include any Pauli gates or any SWAP gates of the Clifford circuit. The Pauli stage includes all Pauli gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any SWAP gates of the Clifford circuit; and The SWAP stage includes all SWAP gates of the Clifford circuit, but excludes any Hadamard gates, any phase gates, any controlled NOT gates, and any Pauli gates of the Clifford circuit.

12. The computer program product according to claim 11, wherein, The program instructions are further executable to cause the processor to: The processor pushes the blocking gate outside the template matching range in the computation level by replacing the blocking gate with a linear combination of Pauli gates.

13. The computer program product according to claim 11, wherein, The program instructions are further executable to cause the processor to: When the template matching is performed in the computing level and a Pauli gate or a SWAP gate is generated in the computing level, the Clifford circuit is repartitioned by the processor.

14. The computer program product according to any one of claims 11 to 13, wherein, The program instructions are further executable to cause the processor to: The processor selects a subset of qubits from the set of qubits; The processor rewires at least one entangled gate in the computing stage such that the target of the at least one entangled gate is a subset of the qubits; as well as The processor replaces the at least one rewired entangled gate with a symbolic Pauli gate, wherein the symbolic Pauli gate is a Pauli gate controlled by a symbolic variable.

15. The computer program product according to claim 14, wherein, The program instructions are further executable to cause the processor to: The processor performs peephole optimization on a subset of the qubits with the symbol Pauli gate by implementing a dynamic programming algorithm.

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