Display substrate, preparation method thereof and display device

Abstract

A display substrate includes: a substrate (30), and a driving circuit layer, a first planarization layer (35), and an organic encapsulation layer (42) sequentially disposed on the substrate (30). The first planarization layer (35) has a first isolation trench (350) in a peripheral region (B1). The organic encapsulation layer (42) includes a first portion (421) and a second portion (422) located in the peripheral region (B1). The second portion (422) is located on the side of the first portion (421) near the display area (AA). The second portion (422) has a first height, and the height of the first portion (421) gradually decreases from the first height to a second height along a direction away from the display area (AA). The first isolation trench (350) is located on the side of the first portion (421) near the display area (AA). The orthographic projection of at least one of the first portion (421) and the second portion (422) of the organic encapsulation layer (42) onto the substrate (30) covers the orthographic projection of the first isolation trench (350) onto the substrate (30).

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate, and a driving circuit layer, a first planarization layer, and an organic encapsulation layer sequentially disposed on the substrate. The substrate includes a display area and a peripheral area at least partially surrounding the display area. The driving circuit layer is located in the peripheral area. The first planarization layer has a first isolation trench in the peripheral area. The organic encapsulation layer includes a first portion and a second portion located in the peripheral area. The second portion is located on the side of the first portion closer to the display area. The second portion has a first height, and the height of the first portion gradually decreases from the first height to a second height along a direction away from the display area. The first height is greater than the second height. The first isolation trench is located on the side of the first portion closer to the display area. At least one of the first portion and the second portion of the organic encapsulation layer, in its orthographic projection onto the substrate, covers the orthographic projection of the first isolation trench onto the substrate.

[0006] In some exemplary embodiments, the display substrate further includes a second planarization layer located on the side of the first planarization layer away from the substrate. The second planarization layer has a second isolation trench in the peripheral region, and the orthographic projection of the second isolation trench onto the substrate at least partially overlaps with the orthographic projection of the first isolation trench onto the substrate.

[0007] In some exemplary embodiments, the orthographic projection of the second isolation trench onto the substrate includes the orthographic projection of the first isolation trench onto the substrate.

[0008] In some exemplary embodiments, in the peripheral region, the first isolation groove extends along a direction parallel to the edge of the display area.

[0009] In some exemplary embodiments, the first isolation trench has a first width, which is 4 micrometers to 15 micrometers, along a direction away from the display area. The first isolation trench has a first depth, which is 1.5 micrometers to 3.5 micrometers, in a direction perpendicular to the substrate.

[0010] In some exemplary embodiments, the peripheral area includes a plurality of circuit areas arranged sequentially along a direction away from the display area, wherein the first isolation slot is located between two adjacent circuit areas.

[0011] In some exemplary embodiments, the plurality of circuit areas in the peripheral area include: a first circuit area, a second circuit area, and a third circuit area arranged sequentially along a direction away from the display area; or, a first circuit area and a second circuit area arranged sequentially along a direction away from the display area. The first isolation groove is located between the first circuit area and the second circuit area.

[0012] In some exemplary embodiments, the plurality of circuit areas in the peripheral area includes at least a first circuit area, a second circuit area, and a third circuit area arranged sequentially along a direction away from the display area. The first isolation groove is located between the second circuit area and the third circuit area.

[0013] In some exemplary embodiments, the first circuit region is provided with a first driving circuit and a plurality of first signal lines providing control signals to the first driving circuit, and the second circuit region is provided with a second driving circuit and a plurality of second signal lines providing control signals to the second driving circuit. The first isolation trench is located between the first signal lines and the second driving circuit in the orthographic projection of the substrate.

[0014] In some exemplary embodiments, the plurality of first signal lines include at least a first initial signal line providing a first initial signal to the first driving circuit; the plurality of second signal lines include at least a first power supply line providing a first voltage signal to the second driving circuit. The first isolation trench has a first distance between its edge near the display area in the orthographic projection of the substrate and the edge of the first initial signal line away from the display area in the orthographic projection of the substrate. The first isolation trench has a second distance between its edge away from the display area in the orthographic projection of the substrate and the edge of the first power supply line near the display area in the orthographic projection of the substrate. The first distance is less than the second distance.

[0015] In some exemplary embodiments, the first distance is 3.5 micrometers to 4.5 micrometers, and the second distance is 5.5 micrometers to 7.2 micrometers.

[0016] In some exemplary embodiments, the first driving circuit is electrically connected to a plurality of first output signal lines, and the second driving circuit is electrically connected to a plurality of second output signal lines; the third circuit area is provided with a third driving circuit, and the third driving circuit is electrically connected to a plurality of third output signal lines; the first output signal lines, the second output signal lines, and the third output signal lines extend toward the display area. The orthographic projection of the first isolation trench on the substrate overlaps with the orthographic projections of the plurality of second output signal lines and the plurality of third output signal lines on the substrate.

[0017] In some exemplary embodiments, the display area is provided with a plurality of pixel circuits. The first driving circuit is configured to provide a reset control signal to the plurality of pixel circuits in the display area via the first output signal line. The second driving circuit is configured to provide a scan signal to the plurality of pixel circuits in the display area via the second output signal line. The third driving circuit is configured to provide a light emission control signal to the plurality of pixel circuits in the display area via the third output signal line.

[0018] In some exemplary embodiments, the display substrate further includes: a first inorganic encapsulation layer located on the side of the organic encapsulation layer near the substrate, a second inorganic encapsulation layer located on the side of the organic encapsulation layer away from the substrate, and a touch structure layer located on the side of the second inorganic encapsulation layer away from the substrate. The touch structure layer includes multiple touch leads in its peripheral region. The orthographic projection of the first isolation trench on the substrate does not overlap with the orthographic projection of the touch leads on the substrate, or the orthographic projection of the first isolation trench on the substrate overlaps with the orthographic projection of at least one touch lead on the substrate.

[0019] In some exemplary embodiments, the plurality of touch leads includes: a plurality of first touch leads, an isolation lead, and a plurality of second touch leads arranged sequentially along a direction away from the display area. Along the direction away from the display area, the isolation lead has a second width, the first touch leads have a third width, and the second touch leads have a fourth width. The second width is greater than the third width and also greater than the fourth width.

[0020] In some exemplary embodiments, the width of the first portion of the organic encapsulation layer is 500 to 1000 micrometers along a direction away from the display area.

[0021] In some exemplary embodiments, the first height is 28 micrometers to 42 micrometers.

[0022] In some exemplary embodiments, the second height is 20 micrometers to 30 micrometers.

[0023] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0024] On the other hand, this disclosure provides a method for fabricating a display substrate. The display substrate includes a display area and a peripheral area at least partially surrounding the display area. The fabrication method includes: forming a driving circuit layer in the peripheral area of ​​a substrate; forming a first planarization layer on the side of the driving circuit layer away from the substrate, the first planarization layer having a first isolation trench in the peripheral area; and forming an organic encapsulation layer on the side of the first planarization layer away from the substrate. The organic encapsulation layer includes a first portion and a second portion located in the peripheral area, the second portion being located on the side of the first portion closer to the display area; the second portion having a first height, the height of the first portion gradually decreasing from the first height to a second height along a direction away from the display area. The first height is greater than the second height. The first isolation trench is located on the side of the first portion closer to the display area, and at least one of the first portion and the second portion of the organic encapsulation layer, in its orthographic projection onto the substrate, covers the orthographic projection of the first isolation trench onto the substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a display device according to at least one embodiment of the present disclosure;

[0028] Figure 2 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 3 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0030] Figure 4 for Figure 3 The provided timing diagram for the pixel circuit;

[0031] Figure 5 This is a schematic diagram of the planar structure of the peripheral region of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 6 for Figure 2 A partial cross-sectional schematic diagram along the P-P' direction;

[0033] Figure 7 This is an equivalent circuit diagram of the first sub-driving circuit of at least one embodiment of the present disclosure;

[0034] Figure 8 for Figure 7 The timing diagram of the first sub-driver circuit shown is shown below;

[0035] Figure 9 This is a partial top view of the surrounding area of ​​at least one embodiment of the present disclosure;

[0036] Figure 10 for Figure 9 A partial cross-sectional view along the Q-Q' direction;

[0037] Figure 11 This is a partial planar schematic diagram of the peripheral region after the formation of the driving circuit layer according to at least one embodiment of the present disclosure;

[0038] Figure 12 This is a partial planar schematic diagram of the surrounding area after the formation of the first planarization layer according to at least one embodiment of the present disclosure;

[0039] Figure 13 This is a partial planar schematic diagram of the surrounding area after the formation of the fourth conductive layer according to at least one embodiment of the present disclosure;

[0040] Figure 14 This is a partial planar schematic diagram of the surrounding area after the formation of the second planarization layer according to at least one embodiment of the present disclosure;

[0041] Figure 15 for Figure 2 Another partial cross-sectional view along the P-P' direction;

[0042] Figure 16 This is another partial planar schematic diagram of the surrounding area after the formation of the second planarization layer according to at least one embodiment of the present disclosure;

[0043] Figure 17 This is a schematic diagram of another planar structure of the peripheral region of a display substrate according to at least one embodiment of the present disclosure;

[0044] Figure 18 for Figure 2 Another partial cross-sectional view along the P-P' direction;

[0045] Figure 19 for Figure 2 Another partial cross-sectional view along the P-P' direction;

[0046] Figure 20 for Figure 2 Another partial cross-sectional view along the P-P' direction;

[0047] Figure 21 This is a schematic diagram of another planar structure of the peripheral region of a display substrate according to at least one embodiment of the present disclosure;

[0048] Figure 22 for Figure 2 Another partial cross-sectional view along the P-P' direction;

[0049] Figure 23 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0050] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0051] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0052] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0053] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0054] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0055] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0056] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0058] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0059] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0060] With the development of flexible OLED display technology and the need for cost reduction, more and more OLED display panels are adopting touch structures integrated with the backplane (e.g., Flexible Multiple Layer on Cell (FMLOC) technology) rather than external touch structures. The FMLOC process involves fabricating a metal mesh-shaped touch electrode layer on the encapsulation layer of the display panel's backplane to achieve touch control. Simultaneously, a touch wiring layer connected to the touch electrode layer is fabricated in the non-display area of ​​the display panel. To prevent moisture intrusion into the display area, waterproof grooves are typically designed in the non-display area of ​​the backplane. However, the design of these waterproof grooves creates height differences in the non-display area, which can lead to metal residue in the touch wiring layer at these height differences, causing short circuits.

[0061] This disclosure provides a display substrate, including: a substrate, and a driving circuit layer, a first planarization layer, and an organic encapsulation layer sequentially disposed on the substrate. The substrate includes a display area and a peripheral area at least partially surrounding the display area. The driving circuit layer is located in the peripheral area. The first planarization layer has a first isolation trench in the peripheral area. The organic encapsulation layer includes a first portion and a second portion located in the peripheral area, with the second portion located on the side of the first portion closer to the display area. The second portion has a first height, and the height of the first portion gradually decreases from the first height to a second height along a direction away from the display area. The first height is greater than the second height. The first isolation trench is located on the side of the first portion closer to the display area. At least one of the second portion and the first portion of the organic encapsulation layer, in its orthographic projection onto the substrate, covers the orthographic projection of the first isolation trench onto the substrate.

[0062] In this disclosure, "height" refers to the vertical distance between the surface of the film layer away from the substrate and the substrate in a direction perpendicular to the display substrate. For example, the height of the organic encapsulation layer is the vertical distance between the surface of the organic encapsulation layer away from the substrate and the substrate in a direction perpendicular to the display substrate.

[0063] The display substrate provided in this embodiment forms a first isolation trench in the first planarization layer in the peripheral area. The first isolation trench blocks moisture from entering the display area. Moreover, the organic encapsulation layer covering the first isolation trench has a flat surface and does not produce a height difference at the recessed position. That is, the organic encapsulation layer can fill the first isolation trench and avoid the generation of a height difference in the peripheral area, thereby avoiding the short circuit risk of the touch lead formed on the side of the organic encapsulation layer away from the substrate.

[0064] In some examples, the organic encapsulation layer includes a third portion in the display area, with the second and third portions of the organic encapsulation layer connected. The third portion has a first height. The second and third portions of the organic encapsulation layer can be referred to as flat regions. The surface of the flat regions of the organic encapsulation layer away from the substrate can be substantially parallel to the plane of the substrate. In this example, the surfaces of the second and third portions of the organic encapsulation layer away from the substrate are flat, without any recesses. In some examples, the first height of the organic encapsulation layer can be approximately 28 micrometers (μm) to 42 μm, and the second height can be approximately 20 μm to 30 μm. However, this embodiment is not limited to this.

[0065] In some examples, the first portion of the organic encapsulation layer can be referred to as a ramp region. The ramp region can refer to the area between the cutoff point (i.e., the second height) and 100% height (i.e., the first height) of the organic encapsulation layer. In the direction perpendicular to the display substrate, the ramp region of the organic encapsulation layer has a certain slope in the direction away from the display area. In this example, the surface of the ramp region of the organic encapsulation layer away from the substrate is also flat, without any recesses. In some examples, the gradual decrease in height of the first portion of the organic encapsulation layer from the first height to the second height in the direction away from the display area can include: the decreasing trend of the height of the first portion in the direction away from the display area can conform to a function of a smooth surface; or, the height of the first portion of the organic encapsulation layer can decrease in a step-like manner in the direction away from the display area. For example, the first part can be divided into multiple consecutive sub-parts, the height of which can decrease sequentially along the direction away from the display area, and each sub-part has the same height; or, the first part can be divided into multiple consecutive sub-parts, the height of which can decrease sequentially along the direction away from the display area, and the height within each sub-part can also decrease sequentially along the direction away from the display area, wherein the functional relationship satisfied by the height decrease within a sub-part may be different from the functional relationship satisfied by the height decrease between sub-parts. However, this embodiment is not limited in this respect. In this example, the change trend of the height of the first part along the direction away from the display area will not have a sudden drop followed by a sudden rise, nor will it have a sudden rise followed by a sudden drop.

[0066] In some examples, the orthographic projection of the second portion of the organic encapsulation layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate. In this example, the height difference in the film layer caused by the first isolation trench can be filled by the second portion of the organic encapsulation layer, and the second portion of the organic encapsulation layer still maintains a flat surface. Alternatively, in some examples, the orthographic projection of the first portion of the organic encapsulation layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate. In this example, the height difference in the film layer caused by the first isolation trench can be filled by the first portion of the organic encapsulation layer, and the first portion of the organic encapsulation layer maintains a flat surface. Alternatively, in some examples, the orthographic projections of both the first and second portions of the organic encapsulation layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate. In this example, the orthographic projection of the first isolation trench onto the substrate may overlap with the boundary between the orthographic projections of the first and second portions of the organic encapsulation layer onto the substrate. The height difference in the film layer caused by the first isolation trench can be filled by both the first and second portions of the organic encapsulation layer, and the organic encapsulation layer maintains a flat surface. However, this embodiment is not limited to this.

[0067] In some exemplary embodiments, the display substrate may further include a second planarization layer located on the side of the first planarization layer away from the substrate. The second planarization layer has a second isolation trench in its peripheral region, the orthographic projection of the second isolation trench onto the substrate at least partially overlapping the orthographic projection of the first isolation trench onto the substrate. In some examples, the orthographic projection of the second isolation trench onto the substrate may include the orthographic projection of the first isolation trench onto the substrate. However, this embodiment is not limited to this. In this example, the organic encapsulation layer may fill the first and second isolation trenches and maintain a flat surface.

[0068] In some exemplary embodiments, the first isolation trench has a first width along a direction away from the display area. The first width can be approximately 4 μm to 15 μm, for example, approximately 10 μm. The first isolation trench has a first depth in a direction perpendicular to the substrate. The first depth can be approximately 1.5 μm to 3.5 μm, for example, approximately 1.5 μm or 2 μm.

[0069] In this disclosure, "width" refers to the dimension in the direction perpendicular to the extension direction. For example, the width of the first isolation trench can be the dimension of the first isolation trench projected onto the substrate in the direction perpendicular to the extension direction. The trench depth represents the vertical distance between the surface of the film layer forming the trench away from the substrate and the bottom surface of the trench in the direction perpendicular to the display substrate.

[0070] In some exemplary embodiments, the peripheral region may include a plurality of circuit areas arranged sequentially along a direction away from the display area. A first isolation slot may be located between two adjacent circuit areas. In some examples, the peripheral region may include two circuit areas, and the first isolation slot may be located between the two circuit areas. Alternatively, the peripheral region may include three or more circuit areas, and the first isolation slot may be located between two adjacent circuit areas on the side closer to the display area. Alternatively, the peripheral region may include three or more circuit areas, and the first isolation slot may be located between any two adjacent circuit areas. However, this embodiment is not limited in this respect.

[0071] The following examples illustrate the solution of this embodiment.

[0072] Figure 1 This is a schematic diagram of the structure of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 1 As shown, the display device may include: a timing controller 11, a data driver 12, gate driving circuits 13 and 14, and a sub-pixel array 15. The sub-pixel array 15 is located in the display area and includes a plurality of regularly arranged sub-pixels PX. The gate driving circuits 13 and 14 may be located in the peripheral areas on opposite sides of the display area. For example, the gate driving circuits 13 and 14 may each include: a scan driving circuit, a light-emitting driving circuit, and a reset driving circuit. The scan driving circuit may be configured to provide scan signals to the sub-pixels PX along scan lines. The light-emitting driving circuit may be configured to provide light-emitting control signals to the sub-pixels PX along light-emitting control lines. The reset driving circuit may be configured to provide reset control signals to the sub-pixels PX along reset control lines. The data driver 12 is configured to provide data signals to the sub-pixels PX along data lines. The timing controller 11 is configured to control the gate driving circuits 13 and 14 and the data driver 12.

[0073] In some exemplary embodiments, timing controller 11 can provide grayscale values ​​and control signals of specifications suitable for data driver 12 to data driver 12. Timing controller 11 can also provide clock signals, initial signals, etc., of specifications suitable for gate driver circuits 13 and 14 to gate driver circuits 13 and 14. Data driver 12 can use the grayscale values ​​and control signals received from timing controller 11 to generate data voltages to be provided to data lines D1 to Dr. For example, data driver 12 can sample grayscale values ​​using a clock signal and apply data signals corresponding to the grayscale values ​​to data lines D1 to Dr on a sub-pixel line basis, where r is a natural number. Gate driver circuits 13 and 14 can use the clock signals, initial signals, etc., received from timing controller 11 to generate gate control signals (e.g., scan signals, light emission control signals, etc.) to be provided to gate lines (e.g., scan lines, light emission control lines, etc.). For example, scan driver circuits can sequentially provide scan signals with on-level pulses to scan lines. In some examples, the scan driver circuit may include a shift register to generate a scan signal by sequentially transmitting a scan initial signal, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. For example, the light-emitting driver circuit may sequentially provide a light-emitting control signal with off-level pulses to the light-emitting control line. The light-emitting driver circuit may include a shift register to generate a light-emitting control signal by sequentially transmitting a light-emitting initial signal, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal.

[0074] Figure 2 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2 As shown, the display substrate of this embodiment may include a display area AA and a non-display area located around the periphery of the display area AA. The non-display area includes a bonding area B2 located on one side of the display area AA and a peripheral area B1 located on the other sides of the display area AA. The bonding area B2 and the peripheral area B1 are connected and surround the display area AA. For example, the peripheral area B1 may include the top border, left border, and right border of the display substrate, and the bonding area B2 may include the bottom border of the display substrate. However, this embodiment is not limited in this respect.

[0075] In some exemplary implementations, such as Figure 2As shown, the display area AA includes at least: multiple sub-pixels PX, multiple gate lines G, and multiple data lines D. The multiple gate lines G extend along a first direction X and are arranged sequentially along a second direction Y. The multiple data lines D extend along the second direction Y and are arranged sequentially along the first direction X. The first direction X and the second direction Y intersect, for example, are perpendicular to each other. The orthographic projections of the multiple gate lines G and the multiple data lines D onto the substrate intersect to form multiple sub-pixel regions, each sub-pixel region containing one sub-pixel PX. Each sub-pixel PX may include pixel circuitry and a light-emitting element electrically connected to the pixel circuitry. The multiple data lines D are electrically connected to the multiple sub-pixels PX and are configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines G are electrically connected to the multiple sub-pixels PX and are configured to provide gate control signals (e.g., scan signals) to the multiple sub-pixels PX. In some examples, the pixel circuit can be a 7T1C (i.e., 7 transistors and 1 capacitor), 3T1C (i.e., 3 transistors and 1 capacitor), or 5T1C (i.e., 5 transistors and 1 capacitor) structure. The light-emitting element can be an OLED device, including a stacked anode and cathode, and an organic light-emitting layer sandwiched between the anode and cathode. However, this embodiment is not limited in this respect.

[0076] In some exemplary embodiments, a pixel unit may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. In some examples, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this.

[0077] In some exemplary embodiments, the gate driver on array (GOA) circuit can be directly disposed on the substrate. For example, multiple driver circuits can be disposed in the peripheral regions B1 on the left and right sides of the display area AA. In some examples, multiple driver circuits can be formed together with the pixel circuit of the sub-pixel during the sub-pixel formation process. However, this embodiment does not limit the location or formation method of the multiple driver circuits.

[0078] In some exemplary embodiments, the data driver 12 may be disposed on a separate chip or printed circuit board to connect to the sub-pixel via a signal access pin disposed in the bonding region B2 of the substrate. For example, the data driver 12 may be disposed in the bonding region in the form of a chip-on-glass, chip-on-plastic, or chip-on-film, to connect to the signal access pin on the substrate. The timing controller 11 may be disposed separately from the data driver 12 or integrally with the data driver 12. However, this embodiment is not limited in this respect.

[0079] Figure 3 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 4 for Figure 3 The provided timing diagram for the pixel circuit is shown.

[0080] In some exemplary implementations, such as Figure 3 As shown, the pixel circuit of this exemplary embodiment may include: six switching transistors (M1, M2, M4 to M7), one driving transistor M3, and one storage capacitor Cst. The six switching transistors are a data writing transistor M4, a threshold compensation transistor M2, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a first reset transistor M1, and a second reset transistor M7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0081] In some exemplary embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0082] In some exemplary embodiments, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0083] In some exemplary implementations, such as Figure 3As shown, the pixel circuit is electrically connected to the scan line GL, data line D, first voltage line PL1, second voltage line PL2, light emission control line EML, first initial signal line INIT1, second initial signal line INIT2, first reset control line RST1, and second reset control line RST2. In some examples, the first voltage line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, and the second voltage line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL is configured to provide the scan signal SCAN to the pixel circuit, the data line D is configured to provide the data signal DATA to the pixel circuit, the light emission control line EML is configured to provide the light emission control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide the first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide the second reset signal RESET2 to the pixel circuit. In some examples, in a row of pixel circuits, the second reset control line RST2 may be connected to the scan line GL to be input with the scan signal SCAN. That is, the second reset signal RESET2(n) received by the nth row pixel circuit is the scan signal SCAN(n) received by the nth row pixel circuit. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 different from the scan signal SCAN. In some examples, in the nth row pixel circuit, the first reset control line RST1 can be connected to the scan line GL of the (n-1)th row pixel circuit to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow bezel of the display substrate can be achieved.

[0084] In some exemplary implementations, such as Figure 3As shown, the driving transistor M3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor M4 is electrically connected to the scan line GL, the first terminal of the data writing transistor M4 is electrically connected to the data line D, and the second terminal of the data writing transistor M4 is electrically connected to the first terminal of the driving transistor M3. The gate of the threshold compensation transistor M2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor M2 is electrically connected to the gate of the driving transistor M3, and the second terminal of the threshold compensation transistor M2 is electrically connected to the second terminal of the driving transistor M3. The gate of the first light-emitting control transistor M5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor M5 is electrically connected to the first voltage line PL1, and the second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M3. The gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control line EML. The first electrode of the second light-emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M3. The second electrode of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor M1 is electrically connected to the gate of the driving transistor M3 and configured to reset the gate of the driving transistor M3. The second reset transistor M7 is electrically connected to the anode of the light-emitting element EL and configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor M1 is electrically connected to the first reset control line RST1. The first electrode of the first reset transistor M1 is electrically connected to the first initial signal line INIT1. The second electrode of the first reset transistor M1 is electrically connected to the gate of the driving transistor M3. The gate of the second reset transistor M7 is electrically connected to the second reset control line RST2. The first electrode of the second reset transistor M7 is electrically connected to the second initial signal line INIT2. The second electrode of the second reset transistor M7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor M3. The second electrode of the storage capacitor Cst is electrically connected to the first voltage line PL1.

[0085] The following reference Figure 4 right Figure 3 The operation of the pixel circuit shown will be explained. Specifically, using... Figure 3 The pixel circuit shown is illustrated using P-type transistors as an example.

[0086] In some exemplary implementations, such as Figure 3 and Figure 4 As shown, during a single frame display period, the operation of the pixel circuit can include: a first stage S1, a second stage S2, and a third stage S3.

[0087] The first stage, S1, is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor M1. The first initial signal provided by the first initial signal line INIT1 is provided to the gate of the driving transistor M3, initializing the gate of the driving transistor M3 and clearing the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor M4, the threshold compensation transistor M2, the first light emission control transistor M5, the second light emission control transistor M6, and the second reset transistor M7. During this stage, the light-emitting element EL does not emit light.

[0088] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data line D outputs the data signal DATA. During this stage, because the second electrode of the storage capacitor Cst is low, the driving transistor M3 is turned on. The low-level scan signal SCAN turns on the threshold compensation transistor M2, the data writing transistor M4, and the second reset transistor M7. The turn on the threshold compensation transistor M2 and the data writing transistor M4 allows the data voltage Vdata output by the data line D to be supplied to the gate of the driving transistor M3 through the turned-on driving transistor M3 and the turned-on threshold compensation transistor M2. The difference between the data voltage Vdata output by the data line D and the threshold voltage of the driving transistor M3 is then charged into the storage capacitor Cst. The voltage at the second electrode of the storage capacitor Cst is Vdata - |Vth|, where Vdata is the data voltage output by the data line D, and Vth is the threshold voltage of the driving transistor M3. The second reset transistor M7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting element EL. This initializes (resets) the anode of the light-emitting element EL, clearing its internal pre-stored voltage and completing the initialization process, ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first reset transistor M1 to turn off. The light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the first light-emitting control transistor M5 and the second light-emitting control transistor M6 to turn off.

[0089] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on. The first voltage signal VDD output by the first voltage line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor M5, driving transistor M3, and second light-emitting control transistor M6, driving the light-emitting element EL to emit light.

[0090] During the driving process of the pixel circuit, the driving current flowing through the driving transistor M3 is determined by the voltage difference between its gate and first terminal. The driving current of the driving transistor M3 is:

[0091] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0092] Where I is the driving current flowing through the driving transistor M3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor M3, Vth is the threshold voltage of the driving transistor M3, Vdata is the data voltage output by the data line D, and VDD is the first voltage signal output by the first voltage line PL1.

[0093] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor M3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor M3.

[0094] Figure 5 This is a schematic diagram of the planar structure of the peripheral region of a display substrate according to at least one embodiment of the present disclosure. Figure 5 for Figure 2 A partial schematic diagram of the central region O1. In some exemplary embodiments, in a plane parallel to the display substrate, the peripheral region B1 may include a plurality of circuit regions (e.g., a first circuit region B11, a second circuit region B12, and a third circuit region B13), an isolation region B14, a crack dam region B15, and a cutting region B16 arranged sequentially along a direction away from the display region AA. A first isolation groove 350 is located between the first circuit region B11 and the second circuit region B12. Figure 2 As shown, in the peripheral region B1, the first isolation groove 350 extends along a direction parallel to the edge of the display region AA. However, this embodiment is not limited to this.

[0095] In some exemplary embodiments, the first circuit region B11 may include a first driving circuit and multiple first signal lines that output control signals (e.g., clock signals, initial signals, and power signals) to the first driving circuit. The first driving circuit is configured to output a first driving signal to the pixel circuit of the display area AA. The second circuit region B12 may include a second driving circuit and multiple second signal lines that output control signals to the second driving circuit. The second driving circuit is configured to output a second driving signal to the pixel circuit of the display area AA. The third circuit region may include a third driving circuit and multiple third signal lines that output control signals to the third driving circuit. The third driving circuit is configured to output a third driving signal to the pixel circuit of the display area AA.

[0096] In some exemplary embodiments, the first driving signal may be a reset control signal, the second driving signal may be a scan signal, and the third driving circuit may be a light emission control signal. For example, the first driving circuit may provide a first reset signal to the pixel circuit via a first reset control line and a second reset control signal to the pixel circuit via a second reset control line; the second driving circuit may provide a scan signal to the pixel circuit via a scan line; and the third driving circuit may provide a light emission control signal to the pixel circuit via a light emission control line. However, this embodiment is not limited in this respect. For example, the first driving signal may be a scan signal, the second driving signal may be a reset control signal, and the third driving signal may be a light emission control signal.

[0097] In some exemplary embodiments, the first driving circuit may include a plurality of cascaded first sub-driving circuits, which may be sequentially arranged along the second direction Y. The first sub-driving circuit is electrically connected to a first output signal line, which may extend along the first direction X to the display area AA. For example, the first output signal line may be electrically connected to a first reset control line and a second reset control line of the display area. The second driving circuit may include a plurality of cascaded second sub-driving circuits, which may be sequentially arranged along the second direction Y. The second sub-driving circuit is electrically connected to a second output signal line, which may extend along the first direction X to the display area AA. For example, the second output signal line may be electrically connected to a scan line of the display area. The third driving circuit may include a plurality of cascaded third sub-driving circuits, which may be sequentially arranged along the second direction Y. The third sub-driving circuit is electrically connected to a third output signal line, which may extend along the first direction X to the display area AA. For example, the third output signal line may be electrically connected to a light emission control line of the display area. However, this embodiment is not limited in this respect.

[0098] In some exemplary embodiments, the first and second sub-driving circuits can both be 8T2C (i.e., 8 transistors and 2 capacitors) structures, and the third sub-driving circuit can be a 10T3C (i.e., 10 transistors and 3 capacitors) structure or a 12T2C (i.e., 12 transistors and 2 capacitors) structure. However, this embodiment is not limited to this.

[0099] In some exemplary embodiments, isolation region B14 may include: a second voltage line, a first isolation dam, and a second isolation dam. The second voltage line may extend along a direction parallel to the edge of the display area AA, and is configured to output a second voltage signal VSS to multiple pixel circuits in the display area AA. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area AA, and are configured to block the organic encapsulation layer in the encapsulation layer and prevent moisture from entering the display area AA. Crack dam region B15 may include multiple cracks, which are configured to reduce the stress on the display area AA during the cutting process, cut off the crack propagation in the direction of the display area AA, and avoid affecting the film structure of the display area AA. Cutting region B16 may include at least one cutting groove, which is configured to be used by the cutting equipment to cut along the cutting groove after all film layers of the display substrate have been prepared.

[0100] Figure 6 for Figure 2 A partial cross-sectional schematic diagram along the P-P' direction. In some exemplary embodiments, such as... Figure 6 As shown, in the direction perpendicular to the display substrate, the display area AA may include: a substrate 30, and a pixel circuit layer, a first planarization layer 35, a light-emitting structure layer, an encapsulation layer, a protective layer 44, and a touch structure layer sequentially disposed on the substrate 30. The touch structure layer of the display area AA includes at least: a plurality of touch electrodes 45. The peripheral area B1 may include: a substrate 30, and a driving circuit layer, a first planarization layer 35, an encapsulation layer, a protective layer 44, and a touch structure layer sequentially disposed on the substrate 30. The touch structure layer of the peripheral area B1 includes at least: a plurality of touch leads 46. However, this embodiment is not limited thereto.

[0101] In some exemplary embodiments, the pixel circuit layer of the display area AA may include multiple pixel circuits. At least one pixel circuit includes multiple transistors and at least one storage capacitor. Figure 6 The diagram illustrates a pixel circuit with a transistor 201 and a storage capacitor 202 as an example. The driving circuit layer of the peripheral region B1 may include a gate driving circuit and multiple signal lines configured to provide control signals to the gate driving circuit. Figure 6The diagram illustrates several first signal lines 221 provided in the first circuit area B11 to provide control signals to the first driving circuit, several second signal lines 222 provided in the second circuit area B12 to provide control signals to the second driving circuit, and several third signal lines 223 provided in the third circuit area B13 to provide control signals to the third driving circuit.

[0102] In some exemplary embodiments, in a direction perpendicular to the display substrate, the driving circuit layer and pixel circuit layer may include: a semiconductor layer disposed on the substrate 30, a first insulating layer 31 covering the semiconductor layer, a first conductive layer disposed on the first insulating layer 31, a second insulating layer 32 covering the first conductive layer, a second conductive layer disposed on the second insulating layer 32, a third insulating layer 33 covering the second conductive layer, and a third conductive layer disposed on the third insulating layer 33. For example, the transistor 201 of the display area AA may include: a first active layer located on the semiconductor layer, a control electrode located on the first conductive layer, and a first electrode and a second electrode located on the third conductive layer. The storage capacitor 202 may include: a first capacitor plate located on the first conductive layer and a second capacitor plate located on the second conductive layer. However, this embodiment is not limited thereto.

[0103] In some exemplary implementations, such as Figure 6 As shown, the third conductive layer of the peripheral region B1 is illustrated using the first signal line 221 located in the first circuit region B11, the second signal line 222 located in the second circuit region B12, and the third signal line 223 located in the third circuit region B13 as examples. The film structure of the transistors and storage capacitors in the gate drive circuit of the peripheral region B1 can be referenced from the film structure of the pixel circuit in the display region AA, and is therefore omitted here. The third conductive layer of the peripheral region B1 may also include a second voltage line PL2.

[0104] In some exemplary implementations, such as Figure 6As shown, the light-emitting structure layer of the display area AA may include multiple film layers constituting the light-emitting element. These multiple film layers may include: an anode 211, a pixel definition layer 214, a cathode 213, and an organic light-emitting layer 212 sandwiched between the anode 211 and the cathode 213. The anode 211 can be connected to the drain electrode of the transistor 201 via a via. The organic light-emitting layer 212 is connected to the anode 211, and the cathode 213 is connected to the organic light-emitting layer 212. The organic light-emitting layer 212 emits light of a corresponding color under the drive of the anode 211 and the cathode 213. In some examples, the organic light-emitting layer 212 may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, the hole injection layer, hole transport layer, and electron blocking layer of all sub-pixels in the display area can be a common layer connected together, and the light-emitting layers of adjacent sub-pixels can have a small overlap or can be isolated. However, this embodiment is not limited in this respect.

[0105] In some exemplary implementations, such as Figure 6 As shown, a first connecting electrode 251 is also provided in the surrounding area B1. The first connecting electrode 251 and the anode 211 are of the same layer structure. A portion of the first connecting electrode 251 is electrically connected to the second voltage line PL2. Multiple vias are provided on the first connecting electrode 251. The second voltage line PL2 can be electrically connected to the cathode 213 through the first connecting electrode 251.

[0106] In some exemplary implementations, such as Figure 6 As shown, the first planarization layer 35 is located on the side of the third conductive layer away from the substrate 30. The first planarization layer 35 has a first isolation trench 350 in the peripheral region B1. The first isolation trench 350 is located between the first circuit region B11 and the second circuit region B12. The first connecting electrode 251, the cathode 213, the first inorganic encapsulation layer 41, and the organic encapsulation layer 42 are sequentially disposed within the first isolation trench 350.

[0107] In some exemplary implementations, such as Figure 6As shown, along the direction away from the display area AA, the first isolation trench 350 has a first width W1. The first width W1 can be approximately 4 μm to 15 μm, for example, approximately 10 μm. In the direction perpendicular to the substrate 30, the first isolation trench 350 has a first depth H3. The first depth H3 can be approximately 1.5 μm to 3.5 μm, for example, approximately 2 μm. However, this embodiment is not limited to this. In this example, by providing a first isolation trench with a first width and a first depth, it is beneficial to release moisture and prevent moisture from intruding into the display area.

[0108] In this example, the first depth of the first insulating trench 350 can be approximately the same as the thickness of the first planarization layer 35. For example, the first planarization layer 35 within the first insulating trench 350 can be completely removed, exposing the surface of the third insulating layer 33. However, this embodiment is not limited to this. In other examples, the first depth of the first insulating trench can be less than the thickness of the first planarization layer. For example, a portion of the first planarization layer 35 within the first insulating trench 350 can be removed, leaving a portion of the first planarization layer 35 intact.

[0109] In this disclosure, "thickness" refers to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer near the substrate in a direction perpendicular to the display substrate. In this disclosure, the height of the film layer may be greater than its thickness.

[0110] In some exemplary implementations, such as Figure 6 As shown, the encapsulation layer may include a first inorganic encapsulation layer 41, an organic encapsulation layer 42, and a second inorganic encapsulation layer 43 stacked together. The first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 may be made of inorganic materials, and the organic encapsulation layer 42 may be made of organic materials. The organic encapsulation layer 42 is disposed between the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43, forming a stacked structure of inorganic material / organic material / inorganic material, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0111] In some exemplary implementations, such as Figure 6 As shown, the organic encapsulation layer 42 has a continuous first portion 421, a second portion 422, and a third portion 423. The third portion 423 is located in the display area AA, and the first portion 421 and the second portion 422 are located in the peripheral area B1. The second portion 422 is located on the side of the first portion 421 closest to the display area AA. Both the third portion 423 and the second portion 422 of the organic encapsulation layer 42 have a first height H1. The height of the first portion 421 gradually decreases from the first height H1 to a second height H2 along a direction away from the display area AA. In this example, the first portion 421 forms a ramp surface.

[0112] In some exemplary implementations, such as Figure 6As shown, the width W0 of the first portion 421 of the organic encapsulation layer 42 can be approximately 500 μm to 1000 μm, for example, approximately 1000 μm. The first height H1 of the organic encapsulation layer 42 can be approximately 28 μm to 42 μm, for example, approximately 35 μm. The second height H2 can be approximately 20 μm to 30 μm, for example, approximately 25 μm. The first height of the organic encapsulation layer in this example ensures that the film height step difference created by the first isolation trench 350 is filled, thereby ensuring the planarization of the surface of the encapsulation layer away from the substrate 30.

[0113] In this exemplary embodiment, such as Figure 6 As shown, the first isolation trench 350 is located on the side of the first portion 421 of the organic encapsulation layer 42 near the display area AA. Furthermore, the orthographic projection of the first isolation trench 350 onto the substrate 30 does not overlap with the orthographic projection of the first portion 421 of the organic encapsulation layer 42 onto the substrate 30. The orthographic projection of the second portion 422 of the organic encapsulation layer 42 onto the substrate 30 can cover the orthographic projection of the first isolation trench 350 onto the substrate 30. In this example, the first portion 421, the second portion 422, and the third portion 423 of the organic encapsulation layer 42 are connected to form a flat surface, meaning that there are no recessed areas on the surface of the organic encapsulation layer 42 away from the substrate 30. Although the first isolation trench 350 in the first flattening layer 35 creates a height difference in the film layer, the second portion 422 of the organic encapsulation layer 42 can fill this height difference, thereby ensuring the flattening of the surface of the encapsulation layer away from the substrate 30. In this way, the protective layer 44 formed on the side of the encapsulation layer away from the substrate 30 also has a flat surface. The touch structure layer formed on the side of the encapsulation layer away from the substrate 30 can be formed on the protective layer 44 with a flat surface, thereby avoiding the risk of short circuits caused by residual adhesive during the fabrication of the touch structure layer due to the unevenness of the encapsulation layer surface.

[0114] In some exemplary implementations, such as Figure 6As shown, isolation region B14 has a first isolation dam 371 and a second isolation dam (not shown). The second isolation dam is located on the side of the first isolation dam 371 away from the display area AA. The first isolation dam 371 is formed by stacking a first dam base and a second dam base. For example, the first dam base of the first isolation dam 371 can be in the same layer as the pixel definition layer 214, and the second dam base can be in the same layer as the isolation pillar layer 38. The second isolation dam can be formed by stacking a first dam base, a second dam base, and a third dam base. The first dam base of the second isolation dam can be in the same layer as the first planarization layer 35, the second dam base can be in the same layer as the pixel definition layer 214, and the third dam base can be in the same layer as the isolation pillar layer 38. The isolation pillar layer 38 can be located on the side of the pixel definition layer 214 away from the substrate 30. The second voltage line disposed in isolation region B14 is located in the third conductive layer and is electrically connected to the cathode 213 through a first connection electrode 251 disposed in the same layer as the anode. The orthographic projection of the second voltage line PL2 of the isolation region B14 onto the substrate 30 may overlap with the orthographic projections of both the first isolation dam 371 and the second isolation dam onto the substrate 30. However, this embodiment is not limited to this.

[0115] In some exemplary embodiments, the minimum distance between the edge of the outermost touch lead 46 of the touch structure layer (i.e., the touch lead furthest from the display area AA along the direction away from the display area AA) and the edge of the first isolation dam 371 on the side closer to the display area AA can be approximately 90 μm to 110 μm, for example, approximately 100 μm. However, this embodiment is not limited to this.

[0116] In some exemplary embodiments, a fourth conductive layer and a second planarization layer are further disposed between the first planarization layer 35 and the anode. The peripheral region of the display substrate in this embodiment will be described below using an 8T2C structure for both the first and second sub-driving circuits. In the following example, the third sub-driving circuit may employ a 10T3C circuit structure. However, this embodiment is not limited to this.

[0117] Figure 7 This is an equivalent circuit diagram of the first sub-driving circuit of at least one embodiment of this disclosure. For example... Figure 7 As shown, the first sub-driving circuit provided in this exemplary embodiment may include: a first transistor T1 to an eighth transistor T8, a first storage capacitor C1, and a second storage capacitor C2. The fourth transistor T4 and the fifth transistor T5 are the output transistors of the first sub-driving circuit.

[0118] In some exemplary implementations, such as Figure 7As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first terminal of the first transistor T1 is electrically connected to the input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the first node N1, the first terminal of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first terminal of the third transistor T3 is electrically connected to the second power supply line VGL, and the second terminal of the third transistor T3 is electrically connected to the second node N2. The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first terminal of the fourth transistor T4 is electrically connected to the first power supply line VGH, and the second terminal of the fourth transistor T4 is electrically connected to the output terminal OUT. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first terminal of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the second terminal of the fifth transistor T5 is electrically connected to the output terminal OUT. The control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply line VGH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1. The control electrode of the eighth transistor T8 is electrically connected to the second power supply line VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3. The first electrode of the first storage capacitor C1 is electrically connected to the first power supply line VGH, and the second electrode of the first storage capacitor C1 is electrically connected to the second node N2. The second electrode of the second storage capacitor C2 is electrically connected to the output terminal OUT, and the first electrode of the second storage capacitor C2 is electrically connected to the third node N3.

[0119] In this exemplary embodiment, the first node N1 is the connection point of the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8. The second node N2 is the connection point of the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the first storage capacitor C1. The third node N3 is the connection point of the eighth transistor T8, the fifth transistor T5, and the second storage capacitor C2.

[0120] In some exemplary embodiments, Figure 7 The first transistor T1 to the eighth transistor T8 in the first sub-driving circuit shown can all be either P-type or N-type transistors. However, this embodiment is not limited to this.

[0121] In some exemplary embodiments, with Figure 7The first sub-driving circuit shown is illustrated using an example where the first transistor T1 to the eighth transistor T8 are all P-type transistors. The example is taken where the input terminal IN of the first sub-driving circuit is electrically connected to the first initial signal line. Figure 8 for Figure 7 The timing diagram of the first sub-driver circuit is shown. Figure 7 and Figure 8 As shown, the first sub-driving circuit of this exemplary embodiment includes eight transistor units (i.e., first transistor T1 to eighth transistor T8), two capacitor units (i.e., first storage capacitor C1 and second storage capacitor C2), three input terminals (i.e., first clock signal terminal CK, second clock signal terminal CB, and input terminal IN), one output terminal (i.e., output terminal OUT), and two power supply terminals (i.e., first power supply line VGH and second power supply line VGL). The first power supply line VGH continuously provides a high-level signal, and the second power supply line VGL continuously provides a low-level signal.

[0122] like Figure 7 and Figure 8 As shown, the operation of the first sub-driving circuit in this embodiment may include the following stages.

[0123] In the first stage Q1, the first clock signal terminal CK provides a low-level first clock signal, and the input terminal IN receives a low-level trigger signal. Therefore, the first transistor T1 and the third transistor T3 are turned on. The turned-on first transistor T1 transmits the low-level trigger signal to the first node N1, thereby making the level of the first node N1 low. Therefore, the second transistor T2 and the fifth transistor T5 are turned on. Since the eighth transistor T8 responds to the low level provided by the second power line VGL and remains in the on state, the level of the third node N3 is the same as the level of the first node N1, i.e., low level. At the same time, this low level is stored in the second storage capacitor C2. In addition, the conducting third transistor T3 transmits a low level to the second node N2, and the conducting second transistor T2 transmits the first clock signal to the second node N2, thereby causing the level of the second node N2 to become low and stored in the first storage capacitor C1. Therefore, the fourth transistor T4 responds to the low level of the second node N2 and conducts to output the high level provided by the first power line VGH to the output terminal OUT. At the same time, the fifth transistor T5 responds to the low level of the third node N3 and conducts to transmit the high level of the second clock signal provided by the second clock signal terminal CB to the output terminal OUT. Thus, at this stage, the first sub-drive circuit outputs a high level.

[0124] In the second stage Q2, the second clock signal terminal CB provides a low-level second clock signal, so the seventh transistor T7 is turned on. The first clock signal terminal CK provides a high-level first clock signal, so the first transistor T1 and the third transistor T3 are turned off. Due to the storage effect of the second storage capacitor C2, the first node N1 can continue to maintain the low level of the previous stage, so the second transistor T2 and the fifth transistor T5 are turned on. Because the second transistor T2 is turned on, the high-level first clock signal from the first clock signal terminal CK is transmitted to the second node N2, and the second node N2 becomes high. Therefore, the sixth transistor T6 and the fourth transistor T4 are turned off, thereby preventing the high-level output provided by the first power line VGH from being output to the output terminal OUT and the first node N1. Because the fifth transistor T5 is turned on, in this stage, the output terminal OUT outputs the low level transmitted by the second clock signal terminal CB.

[0125] In the third stage Q3, the first clock signal terminal CK provides a low-level first clock signal, so the first transistor T1 and the third transistor T3 are turned on. At this time, the high level provided by the first initial signal line is transmitted to the first node N1 and the third node N3, so the fifth transistor T5 and the second transistor T2 are turned off. The second clock signal terminal CB receives a high-level second clock signal, and the seventh transistor T7 is turned off. Since the third transistor T3 is turned on, the low level provided by the second power line VGL is transmitted to the second node N2 and stored in the first storage capacitor C1. Therefore, the fourth transistor T4 and the sixth transistor T6 are turned on. In this stage, the output terminal OUT outputs the high level provided by the first power line VGH.

[0126] In the fourth stage Q4, the first clock signal terminal CK provides a high-level first clock signal, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal terminal CB provides a low-level second clock signal, so the seventh transistor T7 is turned on. Due to the storage effect of the second storage capacitor C2, the level of the first node N1 remains high from the previous stage, thus turning off the second transistor T2 and the fifth transistor T5. Due to the storage effect of the first storage capacitor C1, the second node N2 continues to remain low from the previous stage, thus turning on the sixth transistor T6. The high level provided by the first power line VGH is transmitted to the first node N1 and the third node N3 through the turned-on sixth transistor T6 and seventh transistor T7, thus keeping the first node N1 and the third node N3 at a high level, effectively preventing the fifth transistor T5 from turning on, thereby avoiding erroneous output.

[0127] Figure 9 This is a partial top view of the surrounding area of ​​at least one embodiment of the present disclosure, as shown below. Figure 2 A partial top-view diagram of the central region O1. Figure 9The diagram illustrates two cascaded first sub-drive circuits located in the first circuit region B11, and a portion of two cascaded second sub-drive circuits located in the second circuit region B12. In some examples, the planar structure of the second sub-drive circuit is similar to that of the first sub-drive circuit, and therefore will not be described further here.

[0128] Figure 10 for Figure 9 A partial cross-sectional view along the Q-Q' direction. In some exemplary embodiments, in the direction perpendicular to the display substrate, such as... Figure 10 As shown, the peripheral region B1 may include: a substrate 30, a driving circuit layer, a first planarization layer 35, a fourth conductive layer, a second planarization layer 37, an encapsulation layer, a protective layer 44, and a touch structure layer sequentially disposed on the substrate 30. The driving circuit layer may include: a semiconductor layer disposed on the substrate 30, a first insulating layer 31 covering the semiconductor layer, a first conductive layer disposed on the first insulating layer 31, a second insulating layer 32 covering the first conductive layer, a second conductive layer disposed on the second insulating layer 32, a third insulating layer 33 covering the second conductive layer, and a third conductive layer disposed on the third insulating layer 33. In some examples, the first insulating layer 31 to the third insulating layer 33 may be inorganic insulating layers. The first insulating layer 31 and the second insulating layer 32 may be referred to as gate insulating layers, and the third insulating layer 33 may be referred to as an interlayer insulating layer. The protective layer 44 may be an inorganic material layer. The protective layer 44 may serve as a buffer film layer for the touch structure layer.

[0129] In some exemplary embodiments, a plurality of vias are provided on the third insulating layer 33, and the plurality of vias can expose the surface of the semiconductor layer, the first conductive layer or the second conductive layer, thereby realizing the electrical connection between the third conductive layer and the semiconductor layer, the first conductive layer or the second conductive layer.

[0130] Figure 11 This is a partial planar schematic diagram of the peripheral region after the formation of the driving circuit layer according to at least one embodiment of the present disclosure. Figure 12 This is a partial planar schematic diagram of the surrounding area after the formation of the first planarization layer, according to at least one embodiment of this disclosure. Figure 13 This is a partial planar schematic diagram of the surrounding area after the formation of the fourth conductive layer according to at least one embodiment of the present disclosure. Figure 14 This is a partial planar schematic diagram of the surrounding area after the formation of the second flattening layer, according to at least one embodiment of this disclosure.

[0131] In some exemplary implementations, such as Figure 10 and Figure 11As shown, the semiconductor layer in the peripheral region includes at least: the active layer of a plurality of transistors in the first sub-driving circuit (e.g., the active layer T20 of the second transistor T2 in the first sub-driving circuit), and the active layer of a plurality of transistors in the second sub-driving circuit. The first conductive layer includes at least: the control electrode of a plurality of transistors in the first sub-driving circuit (e.g., the control electrode T23 of the second transistor T2 and the control electrode T33 of the third transistor T3 in the first sub-driving circuit), the first electrode of a plurality of capacitors, and the control electrode of a plurality of transistors in the second sub-driving circuit and the first electrode of a capacitor (e.g., the first electrode C1-1 of the first storage capacitor in the second sub-driving circuit). The second conductive layer includes at least: the second electrode of a plurality of capacitors in the first and second sub-driving circuits (e.g., the second electrode C1-2 of the first storage capacitor in the second sub-driving circuit), a first output signal line 51, a second output signal line 52, and a third output signal line 53. The first output signal line 51 is electrically connected to the output terminal of the first sub-driving circuit (e.g., it can be an integral structure) and extends in the direction of the display area, for example, extending along a first direction X. The second output signal line 52 is electrically connected to the output terminal of the second sub-driving circuit (e.g., it can be an integral structure) and extends toward the display area. The third output signal line 53 is electrically connected to the output terminal of the third sub-driving circuit (e.g., it can be an integral structure) and extends toward the display area. The third conductive layer includes at least: a plurality of first signal lines electrically connected to the first sub-driving circuit (e.g., a first initial signal line STV1, a first clock signal line CLK1, a second clock signal line CLK2, a first power supply line VGH1, and a second power supply line VGL1), a plurality of second signal lines electrically connected to the second sub-driving circuit (e.g., a first power supply line VGH2), and a plurality of third signal lines electrically connected to the third sub-driving circuit.

[0132] In some exemplary implementations, such as Figure 9 and Figure 11 As shown, the first initial signal line STV1, the first clock signal line CLK1, the second clock signal line CLK2, the second power supply line VGL1, and the first power supply line VGH1 of the first circuit area B11 all extend along the second direction Y. The first initial signal line STV1, the first clock signal line CLK1, the second clock signal line CLK2, and the second power supply line VGL1 are located on the side of the first sub-driving circuit away from the display area, and are arranged sequentially along the direction closest to the display area. The first power supply line VGH1 is located on the side of the first sub-driving circuit closest to the display area.

[0133] In some exemplary implementations, such as Figure 11As shown, the input terminal of the first-stage first sub-driver circuit is electrically connected to the first initial signal line STV1. The input terminal IN of the nth-stage first sub-driver circuit and the output terminal of the (n-1)th-stage first sub-driver circuit can be a single unit. The first clock signal terminal of the nth-stage first sub-driver circuit is electrically connected to the first clock signal line CLK1, and the second clock signal terminal is electrically connected to the second clock signal line CLK2. The first clock signal terminal of the (n+1)th-stage first sub-driver circuit is electrically connected to the second clock signal line CLK2, and the second clock signal terminal is electrically connected to the first clock signal line CLK1. Here, n is an integer greater than 1. However, this embodiment is not limited in this respect.

[0134] In some exemplary implementations, such as Figure 11 As shown, the second transistor T2 and the third transistor T3 of the first sub-driving circuit are located near the second power line VGL1 and are arranged sequentially along the second direction Y. The eighth transistor T8 is located between the third transistor T3 and the seventh transistor T7 in the first direction X. The sixth transistor T6 and the seventh transistor T7 are arranged sequentially along the second direction Y. The seventh transistor T7 is located between the eighth transistor T8 and the fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 are arranged sequentially along the second direction Y. The first storage capacitor C1 is located on the side of the fourth transistor T4 closest to the display area, and the second storage capacitor C2 is located on the side of the fifth transistor T5 closest to the display area.

[0135] In some exemplary implementations, such as Figure 9 and Figure 12 As shown, the first planarization layer 35 in the peripheral area is provided with a first isolation trench 350, a first recess 351, and a second recess 352. The first isolation trench 350 is located between the first circuit region B11 and the second circuit region B12. The first recess 351 and the second recess 352 are located in the first circuit region B11. The first recess 351 exposes the surface of the first clock signal line CLK1, and the second recess 352 exposes the surface of the second clock signal line CLK2. The first isolation trench 350 is located on the side of the first recess 351 away from the display area. The orthographic projection of the first isolation trench 350 onto the substrate 30 is located on the side of the first initial signal line STV1 in the first circuit region B11 away from the display area, and on the side of the first storage capacitor and the second storage capacitor of the second sub-driving circuit in the second circuit region B12 closer to the display area.

[0136] In some exemplary implementations, such as Figure 12As shown, the first isolation trench 350 has a first width W1 in its orthographic projection onto the substrate 30. The edge of the first isolation trench 350 near the display area in its orthographic projection onto the substrate 30 has a first distance L1 between it and the edge of the first initial signal line STV1 away from the display area in its orthographic projection onto the substrate 30. The edge of the first isolation trench 350 away from the display area in its orthographic projection onto the substrate 30 has a second distance L2 between it and the edge of the first power line VGH2 electrically connected to the second sub-driving circuit near the display area in its orthographic projection onto the substrate 30. In some examples, the first distance L1 may be less than the second distance L2. In this example, the first width W1 may be approximately 10 μm. The first distance L1 may be approximately 3.5 μm to 4.5 μm, for example, approximately 4 μm. The second distance L2 may be approximately 5.5 μm to 7.2 μm, for example, approximately 6.5 μm. However, this embodiment is not limited in this respect.

[0137] In this exemplary embodiment, the first planarization layer 35 covers the edge of the first initial signal line STV near the first isolation trench 350, and the coverage width is greater than a first distance (e.g., greater than or equal to 4 μm); the first planarization layer 35 covers the edge of the first power line VGH2 near the first isolation trench 350, and the coverage width is greater than a second distance (e.g., greater than or equal to 6.5 μm). This ensures that the first planarization layer 35 covers the edges of adjacent signal lines of the first isolation trench 350, effectively preventing film peeling and improving process quality.

[0138] In some exemplary implementations, such as Figure 12 As shown, the orthographic projection of the first isolation trench 350 onto the substrate does not overlap with the orthographic projections of the first sub-driving circuit and the second sub-driving circuit onto the substrate. The orthographic projection of the first isolation trench 350 onto the substrate overlaps with the orthographic projections of the second output signal line 52 and the third output signal line 53 extending along the first direction X onto the substrate. In this example, since the second output signal line 52 and the third output signal line 53 are located in the second conductive layer, which is covered by the third insulating layer 33, the first isolation trench 350 formed in the first planarization layer 35 will not affect the signal transmission of the second output signal line 52 and the third output signal line 53 in the second conductive layer.

[0139] In some exemplary implementations, such as Figure 10 and Figure 12 As shown, the cross-sectional shape of the first isolation groove 350 in the direction perpendicular to the display substrate can be rectangular or trapezoidal. However, this embodiment is not limited to this.

[0140] In some exemplary implementations, such as Figure 9 and Figure 13As shown, the fourth conductive layer is located on the side of the first planarization layer 35 away from the substrate 30. The fourth conductive layer of the first circuit region B11 in the peripheral area may include: a first auxiliary connection line 361 and a second auxiliary connection line 362. The first auxiliary connection line 361 and the second auxiliary connection line 362 extend along the second direction Y and are arranged sequentially along the first direction X. The first auxiliary connection line 361 is electrically connected to the first clock signal line CLK1 through the first groove 351. The second auxiliary connection line 362 is electrically connected to the second clock signal line CLK2 through the second groove 352. The orthographic projection of the first auxiliary connection line 361 on the substrate can coincide with the orthographic projection of the first clock signal line CLK1 on the substrate, and the orthographic projection of the second auxiliary connection line 362 on the substrate can coincide with the orthographic projection of the second clock signal line CLK2 on the substrate. In this example, the first clock signal line CLK1 and the second clock signal line CLK2 are electrically connected to the auxiliary connection lines, which can realize a double-layer trace design, thereby reducing resistance and improving signal transmission performance. In some examples, the fourth conductive layer of the display area may include: a plurality of anode connection electrodes configured to electrically connect the anode and pixel circuitry of the light-emitting element.

[0141] In some exemplary implementations, such as Figure 14 As shown, the second planarization layer 37 of the first circuit region B11 in the peripheral area covers the first auxiliary connection line 361 and the second auxiliary connection line 362 of the fourth conductive layer, and the second planarization layer 37 is removed at other locations. In this example, the orthographic projection of the second planarization layer 37 onto the substrate does not overlap with the orthographic projection of the first isolation trench 350 onto the substrate. There is a third distance L3 between the edge of the second planarization layer 37 of the first circuit region B11 away from the display area in the orthographic projection onto the substrate and the edge of the first isolation trench 350 near the display area in the orthographic projection onto the substrate. In some examples, the third distance L3 can be approximately 9 μm to 11 μm, for example, the third distance L3 can be approximately 10 μm. However, this embodiment is not limited to this.

[0142] In some exemplary implementations, such as Figure 9 As shown, the touch structure layer in the surrounding area may include multiple touch leads. These multiple touch leads may include multiple first touch leads 461, multiple second touch leads 462, and an isolation lead 463. The multiple touch leads may all extend along the second direction Y and be arranged sequentially along the first direction X. The multiple first touch leads 461 are located on the side of the isolation lead 463 closer to the display area, and the multiple second touch leads 462 are located on the side of the isolation lead 463 farther from the display area. The isolation lead 463 is configured to shield signal interference between the first touch leads 461 and the second touch leads 462.

[0143] In some exemplary embodiments, the first touch lead 461 may be electrically connected to a first touch electrode in the display area, and the second touch lead 462 may be electrically connected to a second touch electrode in the display area. The first touch electrode may be a receiving electrode, and the second touch electrode may be a transmitting electrode. However, this embodiment is not limited in this respect. For example, the first touch lead may be electrically connected to the transmitting electrode, and the second touch lead may be electrically connected to the receiving electrode.

[0144] In some exemplary implementations, such as Figure 9 As shown, along the direction away from the display area, the isolation lead 463 has a second width W2, the first touch lead 461 has a third width W3, and the second touch lead 462 has a fourth width W4. The second width W2 can be greater than the third width W3 and greater than the fourth width W4. In some examples, the second width W2 can be approximately 45 μm to 55 μm, for example, approximately 50 μm; the third width W3 can be approximately 5 μm to 25 μm, for example, approximately 15 μm; and the fourth width W4 can be approximately 10 μm to 15 μm, for example, approximately 10 μm. However, this embodiment is not limited in this respect.

[0145] In some exemplary implementations, such as Figure 9 As shown, the distance between adjacent first touch leads 461 can be approximately the same along the direction away from the display area. The distance between adjacent second touch leads 462 can also be approximately the same. The distance between the isolation lead 463 and the adjacent first touch lead 461 can be approximately equal to the distance between the isolation lead 463 and the adjacent second touch lead 462. The distance between the isolation lead 463 and the adjacent first touch lead 461 is greater than the distance between adjacent first touch leads 461 and also greater than the distance between adjacent second touch leads 462. For example, the distance between adjacent first touch leads 461 can be approximately 2μm to 15μm, the distance between adjacent second touch leads 462 can be approximately 2μm to 15μm, the distance between the isolation lead 463 and the adjacent first touch lead 461 can be approximately 10μm to 30μm, and the distance between the isolation lead 463 and the adjacent second touch lead 462 can be approximately 10μm to 30μm.

[0146] In some exemplary implementations, such as Figure 9 As shown, the orthographic projection of the first touch lead 461 onto the substrate 30 may overlap with the orthographic projection of the first isolation trench 350 onto the substrate 30. However, this embodiment is not limited to this.

[0147] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0148] The fabrication process of the display substrate in this exemplary embodiment may include the following steps.

[0149] (1) A pixel circuit layer and a driving circuit layer are formed on a substrate.

[0150] In some exemplary embodiments, a semiconductor thin film is deposited on a substrate 30, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer disposed on the substrate 30, such as... Figure 11 As shown. The semiconductor layer includes at least: an active layer of transistors for the pixel circuit located in the display area AA, and an active layer of transistors for the gate drive circuit located in the peripheral area B1.

[0151] Subsequently, a first insulating film and a first conductive film are deposited sequentially. The first conductive film is then patterned using a patterning process to form a first insulating layer 31 covering the semiconductor layer and a first conductive layer disposed on the first insulating layer 31, such as... Figure 11 As shown. The first conductive layer includes at least: the control electrode of the transistor of the pixel circuit located in the display area AA and the first electrode of the storage capacitor, and the control electrode of the transistor of the gate drive circuit located in the peripheral area B1 and the first electrode of the storage capacitor. In some examples, the first conductive layer may be referred to as a first gate metal layer.

[0152] Subsequently, a second insulating film and a second conductive film are deposited sequentially. The second conductive film is then patterned using a patterning process to form a second insulating layer 32 covering the first conductive layer, and a second conductive layer disposed on the second insulating layer 32, such as... Figure 11As shown. The second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit located in the display area AA, a second electrode of the storage capacitor of the gate driving circuit located in the peripheral area B1, and a plurality of output signal lines located in the peripheral area B1 and electrically connected to the gate driving circuit. The output signal lines extend toward the display area AA. In some examples, the second conductive layer may be referred to as a second gate metal layer.

[0153] Subsequently, a third insulating film is deposited, and the third insulating film is patterned using a patterning process to form a third insulating layer 33 covering the second conductive layer, such as... Figure 11 As shown. The third insulating layer 33 has multiple vias.

[0154] In some examples, during this patterning process, multiple spaced cracks can be formed in the crack dam area, and grooves can be formed in the cutting area. The first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 in the cracks are removed, exposing the surface of the substrate 30; the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 in the grooves are also removed, exposing the surface of the substrate 30.

[0155] In some examples, a two-step patterning process can be used to form the cracks in the crack dam area and the grooves in the cutting area. In an exemplary embodiment, forming an uneven crack dam structure in the crack dam area can avoid affecting the film structure of the display area and circuit area during the cutting process. Multiple spaced cracks can not only reduce the stress on the display area and circuit area, but also prevent the cracks from propagating in the direction of the display area and circuit area.

[0156] Subsequently, a third conductive thin film is deposited, and the third conductive thin film is patterned using a patterning process to form a third conductive layer on the third insulating layer 33, such as... Figure 11 As shown. The third conductive layer includes at least: a first and second electrode of a transistor in the pixel circuit located in the display area AA; a signal line (e.g., a data line, etc.) located in the display area AA and electrically connected to the pixel circuit; a first and second electrode of a transistor in the gate drive circuit located in the peripheral area B1; and multiple signal lines (e.g., multiple first signal lines, multiple second signal lines, and multiple third signal lines) located in the peripheral area B1 and electrically connected to the gate drive circuit. In some examples, the third conductive layer may be referred to as a first source / drain metal layer.

[0157] In some exemplary embodiments, the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first insulating layer 31 and the second insulating layer 32 may be referred to as gate insulating (GI) layers, and the third insulating layer 33 may be referred to as interlayer insulating (ILD) layers. The first conductive layer, the second conductive layer, and the third conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0158] In some exemplary embodiments, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be made of materials such as glass or quartz, and the flexible substrate may be made of materials such as polyimide (PI). The flexible substrate may be a single-layer structure or a stacked structure composed of inorganic material layers and flexible material layers, which is not limited herein.

[0159] (2) Formation of the first flat layer.

[0160] In some exemplary embodiments, a first planarization film is coated on the substrate 30 on which the aforementioned pattern is formed, and the first planarization film is patterned by a patterning process to form a first planarization layer 35 covering the third conductive layer, such as... Figure 12 As shown, the first planarization layer 35 has a first isolation groove 350 formed in the peripheral region B1.

[0161] In some examples, the first planarization film within the first isolation trench 350 is removed, exposing the surface of the third insulating layer 33. The first isolation trench 350 is configured to remove moisture generated during the patterning process of the first planarization layer, thereby preventing moisture from entering the display area and causing defects such as pixel failure, metal bulging, or film peeling, thus improving process quality.

[0162] In some examples, the first planarization layer 35 may be made of an organic material, such as resin. The thickness of the first planarization layer 35 may be approximately 1.5 μm to 3.5 μm.

[0163] (3) Forming the fourth conductive layer.

[0164] In some exemplary embodiments, a fourth conductive film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the fourth conductive layer is formed by a patterning process, such as... Figure 13 As shown. The fourth conductive layer includes: an anode connection electrode located in the display area AA, and an auxiliary connection line located in the peripheral area B1. The anode connection electrode is configured to connect the pixel circuit and the anode of the light-emitting element.

[0165] (4) Forming a second flat layer.

[0166] In some exemplary embodiments, a second planarization film is coated on the substrate 30 on which the aforementioned pattern is formed, and the second planarization film is patterned by a patterning process to form a second planarization layer 37 covering the fourth conductive layer, such as... Figure 14 As shown. In this example, only the second planarization layer 37 covering the fourth conductive layer may be retained in the surrounding area. However, this embodiment is not limited to this.

[0167] In subsequent processes, an anode, a pixel definition layer, an organic light-emitting layer, and a cathode are sequentially formed in the display area AA. Then, an encapsulation layer is formed. The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked on top of each other. Finally, a protective layer and a touch structure layer disposed on the protective layer are formed.

[0168] In this example, the first isolation trench 350 of the first planarization layer 35 is located on the side of the second circuit area closer to the display area. A first connecting electrode 251, a cathode 213, a first inorganic encapsulation layer 41, and an organic encapsulation layer 42 are sequentially disposed within the first isolation trench 350. The first connecting electrode 251 and the anode 211 are in the same layer. The organic encapsulation layer 42 here has sufficient thickness to fill the height difference in the film layer caused by the first isolation trench 350, thereby ensuring that the surfaces of the encapsulation layer and the protective layer 44 away from the substrate 30 are both flat surfaces. The touch structure layer is formed on a flat surface, which avoids the risk of short circuits in the touch leads caused by residual adhesive during the fabrication process.

[0169] The exemplary embodiments of this disclosure show that the fabrication process of the display substrate has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0170] The structure of the display substrate and its fabrication process disclosed herein are merely illustrative. In the exemplary embodiments, the corresponding structure and patterning processes may be modified and added or reduced as needed, and this disclosure does not limit the scope of the invention.

[0171] Figure 15 for Figure 2 Another partial cross-sectional schematic diagram along the P-P' direction. Figure 16This is another partial planar schematic diagram of the surrounding area after the formation of the second flattening layer, according to at least one embodiment of this disclosure.

[0172] In some exemplary implementations, such as Figure 15 and Figure 16 As shown, a fourth conductive layer and a second planarization layer 37 are sequentially disposed on the side of the first planarization layer 35 away from the substrate 30. The fourth conductive layer of the display area AA may include an anode connection electrode 215, which can electrically connect to the pixel circuit and the anode 211 of the light-emitting element. The fourth conductive layer of the peripheral area B1 may include multiple auxiliary connection lines and a second connection electrode 252. The auxiliary connection lines can be electrically connected to the signal lines of the third conductive layer. The second connection electrode 252 can be electrically connected to the second voltage line PL2 of the third conductive layer, and can also be electrically connected to the first connection electrode 251. The first connection electrode 251 and the anode 211 are in the same layer. The cathode 213 can be electrically connected to the second voltage line PL2 through the first connection electrode 251 and the second connection electrode 252.

[0173] In some exemplary implementations, such as Figure 15 and Figure 16 As shown, the first planarization layer 35 has a first isolation trench 350 in the peripheral region B1. The second planarization layer 37 has a second isolation trench 370 in the peripheral region B1. The first isolation trench 350 and the second isolation trench 370 are located between the first circuit region B11 and the second circuit region B12. The orthographic projection of the second isolation trench 370 onto the substrate 30 may cover the orthographic projection of the first isolation trench 350 onto the substrate 30. However, this embodiment is not limited in this respect. For example, the orthographic projection of the second isolation trench onto the substrate may partially overlap with the orthographic projection of the first isolation trench onto the substrate.

[0174] In some exemplary implementations, such as Figure 15 and Figure 16 As shown, along the direction away from the display area, the first isolation groove 350 has a first width W1, and the second isolation groove 370 has a fifth width W5. The fifth width W5 can be greater than the first width W1. For example, the first width W1 can be approximately 10 μm, and the fifth width W5 can be approximately 27 μm to 33 μm, for example, approximately 30 μm. However, this embodiment is not limited in this respect.

[0175] In some exemplary embodiments, the thickness of the second planarization layer 37 can be approximately 1 μm to 3 μm, for example, approximately 2 μm. The depth of the second isolation trench 370 can be approximately the same as the thickness of the second planarization layer 37. The second planarization layer 37 within the second isolation trench 370 is completely removed, and the second isolation trench 370 can communicate with the first isolation trench 350. Figure 15As shown, the first connecting electrode 251, cathode 213, first inorganic encapsulation layer 41 and organic encapsulation layer 42 can be sequentially disposed in the first isolation trench 350 and the second isolation trench 370.

[0176] In this exemplary embodiment, the first isolation trench 350 and the second isolation trench 370 are configured to remove moisture generated during the patterning process of the first planarization layer 35 and the second planarization layer 37, so as to prevent moisture from entering the display area AA and causing defects such as pixel failure, metal bulging, or film peeling, thereby improving process quality. This example further enhances the moisture removal effect by setting two isolation trenches.

[0177] In some examples, such as Figure 15 As shown, the first isolation dam 371 is formed by stacking a first dam base and a second dam base. The first dam base can be in the same layer as the pixel definition layer 214, and the second dam base can be in the same layer as the isolation column layer 38. However, this embodiment is not limited to this.

[0178] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0179] Figure 17 This is a schematic diagram of another planar structure of the peripheral region of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, in a plane parallel to the display substrate, the peripheral region B1 may include: a plurality of circuit regions (e.g., a first circuit region B11 and a second circuit region B12) arranged sequentially along a direction away from the display region AA, an isolation region B14, a crack dam region B15, and a cutting region B16. A first isolation groove 350 is located between the first circuit region B11 and the second circuit region B12. The first circuit region B11 may include a first driving circuit and a plurality of first signal lines that output control signals (e.g., clock signals, initial signals, and power signals) to the first driving circuit. The first driving circuit is configured to output a first driving signal to the pixel circuit of the display region AA. The second circuit region B12 may include a second driving circuit and a plurality of second signal lines that output control signals to the second driving circuit region. The second driving circuit is configured to output a second driving signal to the pixel circuit of the display region AA.

[0180] In some exemplary embodiments, the first driving signal may be a scanning signal, and the second driving signal may be a light emission control signal. However, this embodiment is not limited to this. For example, the first driving signal may be a light emission control signal, and the second driving signal may be a scanning signal.

[0181] Figure 18 for Figure 2 Another partial cross-sectional view along the P-P' direction. In some exemplary embodiments, such as Figure 18As shown, in the direction perpendicular to the display substrate, the display area AA may include: a substrate 30, and a pixel circuit layer, a first planarization layer 35, a light-emitting structure layer, an encapsulation layer, a protective layer 44, and a touch structure layer sequentially disposed on the substrate 30. The touch structure layer of the display area AA includes at least: a plurality of touch electrodes 45. The peripheral area B1 may include: a substrate 30, and a driving circuit layer, a first planarization layer 35, an encapsulation layer, a protective layer 44, and a touch structure layer sequentially disposed on the substrate 30. The touch structure layer of the peripheral area B1 includes at least: a plurality of first touch leads 461, a plurality of second touch leads 462, and an isolation lead 463.

[0182] In some exemplary implementations, such as Figure 18 As shown, the first planarization layer 35 has a first isolation trench 350 in its peripheral region. The first isolation trench 350 is located between the first circuit region B11 and the second circuit region B12. The orthographic projections of the first portion 421 and the second portion 422 of the organic encapsulation layer 42 onto the substrate 30 overlap with the orthographic projection of the first isolation trench 340 onto the substrate 30. That is, the orthographic projection of the first isolation trench 340 onto the substrate 30 can be located at the boundary between the first portion 421 and the second portion 422 of the organic encapsulation layer 42.

[0183] In some exemplary implementations, such as Figure 18 As shown, the orthographic projection of the shielding lead 463 of the touch structure layer onto the substrate 30 overlaps with the orthographic projection of the first isolation trench 350 onto the substrate 30. For example, the orthographic projection of the shielding lead 463 onto the substrate 30 may cover the orthographic projection of the first isolation trench 350 onto the substrate 30. However, this embodiment is not limited to this.

[0184] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0185] Figure 19 for Figure 2 Another partial cross-sectional view along the P-P' direction. In some exemplary embodiments, such as Figure 19 As shown, the orthographic projection of the first portion 421 of the organic encapsulation layer 42 onto the substrate 30 covers the orthographic projection of the first isolation trench 350 onto the substrate 30. That is, the height of the ramp region of the organic encapsulation layer 42 can fill the height difference in the film layer caused by the first isolation trench 350, and the surface of the ramp region can remain flat. In some examples, the first height of the organic encapsulation layer 42 can be approximately 28 μm to 42 μm, for example, approximately 35 μm. The second height can be approximately 20 μm to 30 μm.

[0186] In some exemplary implementations, such as Figure 19As shown, the orthographic projection of a second touch lead 462 of the touch structure layer onto the substrate 30 may overlap with the orthographic projection of the first isolation trench 350 onto the substrate 30. However, this embodiment is not limited to this.

[0187] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0188] Figure 20 for Figure 2 Another partial cross-sectional view along the P-P' direction. In some exemplary embodiments, such as Figure 20 As shown, the orthographic projection of the touch lead in the touch structure layer onto the substrate 30 and the orthographic projection of the first isolation trench 350 onto the substrate 30 may not overlap. For example, the orthographic projection of the first isolation trench 350 onto the substrate 30 may be located between the orthographic projections of the second touch lead 462 and the shielding lead 463 onto the substrate 30, and may not overlap with the orthographic projections of the second touch lead 462 and the shielding lead 463 onto the substrate 30. However, this embodiment is not limited to this. For example, the orthographic projection of the first isolation trench onto the substrate may be located between the orthographic projections of the first touch lead and the shielding lead onto the substrate, and may not overlap with the orthographic projections of either the first touch lead or the shielding lead onto the substrate.

[0189] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0190] In some other exemplary embodiments, the orthographic projection of the second portion of the organic encapsulation layer onto the substrate covers the orthographic projection of the first isolation trench onto the substrate, and the orthographic projection of the shielding lead of the touch structure layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate, or the orthographic projection of the second touch lead of the touch structure layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate. Alternatively, in some other exemplary embodiments, the orthographic projection of the first portion of the organic encapsulation layer onto the substrate may cover the orthographic projection of the first isolation trench onto the substrate, and the orthographic projection of the shielding lead of the touch structure layer onto the substrate may overlap with the orthographic projection of the first isolation trench onto the substrate. However, this embodiment is not limited in this respect.

[0191] Figure 21 This is another planar structural diagram of the peripheral region of a display substrate according to at least one embodiment of the present disclosure. Figure 22 for Figure 2 Another partial cross-sectional view along the P-P' direction. In some exemplary embodiments, such as Figure 21 and Figure 22As shown, in a plane parallel to the display substrate, the peripheral region B1 may include: a plurality of circuit regions (e.g., a first circuit region B11, a second circuit region B12, and a third circuit region B13) sequentially arranged along a direction away from the display region AA, an isolation region B14, a crack dam region B15, and a cutting region B16. The first planarization layer 25 has a first isolation groove 350 in the peripheral region. The first isolation groove 350 is located between the second circuit region B12 and the third circuit region B13.

[0192] In some examples, the orthographic projections of the first portion 421 and the second portion 422 of the organic encapsulation layer 42 onto the substrate 30 overlap with the orthographic projection of the first isolation trench 340 onto the substrate 30. That is, the orthographic projection of the first isolation trench 340 onto the substrate 30 may be located at the boundary between the first portion 421 and the second portion 422 of the organic encapsulation layer 42. However, this embodiment is not limited to this.

[0193] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0194] This disclosure also provides a method for fabricating a display substrate. The display substrate includes a display area and a peripheral area at least partially surrounding the display area. The fabrication method of this embodiment includes: forming a driving circuit layer in the peripheral area of ​​a substrate; forming a first planarization layer on the side of the driving circuit layer away from the substrate, the first planarization layer having a first isolation trench in the peripheral area; and forming an organic encapsulation layer on the side of the first planarization layer away from the substrate. The organic encapsulation layer includes a first portion and a second portion located in the peripheral area, the second portion being located on the side of the first portion closer to the display area. The second portion has a first height, and the height of the first portion gradually decreases from the first height to a second height along a direction away from the display area. The first height is greater than the second height. The first isolation trench is located on the side of the first portion closer to the display area, and at least one of the first portion and the second portion of the organic encapsulation layer, in its orthographic projection onto the substrate, covers the orthographic projection of the first isolation trench onto the substrate.

[0195] The preparation method of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0196] At least one embodiment of this disclosure also provides a display device, including the display substrate described above.

[0197] Figure 23 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 23As shown, this embodiment provides a display device 91, including a display substrate 910. In some examples, the display substrate 910 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and this disclosure is not limited thereto.

[0198] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0199] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A substrate, and a driving circuit layer, a first planarization layer and an organic encapsulation layer sequentially disposed on the substrate; The substrate includes a display area and at least a peripheral area surrounding the display area; The driving circuit layer is located in the surrounding area; The first planarization layer has a first isolation groove in the peripheral area; The organic encapsulation layer includes a first portion and a second portion located in the peripheral region; the second portion is located on the side of the first portion closer to the display area; the second portion has a first height, and the height of the first portion gradually decreases from the first height to a second height along a direction away from the display area; the first height is greater than the second height. The first isolation trench is located on the side of the first portion close to the display area, and at least one of the first portion and the second portion of the organic encapsulation layer covers the orthogonal projection of the first isolation trench on the substrate. The peripheral region includes a plurality of circuit regions arranged sequentially along a direction away from the display area. The plurality of circuit regions in the peripheral region include a first circuit region and a second circuit region arranged sequentially along a direction away from the display area. The first circuit region is provided with a first driving circuit and a plurality of first signal lines providing control signals to the first driving circuit. The second circuit region is provided with a second driving circuit and a plurality of second signal lines providing control signals to the second driving circuit. The first isolation trench, in its orthographic projection onto the substrate, is located between the first signal lines and the second driving circuit. The plurality of first signal lines include at least: a first initial signal line that provides a first initial signal to the first driving circuit; the plurality of second signal lines include at least: a first power supply line that provides a first voltage signal to the second driving circuit; The first isolation groove has a first distance between the edge of the first isolation groove near the display area in the orthographic projection of the substrate and the edge of the first initial signal line away from the display area in the orthographic projection of the substrate; the first isolation groove has a second distance between the edge of the first isolation groove away from the display area in the orthographic projection of the substrate and the edge of the first power line near the display area in the orthographic projection of the substrate. The first flattening layer covers the edge of the first initial signal line near the first isolation groove, and the coverage width is greater than a first distance; the first flattening layer covers the edge of the first power line near the first isolation groove, and the coverage width is greater than a second distance.

2. The display substrate according to claim 1, wherein, The display substrate further includes: a second planarization layer located on the side of the first planarization layer away from the substrate; the second planarization layer has a second isolation groove in the peripheral region, and the orthographic projection of the second isolation groove on the substrate at least partially overlaps with the orthographic projection of the first isolation groove on the substrate.

3. The display substrate according to claim 2, wherein, The orthographic projection of the second isolation trench onto the substrate includes the orthographic projection of the first isolation trench onto the substrate.

4. The display substrate according to claim 1, wherein, In the surrounding area, the first isolation groove extends along a direction parallel to the edge of the display area.

5. The display substrate according to any one of claims 1 to 4, wherein, Along a direction away from the display area, the first isolation trench has a first width of 4 micrometers to 15 micrometers; and in a direction perpendicular to the substrate, the first isolation trench has a first depth of 1.5 micrometers to 3.5 micrometers.

6. The display substrate according to claim 1, wherein, The surrounding area includes at least a first circuit area, a second circuit area, and a third circuit area arranged sequentially along a direction away from the display area.

7. The display substrate according to claim 1, wherein, The first distance is less than the second distance.

8. The display substrate according to claim 7, wherein, The first distance is 3.5 micrometers to 4.5 micrometers, and the second distance is 5.5 micrometers to 7.2 micrometers.

9. The display substrate according to claim 6, wherein, The first driving circuit is electrically connected to multiple first output signal lines, and the second driving circuit is electrically connected to multiple second output signal lines; the third circuit area is provided with a third driving circuit, and the third driving circuit is electrically connected to multiple third output signal lines; the first output signal lines, the second output signal lines, and the third output signal lines extend toward the display area; The first isolation trench overlaps with the orthographic projection of the plurality of second output signal lines and the plurality of third output signal lines on the substrate.

10. The display substrate according to claim 9, wherein, The display area is provided with multiple pixel circuits; The first driving circuit is configured to provide a reset control signal to a plurality of pixel circuits in the display area via the first output signal line; The second driving circuit is configured to provide scanning signals to a plurality of pixel circuits in the display area via the second output signal line; The third driving circuit is configured to provide light emission control signals to multiple pixel circuits in the display area via the third output signal line.

11. The display substrate according to claim 1, wherein, The display substrate further includes: a first inorganic encapsulation layer located on the side of the organic encapsulation layer close to the substrate, a second inorganic encapsulation layer located on the side of the organic encapsulation layer away from the substrate, and a touch structure layer located on the side of the second inorganic encapsulation layer away from the substrate. The touch structure layer includes multiple touch leads in the surrounding area; The projection of the first isolation trench onto the substrate does not overlap with the projection of the touch lead onto the substrate, or the projection of the first isolation trench onto the substrate overlaps with the projection of at least one touch lead onto the substrate.

12. The display substrate according to claim 11, wherein, The multiple touch leads include: multiple first touch leads, one isolation lead, and multiple second touch leads arranged sequentially along a direction away from the display area; Along a direction away from the display area, the isolation lead has a second width, the first touch lead has a third width, and the second touch lead has a fourth width; The second width is greater than the third width, and also greater than the fourth width.

13. The display substrate according to claim 1, wherein, Along a direction away from the display area, the width of the first portion of the organic encapsulation layer is 500 micrometers to 1000 micrometers.

14. The display substrate according to claim 1, wherein, The first height is 28 micrometers to 42 micrometers.

15. The display substrate according to claim 1, wherein, The second height is 20 to 30 micrometers.

16. A display device comprising a display substrate as claimed in any one of claims 1 to 15.

17. A method for fabricating a display substrate, the display substrate comprising a display area and at least a peripheral area surrounding the display area, the fabrication method comprising: A driving circuit layer is formed in the peripheral region of the substrate. A first planarization layer is formed on the side of the driving circuit layer away from the substrate, and the first planarization layer has a first isolation groove in the peripheral region; An organic encapsulation layer is formed on the side of the first planarization layer away from the substrate. The organic encapsulation layer includes a first portion and a second portion located in the peripheral region, with the second portion located on the side of the first portion closer to the display area. The second portion has a first height, and the height of the first portion gradually decreases from the first height to a second height along a direction away from the display area. The first height is greater than the second height. Wherein, the first isolation trench is located on the side of the first portion close to the display area, and at least one of the first portion and the second portion of the organic encapsulation layer covers the orthogonal projection of the first isolation trench on the substrate. The peripheral region includes a plurality of circuit regions arranged sequentially along a direction away from the display area. The plurality of circuit regions in the peripheral region include a first circuit region and a second circuit region arranged sequentially along a direction away from the display area. The first circuit region is provided with a first driving circuit and a plurality of first signal lines providing control signals to the first driving circuit. The second circuit region is provided with a second driving circuit and a plurality of second signal lines providing control signals to the second driving circuit. The first isolation trench, in its orthographic projection onto the substrate, is located between the first signal lines and the second driving circuit. The plurality of first signal lines include at least: a first initial signal line that provides a first initial signal to the first driving circuit; the plurality of second signal lines include at least: a first power supply line that provides a first voltage signal to the second driving circuit; The first isolation groove has a first distance between the edge of the first isolation groove near the display area in the orthographic projection of the substrate and the edge of the first initial signal line away from the display area in the orthographic projection of the substrate; the first isolation groove has a second distance between the edge of the first isolation groove away from the display area in the orthographic projection of the substrate and the edge of the first power line near the display area in the orthographic projection of the substrate. The first flattening layer covers the edge of the first initial signal line near the first isolation groove, and the coverage width is greater than a first distance; the first flattening layer covers the edge of the first power line near the first isolation groove, and the coverage width is greater than a second distance.

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