Improving error floor performance of bf decoder by identifying unreliable check nodes

Abstract

This disclosure relates to techniques related to improving error floor performance of a belief flip (BF) decoder. In some examples, the error floor performance is improved by determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute flip energies of variable nodes (VNs). In this way, flip energies can be more accurately computed, thereby reducing the error floor. The set of unreliable CNs can be constructed by applying various criteria, such as criteria related to path length to unsatisfied CNs, degree of VNs in paths to unsatisfied CNs, and / or check sum values. Path length and VN degree can be used as selection criteria to determine which CNs qualify to join the set of unreliable CNs. Check sum values can be used as a trigger condition for constructing and / or using the set of unreliable CNs.

Description

Background Technology

[0001] Error correction codes (ECCs) are frequently used in various types of data storage devices, such as NAND flash memory. ECCs are also commonly used in data transmission processes. ECCs involve adding redundant or parity data to a message so that even if one or more errors occur during transmission or storage, a receiver equipped with a decoder can recover the message's code. Typically, an ECC decoder can correct a limited number of errors, the number depending on the type of code used and / or the decoder's own error correction capabilities.

[0002] Low-density parity-check (LDPC) codes are an example of ECC. When decoding ECC (including LDPC decoding), a trade-off typically needs to be made between error correction capability and computational cost (e.g., power consumption or processing time). Generally, higher error correction capability leads to more complex decoding processing, higher power consumption, and / or longer processing time. Bit-flip (BF) decoders and minimum-sum (MS) decoders are examples of ECC decoders capable of performing LDPC code decoding. Compared to more complex decoders such as MS decoders, BF decoders are significantly faster but have lower error correction capability. Summary of the Invention

[0003] Techniques related to improving the error floor performance of a BF decoder are described. Specifically, an example of an improved BF decoding method involving utilizing information about the unreliable check node (CN) during the flip decision is described. The error floor is the region in the Code Failure Rate (CFR) versus Failure Bit Count (FBC) curve where the received codeword sequence contains more than a certain number of errors (failure bits), preventing the decoder from successfully decoding a certain percentage of the codewords in the sequence. The number of code failures in the error floor region is small compared to the number of correctly decoded codewords. However, even a small number of code failures may be unacceptable depending on the performance requirements of the computational environment used to transmit or store data.

[0004] In the example, a method for iteratively decoding LDPC codewords involves identifying unsatisfied CNs in a set of CNs during the first iteration. The set of CNs represents the result of applying the parity equation to the LDPC codeword. The method further involves determining a set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and an unsatisfied CN is less than or equal to the maximum allowed path length. The method further involves calculating the flipping energy of each VN in the set of VNs based on the total number of unsatisfied CNs directly connected to a variable node (VN). The flipping energy of each VN in the set of VNs is further calculated based on the total number of satisfied CNs directly connected to a VN and belonging to the set of unreliable CNs. The method further involves updating the bit values ​​of the set of VNs, wherein the update includes, for each VN in the set of VNs, determining whether to flip the bit value of the VN based on the flipping energy of the VN. The method further involves updating the bit values ​​of the set of CNs based on the updated bit values ​​of the set of VNs for use in the next iteration.

[0005] In the example method described above, the set of unreliable CNs can be determined conditioned on a checksum calculated using the bit values ​​of the set of CNs that are less than or equal to a threshold. Further, the threshold can be set to a value associated with the expected checksum in the error flat region.

[0006] In the example method described above, determining the set of unreliable CNs may involve excluding CNs that are connected to unsatisfied CNs via a height VN. The height VN can be any VN directly connected to CNs exceeding a threshold number. In some implementations, the threshold number of CNs is less than or equal to five.

[0007] In the example method described above, the LDPC codeword can be a quasi-cyclic LDPC codeword.

[0008] In the example method described above, the set of VNs can correspond to a parity check matrix divided into cyclic submatrices. In this case, the method can further involve restricting the use of the set of unreliable CNs to a subset of VNs in each cyclic submatrix when calculating the flip energy. A subset of VNs can be selected by: selecting a subset of VNs starting from a first direction during the first iteration; and selecting a subset of VNs starting from a second direction opposite to the first direction during the next iteration. The subset of VNs can be selected to include either consecutive or discontinuous VNs.

[0009] In the example, the apparatus includes a memory storing LDPC codewords. The apparatus further includes one or more processing units configured to identify unsatisfied CNs within a set of CNs during a first iteration. The set of CNs represents the result of applying parity equations to the LDPC codewords. The one or more processing units are further configured to determine a set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and an unsatisfied CN is less than or equal to the maximum allowed path length. The one or more processing units are further configured to calculate the flip energy of each variable node (VN) in the set of VNs based on the total number of unsatisfied CNs directly connected to VNs and, more importantly, the total number of satisfied CNs directly connected to VNs and belonging to the set of unreliable CNs. The one or more processing units are further configured to update the bit values ​​of the set of VNs by determining, for each VN in the set of VNs, whether to flip the bit value of that VN based on the flip energy of the VN. The one or more processing units are further configured to update the bit values ​​of the set of CNs based on the updated bit values ​​of the set of VNs for use during the next iteration.

[0010] In the example apparatus described above, the apparatus can be configured to determine the set of unreliable CNs only in response to determining that the checksum calculated using the bit values ​​of the set of CNs is less than or equal to a threshold. In some embodiments, the threshold is set to a value associated with the expected checksum in the error flat region.

[0011] In the example apparatus described above, the apparatus can be configured to exclude any CN that is connected to an unsatisfied CN via a height VN from the set of unreliable CNs. The height VN can be any VN directly connected to more than a threshold number of CNs. In some embodiments, the threshold number of CNs is less than or equal to five.

[0012] In the example apparatus described above, the set of VNs may correspond to a parity check matrix divided into cyclic submatrices. In this case, one or more processing units may be further configured to restrict the use of the set of unreliable CNs to a subset of VNs in each cyclic submatrix when calculating the flip energy. To select a subset of VNs, one or more processing units may perform the following operations: during the first iteration, select a subset of VNs starting from a first direction; and during the next iteration, select a subset of VNs starting from a second direction opposite to the first direction. The subset of VNs may be selected to include either consecutive VNs or discontinuous VNs.

[0013] In the example, the error correction system includes multiple LDPC decoders, including at least a first LDPC decoder and a second LDPC decoder. The second LDPC decoder is a BF decoder configured to decode LDPC codewords in a shorter time than the first LDPC decoder. The BF decoder is configured to identify unsatisfied CNs in the set of CNs during the first iteration. The set of CNs represents the result of applying the parity equation to the LDPC codeword. The BF decoder is further configured to determine the set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and an unsatisfied CN is less than or equal to the maximum allowed path length. The BF decoder is further configured to calculate the flip energy of each variable node VN in the set of VNs based on the total number of unsatisfied CNs directly connected to VNs and, more importantly, the total number of satisfied CNs directly connected to VNs and belonging to the set of unreliable CNs. The BF decoder is further configured to update the bit values ​​of the set of VNs by determining, for each VN in the set of VNs, whether to flip the bit value of that VN based on the flip energy. The BF decoder is further configured to update the bit values ​​of the CN set based on the bit values ​​of the updated VN set for use during the next iteration.

[0014] In the example error correction system described above, the BF decoder can be configured to determine the set of unreliable CNs only in response to the determination that the checksum calculated using the bit values ​​of the set of CNs is less than or equal to a threshold. In some implementations, the threshold is set to a value associated with the expected checksum in the error flat region.

[0015] In the example error correction system described above, the BF decoder can be configured to exclude any CN that is connected to an unsatisfied CN via a height VN from the set of unreliable CNs. The height VN is any VN directly connected to more than a threshold number of CNs. In some implementations, the threshold number of CNs is less than or equal to five.

[0016] The illustrative examples mentioned are not intended to limit or define the scope of this disclosure, but are provided to aid understanding. Additional embodiments and examples are discussed in the detailed description, and further explanation is provided therein. Attached Figure Description

[0017] An understanding of the nature and advantages of the various embodiments can be achieved by referring to the following drawings. In the drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second reference numeral to distinguish similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar parts having the same first reference numeral, regardless of the second reference numeral.

[0018] Figure 1 Example graphs of code failure rate versus failure bit count for a conventional BF decoder are shown, along with corresponding graphs of a BF decoder implemented using the example techniques described herein.

[0019] Figure 2 A high-level block diagram of an error correction system according to certain embodiments of the present disclosure is shown.

[0020] Figure 3A and Figure 3B An example parity check matrix and an example diagram representing a parity check matrix are shown according to certain embodiments of the present disclosure.

[0021] Figure 4 An example representation of a set of variable nodes that can be used for loop-based decoding of codewords according to certain embodiments of this disclosure is shown.

[0022] Figure 5 An example structure of a computer system according to certain embodiments of the present disclosure is shown.

[0023] Figure 6 An example of an error correction system including multiple ECC decoders according to certain embodiments of the present disclosure is shown.

[0024] Figure 7 An example process for identifying unreliable check nodes according to certain embodiments of this disclosure is shown.

[0025] Figure 8 A flowchart illustrating an example process for decoding codewords according to certain embodiments of this disclosure is shown.

[0026] Figure 9 A flowchart illustrating an example process for decoding codewords according to certain embodiments of this disclosure is shown.

[0027] Figure 10 A computer system that can be used to implement one or more embodiments of the present disclosure is shown. Detailed Implementation

[0028] In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. These figures and descriptions are not intended to be limiting.

[0029] Techniques related to improving the error flattening performance of bit-flip (BF) decoders are described. In particular, an example of an improved BF decoding method involving reducing the error flattening region of a BF decoder by utilizing information about unreliable check nodes during the flip decision is described. Figure 1 Example graph 105 shows the code failure rate (CFR) versus failure bit count (FBC) of a conventional BF decoder. Figure 1 This is only to illustrate the general shape of curve 105, i.e., its curved shape. Therefore, the units for each axis have been intentionally omitted. Figure 1 As shown, the curve is characterized by an error flattening 110, where a relatively small number of code failures occur once a certain number of failure bits appear in the codeword sequence. For example, forty failure bits might correspond to a CFR of 0.1%. The error flattening 110 has a relatively flat slope, causing the code failure rate to gradually increase with the count of failure bits. Once the count of failure bits exceeds the maximum number of failure bits associated with the error flattening, the code failure rate increases rapidly (e.g., fifty failure bits might correspond to a CFR of 1%) until at some point 100% of the code fails. The error flattening 110 reflects that once a threshold number of failure bits are present, a conventional BF decoder cannot successfully decode the codeword. Ideally, the curve should continue to tend downwards with a steep slope as the number of failure bits decreases. Therefore, the example technique described herein aims to reduce the error flattening by enhancing the error correction capability of the BF decoder.

[0030] Figure 1 Also shown is a graph 120 illustrating the CFR versus FBC of a BF decoder implemented using the example techniques described herein. Figure 1 As shown, curve 120 is the same as curve 105 at high fault bit counts. However, curve 120 shows a lower error flat area (not shown). For the same fault bit count in the error flat area 110 of curve 105, the corresponding code failure rate in curve 120 is significantly lower.

[0031] Figure 2 A high-level block diagram of an error correction system 200 according to certain embodiments of the present disclosure is shown. In the example, a low-density parity-check (LDPC) code is described in conjunction with a data storage device. However, embodiments of the present disclosure are not limited thereto. Rather, embodiments are similarly applied to other uses of LDPC codes, including, for example, data transmission. Furthermore, embodiments of the present disclosure can be similarly applied to other error correction codes that can identify unreliable check nodes.

[0032] LDPC codes are linear block codes defined by a sparse parity check matrix H, which consists of 0s and 1s. In this paper, the term "sparse matrix" refers to a matrix in which the number of non-zero values ​​in each column and each row is much smaller than the dimension. The term "column weight" refers to the number of non-zero values ​​in a specific column of the parity check matrix H. The term "row weight" refers to the number of non-zero values ​​in a specific row of the parity check matrix H. Generally, if the column weights of all columns in the parity check matrix corresponding to the LDPC code are similar, the code is called a "regular" LDPC code. On the other hand, if at least one of the column weights is different from the weights of the other columns, the LDPC code is called "irregular". Generally, irregular LDPC codes provide better error correction capabilities than regular LDPC codes.

[0033] LDPC codes are also classified according to their construction method. They can be constructed using random computer search or algebraic methods. Random computer search construction describes LDPC codes with a parity check matrix based on random computer programming. Algebraic construction refers to the parity check matrix being constructed using a combinatorial method. Quasi-cyclic LDPC (QC-LDPC) codes belong to the latter construction method. One advantage of QC-LDPC codes is their relatively easy implementation in terms of coding procedures. The main characteristic of QC-LDPC codes is that the parity check matrix consists of cyclic submatrices, which can be based on an identity matrix or a small random matrix. Cyclic submatrices can also be created using commutative vectors.

[0034] As shown in the figure, the LDPC encoder 210 receives information bits including data to be stored in the storage system 220. The LDPC-encoded data is output by the LDPC encoder 210 and written to the storage system 220. In various embodiments, the storage system 220 may include various storage types or media, such as (e.g., magnetic) disk drive storage, flash memory, etc. In some embodiments, this technology is applied to a transceiver, and data is transmitted and received via wired and / or wireless channels instead of being written to or read from the storage device. In this case, errors in the received codewords may be introduced during codeword transmission.

[0035] When data is requested or otherwise demanded (e.g., by an application or user storing the data), detector 230 receives data from storage system 220. The received data may include some noise or errors. Detector 230 performs detection on the received data and outputs decision and / or reliability information. For example, a soft-output detector outputs reliability information and a decision for each detected bit. On the other hand, a hard-output detector outputs a decision for each bit without providing corresponding reliability information. As an example, a hard-output detector may output a decision that a particular bit is "1" or "0" without indicating how certain or confident the detector is about that decision. In contrast, a soft-output detector outputs the decision and the reliability information associated with it. Typically, the reliability value indicates the detector's certainty about a given decision. In one example, a soft-output detector outputs the log-likelihood ratio (LLR), where the sign represents the decision (e.g., a positive value corresponds to a "1" decision and a negative value corresponds to a "0" decision) and the magnitude represents the detector's certainty about that decision (e.g., a larger magnitude indicates high reliability or certainty).

[0036] Decision and / or reliability information is passed to LDPC decoder 240, which performs LDPC decoding using the decision and reliability information. The soft input decoder utilizes both the decision and reliability information to decode the codeword. The hard decoder uses only the decision value from the decoder to decode the codeword. The decoded bits generated by LDPC decoder 240 are passed to the appropriate entity (e.g., the user or application requesting the decoded bits). Through appropriate encoding and decoding, the information bits are matched with the decoded bits.

[0037] While the output of detector 230 may be beneficial to some LDPC decoders, not all error correction systems are configured with detectors. Furthermore, the processing performed by detector 230, particularly regarding the computation of reliability information, can be computationally intensive, potentially significantly offsetting the advantages of using a faster decoder such as a BF decoder. Therefore, in some embodiments, LLR or other reliability information provided by a detector such as detector 230 is not used as input to the BF decoder. Instead, the BF decoder can be configured to determine reliability for itself, for example, by identifying unreliable check nodes using techniques described below. However, the output of detector 230 can still be used to generate inputs for other decoders in the error correction system. Error correction system 200 may include multiple ECC or LDPC decoders forming a decoder hierarchy in which decoding is first attempted using a faster and / or less complex decoder (e.g., a BF decoder), followed by a slower and / or more complex decoder (e.g., an MS decoder). Therefore, error correction system 200 may include one or more additional LDPC decoders (e.g., LDPC decoder 250 and LDPC decoder 260), wherein at least some of the additional LDPC decoders (e.g., such as...) Figure 2 As shown, the LDPC decoder 260 does not receive the output of the detector 230. Furthermore, in the case of a BF decoder implemented according to one or more embodiments described herein, such a BF decoder may optionally be configured to use decision information from a detector such as detector 230.

[0038] In various embodiments, such as Figure 2 The error correction system of System 200 can be implemented using a variety of technologies, including Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and / or general-purpose processors (e.g., advanced RISC machine (ARM) cores).

[0039] LDPC codes are typically represented using a bipartite graph. One set of nodes, the variable nodes (VN, also called bit nodes), corresponds to the elements of the codeword, while another set of nodes (e.g., parity nodes) corresponds to the set of parity check constraints satisfied by the codeword. Typically, edge connections are randomly selected. Avoiding short cycles in the graph can improve the error correction capability of LDPC codes. In an (r, c) regular code, n variable nodes (e.g., V0, V1, V2, ..., V...) n-1 Each of the nodes in the array is connected to r check nodes, and the m check nodes (C10, V1, V2, ..., V...) are connected to r check nodes. m-1Each of the nodes in the code is connected to c variable nodes. Each parity node represents a separate parity equation. Therefore, r corresponds to the number of parity equations involving each code bit and the degree of each variable node. Similarly, c corresponds to the number of code bits involved in each parity equation and the degree of each parity node. The number of variable nodes (n) corresponds to the total number of bits (data and parity) in the code, i.e., the codeword length.

[0040] In irregular LDPC codes, the degree of the parity check node is not uniform. Similarly, the degree of the variable nodes is also not uniform. In QC-LDPC codes, the parity check matrix H can be constructed as a p×p matrix block such that the bits in the block participate in only one parity check equation within that block, and each parity check equation in the block involves only one bit in the block. In QC-LDPC codes, a codeword cyclically shifted by p produces another codeword. Here, p is the size of the square matrix, which can be a zero matrix or a cyclic matrix. This is a generalization of cyclic codes, where a codeword cyclically shifted by 1 produces another codeword. A p×p matrix block can be a zero matrix or a cyclically shifted identity matrix of size p×p.

[0041] According to certain embodiments of this disclosure, Figure 3A An example parity check matrix H 300 is shown, and Figure 3B An example bipartite graph corresponding to parity matrix 300 is shown. In this example, parity matrix 300 has six column vectors and four row vectors. In reality, parity matrices are often much larger. Network 302 forms a bipartite graph representing parity matrix 300. Various types of bipartite graphs may exist, including, for example, Tanner graphs.

[0042] Typically, variable nodes in network 302 correspond to column vectors in parity check matrix 300. Parity nodes in network 302 correspond to row vectors in parity check matrix 300. The interconnections between nodes are determined by the values ​​of parity check matrix 300. Specifically, "1" indicates that CN and VN at the corresponding row and column positions are connected. "0" indicates no connection. For example, "1" in the leftmost column vector and the second row vector from the top of parity check matrix 300 corresponds to... Figure 3B The connections between VN304 and CN 310 correspond to each other. In general, the parity node representation is a corrector calculated by applying the parity equation, represented by the parity check matrix 300, to the received codeword. The corrector weight (also called the checksum) can be calculated by summing the bit values ​​of all the parity nodes.

[0043] Message passing algorithms are commonly used for decoding LDPC codes. Several variations of message passing algorithms exist in this field, such as the minimum sum (MS) algorithm and the sum-product (SPA) algorithm. Figure 3BAs shown, message passing uses a network of variable nodes and check nodes. Figure 3A As shown, the connection between the variable node and the parity node is described by the value of the parity check matrix 300, and the connection between the variable node and the parity node corresponds to the value of the parity check matrix 300. The content of the message passed from the variable node to the parity node (or vice versa) depends on the message passing algorithm used.

[0044] In some instances, a hard-decision messaging algorithm can be implemented. In the first step, each variable node sends a message to one or more check nodes connected to that variable node. In this case, the message is a value that each variable node considers correct. The value of a variable node can be initialized based on the received codeword.

[0045] In the second step, each check node uses the information it previously received from the variable nodes to calculate the response to be sent to the variable nodes connected to that check node. This step can be called Check Node Update (CNU). The response message corresponds to the value that the check node believes the variable node should have based on information received from other variable nodes connected to that check node. This response is calculated using a parity equation that makes the sum of the values ​​of all variable nodes connected to a particular check node zero (modulo 2).

[0046] At this point, if all equations at all check nodes are satisfied, meaning the value of each check node is zero, the resulting checksum is also zero. Therefore, the decoding algorithm declares that the correct codeword has been found and terminates decoding. If the correct codeword is not found (e.g., the value of any check node is 1), the iteration continues using messages received by the variable node from the check nodes (e.g., using a majority voting rule) to perform another update from the variable node, determining whether the bit at its position should be 0 or 1. In the majority voting rule, the value of the variable node is set to the value of the majority of check nodes connected to that variable node. The variable node then sends this hard decision message to the check nodes connected to it. Iteration continues until the correct codeword is found, performing a certain number of iterations based on the corrector of the codeword (e.g., the decoded codeword), or a maximum number of iterations if the correct codeword is not found. It is important to note that the soft-decision decoder works similarly; however, each message passed between the check nodes and variable nodes can also include reliability information for each bit.

[0047] In the example, at least one iterative decoder in the error correction system (e.g., error correction system 200) is configured to perform a message passing algorithm as follows. However, the message passing algorithms between decoders may differ. For example, the error correction system may include a second iterative decoder configured to perform a different message passing algorithm. In this instance, L(qij) represents the variable node v. i Send to verification node c j Message; L(r) ji ) indicates the verification node c j Send to variable node v i The message; and L(c i ) represents each variable node v i The initial LLR value. The processing of each variable node of L(qij) can be completed through the following steps:

[0048] (1) Read L(c) from memory i ) and L(r ji ).

[0049] (2) Calculation

[0050] (3) Calculate each L(Qi-sum) – L(r) ij ).

[0051] (4) Output L(Qi-sum) and write it back to memory.

[0052] (5) If this is not the last column of memory, go to step 1 and increment i by 1.

[0053] (6) Calculate the parity check sum (e.g., the calibrator). If they are all equal to zero, the iteration count has reached a threshold and the parity check sum is greater than another threshold, or the iteration count is equal to the maximum limit. Stop the iteration. Otherwise, perform check node processing.

[0054] For each L(r) ji The verification node processing can be performed as follows:

[0055] (1) Read q from memory ij of a line.

[0056] (2) Calculate L(Rj-sum) as shown below:

[0057]

[0058] α ij =sign(L(q) ij )),β ij =|L(q) ij )|,

[0059]

[0060] (3) Calculate each for the verification node

[0061] (4) Let L(r) ji Write back to memory.

[0062] (5) If this is not the last column of memory, go to step 1 and increment j by 1.

[0063] Figure 4 An example representation of a set of variable nodes, according to certain embodiments of this disclosure, is shown that can be used for cycle-based decoding of codewords (e.g., QC-LDPC codewords). As described above, the parity check matrix H can be used for decoding LDPC codewords. Figure 4 In the example, the parity check matrix H400 includes a cyclic submatrix. The cyclic submatrix corresponds to a matrix within the parity check matrix H400, where different columns of that matrix have the same weight. In other words, each column of the parity check matrix H400 corresponds to a variable node. A "1" in the column corresponding to a variable node indicates a connection between that variable node and the check node. The total number of "1s" in that column represents the total number of connections, and this total number is both the weight of the column and the degree of the variable node. Variable nodes represented in the cyclic submatrix have the same number of "1s," and therefore the same number of connections to check nodes (although the check nodes can be different) and the same degree.

[0064] exist Figure 4 In the example, the parity check matrix H 400 comprises a first cyclic submatrix 410 and a second cyclic submatrix 420, among multiple cyclic submatrixes. The first cyclic submatrix 410 comprises a column of positive integers "W1" representing "W1" variable nodes. Each of these variable nodes has a degree of 2, indicating that each variable node is directly connected to two parity check nodes. Similarly, the second cyclic submatrix 420 comprises a column of positive integers "W2" representing "W2" variable nodes. Each of the variable nodes in the cyclic submatrix 420 has a degree of 3.

[0065] Typically, the parity check matrix H 400 includes "W i A set of variable nodes (by "W") i (Column representation). Each set has the same degree. The degrees between sets can be different, and some sets can have the same degree. In the example, "W i "The degree of a set of variable nodes (e.g., the degree of each variable in the set) can be a value between 1 and 20. Degrees less than or equal to five are generally considered low degrees. Degrees greater than or equal to six are generally considered high degrees. The positive integer 'W' represents the degree of each set of variable nodes."i The value "W1" represents the size of the set (e.g., the number of variable nodes, or equivalently, the number of columns) and can be a value between, for example, 1 and 2480. For example, "W1" could be 128, and "W2" could be 256.

[0066] Vertical decoding can be performed based on the parity check matrix H 300. For example, it can be achieved by selecting and processing "W". i "Selection and processing before the next set of variable nodes" W i "A set of variable nodes is used to perform decoding. For example, the variable nodes in the set "W1" are processed first, then the variable nodes in the set "W2", and so on. Typically, each decoding iteration involves processing all cyclic submatrices in the parity check matrix, but not necessarily all at once. For example, a single iteration can occur over multiple clock cycles, with one or more cyclic submatrices being processed in each clock cycle."

[0067] Figure 4 This is merely an example of how a parity check matrix can be divided into cyclic submatrices for processing. Although Figure 4 Each cyclic submatrix is ​​described as all rows across the parity matrix, but this is not always the case. For example, in some embodiments, a cyclic submatrix may correspond only to a subset of the rows within the parity matrix.

[0068] Figure 5 An example structure of a computer system 500 according to certain embodiments of the present disclosure is shown. In the example, the computer system 500 includes a host 510 and one or more solid-state drives (SSDs) 520. The host 510 represents, for example, the SSD 520, a client storing data. The data is stored as codewords in the SSD to implement ECC protection. For example, the SSD may include one or more ECC encoders (e.g., Figure 2 Error correction system for LDPC encoder 210.

[0069] Host 510 can receive requests for client data stored in SSD 500 from the client. In response, the host sends a data read command 512 to SSD 520 when applicable. Each of SSDs 520 processes the received data read command and sends a response 522 to host 510 upon completion of processing. Response 522 may include read data and / or decoding failure. In this example, each of the SSDs includes at least one ECC decoder (e.g., Figure 2(One or more LDPC decoders in the SSD 520). Further, at least one of the SSD 520s may include a BF decoder. Specifically, some or all of the SSD 520s may include a BF decoder that considers information about unreliable check nodes when determining whether to flip the bit value of a variable node, wherein the information about unreliable check nodes is determined by constructing a set of unreliable check nodes using the techniques described below.

[0070] Processing data read commands and sending responses 522 includes decoding codewords stored in the SSD by an ECC decoder to output read data and / or decoding failure. Some of the codewords can be decoded by a BF decoder, for example, by using the combination described above. Figure 4 The description refers to the BF decoder for vertical decoding or some other decoding techniques applied to cyclic submatrices.

[0071] In an example of an SSD 520 including a BF decoder and one or more additional ECC decoders, the SSD can be configured to attempt initial decoding of its stored codewords using the BF decoder. While the BF decoder is decoding, one or more additional ECC decoders can remain inactive. If the BF decoder's decoding is unsuccessful, the SSD can (e.g., based on hierarchical order) select one of the additional ECC decoders to perform decoding. Therefore, one or more additional ECC decoders can be used as backup decoders if the BF decoder cannot fully decode the codewords. The backup decoder does not need to process all the codewords input to the BF decoder. Instead, in some examples, the input to the backup decoder is a subset of the input to the previously selected decoder, where this subset corresponds to the codewords that the previously selected decoder failed to fully decode. Furthermore, some additional ECC decoders can operate in parallel with the BF decoder to perform parallel processing of codewords. For example, as shown below... Figure 6 The discussion suggests that the set of incoming codewords can be distributed between the BF decoder and the MS decoder so that each decoder processes a different subset of the codewords.

[0072] Solid-state drives (SSDs) are typically storage devices that continuously store data or temporarily cache data in non-volatile semiconductor memory for use by storage systems, such as servers and direct-attached storage (DAS) devices in data centers. With an increasing number of applications requiring high data throughput and low transaction latency, SSDs are being used as a viable storage solution to improve performance, efficiency, and reliability. SSDs typically use NAND flash memory and offer higher performance and consume less power than rotating hard disk drives (HDDs). NAND flash memory has some inherent problems associated with it, the two most important being: NAND flash cells wear down during repeated writes, resulting in a limited expected lifespan; and the naturally occurring error rate. SSDs can be designed and manufactured according to a set of industry standards that define specific performance specifications, including latency specifications, to support larger write workloads, more extreme environmental conditions, and recovery from higher bit error rates (BER) than client-side SSDs (e.g., PCs, laptops, and tablets).

[0073] Figure 6 An example of an error correction system 600 including multiple ECC decoders according to certain embodiments of the present disclosure is shown. The error correction system 600 may include, for example... Figure 5 In the SSD520 memory device. Furthermore, the error correction system 600 includes a controller 610, a memory buffer 620 corresponding to the BF decoder 630, and a memory buffer 640 corresponding to the minimum sum (MS) decoder 650. The controller 610 can determine which of the two decoders 630 and 650 will be used to decode different codewords 602 based on an estimate of the number of original bit errors for each of the codewords. Since noise can cause bit errors, codeword 602 may include noisy codewords. The BF decoder 630 outputs a decoded bit 604 corresponding to one or more codewords 602, wherein the decoded bit 604 removes some or all of the noise (e.g., corrects error bits). Similarly, the MS decoder 650 outputs a decoded bit 606 corresponding to the remaining one or more codewords 602, wherein the decoded bit 606 removes some or all of the noise (e.g., corrects error bits).

[0074] If controller 610 determines that the codeword has a severe bit error rate, both decoders 630 and 650 may fail to decode it. In this case, assuming that decoders 630 and 650 are the only decoders in the error correction system 600, controller 610 can instead omit decoding entirely and output the error information. Otherwise, when controller 610 determines that the bit error rate is within the error correction capability of BF decoder 630, the codeword can be assigned to BF decoder 630. Alternatively, when controller 610 determines that the bit error rate is outside the error correction capability of BF decoder 630 but within the error correction capability of MS decoder 650, the codeword can be assigned to MS decoder 650. Assigning the codeword includes storing the codeword into one of memory buffers 620 or 640 according to the determination of controller 610. Memory buffers 620 and 640 are used because in some cases the decoding latency is slower than the data read rate of the host reading codeword 602.

[0075] Therefore, over time, codeword 602 is stored in different input queues of the BF decoder 630 and the MS decoder 650. For typical SSD usage, it is expected that most traffic will go to the BF decoder 630. Therefore, improving the performance of the BF decoder is crucial. Although Figure 6 The diagram shows only one low-latency and high-throughput decoder (BF decoder 630) and one high-error-correction-capability decoder (MS decoder 650), but different numbers of decoders can be used. For example, a second BF decoder can also be used, and the second BF decoder can have the same or different configuration as the BF decoder 630.

[0076] In the example, the BF decoder 630 can process a fixed number of “Wi” variable nodes in one clock cycle. In other words, for each of the “Wi” variable nodes to be processed in that cycle, the BF decoder 630 counts the number of unsatisfied neighboring check nodes. As used herein, the term “neighboring” means directly connected via a single graph edge. Therefore, for a given variable node, neighboring check nodes are those check nodes directly connected to that variable node. However, in some embodiments, neighboring check nodes may be check nodes that are farther apart (e.g., connected via a path of length 2).

[0077] The count of adjacent unsatisfied check nodes is used to calculate the flip energy of the variable node. As described below, the total number of adjacent satisfied but unreliable check nodes can be further considered to calculate the flip energy of at least some variable nodes. Once the flip energy of the variable node is calculated, the BF decoder 630 compares this value with a flip threshold. If the flip energy is greater than the flip threshold, the BF decoder 630 flips the current bit value of the variable node.

[0078] Processing of all variable nodes of an LDPC code in a single iteration can occur over multiple clock cycles. In an example characterized by cyclic submatrices, each clock cycle may involve calculating the flip energy of the variable nodes associated with one or more cyclic submatrices and thus updating the bit values ​​of those variable nodes. Typically, all cyclic submatrices are processed in a single iteration. At the end of the iteration, the BF decoder 630 uses the updated bit values ​​of the variable nodes to update the bit values ​​of the check nodes, and if any of the check nodes is still not satisfied or the maximum allowed number of iterations has not yet been reached, the BF decoder 630 can proceed to the next iteration.

[0079] To improve the error correction capability of BF decoders such as the BF decoder 630, the flip energy of at least some variable nodes can be calculated by considering the total number of adjacent satisfied but unreliable check nodes. This makes the flip energy more indicative of the likelihood of bit errors in variable nodes. Aspects of this disclosure relate to identifying unreliable check nodes, and more specifically, to unreliable check nodes associated with error-flat regions of the BF decoder. Because if the flip energy is calculated solely based on the total number of adjacent unsatisfied check nodes, the flip energy may be very close to (e.g., slightly below or slightly above) the flip threshold, making it difficult to make bit-flipping decisions in error-flat regions. In some cases, this can lead to infinite loops, i.e., without a limit on the maximum allowed number of iterations, some variable nodes and their connected check nodes will infinitely flip back and forth between the same values.

[0080] Error flattening areas in the decoder are attributed to trap sets. Each trap set represents an error pattern and is a specific combination of variable nodes; if the bit values ​​of all variable nodes in the trap set are incorrect, the decoder will be unable to correct these errors. Decoders with higher error correction capabilities will have fewer trap sets and / or larger trap sets compared to decoders with lower error correction capabilities. For example, a traditional BF decoder has a larger number of trap sets compared to an MS decoder, which leads to code failures with a lower failure bit count. As mentioned above, one advantage of BF decoders is their decoding speed. Using decoders with higher error correction capabilities may not always be feasible due to the additional decoding latency. Another option is to use a BF decoder with more complex messaging techniques (e.g., 2-bit bandwidth messages, where one bit is used to indicate node reliability), but this often becomes costly due to increased implementation complexity (e.g., higher logic gate count) and increased power consumption.

[0081] If the correct bit values ​​of at least some of the variable nodes in the trap set can be determined, the trap set can be "decomposed". Once the correct bit values ​​of a few variable nodes (as few as one node) in the trap set are determined, the decoder will be able to determine the correct bit values ​​of the remaining variable nodes. For an iterative decoder, it may require multiple iterations to decompose the trap set and generate the decoded bits of the codeword, but the bit values ​​will eventually converge to their correct values ​​without introducing any significant additional latency beyond the typical processing time of an iterative decoder.

[0082] To reduce error levels, a decoder configured according to one or more embodiments described herein can identify a set of unreliable check nodes so that these unreliable check nodes are taken into account when calculating the flip energy of variable nodes. Unreliable check nodes are check nodes that are connected to unsatisfied check nodes and are therefore potentially unreliable even if they themselves are satisfied. Unreliable check nodes may cause incorrect calculations of the flip energy of the connected variable nodes, as described below. Figure 7 As mentioned above, unreliable verification nodes can be identified based on path length.

[0083] Figure 7 Example procedures for identifying unreliable parity nodes according to certain embodiments of the present disclosure are illustrated. Referring to Figure 700 corresponding to the parity check matrix, the process is described. Figure 7 The process. With Figure 3B Unlike the diagram shown, Figure 700 is expanded to better illustrate the interaction between variable nodes and check nodes, and how the value of a check node affects the value of a variable node, and vice versa, even if the check node and variable node may not be directly connected. Furthermore, it should be understood that Figure 700 may only represent a portion of the parity check matrix; that is, Figure 700 may be a partial graph. In reality, the graph of a parity check matrix is ​​usually much larger, and the paths connecting the various nodes may be more numerous than those shown. Figure 7 The diagram shows something more complex.

[0084] Figure 700 includes node C that did not meet the verification requirements. x 702. The bit values ​​of the variable node and check node in Figure 700 can be initialized based on the received codeword, for example, by setting the bit value of the variable node to the value of the corresponding bit in the codeword and performing check node processing to update the bit value of the check node based on the initial bit value of the variable node and according to the parity check equation. Figure 7 As shown, the verification node 702 failed to meet the requirement through variable node V. a 705 connects to check node C a 704, and through variable node V b 707 connects to check node C b 706. Furthermore, verification nodes 704 and 706 are respectively connected to variable node V.j 701 and V k 703.

[0085] Because variable node 701 is connected to unsatisfied check node 702 (albeit indirectly), the bit value of variable node 701 may be incorrect and may need to be flipped. Similarly, because variable node 703 is connected to unsatisfied check node 702, the bit value of variable node 703 may also need to be flipped. Figure 7 The diagram illustrates a set 710 of five check nodes, including check node 704, directly connected to variable node 701. In error-flat regions, situations often arise where there is no clear majority of adjacent check nodes. For example, three of the five check nodes in set 710 may be satisfied, while the remaining two are not. Therefore, if the decision to flip variable node 701 is based on a majority-voting process considering only the states of adjacent check nodes, the flip decision may not necessarily set the bit value of variable node 701 to the correct value. Furthermore, if the flip decision is based on the flip energy of variable node 701, calculated as by simply summing the number of unsatisfied check nodes in set 710, the flip energy may be very close to the flip threshold. A similar problem may arise with variable node 703, which is directly connected to a set 720 of five check nodes, including check node 706. As explained in further detail below, the presence of unreliable check nodes can also be considered for a more accurate calculation of the flip energy.

[0086] In some examples, a set of unreliable parity nodes is constructed based on identifying nodes that do not meet the parity check. This set of unreliable parity nodes can be a global set applicable to all variable nodes in the parity check matrix. In an iterative decoder, this set of unreliable parity nodes can be reconstructed on each iteration. Figure 7 In the process, the set of unreliable check nodes (750) includes check nodes 704 and 706. To construct the set of unreliable check nodes 750, candidate unreliable check nodes are first identified based on path length. Specifically, candidate unreliable check nodes can be identified as those with a path length less than or equal to the maximum allowed path length. The path length connects to any check node that fails to meet the check (e.g., check node 702). As the path length between a check node and a check node increases, the reliability of the check node increases. In other words, the reliability of a check node is proportional to the path length to the nearest unsatisfied check node. Therefore, the BF decoder can utilize a relatively short maximum allowed path length. (For example, Alternatively, configuration 3) can be used to prevent check nodes connected via longer paths from being considered for inclusion in the set of unreliable check nodes. For example... Figure 7As shown, the length of the connection between the non-compliant check node 702 and check nodes 704 and 706 is 2 (spanning two edges). Therefore, if If the result is 3, then verification nodes 704 and 706 will be identified as candidates.

[0087] Besides path length, another criterion for identifying candidate unreliable check nodes can be the degree of the variable node along the path leading to the unsatisfied check node. The degree of a variable node is the number of check nodes directly connected to it. In error-prone areas, erroneous variable nodes tend to have lower degrees. Therefore, the BF decoder can utilize the relatively low maximum allowed degree (deg). v This configuration excludes check nodes connected to unsatisfied check nodes via height variable nodes from the set of unreliable check nodes. As mentioned above, degrees less than or equal to five are generally considered low degrees, and degrees greater than or equal to six are generally considered high degrees. However, the maximum allowed degree can vary depending on the decoder implementation. Figure 7 In the example, deg v =3, making the variable node V based on a pass degree of 4... c 709 connects to the unsatisfied check node 702, excluding each check node in the set of check nodes 730 from the set of unreliable check nodes 750.

[0088] When constructing the set 750 of unreliable check nodes, the satisfied / unsatisfied states of the check nodes can be ignored. Therefore, the check nodes included in the set 750 of unreliable check nodes can include satisfied check nodes, unsatisfied check nodes, or both. However, as described below, when updating the flip energy of a variable node, only satisfied check nodes within the set of unreliable check nodes can be considered. This is because unsatisfied check nodes may have already been considered during the initial calculation of the flip energy. For example, the flip energy of a variable node can be calculated as the sum of a first term and a second term. The first term corresponds to the total number of adjacent (e.g., directly connected) unsatisfied check nodes. The second term corresponds to the total number of adjacent satisfied check nodes (which also belong to the set of unreliable check nodes). Therefore, in some embodiments, the set of unreliable check nodes can be constructed to include only satisfied check nodes.

[0089] As described above, the set of unreliable check nodes can be a global set applicable to all variable nodes in the parity check matrix. For example, the set 750 of unreliable check nodes can be reconstructed in each iteration after all unsatisfied check nodes are identified in the current iteration. Then, when the flip energy of any variable node needs to be updated during the current iteration, the set 750 of unreliable check nodes can be referenced. The global set of unreliable check nodes provides an efficient way to consider the existence of unreliable check nodes when calculating the flip energy without relying on more complex flip energy calculation techniques and / or more complex forms of reliability information. For example, due to the complexity of the implementation, it may be infeasible to perform a graph search individually for each variable node in order to identify unreliable check nodes for that specific variable node before calculating the flip energy of that specific variable node.

[0090] Figure 8 A flowchart of an example process 800 for decoding a codeword according to certain embodiments of this disclosure is shown. Process 800 can be performed by a BF decoder that receives an ECC (e.g., LDPC code) for decoding. In operation 802, unsatisfied check nodes are identified during the first iteration. The first iteration can be an iteration to compute an initial corrector by applying a parity equation to the bit values ​​of the received codeword. However, the functionality described with respect to the first iteration in process 800 also applies to other iterations. As described above, each check node represents a corresponding bit of the corrector. The checksum (also called the corrector weight) of any particular corrector can be computed by summing the bit values ​​of all bits in the corrector. During iterative decoding, the bit values ​​of the variable nodes are updated to compute a new corrector for each subsequent iteration. A check node is not satisfied when its bit value is 1. A corrector consisting entirely of zeros is associated with an error-free codeword.

[0091] In operation S804, the set of unreliable check nodes is determined as any check node whose path length to an unsatisfied check node (any unsatisfied check node identified in operation 802) is less than or equal to the maximum allowed path length. The function in operation 804 can correspond to: using path length as a selection criterion, identifying an initial set of candidate unreliable check nodes that can be added to the set of unreliable check nodes.

[0092] In operation 806, the set of unreliable check nodes determined in operation 804 is filtered to exclude any check nodes that connect to unsatisfactory check nodes by a variable node whose degree exceeds the maximum permissible degree. The maximum permissible degree may vary depending on the implementation, but is typically set to exclude check nodes connected by a height variable node.

[0093] In operation 808, the flip energy of a variable node is calculated based on the total number of adjacent unsatisfied check nodes. The flip energy is also calculated based on the total number of adjacent check nodes that satisfy the check and belong to the set of unreliable check nodes. For example, the flip energy of a variable node can be calculated as the sum of these two totals. Figure 7 In the example, assuming that check node 704 is satisfied, the flip energy of variable node 701 will increase by 1. Similarly, assuming that check node 706 is satisfied, the flip energy of variable node 703 will increase by 1.

[0094] Further, see the following reference Figure 9 The discussion on using a set of unreliable parity nodes to compute the flip energy may be limited to a subset of the variable nodes. Therefore, not every variable node in the parity matrix needs to compute its flip energy as a function of the number of neighboring parity nodes that satisfy the condition and belong to the set of unreliable parity nodes.

[0095] In operation 810, a separate flip decision is made for each variable node in the parity check matrix. For each variable node, the bit value of the variable node is updated by determining whether to flip the bit value or leave it unchanged based on the flip energy of the variable node. The flip decision may involve comparing the flip energy with a flip threshold, and flipping the bit value in response to determining that the flip energy exceeds the flip threshold.

[0096] In operation 812, the values ​​of the check nodes in the parity check matrix are updated using the bit values ​​of the variable nodes updated in operation 810, in preparation for the next iteration. Process 800 then proceeds to the next iteration, where operations 802 through 812 can be repeated to determine a new set of unreliable check nodes to use when calculating the flip energy in the next iteration. This can continue until a certain maximum allowed number of iterations is reached or the checksum of the current iteration's corrector is zero.

[0097] supply Figure 8 The operation that the BF decoder can perform at a higher level is shown as part of decoding codewords using reliability information obtained as a result of identifying unreliable check nodes. Figure 8 This is an example that only considers the decoding process of unreliable check nodes. Figure 9 A more detailed example of the BF decoding process involving a parity check matrix with cyclic submatrices is shown below. It should be understood that, for example, combinations can be made... Figure 8 and Figure 9 The aspects of the process outlined in the document make process 800 involve additional operations, fewer operations, or operations in a different order.

[0098] Figure 9A flowchart of an example process 900 for decoding a codeword according to certain embodiments of the present disclosure is shown. Process 900 can be performed by a BF decoder that receives an ECC (e.g., a quasi-cyclic LDPC code) for decoding. In operation 902, the bit values ​​of the variable nodes in the parity check matrix are initialized using the received codeword. For example, the bit values ​​of the variable nodes can be set to the values ​​of the corresponding bits in the codeword, which includes data bits and parity bits.

[0099] Additionally, operation 902 includes setting an initial direction for selecting variable nodes. As described below in conjunction with operation 920, a subset of variable nodes can be selected from each cyclic submatrix, and the flip energy of the variable nodes in each selected subset can be updated using information about the unreliable check nodes. In other words, in any given iteration, not every variable node of the cyclic submatrix can have its flip energy calculated using information about the unreliable check nodes. A corresponding index value (e.g., column number) can be assigned to each variable node of the cyclic submatrix. Depending on the direction setting, variable nodes can be selected by increasing or decreasing the index value. In this way, a subset of variable nodes can be selected starting from one end or the opposite end of the cyclic submatrix.

[0100] In operation 904, the bit values ​​of the check nodes are updated based on the bit values ​​of the variable nodes initialized during operation 902. Since this is the first iteration, the check nodes may not have existing bit values, and the update in operation 904 may involve calculating the bit value of each check node using the corresponding parity equation. In this way, the initial corrector can be computed.

[0101] In operation 906, the BF decoder checks if the current iteration equals the maximum allowed number of iterations. The maximum allowed number of iterations can be reconfigured or fixed. If the maximum allowed number of iterations has been reached, process 900 proceeds to operation 908. Otherwise, the process proceeds to operation 910.

[0102] In operation 908, the BF decoder stops decoding and outputs a result, which may include a set of decoded bits, or in some cases, an error message (e.g., one or more flag bits indicating an error code). For example, an error message may be output when operation 908 is performed because the maximum allowed number of iterations has been reached or exceeded before the checksum is zero.

[0103] In operation 910, the BF decoder determines whether the checksum of the current parser (e.g., the initial parser from operation 904) is equal to zero. The checksum is zero when the bit value of each parity node is also zero. If the checksum is zero, this indicates that the codeword has been successfully decoded and process 900 can proceed to operation 908 (stop decoding). Otherwise, the process proceeds to operation 912.

[0104] In operation 912, the flip energy of all variable nodes in the parity check matrix is ​​calculated using the sum of the unsatisfied neighboring parity check nodes. In some examples, for each variable node, the flip energy of the variable node is calculated as the total number of unsatisfied parity check nodes directly connected to the variable node (i.e., via a single edge).

[0105] In operation 914, the BF decoder determines whether the checksum is less than or equal to the checksum threshold CS. th The checksum threshold can be set to a relatively low value (e.g., CS). th =2), to target erroneous flat regions. Erroneous flat regions typically involve a small number of unsatisfied check nodes, so a lower checksum value can be used as a precondition for updating the flip energy based on unreliable check nodes. If the checksum is less than or equal to the checksum threshold, process 900 proceeds to operation 916. Otherwise, the process proceeds to operation 918.

[0106] In operation 916, the BF decoder constructs a global set of unreliable check nodes based on the maximum allowed check node path length and the maximum allowed variable node degree. (As mentioned above...) Figure 7 As discussed, the maximum allowed check node path length refers to the longest allowed check path between an unsatisfied check node and a candidate check node, and the maximum allowed variable node degree refers to the highest allowed degree of any variable node connecting an unsatisfied check node to a candidate check node. Both of these maximum allowed values ​​can be used as criteria for forming a set of unreliable check nodes. The process then proceeds to operation 920.

[0107] In operation 918, the BF decoder flips the values ​​of any variable nodes whose flip energy exceeds the flip threshold. If operation 914 is followed by operation 918, this instructs the BF decoder to operate outside the error flat region. However, the BF decoder can still continue decoding until a stopping condition (e.g., one of the conditions that leads to operation 908) occurs.

[0108] In operation 920, the BF decoder selects a subset of the variable nodes in each loop and updates the flip energy of those selected variable nodes. The update of the flip energy is performed by adding the number of adjacent satisfied check nodes belonging to the set of unreliable check nodes. Therefore, for each variable node belonging to the selected subset, the BF decoder can determine the total number of satisfied check nodes directly connected to the variable node and belonging to the set of unreliable check nodes. The flip energy of the variable node calculated in operation 912 can then be updated by adding this sum.

[0109] A subset of variable nodes is selected based on the selection direction discussed above in conjunction with operation 902. Depending on the selection direction, variable nodes can be selected starting from one side (e.g., the leftmost) or the opposite side (e.g., the rightmost) of the cyclic submatrix. Typically, the subset of variable nodes consists of consecutive variable nodes (e.g., the first five variable nodes or the last five variable nodes). However, some implementations may involve skipping one or more variable nodes, making the subset of variable nodes non-consecutive. For example, a subset of variable nodes can be formed by selecting every other variable node, starting from the leftmost (e.g., the smallest indexed) variable node.

[0110] Limiting the flip energy update to only a subset of the variable nodes in each loop saves processing time. The benefit of using information about unreliable check nodes can be largely achieved without needing to update the flip energy for each variable node. As discussed above, this is because if the correct bit values ​​of even a few variable nodes in the trap set can be determined, the trap set can be decomposed.

[0111] Furthermore, in operation 920, the selection direction will be reversed in the next iteration. In some implementations, the reverse selection direction is performed by toggling a 1-bit flag. Alternating directions between iterations helps avoid reselecting the same variable nodes, thus introducing changes to variable nodes selected based on unreliable check node flip energy modifications. As described above, once the flip energy of the selected subset of variable nodes has been updated and the selection direction has been reversed, process 900 proceeds to the flip decision in operation 918.

[0112] In operation 918, after making a flip decision for each variable node, the BF decoder proceeds to the next iteration (in operation 922), and process 900 returns to operation 904. Therefore, operation 922 may involve incrementing the value of a counter representing the current iteration number. Operations 904 through 922 can be repeated until a stopping condition is met, which causes the decoding in operation 908 to end.

[0113] Figure 10 A computer system 1000 is shown that can be used to implement one or more embodiments of the present disclosure. Figure 10 This is merely an example and does not limit the scope of this disclosure as set forth in the claims. Figure 10 As shown, computer system 1000 may include a display monitor 1010, a computer 1020, a user output device 1030, a user input device 1040, a communication interface 1050, and / or other computer hardware or accessories. Computer system 1000 or selected components of computer system 1000 may be used for implementation. Figure 2 Error correction system 200 and / or Figure 6 Error correction system 600.

[0114] like Figure 10 As shown, computer 1020 may include one or more processors 1060, which communicate with a plurality of peripheral devices via bus subsystem 1090. These peripheral devices may include user output device 1030, user input device 1040, communication interface 1050, and storage subsystems such as random access memory (RAM) 1070 and disk drives or non-volatile memory 1080.

[0115] User input device 1040 includes all possible types of means and mechanisms for inputting information to computer 1020. These may include a keyboard, keypad, touchscreen integrated into the display, audio input devices such as voice recognition systems, microphones, and other types of input devices. In various embodiments, user input device 1040 is typically implemented as a computer mouse, trackball, trackpad, joystick, wireless remote control, drawing tablet, voice command system, eye-tracking system, etc. User input device 1040 typically allows a user to select objects, icons, text, etc., appearing on display monitor 1010 via commands such as clicking buttons.

[0116] User output device 1030 includes all possible types of devices and mechanisms for outputting information from computer 1020. These may include displays (e.g., display monitor 1010), non-visual displays such as audio output devices, etc.

[0117] Communication interface 1050 provides an interface to other communication networks and devices. Communication interface 1050 can be used as an interface for receiving data from and sending data to other systems. Embodiments of communication interface 1050 typically include an Ethernet card, a modem (telephone, satellite, cable, ISDN), an (asynchronous) digital subscriber line (DSL) unit, a FireWire interface, a USB interface, etc. For example, communication interface 1050 can be connected to a computer network, FireWire bus, etc. In other embodiments, communication interface 1050 can be physically integrated onto the motherboard of computer 1020 and can be software, such as softDSL.

[0118] In various embodiments, the computer system 1000 may further include software that enables communication over networks such as HTTP, TCP / IP, RTP / RTSP protocols, etc. In alternative embodiments of this disclosure, other communication software and transport protocols, such as IPX, UDP, etc., may also be used.

[0119] RAM 1070 and disk drive 1080 are examples of tangible media configured to store data such as data (including executable computer code, human-readable code, etc.) as described in embodiments of the present disclosure. Other types of tangible media include: floppy disks, portable hard disks, optical storage media such as CD-ROMs, DVDs, and barcodes, semiconductor memory such as flash memory, non-transitory read-only memory (ROMs), battery-powered volatile memory, network storage devices, etc. RAM 1070 and disk drive 1080 may be configured to store basic programs and data structures that provide the functionality of the present disclosure.

[0120] Software code modules and instructions that provide the functionality of this disclosure may be stored in RAM 1070 and disk drive 1080. These software modules may be executed by processor 1060. RAM 1070 and disk drive 1080 may also provide a repository for storing data used according to this disclosure.

[0121] RAM 1070 and disk drive 1080 may include multiple memories, including main random access memory (RAM) for storing instructions and data during program execution and read-only memory (ROM) for storing fixed, non-temporary instructions. RAM 1070 and disk drive 1080 may include a file storage subsystem for providing persistent (non-volatile) storage for program and data files. RAM 1070 and disk drive 1080 may also include a removable storage system such as removable flash memory.

[0122] The bus subsystem 1090 provides a mechanism for enabling various components and subsystems of the computer 1020 to communicate with each other as intended. Although the bus subsystem 1090 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses.

[0123] It will be apparent to those skilled in the art that many other hardware and software configurations are applicable to this disclosure. For example, computer 1020 may be a desktop, portable, rack-mount, or tablet configuration. Additionally, computer 1020 may be a network of networked computers. In yet another embodiment, the above-described techniques may be implemented on a chip or auxiliary processing board.

[0124] The various embodiments of this disclosure can be implemented in logical form, either in software or hardware, or a combination of both. This logic can be stored as a set of instructions in a computer-readable or machine-readable non-transitory storage medium, the set of instructions being adapted to instruct a processor of a computer system to perform a set of steps disclosed in the embodiments of this disclosure. This logic can form part of a computer program product adapted to direct an information processing apparatus to perform a set of steps disclosed in the embodiments of this disclosure. Based on the disclosure and teachings provided herein, those skilled in the art will understand other ways and / or methods of implementing this disclosure.

[0125] The data structures and code described herein may be stored, in whole or in part, on computer-readable storage media and / or hardware modules and / or hardware devices. Computer-readable storage media include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compressed optical discs), DVDs (digital versatile optical discs or digital video optical discs), or other media now known or hereafter developed capable of storing code and / or data. Hardware modules or devices described herein include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and / or other hardware modules or devices now known or hereafter developed.

[0126] The methods and processes described herein can be implemented, in part or in whole, as code and / or data stored in a computer-readable storage medium or device, such that when a computer system reads and runs the code and / or data, the computer system performs the associated methods and processes. These methods and processes can also be implemented, in part or in whole, in hardware modules or devices, such that when the hardware modules or devices are enabled, they perform the associated methods and processes. The methods and processes disclosed herein can be implemented using a combination of code, data, and hardware modules or devices.

[0127] Although the foregoing embodiments have been described in detail for clarity of understanding, this disclosure is not limited to the details provided. Many alternatives to implementing this disclosure exist. The disclosed embodiments are illustrative and not restrictive.

Claims

1. A method for iterative decoding of low-density parity-check codewords, i.e., LDPC codewords, the method being implemented on a computing device and comprising: During the first iteration, unsatisfied CNs are identified in the set of check nodes, i.e., CNs, where the set of CNs represents the result of applying the parity check equation to the LDPC codeword. Determine a set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and the unsatisfied CN is less than or equal to the maximum allowed path length; The flip energy of each VN in the set of VNs is calculated based on the total number of unsatisfied CNs directly connected to the variable node VN and further based on the total number of satisfied CNs directly connected to the VN and belonging to the set of unreliable CNs. Update the bit values ​​of the set of VNs, wherein the update includes, for each VN in the set of VNs, determining whether to flip the bit value of the VN based on the flip energy of the VN; and Based on the updated bit values ​​of the set of VN, the bit values ​​of the set of CN are updated for use in the next iteration.

2. The method of claim 1, wherein the set of unreliable CNs is determined conditioned on a checksum calculated using bit values ​​of the set of CNs that are less than or equal to a threshold.

3. The method of claim 2, wherein the threshold is set to a value associated with the expected checksum in the error flat region.

4. The method of claim 1, wherein determining the set of unreliable CNs comprises excluding CNs connected to unsatisfied CNs via a height VN, and wherein the height VN is any VN directly connected to more than a threshold number of CNs.

5. The method of claim 4, wherein the number of thresholds for CN is less than or equal to five.

6. The method according to claim 1, wherein the LDPC codeword is a quasi-cyclic LDPC codeword.

7. The method of claim 1, wherein the set of VN corresponds to a parity check matrix divided into cyclic submatrices, the method further comprising: When calculating the flip energy, the use of the set of unreliable CNs is restricted to a subset of VNs in each cyclic submatrix.

8. The method of claim 7, further comprising: During the first iteration, a subset of the VN is selected starting from a first direction; and During the next iteration, a subset of the VN is selected starting from a second direction opposite to the first direction.

9. The method of claim 7, wherein a subset of the VN comprises consecutive VNs.

10. The method of claim 7, wherein a subset of the VN comprises discontinuous VNs.

11. An apparatus comprising: The memory stores low-density parity-check codewords, i.e., LDPC codewords. as well as One or more processing units: During the first iteration, unsatisfied CNs are identified in the set of check nodes, i.e., CNs, where the set of CNs represents the result of applying the parity check equation to the LDPC codeword. Determine a set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and the unsatisfied CN is less than or equal to the maximum allowed path length; The flip energy of each VN in the set of VNs is calculated based on the total number of unsatisfied CNs directly connected to the variable node VN and further based on the total number of satisfied CNs directly connected to the VN and belonging to the set of unreliable CNs. The set of VNs is updated by determining whether to flip the bit value of each VN based on its flip energy for each VN in the set of VNs. and Based on the updated bit values ​​of the set of VN, the bit values ​​of the set of CN are updated for use in the next iteration.

12. The apparatus of claim 11, wherein the apparatus determines the set of unreliable CNs only in response to determining that the checksum calculated using the bit values ​​of the set of CNs is less than or equal to a threshold.

13. The apparatus of claim 12, wherein the threshold is set to a value associated with a checksum expected in the error flat region.

14. The apparatus of claim 11, wherein the apparatus excludes from the set of unreliable CNs any CNs connected to unsatisfied CNs via a height VN, and wherein the height VN is any VN directly connected to more than a threshold number of CNs.

15. The apparatus of claim 14, wherein the number of thresholds of CN is less than or equal to five.

16. The apparatus of claim 11, wherein the set of VNs corresponds to a parity check matrix divided into cyclic submatrices, and wherein the one or more processing units further restrict the use of the set of unreliable CNs to a subset of VNs in each cyclic submatrix when calculating the flip energy.

17. The apparatus of claim 16, wherein the one or more processing units further: During the first iteration, a subset of VN is selected starting from a first direction; and During the next iteration, a subset of the VN is selected starting from a second direction opposite to the first direction.

18. An error correction system, comprising: The first low-density parity-check decoder is the first LDPC decoder; as well as The second LDPC decoder decodes LDPC codewords in a shorter time than the first LDPC decoder. The second LDPC decoder is a bit-flipping decoder. During the first iteration, unsatisfied CNs are identified in the set of check nodes, i.e., CNs, where the set of CNs represents the result of applying the parity check equation to the LDPC codeword. Determine a set of unreliable CNs such that the path length between each CN in the set of unreliable CNs and the unsatisfied CN is less than or equal to the maximum allowed path length; The flip energy of each VN in the set of VNs is calculated based on the total number of unsatisfied CNs directly connected to the variable node VN and further based on the total number of satisfied CNs directly connected to the VN and belonging to the set of unreliable CNs. By determining whether to flip the bit value of each VN in the set of VNs based on the flip energy of the VN, the bit value of the set of VNs is updated. and Based on the updated bit values ​​of the set of VN, the bit values ​​of the set of CN are updated for use in the next iteration.

19. The error correction system of claim 18, wherein the bit-flipping decoder determines the set of unreliable CNs only in response to determining that the checksum calculated using the bit values ​​of the set of CNs is less than or equal to a threshold.

20. The error correction system of claim 18, wherein the bit-flip decoder excludes any CN connected to a non-satisfied CN via a height VN from the set of unreliable CNs, and wherein the height VN is any VN directly connected to more than a threshold number of CNs.

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