Ramp voltage generator and display panel

Abstract

A ramp voltage generator and a display panel are disclosed. The ramp voltage generator includes an output node, a current generation region, and a voltage regulation region. The output node provides a ramp signal. The current generation region is coupled to the output node and includes a detection path to detect output load variations at the output node and adjust the ramp signal provided by the output node based on the output load variations. The voltage regulation region is coupled to the output node to regulate the voltage at the output node.

Description

Technical Field

[0001] This invention relates to a voltage generator, and more particularly to a ramp voltage generator and a display panel. Background Technology

[0002] In recent years, self-emissive displays have emerged, with organic light-emitting diode (OLED) displays and quantum dot light-emitting diode (QLED) displays vying for the exclusive position of liquid crystal displays (LCDs) in display panels. Furthermore, micro-LED displays, based on their numerous superior component characteristics, are expected to become the mainstream of next-generation display technologies.

[0003] In miniature LED displays, pixel circuits receive ramp signals from an external digital-to-analog converter and use these ramp signals, along with written data, to determine the current width of the diodes. Traditionally, digital control signals from a field-programmable gate array (FPGA) are converted into analog signals via a digital-to-analog converter to generate the desired waveform. However, this approach involves a more complex driving architecture and higher costs. Summary of the Invention

[0004] This invention provides a ramp voltage generator and display panel that can detect and compensate for variations in output load, achieving precise grayscale control for pixels.

[0005] The ramp voltage generator of the present invention includes: an output node, a current generation region, and a voltage regulation region. The output node provides a ramp signal. The current generation region is coupled to the output node and includes a detection path to detect output load variations at the output node, and adjusts the ramp signal provided by the output node based on the output load variations. The voltage regulation region is coupled to the output node to regulate the voltage at the output node.

[0006] The display panel of the present invention includes a plurality of pixels, a plurality of gate lines, a plurality of source lines, and a ramp voltage generator as described above. The pixels are arranged in an array. The gate lines individually extend along a first direction and are individually coupled to a portion of the pixels. The source lines individually extend along a second direction perpendicular to the first direction and are individually coupled to a portion of the pixels. The ramp voltage generator is coupled to the pixels to provide ramp signals to the pixels.

[0007] Based on the above, in the ramp voltage generator and display panel of this embodiment, the current generation area detects output load variations at the output node via a detection path, and adjusts the ramp signal provided by the output node based on the output load variations. Therefore, the ramp voltage generator can detect and compensate for output load variations, achieving the ability to precisely control grayscale at the pixel level.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1A A circuit diagram of a ramp voltage generator according to an embodiment of the present invention.

[0010] Figure 1B A schematic diagram of the driving waveform of a ramp voltage generator according to an embodiment of the present invention.

[0011] Figure 2A A circuit diagram of a ramp voltage generator according to another embodiment of the present invention.

[0012] Figure 2B A schematic diagram of the driving waveform of a ramp voltage generator according to another embodiment of the present invention.

[0013] Figure 3 A schematic diagram of a display panel according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100, 200: Slope voltage generator

[0016] 110, 210: Current generation region

[0017] 120, 220: Stabilized voltage range

[0018] 300: Display panel

[0019] A[n], B[n], Q[n], P[n]: Node voltages

[0020] C1: First capacitor

[0021] C2: Second capacitor

[0022] C3: Third capacitor

[0023] C4: Fourth capacitor

[0024] C5: Fifth capacitor

[0025] C6: Sixth capacitor

[0026] C7: Seventh capacitor

[0027] CK, XCK: Clock signals

[0028] Cmp: Compensation period

[0029] d1: First direction

[0030] d2: Second direction

[0031] DL: Source line

[0032] DT1, DT2: Detection paths

[0033] EM[n]: Light emission control signal

[0034] G1-G4: Gate signals

[0035] GL: Gate line

[0036] I REF Current source

[0037] NOP: Output Node

[0038] PX: pixel

[0039] Rt: During reset

[0040] Rt1: First Reset Period

[0041] Rt2: During the second reset

[0042] S1[n]: First control signal

[0043] S1[n+1]: The first control signal of the next stage

[0044] S1-S4: Source signals

[0045] S2[n]: Second control signal

[0046] S2[n+2]: The second control signal of the next level

[0047] SWP: Voltage oscillation period

[0048] T1: First transistor

[0049] T10: Tenth Transistor

[0050] T11: Eleventh transistor

[0051] T12: Twelfth Transistor

[0052] T13: Thirteenth Transistor

[0053] T14: Fourteenth Transistor

[0054] T15: Fifteenth Transistor

[0055] T16: Sixteenth transistor

[0056] T17: The seventeenth transistor

[0057] T18: The eighteenth transistor

[0058] T19: The nineteenth transistor

[0059] T2: Second transistor

[0060] T20: Twentieth Transistor

[0061] T21: Twenty-first transistor

[0062] T22: Twenty-second transistor

[0063] T23: The Twenty-Third Transistor

[0064] T24: Twenty-fourth transistor

[0065] T25: Twenty-fifth transistor

[0066] T26: Twenty-sixth transistor

[0067] T27: The Twenty-Seventh Transistor

[0068] T28: The twenty-eighth transistor

[0069] T3: Third transistor

[0070] T4: Fourth transistor

[0071] T5: Fifth transistor

[0072] T6: Sixth transistor

[0073] T7: Seventh Transistor

[0074] T8: Eighth transistor

[0075] T9: Ninth Transistor

[0076] V GH Gate high voltage

[0077] V GL Gate low voltage

[0078] V H High voltage

[0079] V L Low voltage

[0080] V LL Relatively low voltage

[0081] V REF1 First reference voltage

[0082] V REF2 Second reference voltage

[0083] VS: During voltage stabilization

[0084] Vsweep, Vsweep[n]: ramp signal

[0085] V SWP_H oscillating high voltage

[0086] V SWP_L Oscillating low voltage Detailed Implementation

[0087] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0088] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0089] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0090] Figure 1A A circuit diagram of a ramp voltage generator according to an embodiment of the present invention. Please refer to... Figure 1AIn this embodiment, the ramp voltage generator 100 includes an output node NOP, a current generation region 110, and a voltage regulation region 120. The output node NOP provides a ramp signal Vsweep[n], where n is a leading number. The current generation region 110 is coupled to the output node NOP and includes a detection path DT1 to detect output load variations in the output node NOP via the detection path DT1, and adjusts the ramp signal Vsweep[n] provided by the output node NOP based on the output load variations. The voltage regulation region 120 is coupled to the output node NOP to regulate the voltage of the output node NOP. Therefore, the ramp voltage generator 100 can output the ramp signal Vsweep[n] required by the pixel driven by pulse-width modulation (PWM), and can detect and compensate for output load variations, achieving the ability to accurately control the grayscale of the pixel.

[0091] In this embodiment, the current generating region 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, and a second capacitor C2. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are, for example, P-type transistors, and the first transistor T1, the fourth transistor T4, the first capacitor C1, the second capacitor C2, the eighth transistor T8, and the tenth transistor T10 can form a detection path DT1.

[0092] In this embodiment, the first transistor T1 has the function of receiving a swing high voltage V. SWP_H The transistor has a first terminal, a control terminal, and a second terminal. The second transistor T2 receives the swing low voltage V. SWP_L The first terminal of the transistor T1 includes a control terminal that receives the first control signal S1[n], and a second terminal that is coupled to the control terminal of the first transistor T1. The third transistor T3 has a first terminal, a control terminal that receives the second control signal S2[n], and a second terminal that receives the oscillation low voltage V. SWP_L The second end.

[0093] The first capacitor C1 is coupled between the second terminal of the second transistor T2 and the first terminal of the third transistor T3. The fourth transistor T4 has a first terminal coupled to the second terminal of the first transistor T1, a control terminal receiving the first control signal S1[n+1] (i.e., the third control signal) from the next stage, and a second terminal coupled to the control terminal of the first transistor T1, wherein the first control signal S1[n] and the first control signal S1[n+1] from the next stage differ by a delay unit (e.g., half a clock cycle). The fifth transistor T5 has a function to receive the oscillating low voltage V. SWP_L The first terminal is a control terminal that receives the second control signal S2[n+2] (i.e., the fourth control signal) of the next level, and the second terminal is a second terminal, wherein the second control signal S2[n] differs from the second control signal S2[n+2] of the next level by two delay units (e.g., 2 × 0.5 clock cycles).

[0094] The sixth transistor T6 has a first terminal, a control terminal that receives the light emission control signal EM[n], and a terminal that receives a low voltage V. L The second terminal. The second capacitor C2 is coupled between the first terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The seventh transistor T7 has a first terminal coupled to the first terminal of the sixth transistor T6, a control terminal that receives the first control signal S1[n], and a terminal that receives the swing low voltage V. SWP_L The second terminal. The eighth transistor T8 has a first terminal coupled to the output node NOP, a control terminal that receives the third control signal S1[n+1], and a second terminal coupled to the first terminal of the sixth transistor T6.

[0095] The ninth transistor T9 has a first terminal coupled to the second terminal of the first transistor T1, a control terminal receiving the light emission control signal EM[n], and a second terminal coupled to the output node NOP. The tenth transistor T10 has a first terminal coupled to the output node NOP, a control terminal receiving the first control signal S1[n+1] of the next stage, and a second terminal. Current source I REF It is coupled to the second terminal of the tenth transistor T10.

[0096] In this embodiment, the voltage regulation region 120 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a third capacitor C3, wherein the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are, for example, P-type transistors. The eleventh transistor T11 has a first terminal coupled to the output node NOP, a control terminal, and a terminal for receiving the swing low voltage V. SWP_L The second terminal. The third capacitor C3 is coupled between the control terminal of the eleventh transistor T11 and the clock signal XCK. The twelfth transistor T12 has the function of receiving a relatively low voltage V. LLThe first terminal, the control terminal that receives the second control signal S2[n+2] of the next level, and the second terminal that is coupled to the control terminal of the eleventh transistor T11.

[0097] The thirteenth transistor T13 has the ability to receive oscillating high voltage V. SWP_H The first terminal, the control terminal that receives the second control signal S2[n], and the second terminal that is coupled to the control terminal of the eleventh transistor T11. The fourteenth transistor T14 has a oscillating high voltage V. SWP_H The first terminal, the control terminal that receives the light emission control signal EM[n], and the second terminal that is coupled to the control terminal of the eleventh transistor T11.

[0098] Figure 1B A schematic diagram of the driving waveform of a ramp voltage generator according to an embodiment of the present invention. Please refer to... Figure 1A and Figure 1B In this embodiment, the ramp voltage generator 100 operates sequentially during the first reset period Rt1, the compensation period Cmp, the second reset period Rt2, the voltage oscillation period SWP, and the voltage regulation period VS.

[0099] During the first reset period Rt1, the first control signal S1[n] and the second control signal S2[n] are at the enable level (e.g., gate low voltage V). GL Furthermore, the first control signal S1[n+1] of the next level, the second control signal S2[n+2] of the next level, and the light emission control signal EM[n] are at disabled levels (e.g., high gate voltage V). GH At this time, transistors T2, T3, T7, and T13 are turned on, while transistors T4, T5, T6, T8, T9, T10, T12, and T14 are turned off. Furthermore, the node voltage Q[n] at the control terminal of transistor T1 is a low oscillating voltage V. SWP_L The node voltage B[n] at the first terminal of the second transistor T3 is the oscillating low voltage V. SWP_L The node voltage A[n] at the first terminal of the sixth transistor T6 is the oscillating low voltage V. SWP_L The node voltage P[n] at the control terminal of the eleventh transistor T11 is the oscillating high voltage V. SWP_H The first transistor T1 is controlled by a swing low voltage V. SWP_L When turned on, the eleventh transistor T11 is controlled by the oscillating high voltage V. SWP_H And that's the deadline.

[0100] During the compensation period Cmp, the first control signal S1[n+1] and the second control signal S2[n] of the next stage are enabled, while the first control signal S1[n], the second control signal S2[n+2] of the next stage, and the light emission control signal EM[n] are disabled. At this time, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the thirteenth transistor T13 are turned on, while the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the twelfth transistor T12, and the fourteenth transistor T14 are turned off. Furthermore, the node voltage Q[n] at the control terminal of the first transistor T1 is a swing high voltage V. SWP_H - The critical voltage V of the first transistor T1 TH1 The node voltage B[n] at the first terminal of the second transistor T3 is the oscillating low voltage V. SWP_L The node voltage A[n] at the first terminal of the sixth transistor T6 is the load variation voltage V. Load The node voltage P[n] at the control terminal of the eleventh transistor T11 is the oscillating high voltage V. SWP_H The first transistor T1 is controlled by a threshold voltage V. TH1 When turned on, the eleventh transistor T11 is controlled by the oscillating high voltage V. SWP_H And that's the deadline.

[0101] During the second reset period Rt2, the second control signal S2[n+2] of the next level is enabled, while the first control signal S1[n], the first control signal S1[n+1] of the next level, the second control signal S2[n], and the light emission control signal EM[n] are disabled. At this time, the fifth transistor T5 and the twelfth transistor T12 are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are turned off. Furthermore, the node voltage Q[n] at the control terminal of the first transistor T1 is a swing high voltage V. SWP_H - The critical voltage V of the first transistor T1 TH1 The node voltage B[n] at the first terminal of the second transistor T3 is the oscillating low voltage V. SWP_L The node voltage A[n] at the first terminal of the sixth transistor T6 is the load variation voltage V. Load The node voltage P[n] at the control terminal of the eleventh transistor T11 is a relatively low voltage V. LL In this configuration, the first transistor T1 is turned off because a circuit cannot be formed, while the eleventh transistor T11 is controlled by a relatively low voltage V. LL And it is conductive.

[0102] During the voltage oscillation period (SWP), the light emission control signal EM[n] is at the enabled level, and the first control signal S1[n], the next-stage first control signal S1[n+1], the second control signal S2[n], and the next-stage second control signal S2[n+2] are at the disabled level. At this time, the sixth transistor T6, the ninth transistor T9, and the fourteenth transistor T14 are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the thirteenth transistor T13 are turned off. Furthermore, the node voltage Q[n] at the control terminal of the first transistor T1 and the node voltage B[n] at the first terminal of the second transistor T3 are at the oscillation high voltage V. SWP_H - The critical voltage V of the first transistor T1 TH1 ┼Low voltage V L - Load variation voltage V Load The node voltage A[n] at the first terminal of the sixth transistor T6 is a low voltage V. L The node voltage P[n] at the control terminal of the eleventh transistor T11 is the oscillating high voltage V. SWP_H Among them, the first conducting transistor T1 and the ninth transistor T9 form an oscillating high voltage V. SWP_H The current path between the output node NOP and the current path, and the current flowing through the current path is only related to the low voltage V. L and load variation voltage V Load The eleventh transistor T11 is controlled by the oscillating high voltage V. SWP_H And that's the deadline.

[0103] During the voltage regulation period VS, the first control signal S1[n], the first control signal S1[n+1] of the next stage, the second control signal S2[n], the second control signal S2[n+2] of the next stage, and the light emission control signal EM[n] are at disabled levels. At this time, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are cut off. Furthermore, the node voltage Q[n] at the control terminal of the first transistor T1 and the node voltage B[n] at the first terminal of the second transistor T3 are oscillating high voltage V. SWP_H - The critical voltage V of the first transistor T1 TH1 ┼Low voltage V L - Load variation voltage V Load The node voltage A[n] at the first terminal of the sixth transistor T6 is a low voltage V. LThe node voltage P[n] at the control terminal of the eleventh transistor T11 is pushed and pulled by the clock signal XCK. Among them, the first transistor T1 is still conducting but cannot form a current path, while the eleventh transistor T11 is periodically turned on by the push and pull of the node voltage P[n].

[0104] Based on the above, the current generating region 110 fixes the voltage difference between the first terminal and the control terminal of the first transistor T1, while compensating for the critical voltage V of the first transistor T1. TH1 The variation is used to generate a fixed current so that the current generation region 110 can output the ramp signal Vsweep[n] required by the pixel driven by pulse-width modulation (PWM).

[0105] In this embodiment of the invention, the entire display panel can share the same current source I. REF During the compensation period, Cmp (i.e. the detection phase) discharges the load on the panel and stores its value in the second capacitor C2. When the light emission control signal EM[n] is enabled, it is coupled to the control terminal of the first transistor T1 through the first capacitor C1 and the second capacitor C2, so that the first transistor T1 operates in the saturation region and generates a fixed current, which can output the slope signal Vsweep[n] required by the pixel with a fixed slope.

[0106] In this embodiment of the invention, the clock signal XCK (or clock signal CK) is coupled to the node voltage P[N] through the third capacitor C3, and the eleventh transistor T11 is periodically turned on to regulate the output node NOP.

[0107] Based on the above, this embodiment of the invention proposes a circuit architecture for a ramp voltage generator 100 for applying the ramp signal Vsweep[n] required for pixels driven by pulse-width modulation (PWM) to a Mini LED / Micro LED display panel. This allows for the output of the ramp signal Vsweep[n] required for pixels driven by PWM, and also enables the detection and compensation of variations in the output load.

[0108] Figure 2A A circuit diagram of a ramp voltage generator according to another embodiment of the present invention. Please refer to... Figure 2AIn this embodiment, the ramp voltage generator 200 includes an output node NOP, a current generation region 210, and a voltage regulation region 220. The output node NOP provides a ramp signal Vsweep[n], where n is a leading number. The current generation region 210 is coupled to the output node NOP and includes a detection path DT2 to detect output load variations at the output node NOP via the detection path DT2, and adjusts the ramp signal Vsweep[n] provided by the output node NOP based on the output load variations. The voltage regulation region 220 is coupled to the output node NOP to regulate the voltage of the output node NOP. Therefore, the ramp voltage generator 200 can compensate for output variations caused by the load and maintain a stable output waveform of the ramp signal Vsweep[n].

[0109] In this embodiment, the current generating region 210 includes the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6. Among them, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 are P-type transistors, and the fifteenth transistor T15, the eighteenth transistor T18, the fourth capacitor C4, the sixth capacitor C6, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-third transistor T23 can form a detection path DT2.

[0110] The fifteenth transistor T15 has a first terminal for receiving output node NOP, a control terminal, and a second terminal. The sixteenth transistor T16 has a low voltage V. L The first terminal, the control terminal that receives the first control signal S1[n], and the second terminal that is coupled to the control terminal of the fifteenth transistor T15. The seventeenth transistor T17 has a first reference voltage V. REF1 The first terminal, the control terminal that receives the second control signal S2[n], and the second terminal. The fourth capacitor C4 is coupled between the second terminal of the sixteenth transistor T16 and the second terminal of the seventeenth transistor T17.

[0111] The fifth capacitor C5 is coupled to the first reference voltage V. REF1Between the second terminal of the seventeenth transistor T17. The eighteenth transistor T18 has a first terminal coupled to the second terminal of the fifteenth transistor T15, a control terminal receiving the first control signal S1[n+1] (i.e., the third control signal) of the next stage, and a second terminal coupled to the control terminal of the fifteenth transistor T15, wherein the first control signal S1[n] differs from the first control signal S1[n+1] of the next stage by a delay unit (e.g., half a clock cycle).

[0112] The nineteenth transistor T19 has a first terminal coupled to the second terminal of the seventeenth transistor T17, a control terminal for receiving the light emission control signal EM[n], and a second terminal. The twentieth transistor T20 has a first terminal coupled to the second terminal of the nineteenth transistor T19, a control terminal, and a second terminal. The sixth capacitor C6 is coupled between the second terminal of the seventeenth transistor T17 and the control terminal of the twentieth transistor T20.

[0113] The twenty-first transistor T21 has a second reference voltage V. REF2 The first terminal of the transistor T10 is a control terminal that receives the first control signal S1[n+1] from the next stage, and a second terminal that is coupled to the second terminal of the nineteenth transistor T19. The twenty-second transistor T22 has a first terminal that is coupled to the control terminal of the twentieth transistor T20, a control terminal that receives the first control signal S1[n], and a second terminal that receives the low voltage V. L The second terminal. The twenty-third transistor T23 has a first terminal coupled to the second terminal of the twentieth transistor T20, a control terminal that receives the first control signal S1[n+1] of the next stage, and a second terminal coupled to the control terminal of the twentieth transistor T20.

[0114] The 24th transistor T24 has a first terminal coupled to the second terminal of the 20th transistor T20, a control terminal that receives the light emission control signal EM[n], and a low voltage V. L The second terminal. The twenty-fifth transistor T25 has a first terminal coupled to the second terminal of the fifteenth transistor T15, a control terminal that receives the light emission control signal EM[n], and a low voltage V. L The second end.

[0115] In this embodiment, the voltage regulation region 220 includes a twenty-sixth transistor T26, a twenty-seventh transistor T27, a twenty-eighth transistor T28, and a seventh capacitor C7, wherein the twenty-sixth transistor T26, the twenty-seventh transistor T27, and the twenty-eighth transistor T28 are P-type transistors.

[0116] The twenty-sixth transistor T26 has the ability to receive high voltage V. HThe first terminal, the control terminal, and the second terminal coupled to the output node NOP. The seventh capacitor C7 is coupled between the clock signal CK and the control terminal of the twenty-sixth transistor T26. The twenty-seventh transistor T27 has a low voltage V... L The 28th transistor T28 has a first terminal coupled to the control terminal of the 26th transistor T26, a control terminal receiving the light emission control signal EM[n], and a second terminal coupled to the control terminal of the 26th transistor T26. H The second end.

[0117] Figure 2B A schematic diagram of the driving waveform of a ramp voltage generator according to another embodiment of the present invention. Please refer to... Figure 2A and Figure 2B In this embodiment, the ramp voltage generator 200 operates sequentially during the reset period Rt, the compensation period Cmp, the voltage oscillation period SWP, and the voltage regulation period VS.

[0118] During the reset period Rt, the first control signal S1[n] and the second control signal S2[n] are at the enable level (e.g., gate low voltage V). GL Furthermore, the first control signal S1[n+1] and the light emission control signal EM[n] of the next stage are at a disabled level (e.g., a high gate voltage V). GH At this time, transistors T16, T17, T22, and T27 are turned on, while transistors T18, T19, T21, T23, T24, T25, and T28 are turned off. Furthermore, the node voltage Q[n] at the control terminal of transistor T15 is a low voltage V. L The node voltage B[n] at the second terminal of the seventeenth transistor T17 is the first reference voltage V. REF1 The node voltage A[n] at the control terminal of the twentieth transistor T20 is the second reference voltage V. REF2 The node voltage P[n] at the control terminal of the twenty-sixth transistor T26 is a low voltage V. L Among them, the fifteenth transistor T15 is controlled by a low voltage V. L And when it is turned on, the twentieth transistor T20 is also controlled by the low voltage V. L And conduction, and the twenty-sixth transistor T26 is also controlled by a low voltage V. L And it is conductive.

[0119] During the compensation period Cmp, the first control signal S1[n+1] and the second control signal S2[n] of the next stage are at the enabled level, and the first control signal S1[n] and the light emission control signal EM[n] are at the disabled level. At this time, the seventeenth transistor T17, the eighteenth transistor T18, the twentieth transistor T20, the twenty-first transistor T21, the twenty-third transistor T23, and the twenty-seventh transistor T27 are turned on, and the sixteenth transistor T16, the nineteenth transistor T19, the twenty-second transistor T22, the twenty-fourth transistor T24, the twenty-fifth transistor T25, and the twenty-eighth transistor T28 are turned off. Furthermore, the node voltage Q[n] at the control terminal of the fifteenth transistor T15 is a high voltage V. H - The critical voltage V of the fifteenth transistor T15 TH15 The node voltage B[n] at the second terminal of the seventeenth transistor T17 is the first reference voltage V. REF1 The node voltage A[n] at the control terminal of the twentieth transistor T20 is the second reference voltage V. REF2 - The critical voltage V of the twentieth transistor T20 TH20 The node voltage P[n] at the control terminal of the twenty-sixth transistor T26 is a low voltage V. L Among them, the fifteenth transistor T15 is controlled by the threshold voltage V. TH15 When the transistor is turned on, the twentieth transistor T20 is controlled by the threshold voltage V. TH20 And it is turned on, and the twenty-sixth transistor T26 is controlled by a low voltage V. L And it is conductive.

[0120] During the voltage oscillation period of SWP, the light emission control signal EM[n] is at the enabled level, and the first control signal S1[n], the next-stage first control signal S1[n+1], and the second control signal S2[n] are at the disabled level. At this time, the nineteenth transistor T19, the twenty-fourth transistor T24, the twenty-fifth transistor T25, and the twenty-eighth transistor T28 are turned on, and the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, and the twenty-seventh transistor T27 are turned off. Furthermore, the node voltage Q[n] at the control terminal of the fifteenth transistor T15 is a high voltage V. H - The critical voltage V of the fifteenth transistor T15 TH15 -ΔV, the node voltage B[n] at the second terminal of the seventeenth transistor T17 is the first reference voltage V. REF1 -ΔV, the node voltage A[n] at the control terminal of the twentieth transistor T20 is the second reference voltage V. REF2 - The critical voltage V of the twentieth transistor T20 TH20-ΔV, the node voltage P[n] at the control terminal of the 26th transistor T26 is a high voltage V. H Among them, the fifteenth transistor T15 is controlled by the threshold voltage V. TH15 When the transistor is turned on, the twentieth transistor T20 is controlled by the threshold voltage V. TH20 And it is turned on, and the twenty-sixth transistor T26 is controlled by a high voltage V. H And that's the deadline.

[0121] During the voltage regulation period VS, the first control signal S1[n], the next stage's first control signal S1[n+1], the second control signal S2[n], and the light emission control signal EM[n] are at disabled levels. At this time, transistors T16, T17, T18, T19, T21, T22, T23, T24, T25, T27, and T28 are cut off. Furthermore, the node voltage Q[n] at the control terminal of transistor T15 is high. H - The critical voltage V of the fifteenth transistor T15 TH15 -ΔV, the node voltage B[n] at the second terminal of the seventeenth transistor T17 is the first reference voltage V. REF1 -ΔV, the node voltage A[n] at the control terminal of the twentieth transistor T20 is the second reference voltage V. REF2 - The critical voltage V of the twentieth transistor T20 TH20 -ΔV, the node voltage P[n] at the control terminal of the 26th transistor T26 is a high voltage V. H Among them, the fifteenth transistor T15 is controlled by the threshold voltage V. TH15 While conducting, it cannot form a current path. The twentieth transistor T20 remains conducting but cannot form a loop and is therefore cut off. The twenty-sixth transistor T26 is controlled by the clock signal XCK and is pushed and pulled.

[0122] Based on the above, the current generation region 210 uses a diode-connected architecture to control the threshold voltage V of the fifteenth transistor T15 and the twentieth transistor T20. TH15 and V TH20 Compensation is performed to improve accuracy. The constant current of the twentieth transistor T20 discharges the node voltage B[n] to generate a gradually decreasing waveform. Then, the source follower architecture of the fifteenth transistor T15 is used to stabilize the node voltage Q[n] and the output node NOP at a difference of a critical voltage V. TH15The voltage achieves the technical effect of compensating for the load. Furthermore, CK and XCK are coupled through the seventh capacitor C7 to perform 50% periodic voltage regulation on the output node NOP.

[0123] Figure 3 A system schematic diagram of a display panel according to an embodiment of the present invention. Please refer to... Figure 1A , Figure 1B and Figure 3 In this embodiment, the display panel 300 includes a plurality of pixels PX, a plurality of gate lines GL, a plurality of source lines DL, and ramp voltage generators 100 / 200. The pixels PX are arranged in an array. Each gate line GL receives one of a plurality of gate signals (such as G1-G4), extends along a first direction d1, and is coupled to a portion of the pixels PX. Each source line DL receives one of a plurality of source signals (such as S1-S4), extends along a second direction d2 perpendicular to the first direction d1, and is coupled to a portion of the pixels PX. The ramp voltage generators 100 / 200 are coupled to all pixels PX to simultaneously provide ramp signals Vsweep to all pixels PX. The circuit structure and operation of the ramp voltage generators 100 / 200 can be found in [reference needed]. Figure 1A and Figure 2A As shown, it will not be repeated here.

[0124] In this embodiment, the ramp voltage generator 100 / 200 can be configured on the display panel 300. However, in other embodiments, the ramp voltage generator 100 / 200 can be configured on a thin film substrate connected to the display panel 300. For example, the ramp voltage generator 100 / 200 can be integrated into the source driver. However, this embodiment of the present invention is not limited thereto.

[0125] In summary, the ramp voltage generator and display panel of this invention detect output load variations at the output node via a detection path in the current generation area, and adjust the ramp signal provided by the output node based on these variations. Therefore, the ramp voltage generator can detect and compensate for output load variations, achieving precise grayscale control for pixels.

[0126] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A ramp voltage generator, comprising: An output node is used to provide a ramp signal; A current generation region coupled to the output node includes a detection path to detect an output load variation at the output node and adjust the ramp signal provided by the output node based on the output load variation. as well as A voltage regulation region is coupled to the output node to regulate the voltage of the output node. The current generation region includes: A first transistor has a first terminal for receiving an oscillating high voltage, a control terminal, and a second terminal; A second transistor has a first terminal for receiving an oscillating low voltage, a control terminal for receiving a first control signal, and a second terminal coupled to the control terminal of the first transistor. A third transistor has a first terminal, a control terminal that receives a second control signal, and a second terminal that receives the oscillation low voltage; A first capacitor is coupled between the second terminal of the second transistor and the first terminal of the third transistor; A fourth transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving a third control signal, and a second terminal coupled to the control terminal of the first transistor. A fifth transistor has a first terminal for receiving the oscillating low voltage, a control terminal for receiving a fourth control signal, and a second terminal; A sixth transistor has a first terminal, a control terminal that receives a light emission control signal, and a second terminal that receives a low voltage; A second capacitor is coupled between the first terminal of the third transistor and the first terminal of the sixth transistor; A seventh transistor has a first terminal coupled to the first terminal of the sixth transistor, a control terminal for receiving the first control signal, and a second terminal for receiving the swing low voltage; An eighth transistor has a first terminal coupled to the output node, a control terminal for receiving the third control signal, and a second terminal coupled to the first terminal of the sixth transistor; A ninth transistor has a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving a light emission control signal, and a second terminal coupled to the output node; A tenth transistor, having a first terminal coupled to the output node, a control terminal receiving the third control signal, and a second terminal; and A current source is coupled to the second terminal of the tenth transistor.

2. The ramp voltage generator as claimed in claim 1, wherein the voltage regulation region includes: An eleventh transistor has a first terminal coupled to the output node, a control terminal, and a second terminal receiving the oscillation low voltage; A third capacitor is coupled between the control terminal of the eleventh transistor and a clock signal; A twelfth transistor has a first terminal for receiving a relatively low voltage, a control terminal for receiving the fourth control signal, and a second terminal coupled to the control terminal of the eleventh transistor. A thirteenth transistor has a first terminal for receiving the oscillating high voltage, a control terminal for receiving the second control signal, and a second terminal coupled to the control terminal of the eleventh transistor; and A fourteenth transistor has a first terminal for receiving the oscillating high voltage, a control terminal for receiving the light emission control signal, and a second terminal coupled to the control terminal of the eleventh transistor.

3. The ramp voltage generator as claimed in claim 2, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are each a P-type transistor.

4. The ramp voltage generator as claimed in claim 1, wherein the third control signal is the first control signal of the next stage, and the fourth control signal is the second control signal of the next stage.

5. A ramp voltage generator, comprising: An output node is used to provide a ramp signal; A current generation region coupled to the output node includes a detection path to detect an output load variation at the output node and adjust the ramp signal provided by the output node based on the output load variation. as well as A voltage regulation region is coupled to the output node to regulate the voltage of the output node. The current generation region includes: A fifteenth transistor has a first terminal for receiving the output node, a control terminal, and a second terminal; A sixteenth transistor has a first terminal for receiving a low voltage, a control terminal for receiving a first control signal, and a second terminal coupled to the control terminal of the fifteenth transistor. A seventeenth transistor has a first terminal for receiving a first reference voltage, a control terminal for receiving a second control signal, and a second terminal; A fourth capacitor is coupled between the second terminal of the sixteenth transistor and the second terminal of the seventeenth transistor; A fifth capacitor is coupled between the first reference voltage and the second terminal of the seventeenth transistor; An eighteenth transistor has a first terminal coupled to the second terminal of the fifteenth transistor, a control terminal for receiving a third control signal, and a second terminal coupled to the control terminal of the fifteenth transistor. A nineteenth transistor has a first terminal coupled to the second terminal of the seventeenth transistor, a control terminal for receiving a light emission control signal, and a second terminal; A twentieth transistor has a first terminal coupled to the second terminal of the nineteenth transistor, a control terminal, and a second terminal; A sixth capacitor is coupled between the second terminal of the seventeenth transistor and the control terminal of the twentieth transistor; A twenty-first transistor has a first terminal for a second reference voltage, a control terminal for receiving the third control signal, and a second terminal coupled to the second terminal of the nineteenth transistor; A twenty-second transistor has a first terminal coupled to the control terminal of the twentyth transistor, a control terminal for receiving the first control signal, and a second terminal for receiving the low voltage; A twenty-third transistor has a first terminal coupled to the second terminal of the twentyth transistor, a control terminal for receiving the third control signal, and a second terminal coupled to the control terminal of the twentyth transistor; A twenty-fourth transistor, having a first terminal coupled to the second terminal of the twentyth transistor, a control terminal for receiving the light emission control signal, and a second terminal for receiving the low voltage; and A twenty-fifth transistor has a first terminal coupled to the second terminal of the fifteenth transistor, a control terminal for receiving the light emission control signal, and a second terminal for receiving the low voltage.

6. The ramp voltage generator as claimed in claim 5, wherein the voltage regulation region includes: A twenty-sixth transistor has a first terminal for receiving a high voltage, a control terminal, and a second terminal coupled to the output node; A seventh capacitor is coupled between a clock signal and the control terminal of the twenty-sixth transistor; A twenty-seventh transistor has a first terminal for receiving the low voltage, a control terminal for receiving the second control signal, and a second terminal coupled to the control terminal of the twenty-sixth transistor; and A twenty-eighth transistor has a first terminal coupled to the control terminal of the twenty-sixth transistor, a control terminal for receiving the light emission control signal, and a second terminal for receiving the high voltage.

7. The ramp voltage generator as claimed in claim 6, wherein the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, the twenty-fifth transistor, the twenty-sixth transistor, the twenty-seventh transistor, and the twenty-eighth transistor are each a P-type transistor.

8. The ramp voltage generator as claimed in claim 5, wherein the third control signal is the first control signal of the next stage.

9. A display panel, comprising: Multiple pixels arranged in an array; Multiple gate lines, each extending along a first direction, and each coupled to a portion of the pixels; Multiple source lines, each extending along a second direction perpendicular to the first direction, and each coupled to a portion of the pixels; as well as A ramp voltage generator as described in claim 1 is coupled to the pixels to provide a ramp signal to the pixels.

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