Bidirectional laminated chip fan-out package structure and packaging method

Abstract

The application relates to the technical field of chip packaging, in particular to a bidirectional laminated chip fan-out packaging structure and a packaging method. The packaging structure comprises a second re-wiring layer, characterized in that: the lower end of the second re-wiring layer is connected with a first bump, the upper end of the second re-wiring layer is provided with a bidirectional laminated group, one side of the bidirectional laminated group is provided with a first conductive structure, the upper end of the first conductive structure is connected with a first re-wiring layer, the upper end of the first re-wiring layer is connected with a second bump, the upper end of the second bump is connected with a control chip, the bidirectional laminated group comprises a plurality of stacked functional chip groups and micro bumps, the adjacent functional chip groups are electrically connected through the micro bumps, and the functional chip group comprises a forward chip and a reverse chip which are of the same structure. Compared with the prior art, the packaging structure adopts the first re-wiring layer and the first conductive structure to realize internal interconnection, adopts the second re-wiring layer to replace a substrate to realize external connection, and the cost of packaging is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically to a bidirectional stacked chip fan-out packaging structure and packaging method. Background Technology

[0002] Currently, traditional chip packaging involves directly mounting the chip onto the surface of a substrate (PCB, Printed Circuit Board), and then using wire bonding to achieve electrical connections between the chip pads and the substrate. The substrate, as one of the core materials for chip packaging, accounts for 30%-50% of the total packaging material cost. To cope with the trend towards diversification, miniaturization, and functionalization of electronic devices, the design of the substrate is becoming increasingly complex, and the number of layers is also increasing. This not only leads to an increase in substrate thickness, affecting the overall package thickness, but also further increases the price of the substrate. Furthermore, traditional wire bonding processes can introduce product delays, resulting in low efficiency. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, this invention provides a bidirectional stacked chip fan-out packaging structure and packaging method, solving the problems of high substrate cost and large package thickness in existing packaging technologies.

[0004] To achieve the above objectives, a bidirectional stacked chip fan-out package structure is designed, including a second redistribution layer. The second redistribution layer is characterized by: a first bump connected to its lower end; a bidirectional stacked assembly on its upper end; a first conductive structure on one side of the bidirectional stacked assembly; the first conductive structure connected to the first redistribution layer at its upper end; a second bump connected to the upper end of the first redistribution layer; and a control chip connected to the upper end of the second bump. The bidirectional stacked assembly includes several stacked functional chip groups and microbumps. Adjacent functional chip groups are electrically connected through the microbumps. Each functional chip group includes a forward chip and a reverse chip with identical structures. A step is provided on one side of both the forward and reverse chips, and the step of the forward chip abuts against the step of the reverse chip. A through-hole is provided on the step, and a second conductive structure abutting against the microbump is provided within the through-hole.

[0005] The lower end of the first conductive structure is connected to the second rewiring layer.

[0006] The bidirectional stacked assembly and the outer side of the first conductive structure are provided with a first plastic encapsulation layer.

[0007] The control chip has a second molding layer on its outer side.

[0008] An adhesive layer is provided between adjacent functional chipsets.

[0009] The upper surface of the forward chip step abuts against the lower surface of the reverse chip step.

[0010] The thickness of the step is half the thickness of the forward chip and the reverse chip.

[0011] The present invention also provides a packaging method for a bidirectional stacked chip fan-out package structure, comprising the following steps:

[0012] S1 provides a carrier and forms a separation layer on the surface of the carrier;

[0013] S2, a second redistribution layer is formed on the separation layer;

[0014] S3, a bidirectional stack-up group is arranged above the second redistribution layer;

[0015] S4, molding, forming a first molding layer on the outside of the bidirectional laminate assembly;

[0016] S5, using laser drilling technology to form a deep hole in the first molding layer, with the bottom of the deep hole falling on the second redistribution layer;

[0017] S6 forms the first conductive structure within the deep hole.

[0018] S7, a first redistribution layer is formed on the surface of the first molding layer, and the first redistribution layer is electrically connected to the second redistribution layer through a first conductive structure;

[0019] S8, using laser grooving to create several grooves on the surface of the first redistribution layer;

[0020] S9, a second bump is placed in the groove, and a control chip is arranged on the upper end of the second bump. The first redistribution layer and the control chip are electrically connected through the second bump.

[0021] S10, Plastic Encapsulation: A second plastic encapsulation layer is formed on the outside of the control chip;

[0022] S11, apply a layer of tape to the surface of the second molding layer and invert the overall structure;

[0023] S12, remove the carrier and separation layer, and connect the first bump to the surface of the second redistribution layer;

[0024] S13, Remove tape.

[0025] The specific method for step S3 is as follows:

[0026] S31 provides thinned wafers;

[0027] S32, using ion etching or laser grooving, creates a groove along the pad direction on the back side of the wafer, forming a step.

[0028] S33, through-holes running vertically through the step are set by TSV drilling or deep reactive ion etching, and a second conductive structure is inserted.

[0029] S34 cuts the wafer into individual functional chips to form forward chips and reverse chips;

[0030] S35 lays out the forward and reverse chips with steps horizontally, one forward and one reverse, so that the steps of the forward and reverse chips are aligned in the vertical direction to form a functional chipset.

[0031] S36, which vertically stacks several functional chipsets using an adhesive layer;

[0032] S37, a second conductive structure is formed in the through hole of the step, and electrical connections are formed between several functional chipsets and between the functional chipsets and the second redistribution layer by arranging micro bumps.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] 1. The packaging structure of the present invention uses a first redistribution layer and a first conductive structure to achieve internal interconnection, and uses a second redistribution layer instead of a substrate to achieve external connection, thereby reducing the cost of packaging.

[0035] 2. Vertical connection of functional chips with steps occupies less space and reduces package size compared to staggered stacking; secondly, TSV process shortens the signal propagation path, greatly improves the product's operating speed, and enhances data processing capabilities.

[0036] 3. This invention adopts a three-dimensional stacked packaging structure to integrate chips with different functions, which greatly improves the integration of the packaging. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of the present invention.

[0038] Figure 2 for Figure 1 Top view along the AA direction.

[0039] Figure 3 This is a cross-sectional structural diagram of the carrier of the present invention.

[0040] Figure 4 This is a schematic cross-sectional view of the separation layer formed on the carrier surface according to the present invention.

[0041] Figure 5 This is a schematic cross-sectional view of the structure after the second redistribution layer is formed according to the present invention.

[0042] Figure 6This is a schematic cross-sectional view of the functional chipset after it has been mounted according to the present invention.

[0043] Figure 7 for Figure 6 A schematic diagram of the structure of a mid-function chipset.

[0044] Figure 8 This is a schematic cross-sectional view of the structure after the first encapsulated body is formed according to the present invention.

[0045] Figure 9 This is a schematic diagram of the cross-sectional structure after laser drilling according to the present invention.

[0046] Figure 10 This is a schematic cross-sectional view of the structure after the first conductive structure of the present invention is formed.

[0047] Figure 11 This is a schematic cross-sectional view of the structure after the first redistribution layer is formed according to the present invention.

[0048] Figure 12 This is a schematic diagram of the cross-sectional structure after laser grooving according to the present invention.

[0049] Figure 13 This is a schematic cross-sectional view of the structure after the control chip of the present invention is mounted.

[0050] Figure 14 This is a schematic cross-sectional view of the structure after the second encapsulated body is formed according to the present invention.

[0051] Figure 15 This is a schematic diagram of the cross-sectional structure of the present invention after being inverted and covered with adhesive tape.

[0052] Figure 16 This is a schematic cross-sectional view of the present invention after the carrier is removed.

[0053] Figure 17 This is a schematic diagram of the cross-sectional structure after the first protrusion is formed according to the present invention.

[0054] Figure 18 This is a schematic diagram of the wafer after laser grooving according to the present invention.

[0055] Figure 19 This is a schematic diagram of a wafer used to form the through-hole conductive structure according to the present invention.

[0056] Figure 20 This is a schematic diagram of the functional chip structure with steps according to the present invention.

[0057] Figure 21 This is a schematic diagram of the structure of the functional chip of the present invention.

[0058] See Figures 1 to 21In this structure, 1 is the carrier, 2 is the separation layer, 3 is the second redistribution layer, 301 is the second dielectric layer, 302 is the second metal wiring layer, 4 is the functional chipset, 401 is the forward chip, 402 is the reverse chip, 403 is the second conductive structure, 404 is the microbump, 405 is the step, 5 is the adhesive layer, 6 is the first molding layer, 7 is the deep via, 8 is the first conductive structure, 9 is the first redistribution layer, 901 is the first dielectric layer, 902 is the first metal wiring layer, 905 is the first groove, 10 is the control chip, 11 is the second molding layer, 12 is the tape, 13 is the first bump, 14 is the second bump, 15 is the wafer, 16 is the functional chip, 17 is the pad, and 18 is the second groove. Detailed Implementation

[0059] The present invention will now be further described with reference to the accompanying drawings.

[0060] like Figures 1 to 2 As shown, the lower end of the second redistribution layer 3 is connected to the first bump 13, and the upper end of the second redistribution layer 3 is provided with a bidirectional stacked assembly. A first conductive structure 8 is provided on one side of the bidirectional stacked assembly. The upper end of the first conductive structure 8 is connected to the first redistribution layer 9, and the upper end of the first redistribution layer 9 is connected to the second bump 14. The upper end of the second bump 14 is connected to the control chip 10. The bidirectional stacked assembly includes several stacked functional chip groups 4 and microbumps 404. Adjacent functional chip groups 4 are electrically connected through microbumps 404. The functional chip group 4 includes a forward chip 401 and a reverse chip 402 with the same structure. A step 405 is provided on one side of both the forward chip 401 and the reverse chip 402. The step of the forward chip 401 abuts against the step of the reverse chip 402. A through hole is provided on the step 405. A second conductive structure 403 abuts against the microbump 404 is provided in the through hole.

[0061] The lower end of the first conductive structure 8 is connected to the second rewiring layer 3.

[0062] The bidirectional stacked assembly and the first conductive structure 8 are provided with a first plastic encapsulation layer 6 on the outside.

[0063] The control chip 10 has a second molding layer 11 on its outer side.

[0064] An adhesive layer 5 is provided between the functional chipsets.

[0065] The upper surface of the forward chip 401 step abuts against the lower surface of the reverse chip 402 step.

[0066] The thickness of step 405 is half the thickness of the forward chip 401 and the reverse chip 402.

[0067] like Figures 3 to 17 As shown, a packaging method for a bidirectional stacked chip fan-out package structure includes the following steps:

[0068] S1, a carrier 1 is provided, and a separation layer 2 is formed on the surface of the carrier 1;

[0069] S2, a second redistribution layer 3 is formed on the separation layer 2;

[0070] S3, a bidirectional stack-up group is arranged above the second redistribution layer 3;

[0071] S4, molding, forming a first molding layer 6 on the outside of the bidirectional laminate assembly;

[0072] S5, using laser drilling technology to form a deep hole 7 in the first molding layer 6, the bottom of the deep hole 7 falls on the second redistribution layer 3;

[0073] S6, forming a first conductive structure 8 within the deep hole 7.

[0074] S7, a first redistribution layer 9 is formed on the surface of the first molding layer 6, and the first redistribution layer 9 is electrically connected to the second redistribution layer 3 through the first conductive structure 8;

[0075] S8, using laser grooving, several grooves 905 are set on the surface of the first redistribution layer 9;

[0076] S9, a second bump 14 is placed in the groove 905, and a control chip 10 is arranged on the upper end of the second bump 14. The first redistribution layer 9 and the control chip 10 are electrically connected through the second bump 14.

[0077] S10, Plastic encapsulation, forming a second plastic encapsulation layer 11 on the outside of the control chip 10;

[0078] S11, apply a layer of tape 12 to the surface of the second molding layer 11, and invert the overall structure;

[0079] S12, remove carrier 1 and separation layer 2, and connect first bump 13 to the surface of second redistribution layer 3;

[0080] S13, remove tape 12, forming as shown in the figure. Figure 1 The chip packaging structure shown.

[0081] like Figures 18 to 21 As shown, the specific method for step S3 is as follows:

[0082] S31 provides a thinned wafer 15;

[0083] S32, using ion etching or laser grooving, a groove 18 is formed on the back side of wafer 15 along the direction of pad 17, creating a step 405.

[0084] S33, through-holes running vertically through the step 405 are set by TSV drilling or deep reactive ion etching, and a second conductive structure 403 is inserted.

[0085] S34, the wafer 15 is cut into individual functional chips 16 to form a forward chip 401 and a reverse chip 402;

[0086] S35, the forward chip 401 and the reverse chip 402 with the step 405 are laid out horizontally, one forward and one reverse, so that the steps 405 of the forward chip 401 and the reverse chip 402 are aligned in the vertical direction to form a functional chip group 4.

[0087] S36, Several functional chipsets 4 are vertically stacked through adhesive layer 5;

[0088] S37, a second conductive structure 403 is formed in the through hole of the step 405, and electrical connections are formed between several functional chip groups 4 and between the functional chip groups 4 and the second redistribution layer 3 by arranging micro bumps 404.

[0089] In this invention, the first redistribution layer 9 includes a first dielectric layer 901 and a first metal wiring layer 902, and the second redistribution layer 3 includes a second dielectric layer 301 and a second metal wiring layer 302. The dielectric layer is made of one or more of polyimide, epoxy resin, silicon oxide, and silicone, and the metal wiring layer is made of one or more of copper, nickel, gold, silver, and titanium.

[0090] The first redistribution layer 9 has a first surface 903 and a second surface 904 opposite to each other. The second redistribution layer has a first surface 303 and a second surface 304 opposite to each other. The first surface 901 of the first redistribution layer is electrically connected to the second surface 304 through a first conductive structure 8. The control chip 10 is bonded to the second surface 904 of the first redistribution layer and electrically connected to the second surface 304 of the second redistribution layer using the first conductive structure 8. The first bump 13 bonded to the first surface 303 of the second redistribution layer enables electrical connection to the outside world.

[0091] The first conductive structure 8 is formed within a deep hole 7 by laser drilling in the first molding layer 6, followed by sputtering, electroplating, or chemical plating. The first conductive structure 8 can also be a metal pillar, which can be formed on the surface of the second redistribution layer 3 using sputtering or electroplating before encapsulation.

[0092] The materials of the first conductive structure 8 and the second conductive structure 403 can be one or more of copper, nickel, gold, silver and titanium.

[0093] The functional chip 16 can be a memory chip, and the vertical stacking connection between chips and the electrical connection between the functional chip 16 and the second surface 304 of the second redistribution layer are realized by using microbumps 404.

[0094] The first molding layer 6 and the second molding layer 11 are made of resin.

[0095] The first bump 13, the second bump 14, and the micro bump 404 are made of solder balls.

[0096] The carrier 1 can be made of glass, metal or ceramic materials and can be reused.

[0097] The material for the separation layer 2 can be adhesive tape.

[0098] The cross-section of groove 218 is rectangular, which facilitates subsequent stacking.

Claims

1. A bidirectional stacked chip fan-out package structure, comprising a second redistribution layer, characterized in that: The lower end of the second redistribution layer (3) is connected to the first bump (13). The upper end of the second redistribution layer (3) is provided with a bidirectional stacked group. A first conductive structure (8) is provided on one side of the bidirectional stacked group. The upper end of the first conductive structure (8) is connected to the first redistribution layer (9). The upper end of the first redistribution layer (9) is connected to the second bump (14). The upper end of the second bump (14) is connected to the control chip (10). The bidirectional stacked group includes several stacked functional chip groups (4) and micro bumps (404). Adjacent functional chip groups (4) are electrically connected through micro bumps (404). The functional chip group (4) includes a forward chip (401) and a reverse chip (402) with the same structure. A step (405) is provided on one side of both the forward chip (401) and the reverse chip (402). The step of the forward chip (401) and the step of the reverse chip (402) abut against each other. A through hole is provided on the step (405). A second conductive structure (403) abuts against the micro bump (404) is provided in the through hole.

2. The bidirectional stacked chip fan-out package structure according to claim 1, characterized in that: The lower end of the first conductive structure (8) is connected to the second rewiring layer (3).

3. The bidirectional stacked chip fan-out packaging structure according to claim 1, characterized in that: The bidirectional stacked assembly and the first conductive structure (8) are provided with a first plastic sealing layer (6) on the outside.

4. The bidirectional stacked chip fan-out package structure according to claim 1, characterized in that: The control chip (10) has a second molding layer (11) on its outer side.

5. The bidirectional stacked chip fan-out package structure according to claim 1, characterized in that: An adhesive layer (5) is provided between adjacent functional chipsets.

6. The bidirectional stacked chip fan-out package structure according to claim 1, characterized in that: The upper surface of the forward chip (401) step abuts against the lower surface of the reverse chip (402) step.

7. The bidirectional stacked chip fan-out package structure according to claim 1, characterized in that: The thickness of the step (405) is half the thickness of the forward chip (401) and the reverse chip (402).

8. A packaging method for a bidirectional stacked chip fan-out package structure according to any one of claims 1-7, characterized in that: Includes the following steps: S1, a carrier (1) is provided, and a separation layer (2) is formed on the surface of the carrier (1); S2, a second redistribution layer (3) is formed on the separation layer (2); S3, a bidirectional stack-up group is arranged above the second redistribution layer (3); S4, molding, forming a first molding layer (6) on the outside of the bidirectional laminate assembly. S5, using laser drilling technology to form a deep hole (7) in the first plastic sealing layer (6), the bottom of the deep hole (7) falls on the second redistribution layer (3); S6, forming a first conductive structure (8) within the deep hole (7). S7, a first redistribution layer (9) is formed on the surface of the first encapsulation layer (6), and the first redistribution layer (9) is electrically connected to the second redistribution layer (3) through the first conductive structure (8); S8, using laser grooving to create several grooves (905) on the surface of the first redistribution layer (9). S9, a second protrusion (14) is placed in the groove (905), and a control chip (10) is arranged on the upper end of the second protrusion (14). The first redistribution layer (9) and the control chip (10) are electrically connected through the second protrusion (14). S10, Plastic encapsulation, forming a second plastic encapsulation layer (11) on the outside of the control chip (10); S11, apply a layer of tape (12) to the surface of the second molding layer (11) and invert the overall structure; S12, remove the carrier (1) and the separation layer (2), and connect the first bump (13) to the surface of the second rewiring layer (3); S13, Remove tape (12).

9. The packaging method for a bidirectional stacked chip fan-out package structure according to claim 8, characterized in that: The specific method for step S3 is as follows: S31 provides a thinned wafer (15). S32, using ion etching or laser grooving, a groove (18) is formed on the back side of the wafer (15) along the direction of the pad (17) to form a step (405). S33, through holes are formed on the step (405) by TSV drilling or deep reactive ion etching, and a second conductive structure (403) is placed therein. S34, the wafer (15) is cut into individual functional chips (16) to form a forward chip (401) and a reverse chip (402). S35, the forward chip (401) and the reverse chip (402) with steps (405) are laid out horizontally, one forward and one reverse, so that the steps (405) of the forward chip (401) and the reverse chip (402) are aligned in the vertical direction to form a functional chip group (4). S36, Several functional chipsets (4) are vertically stacked through an adhesive layer (5); S37, a second conductive structure (403) is formed in the through hole of the step (405), and electrical connections are formed between several functional chipsets (4) and between functional chipsets (4) and the second redistribution layer (3) by arranging microbumps (404).

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