Input impedance boosting device robust to parasitic components

Abstract

The present application relates to input impedance boosting device, input impedance boosting device includes: analog-digital conversion circuit; input capacitor, with the input end of analog-digital conversion circuit and ground wire are connected, and the first shielding metal is formed in lower part;Feedback capacitor, with the positive feedback loop of analog-digital conversion circuit is connected, and the second shielding metal is formed in lower part;And impedance boosting unit, with the both ends of feedback capacitor are connected, and the first parasitic component formed between input capacitor and first shielding metal and the second parasitic component formed between feedback capacitor and second shielding metal are used to boost input impedance.

Description

Technical Field

[0001] This invention relates to an input impedance enhancement device, and more specifically, to a technical concept of increasing the input impedance of a circuit by minimizing the influence of parasitic capacitance components. Background Technology

[0002] In voltage measurement circuits, input impedance is an important performance indicator for preventing signal attenuation. Therefore, in order to improve this input impedance, an input impedance boosting circuit based on a positive feedback loop has been disclosed.

[0003] The aforementioned input impedance boosting circuit forms a positive feedback loop between the output and input terminals of the voltage measurement circuit. Where the gain of the voltage measurement circuit is "A" and the input impedance of the voltage measurement circuit is "Z",... SEN “From the input voltage V IN The parasitics generated by the applied node (i.e., the node connected to the input of the voltage measurement circuit) are divided into "Z". P ", used to control the feedback current I FB The impedance on the positive feedback loop is "Z FB Then the input impedance is determined by the input voltage V. IN With input current I IN Defined by the ratio, in the absence of a positive feedback loop, the input impedance can be "Z". P +Z SEN ".

[0004] Among them, the positive feedback loop compensates for the input current I. IN The role of I FB =I P +I SEN (where I) P For flow to Z P (that is, C) P The current I SEN For flow to Z SEN (that is, C) SEN Under the condition of () current), the feedback current I applied to the positive feedback loop FB Generates an infinitely large input impedance.

[0005] The input impedance increased (boosted) by the positive feedback loop can be represented by the following equation 1.

[0006] [Formula 1]

[0007]

[0008] As shown in Equation 1, the positive feedback loop generates (1-A)C FB The negative capacitance region (where C)FB For Z FB ), in (1-A)C FB =C P +C SEN Under these conditions, the input impedance becomes infinitely large. Furthermore, since A is defined as a system (or device) parameter, it can be determined by selecting an appropriate value for C. FB To increase the input impedance.

[0009] That is, existing input impedance boosting circuits are sensitive to parasitic components. Furthermore, C SEN A, C FB As a parameter that can be precisely controlled, C P As a difficult-to-predict parameter, C cannot be eliminated. P In this case, the input impedance depends on the parasitic component C. P .

[0010] Therefore, in order to minimize C P The resulting impact, existing technology uses trimming C FB The method.

[0011] If this fine-tuning method is used, the increased input impedance depends on the trimming resolution, which, in the current technology, is C. FB Using 9-bit C DAC This achieves an input capacitance of 60fF, which translates to a high input impedance of 200GΩ@1Hz.

[0012] However, in existing techniques for improving input impedance using fine-tuning methods, due to the 9-bit C... DAC The additional circuitry logic used for fine-tuning generates unnecessary area and power consumption, thus increasing circuit complexity.

[0013] [Existing Technical Documents]

[0014] [Patent Documents]

[0015] Korean Patent Publication No. 10-2015-0103843, "Storage Capacitor"

[0016] [Non-patent literature]

[0017] J.Lee, G.Lee, H.Kim and S.Cho, "An Ultra-High Input Impedance AnalogFront End Using Self-Calibrated Positive Feedback," in IEEE Journal of Solid-State Circuits, vol.53, no.8, pp.2252-2262, Aug.2018

[0018] Y. Park, J.-H. Cha, S.-H. Han, J.-H. Park and S.-J. Kim, “A 3.8-μW / Ch, 15-GΩ Total Input Impedance Chopper Stabilized Amplifier with Dual PositiveFeedback Loops and Auto-calibration Scheme,” 2021 Symposium on VLSI Circuits Summary of the Invention

[0019] The purpose of this invention is to provide an input impedance enhancement device that can reduce the influence of parasitic capacitance components without requiring additional calibration or fine-tuning processes.

[0020] Furthermore, another object of the present invention is to provide an input impedance enhancement device that not only minimizes power consumption and cost increases due to circuit area, but also enhances input impedance.

[0021] Furthermore, another object of the present invention is to provide an input impedance boosting device that can achieve further improved impedance boosting performance compared to existing technologies that utilize fine-tuning processes.

[0022] An input impedance boosting device according to an embodiment of the present invention may include: an analog-to-digital conversion circuit; an input capacitor connected to the input terminal and ground wire of the analog-to-digital conversion circuit, with a first shielding metal formed at its lower part; a feedback capacitor connected to the positive feedback loop of the analog-to-digital conversion circuit, with a second shielding metal formed at its lower part; and an impedance boosting part connected to both ends of the feedback capacitor, which boosts the input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal.

[0023] According to one embodiment of the present invention, the impedance boosting section can increase the input impedance by copying the first parasitic component and the second parasitic component and adding them to the positive feedback loop.

[0024] According to one embodiment of the present invention, the impedance boosting section may include: a first metal connected to a first terminal of the feedback capacitor; and a third shielding metal formed on the lower part of the first metal and connected to a second terminal of the feedback capacitor.

[0025] According to one embodiment of the present invention, the first shielding metal and the second shielding metal can be connected to the grounding wire respectively.

[0026] According to one embodiment of the present invention, the input impedance boosting device may further include a chopper switch connected to the input terminal of the analog-to-digital conversion circuit.

[0027] According to one embodiment of the present invention, the impedance boosting section may further include a virtual switch connected to both ends of the feedback capacitor.

[0028] According to one embodiment of the present invention, the impedance boosting unit can improve the input impedance by replicating the third parasitic component formed based on the chopper switch using a virtual switch and adding it to the positive feedback loop.

[0029] According to one embodiment of the present invention, the virtual switch and the chopper switch can be formed to the same size.

[0030] According to one embodiment of the present invention, the feedback capacitor and the input capacitor can be metal-oxide-metal (MOM) capacitors.

[0031] According to one embodiment of the present invention, the analog-to-digital conversion circuit can be a continuous-time Delta-Sigma analog-to-digital conversion circuit, which includes: a linear integrator equipped with a linear transconductance unit (linear Gm cell); a body-driven VCO; and a quantizer equipped with a frequency-to-digital converter (FDC).

[0032] According to one embodiment of the present invention, the influence of parasitic capacitance components can be reduced without additional calibration or fine-tuning processes.

[0033] According to one embodiment of the present invention, not only is power consumption and cost increases due to circuit area reduced to the minimum, but input impedance can also be improved.

[0034] According to one embodiment of the present invention, compared with the prior art that utilizes a fine-tuning process, further improved impedance boosting performance can be achieved. Attached Figure Description

[0035] Figure 1 This is a diagram illustrating an input impedance boosting device according to an embodiment of the present invention.

[0036] Figures 2a to 2c A diagram is provided for further detailing an embodiment of the input impedance boosting device of the present invention.

[0037] Figure 3 A diagram is provided for further detailing a linear integrator according to an embodiment of the present invention.

[0038] Figure 4 A diagram is provided for further detailing a body-driven oscillator according to an embodiment of the present invention.

[0039] Figure 5a and Figure 5b The figure shows the performance simulation results of the input impedance boosting device according to an embodiment of the present invention, which is used to further illustrate the invention.

[0040] Explanation of reference numerals in the attached figures

[0041] 100: Input impedance boosting device; ADC: Analog-to-digital converter

[0042] C IN Input capacitor C' IN Feedback capacitor

[0043] 110: First shielding metal; 110-1: First parasitic component

[0044] 120: Second shielding metal; 120-1: Second parasitic component

[0045] 130: Third shielding metal; 140: First shielding metal Detailed Implementation

[0046] Hereinafter, several embodiments of this specification will be described with reference to the accompanying drawings.

[0047] The embodiments and the terms used therein are not intended to limit the technology described in this specification to specific implementation methods, but should be understood to include various modifications, equivalent technical solutions and / or alternative technical solutions of the corresponding embodiments.

[0048] In the following description of various embodiments, detailed descriptions of known functions or structures will be omitted when it is determined that such detailed descriptions may unnecessarily obscure the spirit of the invention.

[0049] Furthermore, the terms used below are defined in consideration of the functionality in various embodiments and may vary depending on the intentions or practices of the user or operator. Therefore, they should be defined based on the entire contents of this specification.

[0050] In describing the accompanying drawings, similar reference numerals were used for similar structural elements.

[0051] Unless the context explicitly indicates otherwise, singular expressions may include plural expressions.

[0052] In this specification, expressions such as “A or B” or “at least one of A and / or B” may include all combinations of items listed together.

[0053] Expressions such as “first,” “second,” “firstly,” or “secondly” can modify the corresponding structural elements regardless of their order or importance. They are only used to distinguish one structural element from other structural elements and do not limit the corresponding structural elements.

[0054] When it is said that a structural element (e.g., a first structural element) is “connected” or “linked” (at the functional or communication level) to other structural elements (e.g., a second structural element), it means that the structural element is directly connected to the other structural elements, or can be connected through another structural element (e.g., a third structural element).

[0055] In this manual, “configured to” may be used interchangeably with “suitable for”, “has the function of”, “changed to”, “made to”, “functions as” or “designed to” at the hardware or software level, depending on the circumstances.

[0056] In certain situations, the expression "a device configured as ~" means that the device, together with other devices or components, "performs a ~ function".

[0057] For example, "processors configured (or designed) to perform A, B and C" refers to general-purpose processors (e.g., central processing unit (CPU) or application processor) that can perform the corresponding tasks by running a dedicated processor (e.g., an embedded processor) or one or more software programs stored in a storage device.

[0058] Furthermore, the term "or" refers to "inclusive or" and not "exclusive or".

[0059] That is, unless otherwise stated or explicitly indicated in the context, the expression “x uses a or b” refers to one of the natural inclusive permutations.

[0060] In the following specific embodiments, the structural elements included in the present invention may be represented as singular or plural according to the disclosed specific embodiments.

[0061] However, the singular or plural expression is chosen appropriately based on the disclosed situation for the sake of convenience in explanation. The following embodiments are not limited to singular or plural structural elements. Structural elements expressed as plural can be composed of singular structural elements, or structural elements expressed as singular can also be composed of plural structural elements.

[0062] On the other hand, although this specification describes specific embodiments, various modifications can be made without departing from the technical concept contained in the multiple embodiments.

[0063] Therefore, the scope of the present invention is not limited to the embodiments described below, but should be defined based on the scope of protection claimed by the invention and its equivalents.

[0064] Figure 1 This is a diagram illustrating an input impedance boosting device according to an embodiment of the present invention.

[0065] Reference Figure 1 An embodiment of the present invention provides an input impedance enhancement device 100 that can reduce the influence of parasitic capacitance components without requiring additional calibration or fine-tuning processes.

[0066] Furthermore, the input impedance boosting device 100 not only minimizes power consumption and cost increases due to circuit area, but also increases input impedance.

[0067] Furthermore, compared to existing technologies that utilize fine-tuning processes, the input impedance boosting device 100 can achieve further improved impedance boosting performance.

[0068] Therefore, the input impedance boosting device 100 may include an analog-to-digital converter (ADC) circuit and an input capacitor C. IN Feedback capacitor C' IN and impedance boosting section.

[0069] For example, an analog-to-digital converter (ADC) circuit can be an analog-to-digital converter circuit with a gain of "2" or "-2" or a continuous-time delta-sigma converter circuit (CTDSM).

[0070] Specifically, the input capacitor C in one embodiment of the present invention IN The first shielding metal 110 can be formed at the bottom of the circuit connected to the input line and ground line of the analog-to-digital converter (ADC).

[0071] Furthermore, the feedback capacitor C' in one embodiment of the present invention IN A second shielding metal 120 can be formed at the bottom of the circuit connected to the positive feedback loop of the Delta-Sigma conversion circuit.

[0072] For example, the first shielding metal 110 and the second shielding metal 120 can be connected to the grounding wire respectively, and can be formed at the bottom of the corresponding capacitor, separated from the capacitor by a predetermined size gap.

[0073] Furthermore, the input capacitor C IN and feedback capacitor C' IN It can be a metal-oxide-metal (MOM) capacitor.

[0074] An embodiment of the present invention includes an impedance boosting section and a feedback capacitor C'. IN The two ends are connected, which can be based on the input capacitor C. IN The first parasitic component 110-1 between the first shielding metal 110 and the first parasitic component 110-1 formed in the feedback capacitor C' IN The second parasitic component 120-1 between the second shielding metal 120 and the second shielding metal 120 increases the input impedance.

[0075] According to one embodiment of the present invention, the impedance boosting units 130 and 140 can increase the input impedance by copying the first parasitic component 110-1 and the second parasitic component 120-1 and adding them to the positive feedback loop.

[0076] According to one embodiment of the present invention, the impedance boosting portions 130 and 140 may include: a first metal 140, and a feedback capacitor C' IN The first terminal is connected; and the third shielding metal 130 is formed at the lower part of the first metal 140, and is connected to the feedback capacitor C'. IN Connect to the second terminal.

[0077] For example, a third shielding metal 130 may be formed below the first metal 140, separated from the first metal 140 by a predetermined size.

[0078] The input impedance boosting device 100 may further include a chopper switch connected to the input terminal of the analog-to-digital converter (ADC). In other words, the chopper switch can be positioned between the ADC and the applied input voltage V.IN Between the nodes.

[0079] According to one embodiment of the present invention, the impedance boosting section may further include a virtual switch, which is connected to the feedback capacitor C' IN The two ends are connected.

[0080] Specifically, the impedance boosting section can increase the input impedance by replicating a third parasitic component based on a chopper switch using a virtual switch and adding it to the positive feedback loop. For example, the virtual switch and the chopper switch can be of the same size.

[0081] On the other hand, the analog-to-digital converter (ADC) can be a continuous-time Delta-Sigma analog-to-digital converter circuit, which includes: a linear integrator equipped with a linear transconductance unit (linear Gm cell); a body-driven oscillator (VCO); and a quantizer equipped with a frequency-to-digital converter (FDC).

[0082] Specifically, the linear integrator can be based on receiving a preset input voltage V. IN The related work of the linear transconductance unit generates a voltage V that is related to the input voltage V. IN The corresponding first output signal.

[0083] Furthermore, the quantizer can generate a second output signal corresponding to the first output signal based on the operation of the volume-driven oscillator that receives the first output signal, and generate a digital output code D corresponding to the second output signal based on the operation of the frequency-to-digital converter that receives the second output signal. OUT .

[0084] More specifically, the analog-to-digital converter (ADC) is a first-order continuous-time Delta-Sigma modulator (CTDSM) composed of a linear integrator 110 with low noise and high linearity characteristics and a quantizer based on a volume-driven oscillator. This not only allows for the conversion of a first-order loop (1...) st It possesses high stability due to its order loop characteristics, and low quantization noise can be achieved within the signal bandwidth by leveraging the inherent noise characteristics of the VCO quantizer.

[0085] In other words, analog-to-digital converters (ADCs) can maximize the overall system's noise performance, linearity, and bandwidth by improving the noise power efficiency and linearity of the integrator and VCO-based quantizer.

[0086] According to one embodiment of the present invention, the analog-to-digital converter (ADC) further includes a 4th-order finite impulse response (4-tap FIR) filter, which is disposed in a Delta-Sigma feedback loop that connects the input of the linear integrator to the output of the quantizer.

[0087] For example, a Delta-Sigma feedback loop can also be a positive feedback loop.

[0088] Specifically, the input impedance of the analog-to-digital converter (ADC) depends on the input capacitor C located between the input terminal of the linear integrator 210 and the ground line. IN and the chopping frequency f at the node connected to the input of the linear integrator. CH (choopping frequency) Existing devices use a chopping frequency equal to or equal to the frequency fs or fs / 2 (where fs is the sampling frequency) to prevent quantization noise aliasing caused by chopping.

[0089] However, in this case, there is a problem that the input impedance drops below 1MΩ due to the high sampling frequency. To solve this problem, the analog-to-digital converter (ADC) circuit can connect a fourth-order finite impulse response filter to the feedback loop to vectorize noise and generate a notch.

[0090] More specifically, the analog-to-digital converter (ADC) circuit can prevent aliasing caused by quantization noise, which manifests as chopping, by filtering quantization noise in the frequency band where aliasing occurs through a fourth-order finite impulse response filter.

[0091] Furthermore, compared to existing devices, the analog-to-digital converter (ADC) circuit can use the fs / 8 notch frequency generated by a 4th-order finite impulse response filter as the chopping frequency to increase the input impedance by a factor of 4.

[0092] Figures 2a to 2c A diagram is provided for further detailing an embodiment of the input impedance boosting device of the present invention.

[0093] Reference Figures 2a to 2c Reference numeral "210" indicates the parasitic capacitance component for the input impedance boosting device, and reference numerals "220" and "230" further illustrate in detail an embodiment of the input impedance boosting device of the present invention.

[0094] In reference numeral "210", to minimize the influence of parasitic capacitance components, an embodiment of the input impedance boosting device of the present invention utilizes a method of replicating (imitating) the parasitic capacitance components and adding them to the positive feedback loop without fine-tuning. For this purpose, the input impedance boosting device can reduce the parasitic capacitance components "C" generated during the chopper switch.P_CH "and at the input capacitor C" IN and feedback capacitor C' IN The parasitic capacitance component "C" occurs P_M-GND "Consider it as the main parasitic capacitance."

[0095] Specifically, when the system gain is "-2", if the feedback capacitor C' IN If the following condition (Equation 2) is met, the input impedance boosting device can achieve an infinitely large impedance.

[0096] [Equation 2]

[0097]

[0098] In reference numerals "220" and "230", the input impedance boosting device of one embodiment of the present invention can utilize the parasitic replication technique, which replicates the parasitic capacitance component as indicated by reference numeral "210".

[0099] The input impedance boosting device can form a shielding metal at the bottom of the metal-oxide-metal (MOM) capacitor, so that the metal-oxide-metal (MOM) capacitor C IN / C' IN It is possible to replicate parasitic capacitance, in which case the parasitic capacitance component "C" is... P_M-GND "It can be defined and easily replicated by the overlap area between the metal layers of a metal-oxide-metal capacitor."

[0100] Furthermore, the input impedance boosting device can replicate the parasitic capacitance component "C" using a virtual switch of the same size as the chopper switch. P_CH Compared to existing methods, the above method not only minimizes the impact of parasitic capacitance, but also achieves a 70-fold increase in impedance.

[0101] Specifically, the input impedance boosting device may include: a chopper switch; an analog-to-digital converter (ADC) connected to the chopper switch; and an input capacitor C. IN A first shielding metal 221 is formed thereon; and a feedback capacitor C' is formed thereon. IN It is set on the positive feedback loop, and a second shielding metal 222 is formed at the bottom.

[0102] Furthermore, the input impedance boosting device may also include an impedance boosting section, and a feedback capacitor C' IN The two ends are connected, based on the structure formed in the input capacitor C. INThe first parasitic component 221-1 between the first shielding metal 221 and the first parasitic component 221-1 formed on the feedback capacitor C' IN The second parasitic component 222-1 between the second shielding metal 222 and the second shielding metal 222 increases the input impedance. For this purpose, the impedance boosting part may include: a first metal, and a feedback capacitor C' IN The first terminal is connected; and the third shielding metal 223 is formed at the lower part of the first metal, and is connected to the feedback capacitor C'. IN Connect to the second terminal.

[0103] According to one embodiment of the present invention, the impedance boosting section can increase the input impedance by replicating the first parasitic component 221-1 and the second parasitic component 222-1 and adding them to the positive feedback loop.

[0104] More specifically, the input impedance boosting device can supply input capacitor C, which is a metal-oxide-metal capacitor. IN and feedback capacitor C' IN The lower part is respectively configured with a first shielding metal 221 and a second shielding metal 222 connected to the grounding wire to control the parasitic capacitance components 221-1 and 222-1.

[0105] Among them, parasitic capacitance components 221-1 and 222-1 can be overlap capacitance, that is, parasitic capacitance component C P_GND1 C P_M-GND2 It can be an overlapping capacitance generated by the individual metal layers and shielding metals of a metal-oxide-metal capacitor.

[0106] That is, in order to eliminate (cancele) the parasitic capacitance component C P_GND1 C P_M-GND2 The resulting parasitic effect can be mitigated by the input impedance boosting device on the feedback capacitor C'. IN Additional metal grounding is provided around the parasitic capacitance component.

[0107] In other words, the input impedance boosting device can be replicated using the impedance boosting section (i.e., C'). P_GND =C' P_GND1 +C' P_GND2 Parasitic capacitance component C P_GND1 C P_M-GND2 This is reflected in the positive feedback loop to minimize the parasitic capacitance component C. P_GND1 C P_M-GND2 The resulting effect, the aforementioned impedance boosting section includes: a first metal, and a feedback capacitor C' IN The first terminal is connected; and the third shielding metal 223 is formed at the lower part of the first metal, and is connected to the feedback capacitor C'. IN Connect to the second terminal.

[0108] On the other hand, the impedance boosting section may also include a virtual switch, along with the feedback capacitor C' IN The two ends are connected and are of the same size as the chopper switch, so that the impedance boosting section can be replicated by a virtual switch (i.e., C'). P_CH The third parasitic component formed by the chopper switch (i.e., C) P_CH =C GS +C J +C GD +C J This is reflected in the positive feedback loop to minimize the parasitic capacitance component C. P_CH The resulting impact.

[0109] Figure 3 A diagram is provided for further detailing a linear integrator according to an embodiment of the present invention.

[0110] Reference Figure 3 In one embodiment of the present invention, the linear integrator 300 serves as the first entity receiving the relevant input of the analog-to-digital converter (ADC) and plays an important role in determining system noise and linearity. Since it plays a major role in determining system noise and linearity, it can be designed to have low noise and high linearity.

[0111] A linear integrator according to an embodiment of the present invention can be based on receiving a preset input voltage V INN V INP The relevant operation of the linear transconductance circuit 310 generates the input voltage V. INN V INP The corresponding first output signal I OUTN I OUTP .

[0112] The linear transconducting circuit 310 may include: multiple operational amplifiers 311; and multiple resistors R. D It is connected to the input terminals of multiple operational amplifiers 311, and multiple resistors R D Each of the three operational amplifiers 311 is connected to one of its terminals via one side, and to the power supply voltage V via the other side. DD The lines are connected.

[0113] Furthermore, the linear integrator 300 may also include a DC current source 320 connected to the output of the linear transconductance circuit 310.

[0114] On the other hand, the linear integrator 300 can be designed as a current-multiplexed operational amplifier by designing multiple operational amplifiers 311 separately in order to improve noise power efficiency.

[0115] In the plurality of transistors constituting the plurality of operational amplifiers 311, the input voltage V is received through the gate terminals of transistors M2 and M4.INP The input voltage V can be received through the gate terminals of transistors M1 and M3. INN Among them, transistors M1 to M4 can be based on the input voltage V. INN and input voltage V INP It functions as a transconductance amplifier.

[0116] According to one embodiment of the present invention, the linear integrator 300 generates a coefficient of performance (COP) based on the input voltage V through unit gain feedback in the linear transconductance circuit 310. INN V INP A current that varies linearly across multiple resistors RD can generate a first output signal corresponding to the change in the generated current.

[0117] Specifically, as the linear circuit change caused by the linear transconductance circuit 310 is replicated to the output terminal through the NMOS transistor, the linear integrator 300 can generate an output current I. OUTN I OUTP Due to the generated output current I OUTN I OUTP The load capacitor flowing into the linear integrator 300 thus maintains linearity, wherein the output current I... OUTN I OUTP It can be converted into a voltage corresponding to the load capacitor (i.e., the first output signal).

[0118] Figure 4 A diagram is provided for further detailing a body-driven oscillator according to an embodiment of the present invention.

[0119] Reference Figure 4 The quantizer in the analog-to-digital converter (ADC) circuit can generate a second output signal corresponding to the first output signal based on the operation of the body-driven oscillator 400 that receives the first output signal from the linear integrator, and generate a digital output code D corresponding to the second output signal based on the operation of the frequency-to-digital converter that receives the second output signal. OUT .

[0120] Specifically, the output frequency variation of existing gate-driven oscillators is reflected by the delay variation of each inverter delay cell, which is generated by the current variation of the PMOS transistor.

[0121] In this case, the input voltage V of the gate-driven oscillator C The G applied to the gate terminal of the PMOS transistor, the G of the PMOS transistorm The characteristics significantly affect the linearity of the gate-driven oscillator. That is, due to the G characteristics of the PMOS transistor... m It has nonlinear characteristics; therefore, the output frequency changes nonlinearly with respect to the input voltage of the gate-driven oscillator.

[0122] Conversely, the body-driven oscillator 400 of one embodiment of the present invention differs from existing gate-driven oscillators in that the input voltage V C+ V C- The delay of the inverting delay unit is applied to the body terminal. Therefore, the delay change of the inverting delay unit is reflected by the change of the threshold voltage of each PMOS transistor and NMOS transistor constituting the inverting delay unit caused by the change of the body voltage.

[0123] That is, in one embodiment of the present invention, the change in input voltage compared to output frequency of the body-driven oscillator 400 is determined by the G of each transistor. mb Features are evident, compared to G m Because of G mb Having linear characteristics, the body-driven oscillator of an embodiment of the present invention can effectively ensure linear characteristics compared to existing gate-driven oscillators.

[0124] Figure 5a and Figure 5b The figure shows the performance simulation results of the input impedance boosting device according to an embodiment of the present invention, which is used to further illustrate the invention.

[0125] Reference Figure 5a and Figure 5b Reference numerals "510" and "520" indicate the input impedance (Z) of an input impedance boosting device according to an embodiment of the present invention. IN ) Measurement results.

[0126] Specifically, in one embodiment of the present invention, the input impedance boosting device has a first shielding metal and a second shielding metal connected to a ground wire respectively disposed in the lower part of the input capacitor and the feedback capacitor, which are metal-oxide-metal capacitors. A first metal connected to the first terminal of the feedback capacitor is disposed therein, and a first metal is formed in the lower part of the first metal and connected to the feedback capacitor C'. IN The third shielding metal is connected to the second terminal, thereby allowing the parasitic capacitance component to be controlled by the input capacitor and the feedback capacitor.

[0127] Furthermore, in one embodiment of the present invention, the input impedance enhancement device can control the parasitic capacitance component formed by the chopper switch by configuring a virtual switch. The virtual switch is connected to both ends of the feedback capacitor and has the same size as the chopper switch.

[0128] In the attached figures “510” and “520”, compared to the theoretical value (unboosted Z) IN According to one embodiment of the present invention, the input impedance boosting device can achieve a boost effect of more than 70 times.

[0129] Furthermore, measurements of 10+ chips showed that the input impedance boosting device of an embodiment of the present invention achieves an input impedance of at least 421MΩ@DC and 147MΩ@1kHz, and consumes only 7% of the overall system area in order to apply the parasitic replication technique of an embodiment of the present invention.

[0130] Ultimately, by utilizing this invention, the influence of parasitic capacitance components can be reduced without the need for additional calibration or fine-tuning processes.

[0131] Furthermore, by utilizing the present invention, not only can power consumption and cost increases due to circuit area be minimized, but input impedance can also be improved.

[0132] Furthermore, when utilizing the present invention, compared to existing technologies that utilize a fine-tuning process, further improved impedance boosting performance can be achieved.

[0133] While embodiments have been described above with reference to the accompanying drawings, those skilled in the art can make various modifications and variations based on the above description. For example, even if the described techniques are performed in a different order than the described methods, and / or the described systems, structures, devices, circuits, and other structural elements are combined or integrated in a different manner than the described methods, or even if they are replaced or substituted by other structural elements or equivalent technical solutions, appropriate results can still be achieved.

[0134] Therefore, other implementation methods, other embodiments, and contents equivalent to the scope of the invention claims also fall within the scope of the invention claims of this invention.

Claims

1. An input impedance boosting device, characterized in that, include: Analog-to-digital converter circuit; An input capacitor is connected to the input terminal of the aforementioned analog-to-digital conversion circuit and the ground wire, and a first shielding metal is formed at the bottom. A feedback capacitor is provided in the positive feedback loop of the analog-to-digital conversion circuit described above. The feedback capacitor has a first terminal and a second terminal and a second shielding metal formed at the bottom. as well as The impedance boosting section is connected to the first and second terminals of the feedback capacitor. It increases the input impedance by replicating the first parasitic component formed between the input capacitor and the first shielding metal and the second parasitic component formed between the feedback capacitor and the second shielding metal, and by adding the replicated first and second parasitic components to the positive feedback loop.

2. The input impedance boosting device according to claim 1, characterized in that, The impedance boosting section mentioned above includes: The first metal is connected to the first terminal of the aforementioned feedback capacitor; and A third shielding metal is formed at the lower part of the first metal and is connected to the second terminal of the feedback capacitor.

3. The input impedance boosting device according to claim 1, characterized in that, The first shielding metal and the second shielding metal are respectively connected to the grounding wire.

4. The input impedance boosting device according to claim 1, characterized in that, Also includes: A chopper switch is connected to the input terminal of the aforementioned analog-to-digital conversion circuit.

5. The input impedance boosting device according to claim 3, characterized in that, Also includes: A chopper switch is connected to the input terminal of the aforementioned analog-to-digital converter circuit. The impedance boosting section mentioned above also includes: A virtual switch is connected to both ends of the aforementioned feedback capacitor. The impedance enhancement section improves the input impedance by replicating a third parasitic component based on the chopper switch through the virtual switch and adding the replicated third parasitic component to the positive feedback loop. The virtual switch is formed to have the same size as the chopper switch.

6. The input impedance boosting device according to claim 1, characterized in that, The aforementioned feedback capacitor and the aforementioned input capacitor are metal-oxide-metal capacitors.

7. The input impedance boosting device according to claim 1, characterized in that, The analog-to-digital converter circuit described above is a continuous-time Delta-Sigma analog-to-digital converter circuit. The aforementioned continuous-time Delta-Sigma analog-to-digital converter circuit includes: A linear integrator, equipped with a linear transconductance unit; Body-driven oscillator; and The quantizer is equipped with a frequency-to-digital converter.

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