Display device, display panel, driving backplane and manufacturing method thereof

Abstract

The present disclosure provides a display device, a display panel, a driving backplane and a manufacturing method of the driving backplane. It relates to the technical field of display. The driving backplane comprises a substrate and a driving layer, the driving layer has a pixel circuit and a data line, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light-emitting control line and a first power supply line; the pixel circuit comprises a storage capacitor and a first type transistor and a second type transistor different in material; the active layers of the first type transistors are arranged in the same layer, and the active layers of the second type transistors are arranged in the same layer; the gate of the first type transistor, the first plate of the storage capacitor, the first gate line and the light-emitting control line are arranged in the same layer; the gate of the second type transistor, the second plate of the storage capacitor, the second gate line, the first reset control line and the first reset data line are arranged in the same layer; the second reset data line is located in the first source-drain layer, and the data line and the first power supply line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device, a display panel, a driving backplane, and a method for manufacturing the driving backplane. Background Technology

[0002] Display panels are widely used in electronic devices such as mobile phones and tablets. Among them, OLED display panels, which use organic light-emitting diodes as light-emitting devices, are more common. Existing OLED display panels generally include a driving backplane and light-emitting devices located on one side of the driving backplane. The driving backplane has circuits that drive the light-emitting devices to emit light. At present, the manufacturing process of the driving backplane is relatively complex and the cost is high.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display device, display panel, driving backplate and manufacturing method thereof, which can simplify the structure and process and reduce costs.

[0005] According to one aspect of this disclosure, a driving backplane is provided, comprising a substrate and a driving layer disposed on one side of the substrate. The driving layer has a pixel circuit and a plurality of traces connected to the pixel circuit. The traces include data lines, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light emission control line, and a first power supply line. The pixel circuit includes a storage capacitor and a plurality of transistors, the transistors including first-type transistors and second-type transistors, wherein the active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line is used to turn on at least two of the transistors of the pixel circuit through a light emission control signal.

[0006] The active layer of each of the first type of transistors is disposed on the same layer of the first semiconductor layer, and the active layer of each of the second type of transistors is disposed on the same layer of the second semiconductor layer.

[0007] The gate of the first type of transistor, the first plate of the storage capacitor, the first gate line, and the light-emitting control line are disposed in the same layer on the first gate layer; the gate of the second type of transistor, the second plate of the storage capacitor, the second gate line, the first reset control line, and the first reset data line are disposed in the same layer on the second gate layer.

[0008] The second reset data line is located in the first source-drain layer, and the data line and the first power line are disposed in the same layer in the second source-drain layer;

[0009] The first semiconductor layer, the first gate layer, the second semiconductor layer, the second gate layer, the first source / drain layer, and the second source / drain layer are distributed sequentially in a direction away from the substrate.

[0010] In one exemplary embodiment of this disclosure, the transistors of the pixel circuit include a first transistor and a second transistor belonging to the second type of transistors, and a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor belonging to the first type of transistors.

[0011] The first terminal of the first transistor is connected to the first reset data line, the second terminal of the first transistor is connected to the gate of the third transistor and the second terminal of the second transistor, and the gate of the first transistor is connected to the first reset control line.

[0012] The first terminal of the second transistor is connected to the second terminal of the third transistor and the first terminal of the sixth transistor, and the gate of the second transistor is connected to the second gate line;

[0013] The first terminal of the third transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor;

[0014] The gate of the fourth transistor is connected to the first gate line; the first electrode of the fourth transistor is connected to the data line.

[0015] The gates of the fifth transistor and the sixth transistor are connected to the light-emitting control line; the first electrode of the fifth transistor is connected to the first power supply line.

[0016] The second electrode of the sixth transistor is connected to the light-emitting device;

[0017] The gate of the seventh transistor is connected to the second reset control line;

[0018] The first plate of the storage capacitor is connected to the gate of the third transistor, and the second plate is connected to the first power supply line.

[0019] In one exemplary embodiment of this disclosure, the active layer of the first type of transistor is made of polysilicon, and the active layer of the second type of transistor is made of metal oxide.

[0020] The driver layer also includes:

[0021] A first gate insulating layer covers the first semiconductor layer; the first gate layer is disposed on the surface of the first gate insulating layer opposite to the substrate.

[0022] A first insulating layer covers the first gate layer; a second semiconductor layer is disposed on the surface of the insulating layer opposite to the substrate.

[0023] A second gate insulating layer covers the second semiconductor layer; a second gate layer is disposed on the surface of the second gate insulating layer opposite to the substrate.

[0024] A second insulating layer covers the second gate layer; the first source / drain layer is disposed on the surface of the second insulating layer opposite to the substrate.

[0025] A first planarization layer covers the first source / drain layer; a second source / drain layer is disposed on the surface of the first planarization layer opposite to the substrate.

[0026] A second planarization layer covers the second source / drain layer.

[0027] In one exemplary embodiment of this disclosure, the pixel circuit array is distributed, and the pixel circuits in the same row are divided into multiple circuit units. Each circuit unit includes two symmetrically arranged pixel circuits. The first power line connecting the two pixel circuits in the same circuit unit is an integral structure, and the second plates of the storage capacitors of the two pixel circuits in adjacent circuit units are an integral structure.

[0028] In one exemplary embodiment of this disclosure, the drive backplane includes a first drive area and a second drive area located outside the first drive area, and the circuit unit is provided in both the first drive area and the second drive area;

[0029] In a row of circuit units within the first driving area, the gap between at least two adjacent circuit units is a first gap, and the gap between at least two adjacent circuit units is a second gap; the width of the second gap is greater than the first gap and greater than the width of at least one pixel circuit; the width of the first gap is less than the width of one pixel circuit.

[0030] In a row of circuit units within the second driving region, the gap between adjacent circuit units is the first gap.

[0031] In one exemplary embodiment of this disclosure, the second reset data line connecting the circuit units in the same row is disconnected in the second gap;

[0032] The first gate layer includes:

[0033] A connection portion is provided at intervals from the gate, the first electrode plate, the first gate line, and the light-emitting control line of the first type of transistor, and a connection portion is provided within a second gap; a second reset data line is connected to the connection portion in the second gap.

[0034] In one exemplary embodiment of this disclosure, the first semiconductor layer includes a plurality of arrayed semiconductor portions, each semiconductor portion including a first semiconductor portion and a second semiconductor portion; the first semiconductor portion is used to form an active layer of each transistor of the pixel circuit; the second semiconductor portion is located within the second gap.

[0035] The gap between two adjacent semiconductor sections in the same row is the first gap.

[0036] In one exemplary embodiment of this disclosure, the second reset control line connected to the pixel circuit in the nth row is multiplexed as the first gate line connected to the pixel circuit in the (n+1)th row.

[0037] According to one aspect of this disclosure, a method for manufacturing a drive backplane is provided, comprising:

[0038] A driving layer is formed on one side of the substrate, the driving layer comprising a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer, a first source / drain layer, and a second source / drain layer sequentially distributed in a direction away from the substrate;

[0039] The driving layer has a pixel circuit and multiple traces connected to the pixel circuit. The traces include a data line, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light emission control line, and a first power supply line. The pixel circuit includes a storage capacitor and multiple transistors, including first-type transistors and second-type transistors. The active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line is used to turn on at least two of the transistors in the pixel circuit via a light emission control signal.

[0040] The active layer of each of the first type of transistors is disposed on the same layer of the first semiconductor layer, and the active layer of each of the second type of transistors is disposed on the same layer of the second semiconductor layer.

[0041] The gate of the first type of transistor, the first plate of the storage capacitor, the first gate line, and the light-emitting control line are disposed in the same layer on the first gate layer; the gate of the second type of transistor, the second plate of the storage capacitor, the second gate line, the first reset control line, and the first reset data line are disposed in the same layer on the second gate layer.

[0042] The second reset data line is located in the first source-drain layer, and the data line and the first power line are located in the second source-drain layer.

[0043] According to one aspect of this disclosure, a display panel is provided, comprising:

[0044] The drive backplane described in any of the above items;

[0045] A light-emitting layer is disposed on the side of the driving layer opposite to the substrate, and includes a plurality of light-emitting devices, each of which is connected to a pixel circuit.

[0046] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0047] This disclosure discloses a display device, display panel, driving backplane, and manufacturing method thereof, which can drive light-emitting devices to emit light through pixel circuits. In the driving backplane, the storage capacitor, the gate of the first type of transistor, the first gate line and the light-emitting control line, the gate of the second type of transistor, the second gate line, the first reset control line and the first reset data line are arranged through two layers: a first gate layer and a second gate layer, instead of using three or more layers. This minimizes the number of film layers, simplifies the structure and process, and reduces costs.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0050] Figure 1 This is a cross-sectional schematic diagram of one embodiment of the drive backplane of this disclosure.

[0051] Figure 2 This is an equivalent circuit diagram of the pixel circuit of one embodiment of the driving backplane of this disclosure.

[0052] Figure 3 for Figure 2 The diagram shows a driving timing diagram for a pixel circuit.

[0053] Figure 4 This is a layout of the semiconductor layer of one embodiment of the drive backplane of this disclosure.

[0054] Figure 5This is a layout of the first gate layer of one embodiment of the drive backplane of this disclosure.

[0055] Figure 6 This is a layout of the second semiconductor layer of one embodiment of the drive backplane of this disclosure.

[0056] Figure 7 This is a layout of the second gate layer of one embodiment of the drive backplane of this disclosure.

[0057] Figure 8 This is a layout of the first source / drain layer of an embodiment of the driving backplane of this disclosure.

[0058] Figure 9 This is a layout of the second source / drain layer of one embodiment of the driving backplane of this disclosure.

[0059] Figure 10 This is a layout of the first semiconductor layer and the first gate layer of one embodiment of the drive backplane of this disclosure.

[0060] Figure 11 This is a layout of the first semiconductor layer to the second gate layer of one embodiment of the drive backplane of this disclosure.

[0061] Figure 12 This is a layout of the first semiconductor layer to the first source / drain layer of one embodiment of the drive backplane of this disclosure.

[0062] Figure 13 This is a layout of the pixel circuitry in one embodiment of the drive backplane of this disclosure. Detailed Implementation

[0063] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0064] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0065] In this document, the row direction X and column direction Y are simply two mutually perpendicular directions. In the accompanying drawings of this disclosure, the row direction X can be horizontal and the column direction Y can be vertical, but are not limited to these. If the drive backplate rotates, the actual orientation of the row direction X and column direction Y may change. The X direction in the accompanying drawings exemplarily shows the row direction, and the Y direction exemplarily shows the column direction.

[0066] This disclosure provides a driving backplane that can be used in a display panel, which may be an OLED display panel. Figure 1 and Figure 2 As shown, the driving backplane may include a substrate SU and a driving layer disposed on one side of the substrate SU. The driving layer has a pixel circuit and multiple traces connected to the pixel circuit. The traces include a data line Da, a first reset control line Re1, a second reset control line Re2, a first reset data line Vinit1, a second reset data line Vinit2, a first gate line G1, a second gate line G2, a light emission control line EM, and a first power supply line VDD. The pixel circuit includes a storage capacitor C and multiple transistors. The transistors include first-type transistors and second-type transistors. The active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line EM is used to turn on at least two transistors of the pixel circuit through a light emission control signal.

[0067] The active layers of each type 1 transistor are co-located on the first semiconductor layer SE1, and the active layers of each type 2 transistor are co-located on the second semiconductor layer SE2. The gate, the first plate of the storage capacitor C, the second gate line G2, the second reset control line Re2, and the light emission control line EM of the type 1 transistor are co-located on the first gate layer GA1. The gate, the second plate of the storage capacitor C C, the first gate line G1, the first reset control line Re1, and the first reset data line Vinit1 of the type 2 transistor are co-located on the second gate layer GA2. The second reset data line Vinit2 is located on the first source-drain layer SD1, and the data line Da and the first power supply line VDD are co-located on the second source-drain layer SD2.

[0068] The first semiconductor layer SE1, the first gate layer GA1, the second semiconductor layer SE2, the second gate layer GA2, the first source / drain layer SD1, and the second source / drain layer SD2 are distributed sequentially along the direction away from the substrate SU.

[0069] The driving backplane of this embodiment can drive the light-emitting device to emit light through the pixel circuit. In the driving backplane, the storage capacitor C, the gate of the first type transistor, the first gate line G1 and the light-emitting control line EM, the gate of the second type transistor, the second gate line G2, the first reset control line Re1 and the first reset data line are set through the first gate layer GA1 and the second gate layer, instead of using three or more layers. This is beneficial to minimizing the number of film layers, simplifying the structure and process, and thus reducing costs.

[0070] The following is a detailed description of the driver backplane disclosed herein:

[0071] The driving backplane can be formed of multiple film layers. For example, the driving backplane may include a substrate SU and a driving layer disposed on one side of the substrate SU. The substrate SU can be the base of the driving backplane and can support the driving layer. The substrate SU can be a rigid or flexible structure, and can be a single-layer or multi-layer structure, without special limitation. The driving layer has driving circuitry, which can be used to drive each light-emitting device of the light-emitting layer to emit light independently to display an image. At the same time, the driving backplane may include a pixel area and a peripheral area located outside the pixel area. For example, the peripheral area may be a continuous or discontinuous annular region surrounding the pixel area.

[0072] The driving circuit may include pixel circuits and peripheral circuits. The pixel circuits may be located within the pixel area; alternatively, a portion of the pixel circuit may be located within the peripheral area. The peripheral circuits are located within the peripheral area and are connected to the pixel circuits. They are used to input driving signals to the pixel circuits to control the light-emitting device to emit light. The peripheral circuits may include gate driving circuits, source driving circuits, and light-emitting control circuits, and may also include other circuits. No specific limitations are placed on the specific structure of the peripheral circuits here.

[0073] In some embodiments of this disclosure, the pixel circuit can be a 7T1C structure, that is, it can have 7 transistors and 1 capacitor. Specifically, such as... Figure 2 As shown, the transistors in the pixel circuit include a first transistor T1 and a second transistor T2 belonging to the second type of transistors, and a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 belonging to the first type of transistors. The third transistor T3 is a driving transistor, wherein:

[0074] The first terminal of the first transistor T1 is connected to the first reset data line Vinit1. The second terminal of the first transistor T1 is connected to the gate GT3 of the third transistor T3 and the second terminal of the second transistor T2 at node N. The gate GT1 of the first transistor T1 is connected to the first reset control line Re1. The first terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The gate GT2 of the second transistor T2 is connected to the second gate line G2. The first terminal of the third transistor T3 is connected to the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5. The gate GT4 of the fourth transistor T4 is connected to the first gate line G1. The first terminal of the fourth transistor T4 is connected to the data line Da. The gates GT5 of the fifth transistor T5 and GT6 of the sixth transistor T6 are connected to the light emission control line EM. The first terminal of the fifth transistor T5 is connected to the first power supply line VDD. The gate GT7 of the seventh transistor T7 is connected to the second reset control line Re2. The first plate of the storage capacitor C is connected to the gate GT3 of the third transistor T3 at node N, and the second plate C2 is connected to the first power supply line VDD.

[0075] This pixel circuit can be connected to a light-emitting device to drive it to emit light. The light-emitting device can be connected between the second terminal of the sixth transistor T6 and the second power supply line VSS. The first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal-oxide transistors, meaning the active layer of the first transistor T1 and the second transistor T2 is N-type metal-oxide. N-type metal-oxide transistors have lower leakage current, thus avoiding leakage current through the first transistor T1 and the second transistor T2 during the light-emitting stage. Of course, the first transistor T1 and the second transistor T2 can also use other metal oxides. Meanwhile, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type polysilicon transistors, meaning the active layer of the third transistor T3 to the seventh transistor T7 is P-type polysilicon. For example, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon transistors. P-type low-temperature polysilicon transistors have high carrier mobility, which is beneficial for realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first reset data line Vinit1 and the second reset data line Vinit2 can output the same or different voltage signals according to the actual situation.

[0076] like Figure 3 As shown, Figure 1The driving timing diagram of the pixel circuit is shown below. G1 represents the timing of the signal for the first gate line G1, G2 represents the timing of the signal for the second gate line G2, Re1 represents the timing of the signal for the first reset control line Re1, Re2 represents the timing of the signal for the second reset control line Re2, EM represents the timing of the signal for the emission control line EM, and Da represents the timing of the signal for the data line Da. The driving method of this pixel circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and an emission stage t4.

[0077] In the first reset phase t1: the first reset control line Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first reset data line Vinit1 inputs a reset signal to node N.

[0078] During the compensation phase t2: the first gate line G1 outputs a high-level signal, the second gate line G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data line Da outputs a data signal to write a voltage Vdata+Vth (i.e., the sum of voltages Vdata and Vth) to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the third transistor T3.

[0079] In the second reset phase t3: the second reset control line Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second reset data line Vinit2 inputs a reset signal to the second terminal of the sixth transistor T6.

[0080] During the light-emitting stage t4: the light-emitting control line EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the third transistor T3 emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0081] The third transistor T3 acts as a driver transistor, and its output current satisfies the following formula:

[0082] I = (μWCox / 2L)(Vgs-Vth) 2

[0083] Where I is the output current of the third transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the channel width of the third transistor T3; L is the channel length of the third transistor T3; Vgs is the gate-source voltage difference of the third transistor T3; and Vth is the threshold voltage of the third transistor T3.

[0084] Based on the formula for the output current of the third transistor T3, substituting the gate voltage Vdata+Vth and source voltage Vdd of the driving transistor in the pixel circuit of this disclosure into the formula, we can obtain: The output current I of the third transistor T3 in the pixel circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth). 2 It can be seen that the output current of this pixel circuit is independent of the threshold voltage Vth of the third transistor T3, but is related to Vdata. This eliminates the influence of the threshold voltage of the third transistor T3 on its output current. The output current can be controlled solely by Vdata, thereby controlling the brightness of the light-emitting device.

[0085] The driving layer will now be described based on the pixel circuit of the 7T1C described in the above embodiment:

[0086] like Figures 4-13 As shown, the multiple pixel circuits in the driving layer are arrayed along the row direction X and the column direction Y. The pixel circuits in the same row are connected to the same first reset control line Re1, and are also connected to the same second reset control line Re2, the same first reset data line Vinit1, the same second reset data line Vinit2, the same first gate line G1, the same second gate line G2, and the same light emission control line EM. The pixel circuits in the same column are connected to the same data line Da and the same first power supply line VDD.

[0087] The first power line VDD connecting the two pixel circuits in the same circuit unit is a single structure, and the second plate of the storage capacitor C of the two pixel circuits in adjacent circuit units is a single structure.

[0088] In some embodiments of this disclosure, such as Figure 1 As shown, the driving layer may further include a first gate insulating layer GI1, a first insulating layer IL1, a second gate insulating layer GI2, a second insulating layer IL2, a first planarization layer PLN1, and a second planarization layer PLN2, wherein:

[0089] The first gate insulating layer GI1 covers the area of ​​the first semiconductor layer SE1 and the substrate SU not covered by the first semiconductor layer SE1. The first gate layer GA1 may be disposed on the surface of the first gate insulating layer GI1 opposite to the substrate SU.

[0090] The first insulating layer IL1 covers the first gate layer GA1; the second semiconductor layer SE2 is disposed on the surface of the insulating layer away from the substrate SU.

[0091] The second gate insulating layer GI2 covers the second semiconductor layer SE2; the second gate layer GA2 is disposed on the surface of the second gate insulating layer GI2 away from the substrate SU.

[0092] The second insulating layer IL2 covers the second gate layer GA2; the first source / drain layer SD1 is disposed on the surface of the second insulating layer IL2 away from the substrate SU.

[0093] The first planarization layer PLN1 covers the first source / drain layer SD1; the second source / drain layer SD2 is disposed on the surface of the first planarization layer PLN1 away from the substrate SU.

[0094] The second planarization layer PLN2 covers the second source / drain layer SD2, and the light-emitting device can be disposed on the surface of the second planarization layer PLN2 away from the substrate SU.

[0095] The materials of the first gate insulating layer GI1, the first insulating layer IL1, the second gate insulating layer GI2, and the second insulating layer IL2 mentioned above can be one or more inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, and one or more of the first gate insulating layer GI1, the first insulating layer IL1, the second gate insulating layer GI2, and the second insulating layer IL2 can be a single-layer or multi-layer structure.

[0096] The first planarization layer PLN1 and the second planarization layer PLN2 can be made of transparent resin or other organic insulating materials, as long as planarization can be achieved.

[0097] The pattern of a portion of the driving layer's film is illustrated below based on a pixel circuit of the aforementioned 7T1C:

[0098] like Figure 4 as well as Figures 10-13 As shown, the first semiconductor layer SE1 may include multiple arrayed semiconductor sections. A pixel circuit includes one semiconductor section, which may include the active layers of each type of transistor in the pixel circuit, namely, the active layers including the third transistor T3 to the seventh transistor T7. Specifically, the active layers are: the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, the sixth active layer ACT6, and the seventh active layer ACT7. The third active layer ACT3 can be used to form the channel region of the third transistor T3; the fourth active layer ACT4 can be used to form the channel region of the fourth transistor T4; the fifth active layer ACT5 can be used to form the channel region of the fifth transistor T5; the sixth active layer ACT6 can be used to form the channel region of the sixth transistor T6; and the seventh active layer ACT7 can be used to form the channel region of the seventh transistor T7.

[0099] The first semiconductor layer SE1 can be made of polycrystalline silicon. Furthermore, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0100] like Figure 5 as well as Figures 10-13 As shown, the first gate layer GA1 may include a first conductive portion GD1, a second gate line G2, a light-emitting control line EM, and a second reset control line Re2. The second gate line G2, the light-emitting control line EM, and the second reset control line Re2 can all extend along the row direction X, but are not limited to straight lines; they can be bent, as long as the extension trend is along the row direction X. The orthogonal projection of the second gate line G2 onto the substrate SU intersects with the orthogonal projection of the fourth active layer ACT4 onto the substrate SU, and the second gate line G2 corresponding to the intersecting region is used to form the gate GT4 of the fourth transistor T4.

[0101] The orthogonal projection of the light-emitting control line EM on the substrate SU intersects with the orthogonal projections of the fifth active layer ACT5 and the sixth active layer ACT6 on the substrate SU, and the light-emitting control line EM corresponding to the intersecting region is used to form the gate of the fifth transistor T5 and the sixth transistor T6.

[0102] The orthographic projection of the second reset control line Re2 on the substrate SU intersects with the orthographic projection of the seventh active layer ACT7 on the substrate SU, and the second reset control line Re2 corresponding to the intersecting region can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion GD1 on the substrate SU at least partially coincides with the orthographic projection of the third active layer ACT3 on the substrate SU, and the first conductive portion GD1 is used to form the gate GT3 of the third transistor T3 and the first plate of the storage capacitor C.

[0103] Furthermore, such as Figures 10-13 As shown, the first gate line G1 connected to the nth row pixel circuit can be multiplexed as the second reset control line Re2 connected to the (n-1)th row pixel circuit, where n is a positive integer not less than 2. Correspondingly, the signals on the first gate line G1 and the second reset control line Re2 are also synchronized; that is, the fourth transistor T4 of the nth row pixel circuit and the seventh transistor T7 of the (n-1)th row pixel circuit are synchronously turned on. This reduces the number of traces, increases the integration density of the pixel circuit, and reduces the area of ​​the pixel circuit.

[0104] like Figure 6 as well as Figures 11-13 As shown, the second semiconductor layer SE2 may include a first active layer ACT1 and a second active layer ACT2 connected along the column direction Y. The first active layer ACT1 is used to form the channel region of the first transistor T1; the second active layer ACT2 is used to form the channel region of the second transistor T2. The material of the second semiconductor layer SE2 may be indium gallium zinc oxide or other metal oxides. Correspondingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.

[0105] like Figure 7 as well as Figures 11-13 As shown, the second gate layer GA2 may include a first reset data line Vinit1, a first reset control line Re1, a second gate line G2, and a second conductive portion GD2. The orthogonal projection of the first reset control line Re1 onto the substrate SU intersects with the orthogonal projection of the first active layer ACT1 onto the substrate SU, and the first reset control line Re1 corresponding to the intersecting region is used to form the gate GT1 of the first transistor T1. The orthogonal projection of the second gate line G2 onto the substrate SU intersects with the orthogonal projection of the second active layer ACT2 onto the substrate SU, and the second gate line G2 corresponding to the intersecting region is used to form the gate GT2 of the second transistor T2. The orthogonal projection of the second conductive portion GD2 onto the substrate SU at least partially coincides with the orthogonal projection of the first conductive portion GD1 onto the substrate SU, and the second conductive portion GD2 is used to form the second electrode of the storage capacitor C.

[0106] In the same pixel circuit, the orthographic projections of the first reset control line Re1, the first gate line G1, the second gate line G2, and the light emission control line EM onto the substrate SU are located between the orthographic projections of the first reset data line Vinit1 and the second reset control line Re2 onto the substrate SU, and are all arranged along the column direction Y. The orthographic projections of the first gate line G1 and the second gate line G2 onto the substrate SU are located between the orthographic projections of the first reset control line Re1 and the light emission control line EM onto the substrate SU. The orthographic projection of the first gate line G1 onto the substrate SU is located between the orthographic projections of the first reset control line Re1 and the second gate line G2 onto the substrate SU. The orthographic projections of the first conductive portion GD1 and the second conductive portion GD2 onto the substrate SU are both located between the orthographic projection of the second gate line G2 onto the substrate SU and the orthographic projection of the light emission control line EM onto the substrate SU.

[0107] like Figure 8 as well as Figures 12-13 As shown, the first source / drain layer SD1 may include a second reset data line Vinit2, a first bridging section SDL1, a second bridging section SDL2, a third bridging section SDL3, a fourth bridging section SDL4, and a fifth bridging section SDL5. The first bridging section SDL1 can connect to the first terminal of the fifth transistor T5 and the second terminal of the storage capacitor C via vias. The second bridging section SDL2 can connect to the second terminal of the second transistor T2, the first terminal of the sixth transistor T6, and the second terminal of the third transistor T3 via vias. The third bridging section SDL3 can connect to the first terminal of the second transistor T2 and the gate GT3 of the third transistor T3 via vias.

[0108] like Figure 7As shown, an opening GDH is formed on the second conductive portion GD2. The orthogonal projection of the via connecting the first conductive portion GD1 and the third bridging portion SDL3 onto the substrate SU lies within the orthogonal projection of the opening GDH onto the substrate SU, so that the conductive structure within the via is insulated from the first conductive portion GD1. The fourth bridging portion SDL4 can be connected to the second terminal of the first transistor T1 and the first reset data line Vinit1 through a via. The fifth bridging portion SDL5 can be connected to the first terminal of the fourth transistor T4 through a via.

[0109] like Figure 9 As shown, the second source / drain layer SD2 may include multiple first power lines VDD and data lines Da. Both the first power lines VDD and Da can extend along the column direction YY and are spaced apart along the row direction X. Figure 8 , Figure 9 and 13 As shown, each column of pixel circuits can be connected to a first power line VDD. For example, the first power line VDD can be connected to the first bridge section SDL1 via a via, thereby connecting to the first terminal of the fifth transistor T5. The data line Da can be connected to the fifth bridge section SDL5 via a via, thereby connecting to the first terminal of the fourth transistor T4.

[0110] In some embodiments of this disclosure, such as Figure 13 As shown, the pixel circuit array is distributed, and the pixel circuit in the same row may include multiple circuit units PC. Each circuit unit PC includes two symmetrically arranged pixel circuits PCa, and adjacent circuit units PC are symmetrically arranged. The aforementioned symmetrical arrangement is also known as mirror arrangement.

[0111] The second plate of the storage capacitor C of the two pixel circuits PCa within the same circuit unit PC can be a single integrated structure. The first electrode of the fifth transistor T5 of the two pixel circuits PCa within the same circuit unit PC can also be a single integrated structure. Furthermore, within the same row of circuit units PC, the first power line VDD connecting two adjacent pixel circuits PCa belonging to different circuit units PC can be a single integrated structure.

[0112] In some embodiments of this disclosure, a driving backplane can be used to implement an under-display camera display panel. The driving backplane may include a transparent display area and a circuit area located outside the transparent display area. The density of pixel circuits in the transparent display area is less than the density of pixel circuits in the circuit area, thereby increasing the light transmittance of the transparent display area. This allows an imaging device to be placed on the side of the substrate SU away from the driving layer, capturing images through the transparent display area, which can also display images, thus realizing the under-display camera function. Furthermore, pixel circuits may not be placed in the transparent display area, but all pixel circuits may be placed in the circuit area, increasing the light transmittance of the transparent display area. To accommodate pixel circuits, at least some pixel circuits may be compressed, i.e., the width of the pixel circuits in the row direction X may be shortened, thereby accommodating more pixel circuits. Simultaneously, the driving backplane also includes multiple connecting lines. One end of a connecting line is connected to a pixel circuit in the circuit area, and the other end extends to the transparent display area for connecting a light-emitting device. This allows the light-emitting device placed in the transparent display area to be connected to the corresponding pixel circuit, realizing under-display camera functionality in the transparent display area.

[0113] In some embodiments of this disclosure, such as Figure 1 and Figure 13 As shown, the first semiconductor layer SE1 may include multiple arrayed semiconductor portions SEPs. The number of semiconductor portions SEPs is less than the number of pixel circuits. The active layer of some transistors of a pixel circuit is located in a semiconductor portion SEP. That is, a pixel circuit has one semiconductor portion SEP, while the semiconductor portions SEPs that do not form pixel circuits are dummy semiconductor portions Sed. The dummy semiconductor portions SEd can be floating.

[0114] At least a portion of the row semiconductor units (SEPs) in each row include the aforementioned dummy semiconductor unit (SEd). The first gate layer may include a connection portion (GC), which may be spaced apart from the gate, first plate, first gate line (G1), and light-emitting control line (EM) of the first type of transistor.

[0115] For a row of pixel circuits corresponding to a row of semiconductor units SEP with a dummy semiconductor unit SEd, the orthogonal projection of a connection GC on the substrate SU can be located between the orthogonal projections of the second gate line G2 and the light-emitting control line EM on the substrate SU, and the connection GC can coincide with the orthogonal projection portion of the dummy semiconductor unit SEd on the substrate SU. Furthermore, the second reset data line Vinit2 connected to the pixel circuit corresponding to the row of semiconductor units SEP is disconnected in the region corresponding to the dummy semiconductor unit SEd and connected to the connection GC, thereby allowing signal transmission through both the connection GC and the second reset data line Vinit2.

[0116] In other embodiments of this disclosure, the display area of ​​the display panel may not have the aforementioned transparent display area, and correspondingly, the driving backplate may not have the first driving area, and each semiconductor part (SEP) may form a pixel circuit.

[0117] This disclosure provides a method for manufacturing a drive backplane, which can be any of the drive backplanes described in the above embodiments. Accordingly, the manufacturing method may include:

[0118] A driving layer is formed on one side of the substrate, the driving layer comprising a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer, a first source / drain layer, and a second source / drain layer sequentially distributed in a direction away from the substrate;

[0119] The driving layer has a pixel circuit and multiple traces connected to the pixel circuit. The traces include a data line, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light emission control line, and a first power supply line. The pixel circuit includes a storage capacitor and multiple transistors, including first-type transistors and second-type transistors. The active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line is used to turn on at least two of the transistors in the pixel circuit via a light emission control signal.

[0120] The active layer of each of the first type of transistors is disposed on the same layer of the first semiconductor layer, and the active layer of each of the second type of transistors is disposed on the same layer of the second semiconductor layer.

[0121] The gate of the first type of transistor, the first plate of the storage capacitor, the first gate line, and the light-emitting control line are disposed in the same layer on the first gate layer; the gate of the second type of transistor, the second plate of the storage capacitor, the second gate line, the first reset control line, and the first reset data line are disposed in the same layer on the second gate layer.

[0122] The second reset data line is located in the first source-drain layer, and the data line and the first power line are located in the second source-drain layer.

[0123] The details of the structure involved in the above manufacturing method have been described in the above implementation of the drive backplane. For details, please refer to the implementation of the drive backplane and its beneficial effects. They will not be repeated here.

[0124] This disclosure provides a display panel that may include a driving backplane and a light-emitting layer, wherein:

[0125] The driving backplane can be any of the driving backplanes described in the above embodiments, and its structure will not be described in detail here. The light-emitting layer can be disposed on the side of the driving layer away from the substrate, and includes multiple light-emitting devices, each of which can be connected to a pixel circuit.

[0126] The light-emitting layer may include multiple light-emitting devices distributed in an array and a pixel definition layer defining each light-emitting device, wherein:

[0127] The pixel definition layer can be located on one side of the driving backplane. The pixel definition layer is used to separate the various light-emitting devices. Specifically, the pixel definition layer can have multiple openings, and the area defined by each opening is the area of ​​one light-emitting device. The shape of the opening, that is, the shape of the outline of the opening's orthographic projection on the driving backplane, can be a polygon, a smooth closed curve, or other shapes. The smooth closed curve can be a circle, an ellipse, or an oval, etc., and no special limitation is made here.

[0128] A pixel circuit can be connected to at least one light-emitting device, thereby emitting light under the drive of a driving circuit. For example, the light-emitting device can be connected to a second source / drain layer and can emit light under the drive of the driving circuit. The light-emitting device can be an organic light-emitting diode, which may include a first electrode, a light-emitting functional layer, and a second electrode sequentially stacked along a direction away from the driving backplane, wherein:

[0129] The first electrode can be disposed on the same surface of the driving backplane as the pixel definition layer, and it can serve as the anode of the light-emitting device. For example, the first electrode can be connected to the second electrode of the sixth transistor and the second electrode of the seventh transistor in the pixel circuit. Each opening of the pixel definition layer exposes a corresponding first electrode. The first electrode can be a single-layer or multi-layer structure, and its material can include one or more of conductive metals, metal oxides, and alloys.

[0130] The light-emitting functional layer is at least partially disposed within the opening, and may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked sequentially in a direction away from the driving backplate. Visible light is generated by causing holes and electrons to recombine into excitons in the light-emitting material layer, and the excitons radiate photons. The specific light-emitting principle will not be detailed here.

[0131] The second electrode may be covered with a light-emitting functional layer, which can serve as the cathode of the light-emitting device. The second electrode may be a single-layer or multi-layer structure, and its material may include one or more of conductive metals, metal oxides, and alloys.

[0132] Furthermore, each light-emitting device can share the same second electrode. Specifically, the second electrode is a continuous conductive layer covering the light-emitting functional layer and pixel definition layer of each light-emitting device. In other words, the orthogonal projection of the second electrode onto the pixel definition layer covers each opening. Simultaneously, the second electrode can be connected to the second power line VSS.

[0133] The encapsulation layer covers the light-emitting layer, protecting it from external water and oxygen corrosion. For example, the encapsulation layer can be implemented using thin-film encapsulation, and may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the surface of the light-emitting layer facing away from the driving backplane; for example, the first inorganic layer may cover the second electrode. The organic layer may be disposed on the surface of the first inorganic layer facing away from the driving backplane, and the boundary of the organic layer is defined inside the boundary of the first inorganic layer. The boundary of the organic layer's orthographic projection on the driving backplane may be located in the peripheral area, ensuring that the organic layer covers all light-emitting devices. The second inorganic layer may cover the organic layer and the first inorganic layer not covered by the organic layer. The second inorganic layer can block water and oxygen intrusion, while the flexible organic layer achieves planarization.

[0134] Furthermore, in some embodiments of this disclosure, the display panel may further include a polarizing layer and a transparent cover plate sequentially distributed on the encapsulation layer along a direction away from the driving backplate, wherein: the polarizing layer is a circular polarizer that reduces the reflection of external light, the specific principle of which will not be described in detail. The transparent cover plate can be adhered to the polarizing layer and can achieve planarization. The transparent cover plate is used to protect the underlying film layer, and its material can be a transparent material such as glass or acrylic, without special limitation.

[0135] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. Its specific structure and beneficial effects can be found in the embodiments of the driving backplate and display panel described above, and will not be repeated here. The display device of this disclosure may be an electronic device with display function such as a mobile phone, tablet computer, or television, which will not be listed here individually.

[0136] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A drive backplane, characterized in that, The device includes a substrate and a driving layer disposed on one side of the substrate. The driving layer has a pixel circuit and multiple traces connected to the pixel circuit. The traces include a data line, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light emission control line, and a first power supply line. The pixel circuit includes a storage capacitor and multiple transistors. The transistors include first-type transistors and second-type transistors, and the active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line is used to turn on at least two of the transistors in the pixel circuit through a light emission control signal. The active layer of each of the first type of transistors is disposed on the same layer of the first semiconductor layer, and the active layer of each of the second type of transistors is disposed on the same layer of the second semiconductor layer. The gate of the first type of transistor, the first plate of the storage capacitor, the first gate line, the second reset control line, and the light emission control line are disposed in the same layer on the first gate layer; the gate of the second type of transistor, the second plate of the storage capacitor, the second gate line, the first reset control line, and the first reset data line are disposed in the same layer on the second gate layer. The second reset data line is located in the first source-drain layer, and the data line and the first power line are disposed in the same layer in the second source-drain layer; The first semiconductor layer, the first gate layer, the second semiconductor layer, the second gate layer, the first source / drain layer, and the second source / drain layer are distributed sequentially in a direction away from the substrate.

2. The drive backplane according to claim 1, characterized in that, The transistors of the pixel circuit include a first transistor and a second transistor belonging to the second type of transistors, and a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor belonging to the first type of transistors. The first terminal of the first transistor is connected to the first reset data line, the second terminal of the first transistor is connected to the gate of the third transistor and the second terminal of the second transistor, and the gate of the first transistor is connected to the first reset control line. The first terminal of the second transistor is connected to the second terminal of the third transistor and the first terminal of the sixth transistor, and the gate of the second transistor is connected to the second gate line; The first terminal of the third transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor; The gate of the fourth transistor is connected to the first gate line; the first electrode of the fourth transistor is connected to the data line. The gates of the fifth transistor and the sixth transistor are connected to the light-emitting control line; the first electrode of the fifth transistor is connected to the first power supply line. The second electrode of the sixth transistor is connected to the light-emitting device; The gate of the seventh transistor is connected to the second reset control line; The first plate of the storage capacitor is connected to the gate of the third transistor, and the second plate is connected to the first power supply line.

3. The drive backplane according to claim 2, characterized in that, The active layer of the first type of transistor is made of polycrystalline silicon, while the active layer of the second type of transistor is made of metal oxide. The driver layer also includes: A first gate insulating layer covers the first semiconductor layer; the first gate layer is disposed on the surface of the first gate insulating layer opposite to the substrate. A first insulating layer covers the first gate layer; a second semiconductor layer is disposed on the surface of the insulating layer opposite to the substrate. A second gate insulating layer covers the second semiconductor layer; a second gate layer is disposed on the surface of the second gate insulating layer opposite to the substrate. A second insulating layer covers the second gate layer; the first source / drain layer is disposed on the surface of the second insulating layer opposite to the substrate. A first planarization layer covers the first source / drain layer; a second source / drain layer is disposed on the surface of the first planarization layer opposite to the substrate. A second planarization layer covers the second source / drain layer.

4. The drive backplane according to claim 3, characterized in that, The pixel circuit array is distributed such that the pixel circuits in the same row include multiple circuit units, each circuit unit includes two symmetrically arranged pixel circuits, and adjacent circuit units are symmetrically arranged. The second plates of the storage capacitors of the two pixel circuits in the same circuit unit are integral structures; the first electrodes of the fifth transistors of the two pixel circuits in the same circuit unit are integral structures.

5. The drive backplane according to claim 4, characterized in that, The first power line connecting two adjacent pixel circuits belonging to different circuit units is a single structure.

6. The drive backplane according to claim 5, characterized in that, The driving backplate includes a transparent display area and a circuit area located outside the transparent display area, wherein the density of the pixel circuits in the transparent display area is less than the density of the pixel circuits in the circuit area; The drive backplate also includes: Multiple connecting lines, one end of which is connected to a pixel circuit in the circuit area, and the other end extends to the transparent display area for connecting a light-emitting device; The first semiconductor layer includes a plurality of arrayed semiconductor sections, the number of which is less than the number of pixel circuits. The active layer of a portion of the transistors of a pixel circuit is located in one of the semiconductor sections. Semiconductor sections in which the pixel circuit is not formed are dummy semiconductor sections.

7. The drive backplane according to claim 6, characterized in that, At least a portion of the semiconductor portion includes the dummy semiconductor portion; the first gate layer includes: The connecting portion is spaced apart from the gate, the first electrode plate, the first gate line, and the light-emitting control line of the first type of transistor; For a row of pixel circuits corresponding to the same row of semiconductors having the dummy semiconductor, the second reset data line connected thereto is disconnected in the region corresponding to the dummy semiconductor and connected to the connection portion; The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the dummy semiconductor portion on the substrate.

8. The drive backplane according to claim 4, characterized in that, The first gate line connected to the pixel circuit in row n is multiplexed as the second reset control line connected to the pixel circuit in row (n-1), where n is a positive integer not less than 2.

9. A method for manufacturing a drive backplane, characterized in that, include: A driving layer is formed on one side of the substrate, the driving layer comprising a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer, a first source / drain layer, and a second source / drain layer sequentially distributed in a direction away from the substrate; The driving layer has a pixel circuit and multiple traces connected to the pixel circuit. The traces include a data line, a first reset control line, a second reset control line, a first reset data line, a second reset data line, a first gate line, a second gate line, a light emission control line, and a first power supply line. The pixel circuit includes a storage capacitor and multiple transistors. The transistors include first-type transistors and second-type transistors, and the active layers of the first-type transistors and the second-type transistors are made of different materials. The light emission control line is used to turn on at least two of the transistors in the pixel circuit through a light emission control signal. The active layer of each of the first type of transistors is disposed on the same layer of the first semiconductor layer, and the active layer of each of the second type of transistors is disposed on the same layer of the second semiconductor layer. The gate of the first type of transistor, the first plate of the storage capacitor, the first gate line, and the light-emitting control line are disposed in the same layer on the first gate layer; the gate of the second type of transistor, the second plate of the storage capacitor, the second gate line, the first reset control line, and the first reset data line are disposed in the same layer on the second gate layer. The second reset data line is located in the first source-drain layer, and the data line and the first power line are located in the second source-drain layer.

10. A display panel, characterized in that, include: The drive backplate according to any one of claims 1-9; A light-emitting layer is disposed on the side of the driving layer opposite to the substrate, and includes a plurality of light-emitting devices, each of which is connected to a pixel circuit.

11. A display device, characterized in that, Includes the display panel as described in claim 10.

Images