An analog system and method for Link16 signals

Abstract

The present invention discloses a Link16 signal simulation system and method. The implementation steps are as follows: a display control terminal generates a message stream; a message parsing module and a message recognition module respectively parse and recognize the message stream; a multiplexer module selects different ports to output data vectors according to an enable signal; a base mode intermediate frequency signal generation link unit generates a Link16 intermediate frequency signal; an RTT mode intermediate frequency signal generation link unit generates a Link16 intermediate frequency signal; a software radio device obtains the simulation result of the Link16 signal to generate a Link16 radio frequency signal. By processing the synchronization word, header message, and message information in vector form in parallel by the header processing module and the message processing, the present invention improves the data and signal processing speed and the real-time performance of the Link16 signal; by adding the verification and validation of the Link16 signal configuration information and the sequence identification code, the reliability of the generated Link16 signal is improved.

Description

Technical Field

[0001] The present invention belongs to the field of wireless communication technology, and relates to a simulation system and method for Link16 signals, which can complete real-time distribution and automated processing of information through Link16 signals. Technical Background

[0002] The data link is a new type of communication technology that supports a wide range of services such as identification friend or foe, precise positioning, and relative navigation. The Link16 signal is the signal waveform of the Link16 data link, which can provide complete and reliable communication services for multiple network users in a complex electromagnetic environment. With the rapid development of information technology, the demand for information real-time is becoming increasingly urgent, and voice communication can no longer meet the requirements in terms of timeliness and transmission capacity. Therefore, objectively, a new information transmission means is needed, and the Link16 system came into being. Compared with traditional voice communication, Link16 has the advantages of strong anti-interference ability, high confidentiality, and high real-time performance. Therefore, the simulation research on Link16 signals not only has great theoretical significance but also is of great significance to the development of China's communication countermeasure technology.

[0003] The traditional Link16 signal simulation system is implemented based on a hybrid architecture of software and hardware, and is composed of a software display control terminal, a CRC check module, an RS coding module, an interleaving module, a CCSK coding module, an MSK modulation module, and a frequency hopping module in cascade. The software display control terminal is responsible for calculating the data stream of the generated signal parameter information, and then sending control commands and the like to the hardware. The CPU+FPGA or CPU+DSP architecture is used to perform CRC encoding, RS encoding, interleaving processing, CCSK encoding, MSK modulation, and frequency hopping processing in sequence to generate a data stream of the signal, and obtain the Link16 radio frequency signal.

[0004] To address the deficiencies of complex system structure and low anti-interference ability in traditional Link16 signal simulation systems and methods, Lin Shuai disclosed a method for simulating Link16 signals based on a general hardware platform in his published paper "Software Design and Implementation of Electromagnetic Environment Signal Simulation Source" (Electronics and Communication Engineering, 2022). The display control terminal is responsible for calculating the data stream of the generated signal parameter information, and through software modeling, the data stream is subjected to CRC encoding, RS encoding, interleaving processing, CCSK encoding, MSK modulation, and frequency hopping processing to obtain the Link16 radio frequency digital signal. Finally, the digital signal is converted into an analog signal through the general hardware platform to obtain the Link16 radio frequency signal. This method realizes hardware components through software, simplifies the system structure, reduces the system cost, and can edit and design signals in relatively complex environmental scenarios and co-simulate multiple signal types, improving the anti-interference ability of the Link16 system. However, its deficiencies are that the header information and message information are processed sequentially in the form of a data stream in the Link16 signal simulation method, resulting in a slow data processing speed and relatively poor real-time performance of the generated Link16 signal; the receiving party cannot verify the received signal, resulting in relatively low reliability of the Link16 signal. Summary of the Invention

[0005] The object of the present invention is to overcome the above-mentioned defects existing in the prior art, and provide a Link16 signal simulation system and method for solving the technical problems of relatively poor real-time performance and low reliability of the Link16 signal generated by the prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A Link16 signal simulation system includes a display control terminal, a multiplexer module, and a software radio device connected in sequence. A basic mode intermediate frequency signal generation link unit and an RTT mode intermediate frequency signal generation link unit arranged in parallel are loaded between the multiplexer module and the software radio device; a message parsing module and a message recognition module arranged in parallel are loaded between the display control terminal and the multiplexer module; the basic mode intermediate frequency signal generation link unit includes a CRC error detection coding module, a data splicing module, a frequency hopping module, and a transmission protection module cascaded in sequence, and a header processing module and a message processing module arranged in parallel are also loaded between the CRC error detection coding module and the data splicing module; the RTT mode intermediate frequency signal generation link unit includes a header processing module, a frequency hopping module, and a transmission protection module cascaded in sequence.

[0008] The above analog system for Link16 signals, the header processing module includes a data addition module, an RS encoding module, a data addition module arranged in parallel, an interleaving module, a data splicing module, a CCSK encoding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

[0009] The above analog system for Link16 signals, the message processing module includes an RS encoding module, an interleaving module, a CCSK encoding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

[0010] An analog method for Link16 signals includes the following steps:

[0011] (1) The display control terminal generates a message stream:

[0012] (1a) The display control terminal sets a fixed frame header F and Link16 signal information including a Link16 signal mode M, header information H, and message information P through a visual interface. Among them, the Link16 signal mode M adopts a basic mode or an RTT mode, and the basic mode adopts one of the STDP mode, P2SP mode, P2DP mode, and P4SP mode;

[0013] (1b) The display control terminal performs an AND calculation on the Link16 signal information, and splices the fixed frame header F, the Link16 signal information, and the check bit C obtained from the AND calculation into a message stream Message:

[0014] Message = F + M + H + P + C

[0015] H = Slot + TI + TN + DP + SDU

[0016] C = F & M & H & P

[0017] Among them, Slot represents the time slot type, TI represents the transmission indicator, TN represents the track number, DP represents the synchronization word, SDU represents the serial number of the secure data unit, and & represents the AND calculation;

[0018] (2) The message parsing module and the message recognition module respectively parse and recognize the message stream:

[0019] The message parsing module adds the Link16 signal mode M in the message stream Message to the header message H in the form of a label to form a labeled header message and the message message and will and respectively store in the form of vectors to obtain a header vector and a message vector Then will and The data vector formed is transmitted to an input port of the multiplexer module; at the same time, the message recognition module determines whether the Link16 signal pattern M in the message stream Message is the RTT mode. If so, an enable signal En1 with a state of 1 is generated, otherwise, an enable signal En0 with a state of 0 is generated, and En0 or En1 is transmitted to another input port of the multiplexer module;

[0020] (3) The multiplexer module selects and outputs the data vector from different ports according to the enable signal:

[0021] The multiplexer module determines whether the received enable signal is En0. If so, the received data vector is output through the port connected to the intermediate frequency signal generation link unit in the basic mode, and step (4) is executed. Otherwise, the received data vector is output through the port connected to the intermediate frequency signal generation link unit in the RTT mode, and step (5) is executed;

[0022] (4) The intermediate frequency signal generation link unit in the basic mode generates the Link16 intermediate frequency signal:

[0023] The intermediate frequency signal generation link unit in the basic mode generates the Link16 intermediate frequency signal sig through the received data vector IF and executes step (6);

[0024] (5) The intermediate frequency signal generation link unit in the RTT mode generates the Link16 intermediate frequency signal:

[0025] The intermediate frequency signal generation link unit in the RTT mode generates the RTT mode Link16 intermediate frequency signal sig through the received data vector RIF and executes step (6);

[0026] (6) The software radio device obtains the analog result of the Link16 signal:

[0027] The software radio device performs spectral translation on the received Link16 intermediate frequency signal sig IF or sig RIF , performs digital-to-analog conversion on the radio frequency signal after spectral translation, and then filters the Link16 analog signal obtained by digital-to-analog conversion to obtain the Link16 radio frequency signal sig RF .

[0028] Compared with the prior art, the present invention has the following advantages:​

[0029] 1. In the display control terminal of the Link16 signal simulation system of the present invention, a message parsing module and a message recognition module arranged in parallel are loaded between the display control terminal and the multiplexer module. They can parse and recognize configuration information in the form of a message stream containing a check bit, and perform data verification on the check bit when receiving the configuration information, avoiding the impact of directly receiving the configuration information on the reliability of the Link16 signal in the prior art, and effectively improving the reliability of generating the Link16 signal.

[0030] 2. In the Link16 signal simulation system of the present invention, a header processing module and a message processing module arranged in parallel process the synchronization word and header information in the form of a vector through the header processing module, and process the message information in the form of a vector through the message processing module, avoiding the impact of sequential processing of the synchronization word, header information, and message information in the form of a data stream on the data and signal processing speed in the prior art, and effectively improving the real-time performance of the Link16 signal.

[0031] 3. In the Link16 signal simulation method of the present invention, CRC error detection coding, RS coding, interleaving processing, CCSK coding, MSK modulation, pulse modulation, and frequency hopping processing add a sequence identification code to the input vector, and the transmission protection module sequentially generates a transmission protection section based on the sequence identification code and adds it to the message data and then outputs it, enabling the receiving party to parse the Link16 signal according to the sequence of the sequence identification code in the transmission protection section, avoiding the impact of using fixed-byte filling as the transmission protection section on the reliability of the Link16 signal in the prior art, and effectively improving the reliability of generating the Link16 signal. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of the Link16 signal simulation system of the present invention.

[0033] Figure 2 It is a schematic structural diagram of the intermediate frequency signal generation link unit in the basic mode of the present invention.

[0034] Figure 3 It is a schematic structural diagram of the intermediate frequency signal generation link unit in the RTT mode of the present invention.

[0035] Figure 4 It is a schematic structural diagram of the header processing module of the present invention.

[0036] Figure 5 It is a schematic structural diagram of the message processing module of the present invention.

[0037] Figure 6 It is a flowchart of the implementation of the Link16 signal simulation method of the present invention. Detailed Embodiments

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0039] Referring to Figure 1 , a simulation system for Link16 signals includes a display control terminal, a multiplexer module, and a software radio device connected in sequence. A basic mode intermediate frequency signal generation link unit and an RTT mode intermediate frequency signal generation link unit arranged in parallel are loaded between the multiplexer module and the software radio device; a message parsing module and a message recognition module arranged in parallel are loaded between the display control terminal and the multiplexer module.

[0040] The display control terminal is used to configure Link16 signal parameters and encapsulate them into a message stream;

[0041] The message parsing module is used to perform data parsing on the message stream output by the display control terminal;

[0042] The message recognition module is used to recognize the Link16 signal mode in the message stream output by the display control terminal and generate an enabling signal;

[0043] The multiplexer module is used to output the data parsed by the message parsing module through different ports according to the enabling signal;

[0044] The basic mode intermediate frequency signal generation link unit is used to generate a basic mode Link16 intermediate frequency signal;

[0045] The RTT mode intermediate frequency signal generation link unit is used to generate an RTT mode Link16 intermediate frequency signal;

[0046] The software radio device is used to up-convert the basic mode Link16 intermediate frequency signal generated by the basic mode intermediate frequency signal generation link unit or the RTT mode Link16 intermediate frequency signal generated by the RTT mode intermediate frequency signal generation link unit into a radio frequency signal;

[0047] By separately performing verification parsing and recognition on the message stream generated by the display control terminal through the message parsing module and the message recognition module arranged in parallel, the data vector and the enabling signal are separated, simplifying the signal processing flow and improving the reliability of the signal transmission information.

[0048] Referring to Figure 2 , the basic mode intermediate frequency signal generation link unit includes a CRC error detection coding module, a data splicing module, a frequency hopping module, and a transmission protection module connected in cascade in sequence. A header processing module and a message processing module arranged in parallel are also loaded between the CRC error detection coding module and the data splicing module.

[0049] The CRC error detection coding module is used to perform CRC error detection coding on the data vector ;

[0050] The header processing module is used to perform header word processing on the header vector ;

[0051] The message processing module is used to perform message word processing on the message CRC coding vector ;

[0052] The data splicing module is used to splice the double-pulse vector output by the header processing module and the message pulse vector output by the message processing module ;

[0053] The frequency hopping module is used to perform frequency hopping processing on the combined pulse vector output by the data splicing module ;

[0054] The transmission protection module is used to add a transmission protection section to the tagged frequency hopping signal output by the frequency hopping module to complete the framing of the basic mode Link16 signal;

[0055] The header word processing and the message word processing are performed in parallel by the header processing module and the message processing module arranged in parallel, which reduces the processing complexity while improving the data processing and signal processing speeds; then the double-pulse vector and the message pulse vector are spliced by the data splicing module to obtain the combined pulse vector to realize the framing of the synchronization word, header information and message information, and then a frequency mixing is performed by the frequency hopping module to obtain a tagged frequency hopping signal with a high frequency hopping rate Finally, the Link16 signal framing is completed by the transmission protection module to obtain the Link16 intermediate frequency signal sig IF .

[0056] Refer to Figure 3 , the RTT mode intermediate frequency signal generation link unit includes a header processing module, a frequency hopping module and a transmission protection module cascaded in sequence.

[0057] The header processing module is used to perform header word processing on the header vector ;

[0058] The frequency hopping module is used to perform frequency hopping processing on the double-pulse vector output by the data splicing module ;

[0059] The transmission protection module is used to perform transmission protection on the tagged RTT mode frequency hopping signal output by the frequency hopping module Add a transmission protection section to complete the framing of Link16 signals in RTT mode;

[0060] The RTT mode only processes the synchronization word and header information, and the link is simpler compared to the link unit for generating intermediate frequency signals in the basic mode. By separating the link for generating intermediate frequency signals in the RTT mode from the link for generating intermediate frequency signals in the basic mode, the signal synthesis process is simplified, and the data processing and signal processing speeds in the RTT mode are improved.

[0061] Refer to Figure 4 , the header processing module includes a data addition module, an RS encoding module, a data addition module arranged in parallel, an interleaving module, a data splicing module, a CCSK encoding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

[0062] The data addition module is used to add the header vector and the synchronization word DP;

[0063] The RS encoding module is used to perform RS encoding on the header vector ;

[0064] The interleaving module is used to perform interleaving processing on the header word RS encoding vector output by the RS encoding module ;

[0065] The data splicing module is used to perform splicing processing on the synchronization vector output by the data addition module and the interleaved header vector output by the interleaving module ;

[0066] The CCSK encoding module is used to perform CCSK encoding and encryption processing on the synchronization header vector output by the data splicing module ;

[0067] The MSK modulation module is used to perform MSK modulation on the synchronization header word encrypted spread spectrum code vector output by the CCSK encoding module ;

[0068] The pulse modulation module is used to perform dual-pulse modulation on the synchronization header signal output by the MSK modulation module ;

[0069] Refer to Figure 5 , the message processing module includes an RS encoding module, an interleaving module, a CCSK encoding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

[0070] The RS encoding module is used to perform RS encoding on the message CRC encoding vector output by the CRC error detection encoding module ;

[0071] The interleaving module is used to perform interleaving processing on the message RS - coding vector output by the RS - coding module ;

[0072] The CCSK - coding module is used to perform CCSK coding and encryption processing on the interleaved message vector output by the interleaving module ;

[0073] The MSK - modulation module is used to perform MSK modulation on the encrypted spread - spectrum code vector of the message output by the CCSK - coding module ;

[0074] The pulse - modulation module is used to perform pulse modulation on the message signal output by the MSK - modulation module ;

[0075] Referring to Figure 6 , the method for simulating Link16 signals includes the following steps:

[0076] Step 1) The display control terminal generates a message stream:

[0077] Step 1a) The display control terminal sets configuration information through a visual interface. The configuration information consists of a fixed frame header F and Link16 signal information including a Link16 signal mode M, header information H, and message information P. Among them, the Link16 signal mode M adopts a basic mode or an RTT mode, and the basic mode adopts one of the STDP mode, P2SP mode, P2DP mode, and P4SP mode;

[0078] Step 1b) The display control terminal performs an AND calculation on the Link16 signal information, and splices the fixed frame header F, Link16 signal information, and the check bit C obtained from the AND calculation into a message stream Message:

[0079] Message = F + M + H + P + C

[0080] H = Slot + TI + TN + DP + SDU

[0081] C = F & M & H & P

[0082] where Slot represents the time - slot type, TI represents the transmission indicator, TN represents the track number, DP represents the synchronization word, SDU represents the serial number of the secure data unit, and & represents the AND calculation;

[0083] Step 2) The message parsing module and the message recognition module respectively perform parsing and recognition on the message stream

[0084] The message parsing module performs an AND operation on the fixed frame header F and the Link16 signal information in the message stream Message to obtain the received check bit C rx , and uses the received check bit C rx to check the message stream Message, and then adds the Link16 signal pattern M in the message stream Message to the header message H and the packet message P in the form of a tag to form a tagged header message and the packet message and stores them and respectively in the form of vectors to obtain the header vector and the packet vector Then and The data vector formed is transmitted to an input port of the multiplexer module; at the same time, the message recognition module determines whether the Link16 signal pattern M in the message stream Message is the RTT mode. If so, it generates an enable signal En1 with a status of 1, otherwise, it generates an enable signal En0 with a status of 0, and transmits En0 or En1 to another input port of the multiplexer module;

[0085] The message parsing module and the message recognition module perform data verification on the check bits when receiving the configuration information, avoiding the impact of directly receiving the configuration information on the reliability of the Link16 signal, and effectively improving the reliability of the Link16 signal information.

[0086] Step 3) The multiplexer module selects different ports to output the data vector according to the enable signal:

[0087] The multiplexer module determines whether the received enable signal is En0. If so, it outputs the received data vector through the port connected to the intermediate frequency signal generation link unit in the basic mode, and executes step 4), otherwise it outputs the received data vector through the port connected to the intermediate frequency signal generation link unit in the RTT mode, and executes step 5);

[0088] Step 4) The intermediate frequency signal generation link unit in the basic mode generates the Link16 intermediate frequency signal:

[0089] The intermediate frequency signal generation link unit in the basic mode generates the Link16 intermediate frequency signal sig through the received data vector IF , and the implementation steps are:

[0090] Step 4a) The CRC error detection coding module splits the received data vector into the header vector and the message vector and use the message vector and the track number TN in the header vector to form a 225-bit binary sequence vector Then and the encoding generating polynomial g crc (x)=x 12 +1 corresponding binary vector perform binary division to obtain a 15-bit parity check vector Divide the parity check vector into three groups of parity check sub-vectors with 5 bits per group and Divide the message vector into three groups of message sub-vectors with 70 bits per group and Concatenate the three groups of parity check sub-vectors and the three groups of message sub-vectors in sequence to obtain the CRC encoding vector At the same time, generate a sequence identification tag S with a status of 0 crc ; then add S crc to the CRC encoding vector to obtain the message CRC encoding vector Finally, combine the header vector and the message CRC encoding vector to form the CRC encoding data vector

[0091] The CRC error detection encoding module performs CRC error detection encoding on the binary sequence vector with vectors as the processing unit, improving the data processing speed and the real-time performance of Link16 signals; the CRC error detection encoding module adds the sequence identification tag S to the encoded CRC encoding vector crc , enabling CRC decoding based on the sequence identification tag information during signal reception and improving the reliability of Link16 signals;

[0092] Step 4b) The header processing module performs header word processing on the header vector in the received CRC encoding data vector :

[0093] Step 4b1) The data addition module clears the received CRC encoding data vector and re-adds the header vector to obtain the header vector

[0094] Step 4b2) The RS encoding module encodes the received header vector Split into 7 groups of header sub-vectors and Add 8 groups of zero vectors with the same size as the header sub-vectors in front of the 7 groups of header sub-vectors After combination, obtain the RS vector to be encoded Put into a 15-row and 5-column matrix , and then convert the data in each row from binary to decimal with the leftmost bit being the highest bit to obtain a matrix Z containing 15 decimal data H , for the matrix Z H Perform finite field conversion to obtain a Galois field vector For the Galois field vector Divide by the generating polynomial To obtain a check vector including 16 groups of sub-vectors Intercept the last 9 groups of sub-vectors to obtain the check vector of the header word Meanwhile, generate a sequence identification label S with status 1 rs ; then for S rs Add it to the header vector to obtain the header label vector For the header label vector and the check vector Form the RS encoding vector of the header word Output;

[0095] The RS encoding module performs RS encoding on the header vector with vectors as the processing unit, improving the data processing speed and the real-time performance of Link16 signals; the RS encoding module adds the sequence identification label S to the header vector rs , enabling RS decoding based on the sequence identification label information during signal reception and improving the reliability of Link16 signals;

[0096] In step 4b3), the data addition module reads the sync word DP in the RS encoding vector of the header word , clears the received RS encoding vector of the header word and adds the sync word DP to obtain the sync vector Output; meanwhile, the interleaving module sequentially stores the RS encoding vector of the header word row by row into a 4-row and 4-column interleaving matrix E 4×4 , and after all are stored, reads them out column by column to obtain the interleaved header word vector Meanwhile, generate a sequence identification label S with status 2 i ; then for S i Add it to ​Obtain an interleaved header vector Output;

[0097] The interleaving module performs interleaving processing on the header word RS-coded vector in vector units which improves the data processing speed and the real-time performance of Link16 signals; the interleaving module adds a sequence recognition tag S to the interleaved header word vector i so that the de-interleaving process can be performed according to the sequence recognition tag information during signal reception, improving the reliability of Link16 signals;

[0098] Step 4b4) The data splicing module splices the received synchronization vector and the interleaved header vector to obtain a synchronization header vector

[0099] The data splicing module splices and in vector units, improving the signal processing speed and the real-time performance of Link16 signals;

[0100] Step 4b5) The CCSK encoding module obtains the initial state of the chip vector set in advance, and cyclically shifts the synchronization header vector 5 bits at a time to calculate the corresponding chip vectors for each group Convert the chip vectors to decimal numbers and combine them to obtain a synchronization header spread spectrum code vector Then is XOR-logically operated with a pseudo-random noise of the same length to obtain a synchronization header encrypted spread spectrum code vector At the same time, a sequence recognition tag S with a state of 3 is generated ccsk ; Add S ccsk to the synchronization header encrypted spread spectrum code vector to obtain a synchronization header word encrypted spread spectrum code vector Output.

[0101] The CCSK encoding module performs CCSK encoding on the synchronization header vector in vector units, improving the data processing speed and the real-time performance of Link16 signals; the CCSK encoding module adds a sequence recognition tag S to the synchronization header encrypted spread spectrum code vector ccsk so that the CCSK decoding can be performed according to the sequence recognition tag information during signal reception, improving the reliability of Link16 signals;

[0102] Step 4b6) The MSK modulation module modulates the synchronization header word encrypted spread spectrum code vector Perform differential encoding to obtain a differential encoding vector of the synchronization header word The Obtain the odd vector of the synchronization header word through serial-to-parallel conversion And the even vector of the synchronization header word The And Are respectively multiplied by cos(πt / 2T)cos(ω s t) and sin(πt / 2T)sin(ω s t) to obtain the odd vector of the synchronization header word MSK signal And the even vector of the synchronization header word MSK signal The Subtract To obtain the synchronization header word MSK vector The Obtain the MSK signal through a band-pass filter Simultaneously generate a sequence recognition tag S with a state of 4 msk ; Add S msk To the MSK signal To obtain the synchronization header signal

[0103] The MSK modulation module uses vectors as the processing unit to encrypt and spread-spectrum code vectors of the synchronization header word Perform MSK signal modulation, which improves the data processing speed and the real-time performance of Link16 signals; the MSK modulation module adds the MSK signal Add the sequence recognition tag S msk , enabling MSK demodulation based on the sequence recognition tag information during signal reception, improving the reliability of Link16 signals;

[0104] Step 4b7) The pulse modulation module splits the synchronization header signal Into groups of 6.4 us each to obtain signals Signal ... Signal In the signal Signal ... Signal Subsequently, add signals with a state of 0 and a duration of 6.6 us in sequence to obtain Pulse L1, Pulse L2... Pulse L n ; Then repeat Pulse L1, Pulse L2... Pulse L n To obtain Pulse L1', Pulse L2'... Pulse L n ', and add Pulse L1', Pulse L2'... Pulse L n ' to Pulse L1, Pulse L2... Pulse L n In sequence to obtain the pulse vector Simultaneously generate a sequence recognition tag S with a status of 5 p ; Add S p to the pulse vector to obtain a double-pulse vector

[0105] The pulse modulation module performs double-pulse modulation on the synchronization header signal in units of vectors, which improves the signal processing speed and the real-time performance of Link16 signals; The pulse modulation module adds the sequence recognition tag S to the double-pulse vector p , enabling double-pulse demodulation based on the sequence recognition tag information during signal reception and improving the reliability of Link16 signals;

[0106] Step 4c) The message processing module performs message processing on the message CRC-encoded data vector in the message CRC-encoded vector :

[0107] Step 4c1) The RS encoding module stores the message CRC-encoded vector in the message CRC-encoded vector into a 15-row and 5-column matrix , then converts the data in each row from binary to decimal with the leftmost bit being the highest bit to obtain a matrix Z containing 15 decimal data P . Perform a finite field conversion on the matrix Z P to obtain a message word Galois field vector Divide the message word Galois field vector by the generating polynomial to obtain a message word check vector Simultaneously generate a sequence recognition tag S with a status of 1 rs ; Combine the message CRC-encoded vector with the header word check vector to obtain a vector Add S rs to the vector to obtain a message word RS-encoded vector Output;

[0108] The RS encoding module performs RS encoding on the message CRC-encoded vector in units of vectors, which improves the data processing speed and the real-time performance of Link16 signals; The RS encoding module adds the sequence recognition tag S to the vector rs , enabling RS decoding based on the sequence recognition tag information during signal reception and improving the reliability of Link16 signals;

[0109] Step 4c2) The interleaving module obtains the preset initial state of the pseudo-random sequence, and performs a 93-bit pseudo-random sequence mapping on the RS-coded vector of the message text to obtain the interleaved message text vector Meanwhile, a sequence recognition tag S with state 2 is generated i ; then S i is added to to obtain the interleaved message vector for output;

[0110] The interleaving module performs interleaving processing on the RS-coded vector of the message text in units of vectors, which improves the data processing speed and the real-time performance of the Link16 signal; the interleaving module adds the sequence recognition tag S to the interleaved message text vector i , enabling de-interleaving processing based on the sequence recognition tag information during signal reception, which improves the reliability of the Link16 signal; the interleaving modules in the header processing module and the message processing module respectively use the methods of interleaving matrix and pseudo-random code mapping for interleaving processing, which improves the anti-jamming ability of the Link system.

[0111] Step 4c3) The CCSK encoding module obtains the preset initial state of the chip vector, and cyclically shifts the interleaved message vector left by 5 bits for each group to calculate the corresponding header word chip vector for each group The header word chip vector is converted to a decimal number and combined to obtain the spread spectrum code vector Then the spread spectrum code vector is subjected to an exclusive OR logical operation with an equal-length pseudo-random noise to obtain the encrypted spread spectrum code vector Meanwhile, a sequence recognition tag S with state 3 is generated ccsk ; S ccsk is added to the encrypted spread spectrum code vector to obtain the encrypted spread spectrum code vector of the message text for output;

[0112] The CCSK encoding module performs interleaving processing on the interleaved message vector in units of vectors, which improves the data processing speed and the real-time performance of the Link16 signal; the CCSK encoding module adds the sequence recognition tag S to the encrypted spread spectrum code vector i , enabling CCSK demodulation based on the sequence recognition tag information during signal reception, which improves the reliability of the Link16 signal;

[0113] Step 4c4) The MSK modulation module performs MSK modulation on the encrypted spread spectrum code vector of the message text Differential encoding is performed to obtain the differential encoding vector of the message text The The odd vector of the message text is obtained through serial-to-parallel conversion and the even vector of the message text The and are respectively multiplied by cos(πt / 2T)cos(ω s t) and sin(πt / 2T)sin(ω s t) to obtain the odd vector of the MSK signal of the message text and the even vector of the MSK signal of the message text The is subtracted from to obtain the MSK vector of the message text The is passed through a band-pass filter to obtain the MSK signal Meanwhile, a sequence recognition tag S with a state of 4 is generated msk ; S msk is added to the MSK signal to obtain the message signal

[0114] The MSK modulation module performs MSK signal modulation on the encrypted spread-spectrum code vector of the message text with the vector as the processing unit, improving the data and signal processing speed and the real-time performance of the Link16 signal; the MSK modulation module adds the sequence recognition tag S to the MSK signal so that MSK demodulation can be performed according to the sequence recognition tag information during signal reception, improving the reliability of the Link16 signal; msk

[0115] Step 4c5) The pulse modulation module judges the Link16 signal mode M tag. When M is the P2SP mode and the P4SP mode, the message signal is split into groups of 6.4 us each to obtain signals Sig P1 , signal ... signal In the signal signal ... signal signals with a state of 0 and a duration of 6.6 us are sequentially added behind to obtain pulses P1, P2... pulse P n , and pulses P1, P2... pulse P n are combined to obtain the message pulse vector Otherwise, pulses P1, P2... pulse P n are repeated to obtain pulses P1', P2'... pulse P n ​', add pulse P1', pulse P2'... pulse P n ' to pulse P1, pulse P2... pulse P n in sequence and combine them to obtain a pulse vector At the same time, generate a sequence recognition label S with a status of 5 p ; Add S p to the pulse vector to obtain a message pulse vector

[0116] The pulse modulation module processes the message signal in units of vectors for dual-pulse modulation, which improves the signal processing speed and the real-time performance of Link16 signals; the pulse modulation module adds the sequence recognition label S to the pulse vector p , enabling pulse demodulation based on the sequence recognition label information during signal reception and improving the reliability of Link16 signals;

[0117] Step 4d) The data splicing module splices the dual-pulse vector and the message pulse vector into a combined pulse vector

[0118] The data splicing module splices the dual-pulse vector and the message pulse vector in units of vectors, which improves the signal processing speed and the real-time performance of Link16 signals;

[0119] Step 4e) The frequency hopping module judges the Link16 signal mode M label in the combined pulse vector . When M is the STDP mode and the P2DP mode, mix each of the two pulses in each dual-pulse symbol packet in the combined pulse vector with a cosine signal generated by a pseudo-random source with a frequency in the range of 3 MHz to 258 MHz and a duration of 13 us to obtain a frequency hopping signal sig with a frequency hopping rate of 79623 Hop / s Hf ; When M is the P2SP mode and the P4SP mode, mix each single-pulse symbol packet in the combined pulse vector with a cosine signal generated by a pseudo-random source with a frequency in the range of 3 MHz to 258 MHz and a duration of 26 us to obtain a frequency hopping signal sig with a frequency hopping rate of 38461.5 Hop / s Hf ; While judging the Link16 signal mode M label, generate a sequence recognition label S with a status of 6 H , and add S H to the frequency hopping signal to obtain a frequency hopping signal with a label

[0120] The frequency hopping module takes vectors as the processing unit for the combined pulse vector to perform frequency hopping processing, which improves the signal processing speed and the real-time performance of Link16 signals; the frequency hopping module adds the sequence recognition tag S to the pulse vector p , so that when receiving the signal, the de-hopping processing can be performed according to the sequence recognition tag information, improving the reliability of Link16 signals; compared with the radio frequency frequency hopping in the prior art, the frequency hopping module first performs intermediate frequency pre-hopping on the input signal and then performs secondary mixing through a software radio device, with higher accuracy of the frequency hopping result and increased reliability of generating Link16 signals.

[0121] Step 4f) The transmission protection module judges the Link16 signal mode M tag in the tagged frequency hopping signal . When M is the STDP mode or the P2SP mode, the sequence recognition codes S including S in the frequency hopping signal crc , S rs , S i , S ccsk , S msk , S p and S H are sequentially and repeatedly spliced to form a transmission protection segment F with a duration of 4.4585 milliseconds L . F L is added after to obtain the Link16 intermediate frequency signal sig IF ; when M is the P2DP mode or the P4SP mode, the sequence recognition code S is sequentially and repeatedly spliced to form a transmission protection segment F with a duration of 2.0405 milliseconds S . F S is added after to obtain the Link16 intermediate frequency signal sig IF , and step 6) is executed;

[0122] The transmission protection module reads the sequence recognition code S of the input signal, sequentially forms a transmission protection segment and adds it to the tagged frequency hopping signal and then outputs it, so that the receiver can parse the Link16 signal according to the sequence of the sequence recognition codes in the transmission protection segment, enhancing the anti-interference ability of the Link16 signal and improving the reliability of the Link16 signal;

[0123] Step 5) The RTT mode intermediate frequency signal generation link unit generates the Link16 intermediate frequency signal:

[0124] The RTT mode intermediate frequency signal generation link unit passes the received data vector Generate the Link16 intermediate frequency signal sig RIF , and the implementation steps are as follows:

[0125] Step 5a) The header processing module performs header word processing on the header vector in the received CRC-encoded data vector :

[0126] Step 5a1) The data addition module splits the received CRC-encoded data vector to obtain the header vector and the message CRC-encoded vector empties the received CRC-encoded data vector and re-adds the header vector to obtain the header vector

[0127] Step 5a2) The RS encoding module splits the received header vector into 7 groups of header sub-vectors and adds 8 groups of zero vectors with the same size as the header sub-vectors in front of the 7 groups of header sub-vectors After combination, the RS vector to be encoded is obtained Store into a 15-row and 5-column matrix , and then convert the data in each row from binary to decimal with the leftmost bit being the highest bit to obtain a matrix Z containing 15 decimal data H , perform a finite field conversion on the matrix Z H to obtain a Galois field vector Divide the Galois field vector by the generator polynomial to obtain a check vector including 16 groups of sub-vectors Take the last 9 groups of sub-vectors to obtain the check vector of the header word At the same time, generate a sequence recognition label S with a status of 1 ; then add S rs to the header vector rs to obtain the header label vector Combine the header label vector and the check vector to form the header word RS encoding vector Output;

[0128] The RS encoding module processes the header vector in units of vectors ​RS coding is performed, which improves the data processing speed and the real-time performance of Link16 signals; the RS coding module adds the sequence recognition tag S to the header vector rs , enabling RS decoding based on the sequence recognition tag information during signal reception and improving the reliability of Link16 signals;

[0129] Step 5a3) The data addition module reads the sync word DP in the header word RS coding vector , clears the received header word RS coding vector and adds the sync word DP to obtain the sync vector for output; meanwhile, the interleaving module sequentially stores the header word RS coding vector row by row into a 4-row and 4-column interleaving matrix E 4×4 , and after all are stored, reads them out column by column to obtain the interleaved header word vector Meanwhile, a sequence recognition tag S with status 2 is generated i ; then S i is added to to obtain the interleaved sync header vector for output;

[0130] The interleaving module performs interleaving processing on the header word RS coding vector in vector units, improving the data processing speed and the real-time performance of Link16 signals; the interleaving module adds the sequence recognition tag S to the interleaved header word vector i , enabling de-interleaving processing based on the sequence recognition tag information during signal reception and improving the reliability of Link16 signals;

[0131] Step 5a4) The data splicing module splices the received sync vector and the vector after interleaving processing to obtain the sync header vector

[0132] The data splicing module performs splicing on and in vector units, improving the signal processing speed and the real-time performance of Link16 signals;

[0133] Step 5a5) The CCSK coding module obtains the initial state of the chip vector set in advance, cyclically shifts the sync header vector 5 bits at a time to the left to calculate the corresponding chip vectors for each group Converts the chip vectors to decimal numbers and combines them to obtain the sync header spreading code vector Then Perform an exclusive OR logical operation with a pseudo-random noise of equal length to obtain a synchronized header encrypted spread spectrum code vector Simultaneously generate a sequence identification tag S with a status of 3 ccsk ; Add S ccsk to the synchronized header encrypted spread spectrum code vector to obtain a synchronized header word encrypted spread spectrum code vector Output;

[0134] The CCSK encoding module performs CCSK encoding on the synchronized header vector in vector units, improving the data processing speed and the real-time performance of Link16 signals; the CCSK encoding module adds the sequence identification tag S to the synchronized header encrypted spread spectrum code vector ccsk , enabling CCSK decoding based on the sequence identification tag information during signal reception and improving the reliability of Link16 signals;

[0135] Step 5a6) The MSK modulation module performs differential encoding on the synchronized header word encrypted spread spectrum code vector to obtain a synchronized header word differentially encoded vector Perform serial-to-parallel conversion to obtain a synchronized header word odd vector and a synchronized header word even vector Perform and multiply them separately with cos(πt / 2T)cos(ω s t) and sin(πt / 2T)sin(ω s t) to obtain a synchronized header word MSK signal odd vector and a synchronized header word MSK signal even vector Perform subtract to obtain a synchronized header word MSK vector Perform pass it through a band-pass filter to obtain an MSK signal Simultaneously generate a sequence identification tag S with a status of 4 msk ; Add S msk to the MSK signal to obtain a synchronized header signal

[0136] The MSK modulation module performs MSK signal modulation on the synchronized header word encrypted spread spectrum code vector in vector units, improving the data and signal processing speeds and the real-time performance of Link16 signals; the MSK modulation module adds the sequence identification tag S to the MSK signal msk, enabling MSK demodulation based on sequence recognition tag information during signal reception, improving the reliability of Link16 signals;

[0137] Step 5a7) The pulse modulation module splits the synchronization header signal into groups of 6.4 us each to obtain signals Signal …… Signal In the signal Signal …… Signal After that, signals with a state of 0 and a duration of 6.6 us are successively added to obtain Pulse L1, Pulse L2... Pulse L n ; Then Pulse L1, Pulse L2... Pulse L n are repeated to obtain Pulse L1', Pulse L2'... Pulse L n ', and Pulse L1', Pulse L2'... Pulse L n ' are successively added to Pulse L1, Pulse L2... Pulse L n to obtain a pulse vector At the same time, a sequence recognition tag S with a state of 5 is generated p ; S p is added to the pulse vector to obtain a double-pulse vector

[0138] The pulse modulation module performs double-pulse modulation on the synchronization header signal using the vector as the processing unit, improving the signal processing speed and the real-time performance of Link16 signals; The pulse modulation module adds the sequence recognition tag S to the double-pulse vector p , enabling double-pulse demodulation based on sequence recognition tag information during signal reception, improving the reliability of Link16 signals;

[0139] Step 5b) The frequency hopping module mixes each of the two pulses in each double-pulse symbol packet in the double-pulse vector with a cosine signal that is pseudo-random in the range of 3 MHz to 258 MHz and has a duration of 13 us generated by a pseudo-random source to obtain an RTT mode frequency hopping signal sig RHf with a frequency hopping rate of 79623 Hop / s; At the same time, a sequence recognition tag S with a state of 6 is generated H , and S H is added to the frequency hopping signal to obtain a tagged RTT mode frequency hopping signal

[0140] The frequency hopping module performs frequency hopping on the double-pulse vector Frequency hopping processing is performed to improve the signal processing speed and the real-time performance of Link16 signals; the frequency hopping module combines double pulse vectors to add sequence recognition tag S p , enabling the de-hopping process to be carried out according to the sequence recognition tag information during signal reception, thus improving the reliability of Link16 signals; compared with the radio frequency frequency hopping in the prior art, the input signal is pre-hopped at intermediate frequency in the frequency hopping module, with higher frequency hopping point accuracy, increasing the reliability of generating Link16 signals;

[0141] Step 5c) The transmission protection module combines the sequence recognition codes S including S crc , S rs , S i , S ccsk , S msk , S p and S H in the frequency hopping signal in sequential and repeated splicing to form a transmission protection segment F with a duration of 3.339 milliseconds R , add F R to to obtain the RTT mode Link16 intermediate frequency signal sig RIF , and execute step 6);

[0142] The transmission protection module reads the sequence recognition code S of the input signal, sequentially forms a transmission protection segment and adds it to the frequency hopping signal and then outputs it, enabling the receiver to parse the Link16 signal according to the sequence of the sequence recognition codes in the transmission protection segment, enhancing the anti-interference ability of the Link16 signal and improving the reliability of the Link16 signal;

[0143] Step 6) The software radio device obtains the simulation result of the Link16 signal:

[0144] The software radio device mixes the received Link16 intermediate frequency signal sig IF or sig RIF with a mixer having a carrier frequency of 957 MHz to complete spectrum shifting and obtain a radio frequency signal The radio frequency signal is converted from the digital domain to the analog domain through DAC for digital-to-analog conversion, and then the Link16 analog signal obtained from the digital-to-analog conversion is filtered to make the generated signal smoother, obtaining the Link16 radio frequency signal sig RF .

Claims

1. An analog system for Link16 signals, comprising a display control terminal, a multiplexer module and a software radio device connected in sequence, and a basic mode intermediate frequency signal generation link unit and an RTT mode intermediate frequency signal generation link unit arranged in parallel are loaded between the multiplexer module and the software radio device; characterized in that, A message parsing module and a message recognition module arranged in parallel are loaded between the display control terminal and the multiplexer module; the intermediate frequency signal generation link unit in the basic mode includes a CRC error detection coding module, a data splicing module, a frequency hopping module, and a transmission protection module cascaded in sequence. A header processing module and a message processing module arranged in parallel are also loaded between the CRC error detection coding module and the data splicing module; the intermediate frequency signal generation link unit in the RTT mode includes a header processing module, a frequency hopping module, and a transmission protection module cascaded in sequence.

2. The analog system of a Link16 signal according to claim 1, wherein, The header processing module includes a data addition module, an RS coding module, a data addition module and an interleaving module arranged in parallel, a data splicing module, a CCSK coding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

3. The analog system of a Link16 signal according to claim 1, characterized in that, The message processing module includes an RS coding module, an interleaving module, a CCSK coding module, an MSK modulation module, and a pulse modulation module cascaded in sequence.

4. A simulation method of the Link16 signal simulation system according to claim 1, characterized in that, It includes the following steps: (1) The display control terminal generates a message stream: (1a) The display control terminal sets a fixed frame header F and Link16 signal information including a Link16 signal mode M, header information H, and message information P through a visual interface. Among them, the Link16 signal mode M adopts the basic mode or the RTT mode, and the basic mode adopts one of the STDP mode, P2SP mode, P2DP mode, and P4SP mode; (1b) The display control terminal performs an AND calculation on the Link16 signal information, and splices the fixed frame header F, the Link16 signal information, and the check bit C obtained from the AND calculation into a message stream Message: Message = F + M + H + P + C H = Slot + TI + TN + DP + SDU C = F & M & H & P Among them, Slot represents the time slot type, TI represents the transmission indicator, TN represents the track number, DP represents the synchronization word, SDU represents the serial number of the secure data unit, and & represents the AND calculation; (2) The message parsing module and the message recognition module respectively parse and recognize the message stream: The message parsing module adds the Link16 signal pattern M in the message stream Message to the header message H and the packet message P in the form of tags to form a tagged header message and the packet message and stores them and in the form of vectors respectively to obtain a header vector and a packet vector Then, it transmits the data vector formed by and to an input port of the multiplexer module; meanwhile, the message recognition module determines whether the Link16 signal pattern M in the message stream Message is the RTT mode. If so, it generates an enable signal En1 with a status of 1, otherwise, it generates an enable signal En0 with a status of 0, and transmits En0 or En1 to another input port of the multiplexer module; (3) The multiplexer module selects different ports to output the data vector according to the enable signal: The multiplexer module determines whether the received enable signal is En0. If so, it outputs the received data vector through the port connected to the base mode intermediate frequency signal generation link unit, and executes step (4). Otherwise, it outputs the received data vector through the port connected to the RTT mode intermediate frequency signal generation link unit, and executes step (5); (4) The intermediate frequency signal generation link unit in the basic mode generates a Link16 intermediate frequency signal: The intermediate frequency signal generation link unit in the basic mode generates the Link16 intermediate frequency signal sig through the received data vector IF and performs step (6); (5) The intermediate frequency signal generation link unit in the RTT mode generates a Link16 intermediate frequency signal: The intermediate frequency signal generation link unit in the RTT mode generates the RTT mode Link16 intermediate frequency signal sig through the received data vector and executes step (6); RIF ​ (6) The software radio device obtains the analog result of the Link16 signal: The software radio device performs spectrum shifting on the received sig IF or sig RIF and performs digital-to-analog conversion on the radio frequency signal sig in the digital domain after spectrum shifting Drf and then filters the Link16 analog signal obtained through digital-to-analog conversion to obtain the Link16 radio frequency signal sig RF .

5. The simulation method according to claim 4, wherein In step (4), the intermediate frequency signal generation link unit in the basic mode generates a Link16 intermediate frequency signal sig from the received data vector IF . The implementation steps are as follows: (4a) The CRC error detection coding module splits the received data vector into a header vector and a message vector and forms a binary sequence vector by combining the track number TN in the message vector with the header vector. Then, it performs CRC error detection coding on to obtain a CRC coding vector and simultaneously generates a sequence identification tag S crc ; then it adds S crc to the CRC coding vector to obtain a message CRC coding vector Finally, it combines the header vector and the message CRC coding vector to form a CRC coding data vector ​ (4b) The header processing module performs header word processing on the header vector in the received CRC-encoded data vector The implementation steps are as follows: (4b1) The data addition module clears the CRC-encoded data vector and re-adds the header vector to obtain the header vector in and then outputs it; (4b2) The RS encoding module splits the received header vector into 7 groups of header sub-vectors and Add 8 groups of zero vectors equal in size to the header sub-vectors in front of the 7 groups of header sub-vectors to obtain the RS vector to be encoded That is Then perform RS encoding on the RS vector to be encoded to obtain a parity vector including 16 groups of sub-vectors Intercept the last 9 groups of sub-vectors to obtain the parity vector of the header word At the same time, generate a sequence recognition label S with a status of 1 rs ; Then add S rs to the header vector to obtain the header label vector Combine the header label vector and the parity vector to form the header word RS encoding vector Output;​ (4b3) The data addition module clears the received header word RS - encoded vector and adds the synchronization word DP to obtain a synchronization vector for output; meanwhile, the interleaving module performs header word interleaving processing on the header word RS - encoded vector through an interleaving matrix E 4×4 to obtain an interleaved header word vector and simultaneously generates a sequence recognition tag S i ; then add S i to to obtain an interleaved header vector for output. (4b4) The data splicing module splices the received synchronization vector and the interleaved header vector to obtain the synchronization header vector (4b5) The CCSK encoding module maps the synchronization header vector to obtain a synchronization header spreading code vector through CCSK sequence mapping Then is XOR-logically operated with a pseudo-random noise of equal length to obtain a synchronized header encrypted spreading code vector Meanwhile, a sequence identification tag S is generated ccsk ; Add S ccsk to the synchronized header encrypted spreading code vector to obtain a synchronized header word encrypted spreading code vector Output; (4b6) The MSK modulation module encrypts the synchronization header word with the spreading code vector and performs MSK modulation to obtain an MSK signal Meanwhile, a sequence recognition tag S msk is generated; S msk is added to the MSK signal to obtain a synchronization header signal (4b7) The pulse modulation module splits the synchronization header signal to obtain signals Signal Signal At signal Signal Signal After that, signals with a state of 0 and a duration of 6.6 us are sequentially added to obtain pulses L1, L2... L n ; Then, pulses L1, L2... L n are repeated to obtain pulses L1', L2'... L n ', and pulses L1', L2'... L n ' are sequentially added to pulses L1, L2... L n to obtain a pulse vector At the same time, a sequence recognition label S is generated p ; S p is added to the pulse vector to obtain a double-pulse vector (4c) The message processing module processes the message CRC encoding vector in the received CRC encoding data vector The message CRC encoding vector in for message word processing. The implementation steps are as follows: (4c1) The RS encoding module performs RS encoding on the message CRC encoding vector in the data vector to obtain a check vector and simultaneously generates a sequence recognition tag S rs ; combines the message CRC encoding vector with the check vector to obtain a vector Adds S rs to the vector to obtain the message word RS encoding vector and outputs it. (4c2) The interleaving module performs pseudo-random sequence mapping on the RS-coded vector of the message text to obtain the interleaved message text vector and simultaneously generates the sequence identification tag S i ; then add S i to to obtain the interleaved message vector for output. (4c3) The CCSK encoding module interleaves the message vector and performs CCSK sequence mapping to obtain the spread spectrum code vector Then, the spread spectrum code vector is subjected to an exclusive OR logical operation with a pseudo-random noise of equal length to obtain the encrypted spread spectrum code vector At the same time, a sequence identification tag S is generated ccsk ; S ccsk is added to the encrypted spread spectrum code vector to obtain the message encrypted spread spectrum code vector and output; (4c4) The MSK modulation module encrypts the message text with the spreading code vector and performs MSK modulation to obtain an MSK signal Meanwhile, a sequence recognition tag S is generated msk ; Add S msk to the MSK signal to obtain a message signal (4c5) The pulse modulation module determines the Link16 signal mode M tag. When M is in the P2SP mode and P4SP mode, the message signal is split to obtain signals signal signal n ≤ 186, and then signals with a status of 0 and a duration of 6.6 us are sequentially added after signal signal signal to obtain pulses P1, P2... P n , and pulses P1, P2... P n are combined to obtain the message pulse vector Otherwise, the message signal is split to obtain signals signal signal and then signals with a status of 0 and a duration of 6.6 us are sequentially added after signal signal signal to obtain pulses P1, P2... P n , and pulses P1, P2... P n are repeatedly obtained as pulses P1', P2'... P n ', and pulses P1', P2'... P n ' are sequentially added to pulses P1, P2... P n and then combined to obtain the pulse vector Meanwhile, the sequence recognition tag S p ; S p is added to the pulse vector to obtain the message pulse vector (4d) The data splicing module splices the double-pulse vector and the message pulse vector into a combined pulse vector (4e) The frequency hopping module judges the Link16 signal mode M label in the combined pulse vector . When M is in the STDP mode and P2DP mode, the two pulses in each double-pulse symbol packet in the combined pulse vector are respectively mixed with the cosine signal generated by the pseudo-random source to obtain the frequency hopping signal sig Hf ; when M is in the P2SP mode and P4SP mode, each single-pulse symbol packet in the combined pulse vector is mixed with the cosine signal generated by the pseudo-random source to obtain the frequency hopping signal sig Hf ; meanwhile, a sequence recognition label S H is generated, and S H is added to the frequency hopping signal to obtain the frequency hopping signal with label (4f) The transmission protection module judges the Link16 signal mode M tag in the tagged frequency-hopping signal . When M is in the STDP mode or the P2SP mode, the frequency-hopping signal includes the sequence identification codes S crc , S rs , S i , S ccsk , S msk , S p and S H . The sequence identification codes S are sequentially and repeatedly spliced to form the transmission protection segment F L . F L is added after to obtain the Link16 intermediate frequency signal sig IF ; when M is in the P2DP mode or the P4SP mode, the sequence identification code S is sequentially and repeatedly spliced to form the transmission protection segment F S . F S is added after to obtain the Link16 intermediate frequency signal sig IF .

6. The simulation method according to claim 4, characterized in that In step (5), the intermediate frequency signal generation link unit in the RTT mode generates the RTT mode Link16 intermediate frequency signal sig through the received data vector The implementation steps are as follows: RIF to generate the RTT mode Link16 intermediate frequency signal sig (5a) The header processing module processes the header vector in the received data vector The steps for performing header word processing on the header vector are as follows: (5a1) The data addition module clears the CRC-encoded data vector and re-adds the header vector to obtain the header vector in and then outputs it; (5a2) The RS encoding module receives the header vector Split into 7 groups of header sub-vectors and Add 8 groups of zero vectors equal in size to the header sub-vectors before the 7 groups of header sub-vectors Get the RS vector to be encoded Right now Then the RS vector to be encoded Perform RS encoding to obtain 16 groups of sub-vectors The check vector Cut the last 9 groups of sub-vectors to get the check vector of the header word At the same time, a sequence identification tag S is generated rs ; Then S rs Add in header vector , get the header label vector The header label vector Sum check vector The RS code vector of the header word Output; (5a3) The data addition module clears the received header word RS-encoded vector and adds the synchronization word DP to obtain a synchronization vector for output; meanwhile, the interleaving module interleaves the header word RS-encoded vector through an interleaving matrix E 4×4 to perform interleaving processing on the header word and obtain an interleaved header word vector and simultaneously generates a sequence recognition tag S i ; then S i is added to to obtain an interleaved synchronization header vector for output. (5a4) The data splicing module splices the received synchronization vector and the vector after interleaving processing to obtain a synchronization header vector (5a5) The CCSK coding module maps the synchronization header vector to obtain a synchronization header spreading code vector through CCSK sequence mapping Then perform an exclusive OR logical operation with a pseudo-random noise of equal length to obtain a synchronized header encrypted spreading code vector At the same time, generate a sequence identification label S ccsk ; Add S ccsk to the synchronized header encrypted spreading code vector to obtain a synchronized header word encrypted spreading code vector Output; (5a6) The MSK modulation module encrypts the synchronization header word with the spreading code vector and performs MSK modulation to obtain an MSK signal Meanwhile, a sequence identification tag S is generated msk ; Add S msk to the MSK signal to obtain a synchronization header signal (5a7) The pulse modulation module splits the synchronization header signal to obtain signals Signal Signal Among the signals Signal Signal Then, zero signals with a status of 0 are sequentially added to obtain pulses L1, L2... L n ; Then, pulses L1, L2... L n are repeated to obtain pulses L1', L2'... L n ', and pulses L1', L2'... L n ' are sequentially added to pulses L1, L2... L n to obtain a pulse vector At the same time, a sequence recognition tag S is generated p ; S p is added to the pulse vector to obtain a double-pulse vector (5b) The frequency hopping module mixes the two pulses in each double-pulse symbol packet in the double-pulse vector with the cosine signal generated by the pseudo-random source respectively to obtain the frequency hopping signal sig RHf in the RTT mode; meanwhile, a sequence recognition tag S H is generated, and S H is added to the frequency hopping signal to obtain the frequency hopping signal with tag in the RTT mode (5c) The transmission protection module splices the hopping signal including S crc , S rs , S i , S ccsk , S msk , S p and S H in sequence recognition code S in order to repeatedly splice and form the transmission protection segment F R , and add F R to to obtain the RTT mode Link16 intermediate frequency signal sig RIF .

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