Vertical metal sensing method for dc-dc converter

Abstract

The present disclosure relates to a vertical metal sensing method for a DC-DC converter. In a DC-DC converter, a layout is designed to enable connecting the converter output node to an output bump with a conductive trace, at which a load is attached as a sense resistor. The layout forces the output current to go down into a lower metallization level of an interconnect layer to reach the converter output node before the output current flows up into the conductive trace and out through the output bump. The conductive trace includes resistance pillars connected in parallel or in series between the lower metallization level and a top metallization layer of the conductive trace, the resistance of the resistance pillars being substantially greater than the resistance of the lower metallization level and the top metallization layer of the conductive trace.

Description

[0001] Cross-references to related applications

[0002] This application is a continuation-in-part of U.S. Patent Application No. 17 / 680,666, filed on February 25, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to the field of DC-DC voltage converters, and more specifically, to hardware and methods for sensing input current and output voltage / current in a switched capacitor DC-DC voltage converter. Background Technology

[0004] Now for reference Figures 1-2 The example describes a known switched-capacitor DC-DC converter 10. The DC-DC converter 10 has an input (shown as node A) connected to an input pin to receive a bus voltage VBUS. An n-channel transistor QSW has a source connected to node A, a drain connected to node B, and a gate controlled by a power control circuit 1. A current sensing circuit 2 is connected between nodes A and B, with node B connected to the PMID pin. Due to switching operation, ripple current occurs in the switched-capacitor DC-DC converter 10, and therefore the switching portion of the DC-DC converter 10 is split into two paths / phases to reduce ripple: one path from node C (connected to node B) to the output pin VOUT, and another path from node D (connected to node B) to the output pin VOUT.

[0005] More specifically, the first path includes: an n-channel transistor QCH1 having a drain connected to node C, a source connected to the CTOP SC1 pin, and a gate connected to the switch control circuit 3; an n-channel transistor QDH1 having a drain connected to the CTOP SC1 pin, a source connected to the output pin VOUT, and a gate connected to the switch control circuit 3; an n-channel transistor QCL1 having a drain connected to the output pin VOUT, a source connected to the CBOT SC1 pin, and a gate connected to the switch control circuit 5; and an n-channel transistor QDL1 having a drain connected to the CBOT SC1 pin, a source connected to ground, and a gate connected to the switch control circuit 5.

[0006] More specifically, the second path includes: an n-channel transistor QCH2 having a drain connected to node D, a source connected to the CTOP SC2 pin, and a gate connected to the switch control circuit 4; an n-channel transistor QDH2 having a drain connected to the CTOP SC2 pin, a source connected to the output pin VOUT, and a gate connected to the switch control circuit 4; an n-channel transistor QCL2 having a drain connected to the output pin VOUT, a source connected to the CBOT SC2 pin, and a gate connected to the switch control circuit 6; and an n-channel transistor QDL2 having a drain connected to the CBOT SC2 pin, a source connected to ground, and a gate connected to the switch control circuit 6.

[0007] Input current is typically measured at either node A or node B. Ideally, current measurement at node B is preferred because it also tracks the current coming from the PMID pin. However, due to physical layout constraints, node B may not be easily accessible, and therefore, the currents at nodes C and D (which are easily accessible) are measured and summed. However, despite using two paths to reduce ripple current, an undesirable amount of ripple current still exists.

[0008] These ripple current issues will now be discussed in more detail, first for single-path switched-capacitor DC-DC converters and then for dual-path switched-capacitor DC-DC converters.

[0009] refer to Figure 3 Example, Figure 3 A simple, known switched-capacitor DC-DC converter 11 is shown. The switched-capacitor DC-DC converter 11 is formed by a sensing resistor Rs connected between the input IN and a first terminal of a first switch S1, a capacitor C connected between the second terminal of the first switch S1 and ground, and a second switch S2 connected between the capacitor C and the output OUT. Figure 4 The timing diagram showing the operation of the circuit can be seen, in which ripple (amplitude spikes) can be observed in the current I_Rs flowing through the sensing resistor Rs at each instance of switch S1 being closed.

[0010] Now for reference Figure 5 Example, Figure 5A simple, known two-path switched capacitor DC-DC converter 12 is shown. The two-path switched capacitor DC-DC converter 12 is formed by: a first sensing resistor Rs1 connected between the input IN and a first terminal of a first switch S11; a first capacitor C1 connected between the second terminal of the first switch S11 and ground; and a second switch S21 connected between the capacitor C11 and the output OUT; and a second sensing resistor Rs2 connected between the input IN and a first terminal of a third switch S12; a second capacitor C2 connected between the second terminal of the third switch S12 and ground; and a fourth switch S22 connected between the second capacitor C2 and the output OUT. Figure 6 The timing diagram showing the operation of the circuit can be seen, in which ripple can be observed in the current I_Rs1 flowing through the sensing resistor Rs1 at each instance of switch S11 being closed, and ripple can be observed in the current I_Rs2 flowing through the sensing resistor Rs2 at each instance of switch S12 being closed.

[0011] Although the ripples in I_Rs1 and I_Rs2 are smaller in amplitude than the ripples in I_Rs (from... Figure 4 However, these ripple currents still exist. Therefore, current sensing technology focuses on filtering these ripple currents.

[0012] Now go to Figure 7 The example shown is a prior art current sensor 13. It is assumed here that resistors Rs1 and Rs2 are... Figure 5 The sensing resistor of the dual-path switched capacitor DC-DC converter 12 is shown, wherein the rest of the dual-path switched capacitor DC-DC converter 12 is not shown for simplicity. The current sensor 13 includes a first amplifier 14 and a second amplifier 17. The first amplifier 14 has a resistor Rs1 connected across its input terminals and provides an output to a first input of the multiplexer 16 via a low-pass filter 15, and the second amplifier 17 has a resistor Rs2 connected across its input terminals and provides an output to a second input of the multiplexer (MUX) 16 via a low-pass filter 18. Since the currents I_Rs1 and I_Rs2 are out of phase, the MUX 16 is configured to switch accordingly between allowing these currents to pass through, such that the output of the MUX 16 is actually the sum of currents I_Rs1 and I_Rs2. An analog-to-digital converter (ADC) 19 digitizes the output of the MUX 16 to produce a digital code representing the sum of the sensed currents I_Rs1 and I_Rs2.

[0013] In operation, the frequencies of currents I_Rs1 and I_Rs2 will be approximately equal to the switching frequency of the switches in the two-path switched capacitor DC-DC converter. Therefore, in order to sense the voltage across the sensing resistors Rs1 and Rs2 using ADC 19, the sampling frequency of ADC 19 will need to be significantly higher than the frequencies of currents I_Rs1 and I_Rs2 to avoid aliasing, increased cost, and complexity. Therefore, low-pass filters 15 and 18 are used to average the currents I_Rs1 and I_Rs2, thereby removing their high-frequency components and enabling the use of a slower ADC.

[0014] While this design of the current sensor 13 can produce acceptable results, note that it utilizes two amplifiers 14 and 17, two low-pass filters 15 and 18, and a MUX 19. Depending on the switching frequency of the two-path switched-capacitor DC-DC converter, these low-pass filters 15 and 18 can be relatively large. Therefore, the design of the current sensor 13 may be much larger than desired (especially if amplifiers 14 and 17 are fully differential), and thus requires further development. Summary of the Invention

[0015] This document discloses a circuit comprising: a first switching element directly electrically connected to a first node along a first conductive path; a second switching element directly electrically connected to the first node along a second conductive path; and an output bump directly electrically connected to the first node along a third conductive path.

[0016] The third conductive path includes: a first continuous conductive stack extending along the first and second conductive paths and directly electrically connected between the first and second switching elements; a first disconnected conductive stack portion directly electrically connected to the first switching element and extending toward but not reaching the first node; wherein the first disconnected conductive stack portion is carried by and electrically connected to the first continuous conductive stack; a second disconnected conductive stack portion directly electrically connected to the second switching element and extending toward but not reaching the first node, such that the first and second disconnected conductive stack portions are separated by a notch; wherein the second disconnected conductive stack portion is carried by and electrically connected to the first continuous conductive stack; a central conductive stack portion directly electrically connected between the first node and the output bump, the central conductive stack portion being partially carried by and electrically connected to the first continuous conductive stack within the notch; and a second conductive stack extending between the first continuous conductive stack at the first node and the output bump, the second conductive stack being electrically connected to the first continuous conductive stack; wherein the central conductive stack portion is also partially carried by and electrically connected to the second conductive stack within the notch.

[0017] The second conductive stack can be a second continuous conductive stack.

[0018] The central conductive stack may be formed of: a plurality of resistor pillars spaced apart from each other along a third conductive path between the first node and the output bump, each resistor pillar being carried by and in electrical contact with a second continuous conductive stack; and a continuous metal sheet carried by and in electrical contact with the plurality of resistor pillars, the continuous metal sheet extending along the third conductive path between the first node and the output bump; wherein the resistance of the resistor pillars among the plurality of resistor pillars is substantially greater than the resistance of the second continuous conductive stack.

[0019] Each of the multiple resistor pillars may be formed by a first conductive sheet and a second conductive sheet. The first conductive sheet is carried by and electrically connected to a second continuous conductive stack, and the second conductive sheet is carried by and electrically connected to the first conductive sheet. The second conductive sheet extends between the first conductive sheet and the continuous metal sheet, such that current flows from the second continuous conductive stack into the first conductive sheet and through the second conductive sheet into the continuous metal sheet.

[0020] The first conductive sheet can be carried on top of the first via layer, which is sandwiched between the first conductive sheet and the second continuous conductive stack, and the first via layer electrically connects the second continuous conductive stack to the first conductive sheet.

[0021] The second conductive sheet can be carried on top of the second via layer, which is sandwiched between the second conductive sheet and the first conductive sheet, and the second via layer electrically connects the first conductive sheet to the second conductive sheet.

[0022] The continuous metal sheet can be supported on top of the third via layer, which is sandwiched between the continuous metal sheet and the second conductive sheet, and the third via layer electrically connects the second conductive sheet to the continuous metal sheet.

[0023] The central conductive stack may be formed of: a resistor column stack extending along a third conductive path between the first node and the output bump, the resistor column stack being carried and electrically contacted by a second continuous conductive stack; and a continuous metal sheet being carried and electrically contacted by the resistor column stack, the continuous metal sheet extending along the third conductive path between the first node and the output bump; wherein the resistance of the resistor column among the plurality of resistor columns is substantially greater than the resistance of the second continuous conductive stack in the direction from the second continuous conductive stack to the continuous metal sheet.

[0024] The resistor stack can be formed from the following: a first continuous conductive sheet carried and electrically connected to a second continuous conductive stack, the first continuous conductive sheet extending along a third conductive path between a first node and an output bump; a second continuous conductive sheet carried and electrically connected to the first continuous conductive sheet, the second continuous conductive sheet extending along the third conductive path between the first node and the output bump; and a second continuous conductive sheet extending between the first continuous conductive sheet and a continuous metal sheet, such that current flows from the second continuous conductive stack into the first continuous conductive sheet and through the second continuous conductive sheet into the continuous conductive sheet.

[0025] This document also discloses a current sensor comprising: a sensing resistor coupled between a first terminal and a second terminal; and an amplifier circuit. The amplifier circuit comprises: an amplifier having an input coupled to the first terminal and the second terminal and an output, generating a voltage representing the input at the output; a first resistor coupled to at least one of the inputs of the amplifier; and a second resistor coupled to at least one of the inputs of the amplifier.

[0026] The gain of the amplifier circuit is based on the resistance of the second resistor and the ratio of the resistance of the sensing resistor to the resistance of the first resistor. The first resistor and the sensing resistor are arranged in a ratioistic relationship, and the first resistor and the sensing resistor change temperature substantially equally during operation, such that the resistance of the first resistor and the sensing resistor changes substantially equally with temperature.

[0027] The sensing resistor includes: a plurality of resistive pillars spaced apart from each other along a conductive path between a first terminal and a second terminal, wherein a first resistive pillar is directly electrically connected to the first terminal and a last resistive pillar is directly electrically connected to the second terminal; a plurality of conductive stacks spaced apart from each other along the conductive path between the first terminal and the second terminal, wherein a first conductive stack carries and is in direct electrical contact with a first resistive pillar, a last conductive stack carries and is in direct electrical contact with a last resistive pillar, and each conductive stack carries and is in direct electrical contact with two adjacent resistive pillars; and a continuous metal sheet carried and in contact with the plurality of resistive pillars, the continuous metal sheet extending along the conductive path between the first terminal and the second terminal; wherein the resistance of the resistive pillars is substantially greater than the resistance of the conductive stacks.

[0028] Each of the plurality of resistor pillars may be formed by a first conductive sheet and a second conductive sheet, the first conductive sheet being carried by and electrically connected to its associated conductive stack, the second conductive sheet being carried by and electrically connected to the first conductive sheet, the second conductive sheet extending between the first conductive sheet and a continuous metal sheet, such that current flows from the associated conductive stack into the first conductive sheet and through the second conductive sheet into the continuous metal sheet. Attached Figure Description

[0029] Figure 1 This is a schematic block diagram of a known switched-capacitor DC-DC converter that includes current sensing;

[0030] Figure 2 yes Figure 1 A graphical representation of the current flow direction in a switched capacitor DC-DC converter;

[0031] Figure 3 This is a schematic diagram of a known single-path switched capacitor DC-DC converter;

[0032] Figure 4 It is shown Figure 3 Timing diagram of the operation of the switched capacitor DC-DC converter during operation;

[0033] Figure 5 This is a schematic diagram of a known two-path switched capacitor DC-DC converter;

[0034] Figure 6 It is shown Figure 5 Timing diagram of the operation of the switched capacitor DC-DC converter during operation;

[0035] Figure 7 It is used for, for example Figure 5 A schematic block diagram of a known current sensor for a dual-path switched capacitor DC-DC converter;

[0036] Figure 8 This illustrates the use of the methods described in this article, such as Figure 5 A diagram illustrating the desired operating principle of a current sensor in a dual-path switched capacitor DC-DC converter.

[0037] Figure 9 This is what is publicly disclosed in this article for use in, for example Figure 5 A schematic block diagram of a current sensor in a dual-path switched capacitor DC-DC converter;

[0038] Figure 10 This indicates during operation Figure 9 The curves of the total current and voltage waveforms within the current sensor;

[0039] Figure 11This indicates during operation Figure 9 A greatly magnified portion of the current and voltage waveforms within the current sensor.

[0040] Figure 12 This is implemented in an example two-path switched capacitor DC-DC converter. Figure 9 A schematic block diagram of a current sensor;

[0041] Figure 13 This is a schematic block diagram of a current sensor disclosed herein, such as one that can be used to sense the current through a sensing resistor;

[0042] Figure 14 This is a schematic block diagram of another current sensor disclosed herein, such as one that can be used to sense the current passing through a sensing resistor;

[0043] Figure 15 It is shown Figure 14 The timing diagram of the switching of the current sensor during operation;

[0044] Figure 16 It is shown Figure 14 A top plan view of the on-silicon formation of resistors R1 and Rs of the current sensor;

[0045] Figure 17 yes Figure 16 Cross-sectional view along the YY and ZZ lines of the first possible configuration of the basic resistor units R1 and Rs shown;

[0046] Figure 18 yes Figure 16 Cross-sectional view along the YY and ZZ lines of the second possible configuration of the basic resistor units R1 and Rs shown;

[0047] Figure 19 yes Figure 16 Cross-sectional view along lines YY and ZZ of the third possible configuration of the basic resistor units R1 and Rs shown.

[0048] Figure 20 It shows when using Figure 19 Configuration Figure 15 A magnified top view of the current sensor resistors R1 and Rs formed on silicon.

[0049] Figure 21 This is a schematic diagram of a configurable voltage / current sensor disclosed in this article, which can be used to sense battery voltage, high-side battery current and low-side battery current, as well as its connection to the entire wireless charging system.

[0050] Figure 22AThis indicates when sensing battery voltage Figure 21 Timing diagram of the switching and differential input voltage of the configurable voltage / current sensor;

[0051] Figure 22B This indicates that when sensing the high-side battery current... Figure 21 Timing diagram of the switching and differential input voltage of the configurable voltage / current sensor;

[0052] Figure 22C This indicates that when sensing the low-side battery current... Figure 21 Timing diagram of the switching and differential input voltage of the configurable voltage / current sensor;

[0053] Figure 23 This is a schematic diagram of a second embodiment of the configurable voltage / current sensor disclosed herein, which may be used to sense battery voltage, high-side battery current and low-side battery current, as well as its connection to the entire wireless charging system.

[0054] Figure 24 This is a schematic diagram of a third embodiment of the configurable voltage / current sensor disclosed herein, which can be used to sense battery voltage, high-side battery current, and low-side battery current, as well as its connection to the overall wireless charging system; and

[0055] Figure 25 This is what is disclosed in this article and Figure 1 A similar schematic diagram shows a configurable voltage / current sensor, which can be used to sense battery voltage, high-side battery current, and low-side battery current, as well as its connection to the entire wireless charging system that also performs power current sensing.

[0056] Figure 26A This is a schematic block diagram of the switching converter described herein, which includes discrete resistors RA, RB, and Rs for sensing the output current.

[0057] Figure 26B This is a schematic block diagram of the switching converter described herein, which includes a discrete resistor Rs for sensing the output current.

[0058] Figure 27 This shows the use of resistors RA and RB. Figure 26A The diagram shows the controlled current sensing performed by the switching converter.

[0059] Figure 28 This shows the use of resistor Rs to... Figure 26B The diagram shows the uncontrolled current sensing performed by the switching converter.

[0060] Figure 29This is a schematic block diagram of the switch converter described herein, which includes a resistor Rs formed by a conductive path from node N2 to output bump BB for sensing output current.

[0061] Figure 30 It is from node N2 to the output bump BB. Figure 29 A schematic perspective view of the layout of the conductive paths.

[0062] Figure 31 It is from node N2 to the output bump BB. Figure 29 A schematic side view of the layout of the conductive paths.

[0063] Figure 32 This is in an embodiment where the conductive pillars are connected in parallel. Figure 29 Cross-sectional view of two conductive pillars in the conductive path.

[0064] Figure 33 This is in an embodiment where the conductive pillars are connected in series. Figure 29 Cross-sectional view of two conductive pillars in the conductive path.

[0065] Figure 34 It is from node N2 to the output bump BB. Figure 29 A schematic perspective view of an alternative layout for the conductive path.

[0066] Figure 35 This is in an embodiment where the conductive pillars are connected in parallel. Figure 34 Cross-sectional view of two conductive pillars in the conductive path. Detailed Implementation

[0067] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to other embodiments and applications besides those described in detail above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features disclosed or suggested herein. Note that in the following description, unless stated to the contrary, any of the above-described resistors or resistors are discrete devices, and not merely electrical leads between two points. Therefore, any of the above-described resistors or resistors coupled between two points has a greater resistance than a lead between those two points, and such a resistor or resistor cannot be interpreted as a lead. Similarly, unless stated to the contrary, any of the above-described capacitors or capacitors are discrete devices, and unless stated to the contrary, any of the above-described capacitors or capacitors are not parasitic devices. Furthermore, unless stated to the contrary, any of the above-described inductors or capacitors are discrete devices, and unless stated to the contrary, any of the above-described inductors or capacitors are not parasitic devices.

[0068] Now for reference Figure 8 ,remember Figure 5 The dual-path switched capacitor DC-DC converter 12 has a current sensor that aims to sense the current I_Rs1 flowing through sensing resistor Rs1 and the current I_Rs2 flowing through sensing resistor Rs2, and then sums I_Rs1 and I_Rs2 to generate an output current I_Out, which represents the input current to the dual-path switched capacitor DC-DC converter 12.

[0069] Now for reference Figure 9 A current sensor 20 performing this function is described. The current sensor 20 includes a first amplifier 21 and a second amplifier 22. The input of the first amplifier 21 is connected across a sensing resistor Rs1, and the input of the second amplifier 22 is connected across a sensing resistor Rs2. The outputs of amplifiers 21 and 22 are connected to the input of a summing amplifier 23.

[0070] The summing amplifier 23 includes a first resistor R1 connected between the output of amplifier 21 and node N1, and a second resistor R2 connected between the output of amplifier 22 and node N1. The non-inverting terminal of the third amplifier 24 (e.g., an operational amplifier) ​​is connected to node N1, and its inverting terminal is connected to node N2. A third resistor R3 is connected between node N1 and the output of the third amplifier 24, and a fourth resistor R4 is connected between node N2 and the output of the third amplifier 24. A fifth resistor R5 is connected between node N2 and ground.

[0071] The low-pass filter 25 filters the output of the summing amplifier 23.

[0072] In operation, amplifier 21 outputs a voltage Vamp1 indicating the current I_Rs1 through sensing resistor Rs1, and amplifier 22 outputs a voltage Vamp2 indicating the current I_Rs2 through sensing resistor Rs2. Summing amplifier 23 sums the voltages across sensing resistors Rs1 and Rs2 to produce a voltage VOpamp as output, which is filtered by low-pass filter 25. Low-pass filter 25 provides an output Vlpf, which can be read, and from the output Vlpf, the input current of the dual-path switched-capacitor DC-DC converter 12 can be determined.

[0073] The summation performed by summing amplifier 23 results in a ripple frequency in the output signal Vlpf that is twice the switching frequency of the dual-path switched capacitor DC-DC converter 12. Consequently, the cutoff frequency of the low-pass filter 25 is doubled, resulting in a reduction in the resistance and capacitance of the resistors and capacitors within the low-pass filter 25, thereby halving the physical size of the resistors and capacitors. Therefore, with Figure 7Compared to the current sensor 13, the low-pass filter 25 of the current sensor 20 occupies only one-quarter of the physical area (because there is one low-pass filter instead of two, and because the resistor and capacitor area of ​​this single low-pass filter is half the resistor and capacitor area of ​​any one of the low-pass filters in the current sensor 13). This significantly reduces the total area consumed by the current sensor 20 compared to the prior art current sensor 13, which is advantageous in many applications where space savings are required.

[0074] exist Figures 10-11 The waveform showing the operation of the current sensor 20 can be seen in the image. The complete waveform can be viewed in... Figure 10 The waveform that can be seen, and greatly magnified, can be seen in [the image / image]. Figure 11 I saw it in the middle.

[0075] Figure 12 An example embodiment of a current sensor 20 for detecting the input current I_in from power supply 19 to a two-path switched-capacitor DC-DC converter 12 is shown. Note that a single input node IN of the two-path switched-capacitor DC-DC converter 12 receives the input current I_IN, which is split into two paths and fed to a switching block 27 containing switched-capacitor circuits SC1 and SC2, and the outputs of switched-capacitor circuits SC1 and SC2 are combined at the output node OUT to power a load 18 such as a voltage regulator. A sensing resistor Rs1 is connected between the input node IN and the switched-capacitor circuit SC1, and a sensing resistor Rs2 is connected between the input node IN and the switched-capacitor circuit SC2.

[0076] As those skilled in the art will understand, power supply 19 includes a rectifier bridge formed by diodes D1-D4, which rectifies the current induced in coil L and charges energy storage capacitor Ct by means of a time-varying signal.

[0077] As those skilled in the art will also understand, the sensing resistors Rs1 and Rs2 can be external discrete resistors or on-chip resistors positioned spaced apart from the resistors R1-R5 of the current sensor 20. It is known that the resistance of a resistor varies with temperature. Therefore, the resistance changes of the sensing resistors Rs1 and Rs2 during operation will differ from the resistance changes of the resistors R1-R5 because they will be exposed to different temperatures, especially if the sensing resistors Rs1 and Rs2 are external resistors. This can reduce the accuracy of the current sensor 20. Typically, to overcome this, the resistors R1-R5 can be precisely matched and / or precisely fine-tuned to help provide accurate known gain from the operational amplifier 24.

[0078] This can be expensive and increases production time, especially when Rs1 and Rs2 are off-chip resistors, as any compensation is performed at the module level after the chip has been assembled in its environment. Therefore, further progress has been made, which will now be discussed. To address this issue, the resistors can be on-chip resistors and can be arranged together in a ratiometric layout on a single integrated circuit substrate, such that one or more selected resistors among the resistors R1-R5 of the current sensor 20, as well as the sensing resistors Rs1 and Rs2, change equally with temperature, while one or more other resistors among R1-R5 are designed to have a near-zero temperature coefficient and not change too much with temperature, and precise matching of the resistors among R1-R5 is not performed. In fact, this concept can be applied to any current sensing application and is not limited to current sensing within switched-capacitor DC-DC converters.

[0079] For ease of explanation, let's first consider including Figure 13 The following is a simplified example of the circuitry for the current sensor 30. Here, power supply 19 provides input current to a switched-capacitor DC / DC converter 12, which includes an input sensing resistor Rs and a switched-capacitor circuit SC. The input current (labeled I_Rs) flows through the input sensing resistor Rs, and the converter 12 then supplies power to the load. The sensing resistor Rs is connected between nodes N1 and N2. The current sensor 30 senses the current I_Rs and generates an output voltage VOUT indicating the current I_Rs. The current sensor 30 includes an operational amplifier 31, which has a non-inverting terminal connected to node N1 via resistor R1, and a resistor R2 connected between the non-inverting terminal and ground. The operational amplifier 31 also has an inverting terminal connected to node N2 via resistor R3, and a resistor R4 connected between the inverting terminal and the output of the operational amplifier 31.

[0080] The sensing resistor Rs is located outside the current sensing circuit 30. Therefore, the resistance of the sensing resistor Rs, as well as the resistances of resistors R1 and R2 in the current sensor 30, changes differently with temperature, thus reducing the accuracy of the output voltage VOUT. To address this issue, resistors R1, R2, R3, and R4 are matched (e.g., via fine-tuning) to help ensure accurate gain, where the temperature variation of the sensing resistor Rs remains uncompensated. As previously mentioned, this can be costly and increases production time, and is therefore undesirable. Other known methods of addressing this problem are also undesirable.

[0081] Now for reference Figure 14An embodiment of a current sensor 40 is described, which addresses these issues by utilizing a ratiometric layout of its resistors. First, the current sensor 40 will be described, and then the specific substrate-level layout details of the resistors will be described.

[0082] A current sensor 40 receives an input current I_Rsense from a power supply 19 (e.g., a rectifier bridge), wherein the current sensor is connected to the power supply 19 at node N1. A sensing resistor Rsense (e.g., 4mΩ) is connected between node N1 and node N2. A regulator 43 receives an input from node N2 and provides an output to load 18.

[0083] Chopper 41 is coupled between nodes N1 / N2 and nodes N3 / N4. Chopper 41 includes a switch S1a connected between nodes N2 and N4 and a switch S1b connected between nodes N2 and N3. Chopper 41 also includes a switch S2a connected between nodes N1 and N4 and a switch S2b connected between nodes N1 and N3.

[0084] Current source I1 is connected between nodes N3 and N5 and is arranged to sink current from node N3 and source current to node N5. The source of the high-voltage p-channel transistor MP1 is connected to node N5, its drain is connected to node N7, and its gate is connected to the collector of the PNP transistor Q1. Current source I3 is connected between node N7 and ground, wherein current source I3 sinks current from node N7 and sources current to ground. The collector of the PNP transistor Q1 is also connected to current source I5, which sinks current from the collector of Q1 and sources current to ground. The emitter of the PNP transistor Q1 is connected to node N3, and the base of the PNP transistor Q1 is connected to node N5.

[0085] Current source I2 is connected between nodes N4 and N6, and is arranged to draw current from node N4 and supply current to node N6. The source of the high-voltage p-channel transistor MP2 is connected to node N6, its drain is connected to node N8, and its gate is connected to the collector of PNP transistor Q2. Current source I4 is connected between node N8 and ground, wherein current source I4 draws current from node N8 and supplies current to ground. The collector of PNP transistor Q2 is also connected to current source I6, which draws current from the collector of Q2 and supplies current to ground. The emitter of PNP transistor Q2 is connected to node N4, and the base of PNP transistor Q2 is connected to node N6.

[0086] Resistor R1 (e.g., 2kΩ) is connected between node N5 and node N6.

[0087] The non-inverting terminal of differential amplifier 41 is connected to node N8, and its inverting terminal is connected to node N7. Resistor R2 (e.g., 50kΩ) is connected between node N8 and the first output of amplifier 41, and resistor R2b (e.g., 50kΩ) is connected between node N7 and the second output of amplifier 41. Switch S9a is connected between node N8 and the first output of amplifier 41, and switch S9b is connected between node N7 and the second output of amplifier 41. The outputs of amplifier 41 are also differential, wherein a first output voltage VoutP is generated at the first output and a second output voltage VoutN is generated at the second output. Analog-to-digital converter 42 digitizes the differential signal represented by VoutP and VoutN.

[0088] In operation, the voltage across Rsense generated by the input current I_Rsense across resistor R1 is reproduced, where high-voltage transistors MP1 and MP2 perform level shifting, and the differential current representing the input current I_Rense is output from the drain of transistors MP1 and MP2 to amplifier 41, which converts the differential current into a differential voltage represented by VoutP and VoutN.

[0089] Figure 15 The switching sequence of chopper 41 is shown. At the beginning of each cycle, as shown, switches S1a and S1b, as well as S9a and S9b, are closed, while switches S2a and S2b are open to automatically zero amplifier 41. Thereafter, alternating switching of S1a / S2a and S1b / S2b is performed at the ADC sampling rate, where S1a / S2b are out of phase with each other at any given time, and S1b / S2a are out of phase with each other at any given time.

[0090] The gain of the current sensor 40 can be calculated as follows:

[0091]

[0092] Note that if the change in resistance R1 with temperature is equal to the change in resistance Rsense with temperature, these changes will cancel each other out. Therefore, it is desirable for R1 and Rsense to track each other with temperature. Furthermore, it is observed that the gain is affected by the change in R2, so R2 is designed to have a thermal constant as close to zero as possible (e.g., R2 is a poly-resistor) so that the gain of the current sensor 40 can be tuned by adjusting R2. One way to achieve a zero thermal constant is to divide R2 into two resistors made of materials with opposite temperature coefficients (e.g., divided into resistor R2_1 with a temperature coefficient of +1% and resistor R2_2 with a temperature coefficient of -1%). As an alternative to using resistor R2, a 1 / sC switched capacitor can be used, which has an extremely low temperature dependence dominated by C and can use a stable switching frequency.

[0093] Figure 16 The diagram shows a top plan view of resistors R1 and Rs formed on an integrated circuit substrate 40. Rs is formed by multiple "elementary" resistor structures connected in parallel, while R1 is formed by multiple "elementary" resistor structures connected in series. The basic resistor structures are multilayered, and as shown in... Figure 16 As can be observed, the basic resistor structure forming the sensing resistor Rs is surrounded on both sides by the basic resistor structure forming the resistor R1, such that Rs and R1 will heat and cool to substantially the same temperature at substantially the same rate during operation.

[0094] exist Figure 17 The first possible implementation shown in the cross-section (which is) Figure 16 In the top plan view (cross-sectional view along the YY and ZZ lines), the basic resistor structures 41 and 43 forming R1 and Rs can be implemented by parallel metal sheets, wherein the length L_Rs of the metal sheet used to form the Rs stack structure is generally equal to the length L_R1 of the metal sheet used to form the R1 stack structure, and it is assumed that the width W_Rs of the metal sheet used to form the Rs stack structure is generally equal to the width W_R1 of the metal sheet used to form the R1 stack structure. Note that the resistance of the vias connecting the corresponding metal sheets of R1 and Rs is small but not negligible compared to the resistance of the metal sheets (e.g., a few percent of the resistance of the metal sheets), wherein the number of vias connecting the corresponding metal sheets of R1 and Rs is equal or as equal as possible.

[0095] To form the basic resistor structure 41 for forming the sensing resistor Rs, such as Figure 17As shown, parallel metal sheets M1, M2, and M3 of equal length, width, and thickness are connected to each other (parallel electrical connection) through vias. Metal sheet M1 is connected to metal sheet M2 on its opposite side through via v1, and metal sheet M2 is connected to metal sheet M3 on its opposite side through via v2. In the basic resistor structure 41 not located on the outer or inner circumference (the inner circumference is where resistor structure 41 of resistor R1 faces resistor structure Rs), terminals are formed by a pair of metal sheets M4 and connected to the opposite ends of metal sheet M3 through via v3. These terminals M4 are also connected to the metal sheet M3 of the adjacent resistor structure 41 through via v3. When the basic resistor structure 41 is located on the inner or outer circumference, it lacks metal sheet M4 and via v3 on the side facing the inner circumference.

[0096] The resistance obtained by resistor Rs is:

[0097]

[0098] The desired number of such basic resistor structures 41 are connected in parallel to produce the desired resistance R1.

[0099] To form the basic resistor structure 43 used to form resistor R1, such as Figure 17 As shown, parallel metal sheets M1, M2, and M3 are connected to each other via vias (series electrical connection). Here, metal sheets M2 and M3 are each divided into two parts; for ease of reading, this is referred to as... Figure 17 The left and right pieces are referred to as the left and right pieces, respectively. The left pieces of M2 and M3 have the same length, width, and thickness, as do the right pieces of M2 and M3. Metal sheet M1 is a single, single metal sheet whose length is negligibly greater than the combined length of the left and right pieces M2 and M3. Metal sheet M1 is connected to the left piece M2 at one end via via v1 and to the right piece M2 at the other end via via v1. The left piece M2 is connected to the left piece M3 via via v2, with via v2 and via v1 located on opposite sides of M2. The left piece M3 is connected to the left piece M4 via via v3, with via v3 and via v2 located on opposite sides of M3. The right piece M2 is connected to the right piece M3 via via v2, and the right piece M3 is connected to the right piece M4 via via v3.

[0100] The resistance obtained by resistor R1 is:

[0101] R1 = R M1 +R M2 +R M3

[0102] The desired number of such basic resistor structures 43 are connected in series to produce the desired resistance of RS.

[0103] Figure 17 The proposed structure is advantageous for designing very low Rs and high R1 values ​​within a small silicon area because it benefits from the parallelism of metals M1, M2, and M3 in Rs and the serialization of M1, M2, and M3 in R1. However, it can also be observed in structure 41 that, assuming termination in metal M4, the current circulating from node A to node B within the basic Rs may not be uniformly distributed across M3, M2, and M1 due to vias v2 and v1 along the path. With the construction of the serial structure R1, a uniform current flows through M1, M2, and M3. Therefore, since a portion of the contribution of M1, M2, and M3 is uniform in R1, while the contributions of M1 and M2 are smaller than in Rs, resulting in a relatively high contribution of M3, Rs and R1 may suffer from undesirable matching. Since the behavior of the three metal layers M1, M2, and M3 may differ, therefore... Figure 17 The proposed structure is not optimized for temperature effects, but it presents a good compromise for smaller areas.

[0104] exist Figure 18 The second possible implementation shown in the cross-section (which is also) Figure 16 In the top view of the cross-section along the YY and ZZ lines, the basic resistor structures 41 and 43 that form Rs and R1 can have the same structure, wherein the resistance difference between R1 and Rs depends on how many basic resistor structures 41 and 43 are used to form each resistor.

[0105] Here, in order to form the basic resistor structure 43 for forming resistor R1, as follows: Figure 18 As shown, parallel metal sheets M1, M2, and M3 are connected to each other via vias (series electrical connection). Here, metal sheets M2 and M3 are each divided into two parts; for ease of reading, this is referred to as... Figure 18The left and right pieces are referred to as the left and right pieces, respectively. The left pieces of M2 and M3 have the same length, width, and thickness, as do the right pieces of M2 and M3. Metal sheet M1 is a single, single metal sheet whose length is negligibly greater than the combined length of the left and right pieces M2 and M3. Metal sheet M1 is connected to the left piece M2 at one end via via v1 and to the right piece M2 at the other end via via v1. The left piece M2 is connected to the left piece M3 via via v2, with via v2 and via v1 located on opposite sides of M2. The left piece M3 is connected to the left piece M4 via via v3, with via v3 and via v2 located on opposite sides of M3. The right piece M2 is connected to the right piece M3 via via v2, and the right piece M3 is connected to the right piece M4 via via v3.

[0106] The resistance obtained by resistor R1 is:

[0107] R1 = R M1 +R M2 +R M3

[0108] To form the basic resistor structure 41 used to form resistor Rs, such as Figure 18 As shown, parallel metal sheets M1, M2, and M3 are connected to each other via vias (series electrical connection). Here, metal sheets M2 and M3 are each divided into two parts; for ease of reading, this is referred to as... Figure 18 The left and right pieces are referred to as the left and right pieces, respectively. The left pieces of M2 and M3 have the same length, width, and thickness, as do the right pieces of M2 and M3. Metal sheet M1 is a single, single metal sheet whose length is negligibly greater than the combined length of the left and right pieces M2 and M3. Metal sheet M1 is connected to the left piece M2 at one end via via v1 and to the right piece M2 at the other end via via v1. The left piece M2 is connected to the left piece M3 via via v2, with via v2 and via v1 located on opposite sides of M2. The left piece M3 is connected to the left piece M4 via via v3, with via v3 and via v2 located on opposite sides of M3. The right piece M2 is connected to the right piece M3 via via v2, and the right piece M3 is connected to the right piece M4 via via v3.

[0109] The resistance obtained by resistor Rs is:

[0110] Rs = R M1 +R M2 +R M3

[0111] The desired number of such basic resistor structures 43 and 41 are connected in parallel and in series to produce the desired resistances R1 and RS.

[0112] Figure 18 The proposed structure is advantageous because it provides similar basic modules for constructing resistors Rs and R1, and it allows for the achievement of the best possible match for temperature effects. However, due to the series connection of elements M1, M2, and M3 in Rs, the area required for outputting low values ​​of Rs may be significantly larger than that required by utilizing [other technologies]. Figure 17 The previous Rs of the topology.

[0113] exist Figure 19 The cross-section (also) Figure 16 The top view plan, the cross-sectional view along the YY and ZZ lines, and Figure 20 In the third possible embodiment shown in the enlarged top view (cross-sectional view along the YY line), the metal layers M3 forming the basic resistor structures 41 and 43 of Rs and R1 can have the same structure in terms of length and thickness, but the width of the basic resistor structure 43 forming R1 is greater than the width of the basic resistor structure 41 forming Rs, as shown in the enlarged top view (cross-sectional view along the YY line). Figure 20 This can be observed in the magnified top-down plan view.

[0114] In the basic resistor structure 41 that forms Rs in this example, the metal sheet M3 is connected to the left and right metal sheets M4 at its end through a via v3, and multiple such basic resistor structures 41 are connected in parallel by sharing the metal sheet M4 with their metal sheets M3.

[0115] In this example, in the basic resistor structure 43 forming R1, a given metal strip M3 is connected at its end to the left and right metal strips M4 via a via v3, and multiple such basic resistor structures 43 are connected in series by sharing some metal strips in the metal strip M4 with their metal strips M3. For example, in Figure 20 In the top view of R1 shown, the central basic resistor structure 43 shares its right side M4 with the M3 of the bottom basic resistor structure 43, and the central basic resistor structure 43 shares its left side M4 with the M3 of the top basic resistor structure 43, thus forming a serpentine structure to connect the basic resistor structures 43 in series.

[0116] As with the first and second embodiments, this third embodiment is very useful, although it should be understood that unequal widths may cause slight gain errors (which can be corrected by fine-tuning R2). It should also be understood that for both Rs and R1 with the same width, basic resistor units 43 and 41 can be used, but the number of such basic resistor units 43 for R1 is increased to meet the desired resistance. It should be noted that this third embodiment has the advantage that a relatively reasonable silicon area can be used because Rs can be tuned to a low value due to the larger W_Rs, while R1 can still achieve a high resistance value due to the smaller W_R1 and the series connection. This structure allows for similar current flow because it uses a single layer of metal and is vertically stacked in completely similar manner in Rs and R1, thus also providing the best possible match for temperature effects. Figure 17 and Figure 18 The flexibility of this structure comes at the cost of absolute system matching between Rs and R1, as described above. However, this is a small cost, because the gain can be easily adjusted at the chip level during production.

[0117] Now for reference Figure 21 Another embodiment of a voltage / current sensor 100 for sensing load voltage and load current is described. Here, the load 18 is from a power source 19' (which may be...) Figure 12 The power supply 19' shown, and in particular, can be the output of the power converter 27, but can also be the output of the rectifier bridge, is a battery that receives the input current.

[0118] Battery 18 is coupled to power supply 19' via high-side sensing resistor RsenseH and to ground via low-side sensing resistor RsenseL. The node between power supply and high-side sensing resistor RsenseH is labeled NIP, the node between high-side sensing resistor RsenseH and battery 18 is labeled NVP, the node between battery 18 and low-side sensing resistor RsenseL is labeled NVN, and the node between low-side sensing resistor RsenseL and ground is labeled NIN.

[0119] Input multiplexer 101 has inputs connected to nodes NIP, NVP, NVN, and NIN, and outputs connected to nodes INP and INN. Input multiplexer 101 includes: a switch S1a connected between node NIP and node INP, a switch S2a connected between node NVP and node INP, a switch S3a connected between node NVN and node INP, and a switch S4a connected between node NIN and node INN. Input multiplexer 101 also includes: a switch S1b connected between node NIP and node INN, a switch S2b connected between node NVP and node INN, a switch S3b connected between node NVN and node INN, and a switch S4b connected between node NIN and node INN.

[0120] The first programmable gain circuit 102 has an input connected to node INP, an output connected to the non-inverting input terminal of the differential amplifier 110, and an output connected to the inverting output terminal of the differential amplifier 110. The first programmable gain circuit 102 includes: a switch S6a connected between node INP and node N1, a switch S5a connected between node INP and node N2, a switch S7a connected between node N1 and the inverting output terminal of the differential amplifier 110, a switch S8a connected between node N2 and the inverting output terminal of the differential amplifier 110, and a switch S9a connected between the non-inverting input terminal and the inverting output terminal of the differential amplifier 110. A capacitor C1a is connected between node N2 and the non-inverting input terminal of the differential amplifier 110, and a capacitor C2a is connected between node N1 and the non-inverting input terminal of the differential amplifier circuit 110.

[0121] The second programmable gain circuit 103 has an input connected to node INN, an output connected to the inverting input terminal of the differential amplifier 110, and an output connected to the non-inverting output terminal of the differential amplifier 110. The second programmable gain circuit 103 includes: a switch S6b connected between node INN and node N3; a switch S5b connected between node INN and node N4; a switch S7b connected between node N3 and the non-inverting output terminal of the differential amplifier 110; a switch S8b connected between node N4 and the non-inverting output terminal of the differential amplifier 110; and a switch S9b connected between the inverting input terminal and the non-inverting output terminal of the differential amplifier 110. A capacitor C1b is connected between node N4 and the inverting input terminal of the differential amplifier 110, and a capacitor C2b is connected between node N3 and the inverting input terminal of the differential amplifier 110.

[0122] An anti-aliasing filter 111 is connected to the inverting and non-inverting output terminals of a two-terminal differential amplifier 110 and filters the signal from it to generate differential output voltages VoutP and VoutN. These differential output voltages VoutP and VoutN are sampled by an analog-to-digital converter 112 to generate a digital output DOUT. The digital output DOUT can represent the voltage Vbat across battery 18, the high-side current IbatH entering battery 18, or the low-side current IbatL flowing from battery 18 to ground, depending on the mode. The digital output DOUT can be digitized and read.

[0123] State machine 113 controls the operation of switches S1a-S9a and S1b-S9b.

[0124] Now refer to another source Figure 22A This describes the operation of the voltage / current sensor performing battery voltage Vbat sensing. To perform battery voltage Vbat sensing, state machine 113 closes switches S5a, S5b, S7a, and S7b, and opens switches S1a, S2b, S4a, S4b, S6a, S6b, S8a, and S8b.

[0125] At time T1, switches S2a, S2b, S9a, and S9b are closed, connecting node NVP to capacitor C1a and capacitor C1b. Capacitors C1a and C1b have the same capacitance value, and therefore, between times T1 and T2, the same input is applied to both input terminals of differential amplifier 110, while the closing of switches S9a and S9b short-circuits the input of differential amplifier 110 to its output, thus performing an auto-zeroing operation. For example, the auto-zeroing phase occurring between times T1 and T2 can last for 10 μs. Note that the auto-zeroing operation can alternatively be performed by applying any two identical voltages to the inputs of differential amplifier 110.

[0126] At time T2, switches S2b, S9a, and S9b are open, while switch S3b is closed, and switches S2a and S3a do not change state. This connects node NVP to capacitor C1a and node NVN to capacitor C1b. Therefore, here, capacitors C1a and C1b are used as input capacitors, and switches S7a and S7b remain closed, making capacitors C2a and C2b act as feedback capacitors. The voltage Vbat across battery 18 is measured with a gain of C1a / C2a (or C1b / C2b, i.e., C1a and C1b have equal capacitance, and C2a and C2b have equal capacitance). For example, assuming the value of C2a is 5 times the value of C1a, the gain used by differential amplifier 110 during battery voltage measurement is 1 / 5. Figure 22AAs can be observed, the differential output VoutP-VoutN provided by differential amplifier 110 rises from ground at time T1 to a value higher than 1 between times T2 and T3. For example, the first measurement can last for 20 μs.

[0127] Then, chopping begins at time T3, where switches S2b and S3a are closed and open, while switches S9a and S9b remain unchanged. This connects node NVP to capacitor C1b and node NVN to capacitor C1a. This has the effect of inverting the differential output VoutP-VoutN for the first time. Chopping continues at time T4, where switches S2a and S3b are closed and open, while the remaining switches remain unchanged. This returns the switches to their state between times T2 and T3, where the differential output VoutP-VoutN is then inverted again.

[0128] The purpose of chopping is to shift the signal in the frequency domain so as to ultimately suppress amplifier noise during de-chopping. For example, these chopping stages can each last 20 μs. Although two chopping stages are shown, additional chopping stages can be performed, such as providing a measurement stage and fifteen chopping stages (which together define an acquisition cycle). The acquisition cycle can be repeated to improve sensing accuracy, for example, by performing digital averaging or filtering on the output DOUT of the ADC 112. De-chopping is also performed in this stage to reconstruct the value of the battery voltage Vbat in the digital domain.

[0129] Now refer to another source Figure 22B This describes the operation of the voltage / current sensor performing high-side current IbatH sensing. To perform high-side current IbatH sensing, state machine 113 closes switches S6a, S6b, S8a, and S8b, and opens switches S3a, S3b, S4a, S4b, S5a, S5b, S7a, and S7b.

[0130] At time T1, switches S2a, S2b, S9a, and S9b are closed, connecting node NVP to capacitors C2a and C2b. Capacitors C2a and C2b have the same capacitance value, and therefore, between times T1 and T2, the same input is applied to both input terminals of differential amplifier 110, while the closing of switches S9a and S9b short-circuits the inputs of differential amplifier 110 to its output, thus performing an auto-zero operation. Note that the auto-zero operation can alternatively be performed by applying any two identical voltages to the inputs of differential amplifier 110.

[0131] At time T2, switches S2b, S9a, and S9b are open, while switch S1b is closed, and switches S2a and S1a remain unchanged. This connects the voltage at node NIP to capacitor C2b and the voltage at node NVP to capacitor C2a. Therefore, differential amplifier 110 senses the voltage drop across the high-side sense resistor RsenseH during this stage, which represents the high-side current IbatH. Here, capacitors C2a and C2b are used as input capacitors, while capacitors C1a and C1b are used as feedback capacitors. Therefore, it is assumed that the capacitance values ​​of capacitors C2a and C2b are five times the capacitance values ​​of capacitors C1a and C1b, resulting in a gain of 5.

[0132] Then, chopping begins at time T3, at which point switches S2a and S1b are open, while switches S2b and S1a are closed, and the remaining switches remain in their current states. This connects node NVP to capacitor C2b and node NIP to capacitor C2a. This has the effect of inverting the differential output VoutP-VoutN for the first time.

[0133] Chopping continues at time T4, where switches S2b and S1a are open, while switches S2a and S1b are closed, and the remaining switches do not change state. This returns the switches to their state between times T2 and T3, where the differential output VoutP - VoutN is then inverted again. Although two chopping phases are shown, additional chopping phases can be performed, such as providing a measurement phase and fifteen chopping phases (which together define a sampling period). The sampling period can be repeated to improve sensing accuracy, for example, by digital averaging or filtering the output DOUT of the ADC 112. De-chopping is performed to reconstruct the value of the high-side current IbatH in the digital domain.

[0134] Now refer to another source Figure 22C This describes the operation of the voltage / current sensor performing low-side current IbatL sensing. To perform low-side current IbatL sensing, state machine 113 closes switches S6a, S6b, S8a, and S8b, and opens switches S1a, S1b, S2a, S2b, S5a, S5b, S7a, and S7b.

[0135] At time T1, switches S3a, S3b, S9a, and S9b are closed, connecting node NVN to capacitors C2a and C2b. Capacitors C2a and C2b have the same capacitance value, and therefore, between times T1 and T2, the same input is applied to both input terminals of differential amplifier 110, while the closing of switches S9a and S9b short-circuits the input of differential amplifier 110 to its output, thus performing an auto-zero operation. Note that the auto-zero operation can alternatively be performed by applying any two identical voltages to the inputs of differential amplifier 110.

[0136] At time T2, switches S3b, S9a, and S9b are open, while switch S4b is closed, and switches S3a and S4a do not change state. This connects the voltage at node NIN to capacitor C2b and the voltage at node NVN to capacitor C2a. Therefore, differential amplifier 110 senses the voltage drop across the low-side sense resistor RsenseL during this stage, which represents the low-side current IbatL. Here, capacitors C2a and C2b are used as input capacitors, while capacitors C1a and C1b are used as feedback capacitors. Therefore, it is assumed that the capacitance values ​​of capacitors C2a and C2b are five times the capacitance values ​​of capacitors C1a and C1b, and the gain is 5.

[0137] Then, chopping begins at time T3, when switches S3a and S4b are open, while switches S3b and S4a are closed, and the remaining switches remain in their current states. This connects node NVN to capacitor C2b and node NIN to capacitor C2a. This has the effect of inverting the differential output VoutP-VoutN for the first time. Chopping continues at time T4, where switches S3b and S4a are open, while switches S3a and S4b are closed, and the remaining switches do not change their states. This returns the switches to their state between times T2 and T3, where the differential output VoutP-VoutN is then inverted again. Although two chopping phases are shown, additional chopping phases can be performed, such as providing a measurement phase and fifteen chopping phases (which together define a sampling period). The sampling period can be repeated to improve sensing accuracy, for example, by digital averaging or filtering performed on the output DOUT of the ADC 112. De-chopping is performed to reconstruct the value of the low-side current IbatL in the digital domain.

[0138] From the above description of the measurement modes for battery voltage Vbat, high-side current IbatH, and low-side current IbatL, it can be seen that which capacitors C1a, C1b or C2a, C2b are used as input capacitors, and which capacitors C1a, C1b or C2a, C2b are used as feedback capacitors, can be selected. Therefore, the gain for any given sensing stage can be selected through the operation of programmable gain circuits 102 and 103.

[0139] In some applications, low-side current IbatL sensing may not be required. In such cases, such as... Figure 23 As shown, the input multiplexer 101' is modified to remove switches S4a and S4b. Otherwise, Figure 23 The voltage / current sensor 100' remains with Figure 21 The same.

[0140] Now for reference Figure 24 An embodiment of a voltage / current sensor 100” that allows for a wider range of programmable gain is described. Here, with Figure 21 Compared to the voltage / current sensor 100, the power supply 19', input multiplexer 101, and dual-ended differential amplifier 110 remain the same, but the first programmable gain circuit 102' and the second programmable gain circuit 103' are modified.

[0141] The first programmable gain circuit 102' has an input connected to node INP, and an output connected to the non-inverting input terminal of the differential amplifier 110, and an output connected to the inverting output terminal of the differential amplifier 110. The first programmable gain circuit 102' includes: a switch S6a connected between node INP and node N10; a switch S7a connected between node N10 and the inverting output terminal of the differential amplifier 110; a switch S61a connected between node INP and node N11; a switch S62a connected between node N11 and the non-inverting input terminal of the differential amplifier 110; a switch S5a connected between node INP and node N12; and a switch S63 connected between node N12 and the inverting output terminal of the differential amplifier 110. The switches S8a between the output terminals, S51a between node INP and node N13, S53a between node N13 and the non-inverting input terminal of differential amplifier 110, S9a between the non-inverting input terminal and the inverting output terminal of differential amplifier 110, S52a between node INP and node N14, and S54a between node N14 and the non-inverting input terminal of differential amplifier 110.

[0142] The second programmable gain circuit 103' has an input connected to node INN, and an output connected to the inverting input terminal of the differential amplifier 110, and an output connected to the non-inverting output terminal of the differential amplifier 110. The second programmable gain circuit 103' includes: a switch S6b connected between node INN and node N15; a switch S7b connected between node N15 and the non-inverting output terminal of the differential amplifier 110; a switch S61b connected between node INN and node N16; a switch S62b connected between node N16 and the inverting input terminal of the differential amplifier 110; a switch S5b connected between node INN and node N17; and a switch S62b connected between node N17 and the non-inverting output terminal of the differential amplifier 110. The switches S8b between the output terminals, S51b between node INN and node N18, S53b between node N18 and the inverting input terminal of the differential amplifier circuit 110, S9b between the inverting input terminal and the non-inverting output terminal of the differential amplifier 110, S52b between node INN and node N19, and S54b between node N19 and the inverting output terminal of the differential amplifier circuit 110.

[0143] Capacitor C2a is connected between node N10 and the non-inverting input terminal of differential amplifier 110, capacitor C61a is connected between node N11 and the non-inverting input terminal of differential amplifier 110, capacitor C1a is connected between node N12 and the non-inverting input terminal of differential amplifier 110, capacitor C51a is connected between node N13 and the non-inverting input terminal of differential amplifier 110, and capacitor C52a is connected between node N14 and the non-inverting input terminal of differential amplifier 110.

[0144] Capacitor C2b is connected between node N15 and the inverting input terminal of differential amplifier 110, capacitor C61b is connected between node N16 and the inverting input terminal of differential amplifier 110, capacitor C1b is connected between node N17 and the inverting input terminal of differential amplifier 110, capacitor C51b is connected between node N18 and the inverting input terminal of differential amplifier 110, and capacitor C52b is connected between node N19 and the inverting output terminal of differential amplifier circuit 110.

[0145] Operation and the above regarding Figure 24The same procedure is followed, except that here, programmable gain circuits 102' and 103' allow selection from capacitors C2a, C2b, C61a, C61b, C1a, C1b, C51a, C51b, C52a, and C52b as input and feedback capacitors. Here, the capacitance values ​​of capacitors C2a and C61a can be five times the capacitance value of capacitor C1a, the capacitance value of capacitor C51a can be 0.5 times the capacitance value of capacitor C1a, and the capacitance value of capacitor C52a can be 0.25 times the capacitance value of capacitor C1a. Similarly, the capacitance values ​​of capacitors C2b and C61b can be five times the capacitance value of capacitor C1b, the capacitance value of capacitor C51b can be 0.5 times the capacitance value of capacitor C1b, and the capacitance value of capacitor C52b can be 0.25 times the capacitance value of capacitor C1b. Therefore, the gain range here can be from 1 / 40 (capacitors C52a and C52b are used as input capacitors, and capacitors C2a / C61a and C2b / C61b are connected in parallel and used as feedback capacitors) to 40 (capacitors C2a / C61a and C2b / C51b are connected in parallel and used as input capacitors, and capacitors C52a and C52b are used as feedback capacitors).

[0146] The voltage / current sensors 100, 100', and 100” with programmable gain described herein offer several advantages. They utilize an input capacitor to block the bias DC current. Furthermore, the capacitor used can be a MOM (metal oxide metal) capacitor to provide resistance to piezoelectric effects caused by mechanical stress. In addition, the use of auto-zeroing and chopping is employed to eliminate noise and residual offset effects and to provide insensitivity to common-mode of the measured signal.

[0147] Finally, it is clear that modifications and changes can be made to the descriptions and illustrations herein without departing from the scope of this disclosure as defined in the appended claims. For example, Figure 25 The illustration shows one embodiment of sensor 100, which utilizes... Figure 21 19' power supply and Figure 21 The remainder of the circuitry is used to provide current sensing and the aforementioned battery voltage / current sensing immediately following the rectifier bridge 19.

[0148] Alternative designs and layouts for the sensing resistor Rs that can be used in the current sensor disclosed herein are now described.

[0149] However, firstly, consider Figure 26AThe converter 200 includes: an n-channel transistor S1, whose drain is connected to node VTOP, whose source is connected to node N1, and whose gate is coupled to a control signal φ1; and an n-channel transistor S2, whose drain is connected to node N1, whose source is connected to a resistor RA, and whose gate is coupled to a control signal φ2. Resistor RA is connected between the source of transistor S2 and node N2, and resistor RB is connected between node N2 and the drain of transistor S3. The drain of N-channel transistor S3 is connected to resistor RB, its source is connected to node N3, and its gate is coupled to the control signal φ1. The drain of N-channel transistor S4 is connected to the source of transistor S3, its source is connected to ground, and its gate is coupled to the control signal φ2. A resistor Rs (which may be a parasitic resistance) is connected between node N2 and the output bump BB. A load (represented by a load resistor RL and a load capacitance CL connected in parallel) is connected to the output bump BB. The bump itself may be resistive, which is... Figure 26A Not shown in the image.

[0150] In this design, it may be necessary to evaluate the output current IOUT supplied by the source to the load CL / RL. This evaluation can be performed by measuring the voltage across resistor RA during high-side conduction and / or measuring the voltage across resistor RB during low-side conduction. Alternatively, the evaluation can be performed by measuring the voltage across resistor Rs during high-side conduction, low-side conduction, or both. As another alternative, resistors RA and RB may be absent, and the evaluation can be performed by measuring the voltage across resistor Rs during high-side conduction, low-side conduction, or both, as... Figure 26B As shown.

[0151] One problem with evaluating the output current IOUT based on measurements of the voltage across resistors RA and RB is that, to obtain a well-controlled (“controlled” here is used to define elements with deterministic values ​​in mass production) resistor, it must be formed using actual physical planar resistances inserted in series with the source of S2 and the drain of S3, and independent of parasitic resistances that are not well-controlled. Therefore, RA and RB may consume undesirable area. See also Figure 27 , Figure 27 The area occupied by transistors S1-S4 and the area occupied by planar resistors RA and RB are shown. Sensing is performed across the planar resistors RA or RB depending on whether the high-side or low-side conduction of the converter 200 is achieved. Since these resistors RA and RB are integrated planar elements, and their performance across temperature can be predicted based on the material properties and layout, the sensing can be considered “controlled.”

[0152] We now consider a scenario where people prefer to rely on Rs instead of RA and / or RB, such as... Figure 26B As shown. Reference Figure 28 This best explains the problems in evaluating the output current IOUT based on resistor Rs. Here, voltage sensing is performed across the parasitic resistance path represented by resistor Rs. Assuming the source of S2 is directly connected to the drain of S3 and the common node N2 is connected to the output bump, and considering the parasitic characteristics of resistor Rs from the common point (node ​​N2) to the output bump BB, the sensing is "uncontrolled," and its performance across temperature may be unpredictable due to component variations.

[0153] Therefore, now refer to Figure 29 Describe the improvements made to the design of converter 200'.

[0154] Converter 200' includes: an n-channel transistor S1 with its drain connected to node VTOP, its source connected to node N1, and its gate coupled to a control signal φ1; and an n-channel transistor S2 with its drain connected to node N1, its source connected to node N2, and its gate coupled to a control signal φ2. An n-channel transistor S3 has its drain connected to node N2, its source connected to node N3, and its gate coupled to the control signal φ1. An n-channel transistor S4 has its drain connected to the source of transistor S3, its source connected to ground, and its gate coupled to the control signal φ2. Here, the resistance shown as Rs represents the parasitic resistance formed by the conductive path between node N2 and the "lower" portion BB1 of the output bump BB (see [link to relevant documentation]). Figure 30 The load (represented by the load resistor RL and load capacitor CL connected in parallel) is connected to the "upper" portion BB2 of the output bump BB (see [link]). Figure 30 The parasitic resistance of the bump is labeled Rbump and represents the actual electrical path from the "lower" portion BB1 of the bump BB to the "upper" portion BB2 of the bump BB. The parasitic resistance Rbump of the bump is not used as part of the sensing path.

[0155] The output current IOUT flows from node N2 through resistor Rs to the output "lower" portion BB1 of bump BB. The non-inverting input terminal of sense amplifier 201 is coupled to node N2, and its inverting input terminal is coupled to BB1. Based on these inputs, a sense voltage VSENSE is generated, which represents the current IOUT flowing through resistor Rs.

[0156] Now for reference Figures 30-32 This describes the resistor Rs, which, as described above, is a conductive path in the interconnect region between node N2 and the "lower" portion BB1 of the output bump BB. Specifically, Figure 30The diagram shows traces from transistors S2 and S3 (or their appropriate source / drain regions), and the conductive path between node N2 and the “lower” portion BB1 of the output bump BB. As shown, the conductive path from the source of transistor S2 to the drain of transistor S3 is formed by a continuous conductive stack 201 extending continuously from the source of transistor S2 toward BB1 and from BB1 toward the drain of transistor S3. A first portion 204a of the conductive stack 204 is disconnected from the source of transistor S2 toward BB1 (but does not reach BB1), and a second portion 204b of the conductive stack 204 is disconnected from the drain of transistor S3 toward BB1 (but does not reach BB1). The first portion 204a and the second portion 204b are separated by a notch 210.

[0157] The disconnected conductive stack portions 204a and 204b are stacked on and carried by the continuous conductive stack 201, and are separated by the notch 210 as described above.

[0158] The continuous conductive stack 201 is formed by a metal sheet 202 in a first metal layer M1, which forms the bottom layer. The continuous conductive stack 201 includes a metal sheet 203 located in a second metal layer M2, which covers and is in electrical contact with the metal sheet 202 in the first metal layer M1, and the electrical contact is formed by a first via layer V1.

[0159] The disconnected conductive stack portion 204a is formed by the following: a metal sheet 205a in the third metal layer M3, which covers and is electrically in contact with the metal sheet 203 in the second metal layer M2, the electrical contact being formed by the second via layer V2; a metal sheet 206a in the fourth metal layer M4, which covers and is electrically in contact with the metal sheet 205a in the third metal layer M3, the electrical contact being formed by the third via layer V3; and a metal sheet 207a in the fifth metal layer M5, which covers and is electrically in contact with the metal sheet 206a in the fourth metal layer M4, the electrical contact being formed by the fourth via layer V4.

[0160] The disconnected conductive stack portion 204b is formed by the following: a third metal sheet 205b in the third metal layer M3, which covers and is in electrical contact with the second metal sheet 203 in the second metal layer M2, the electrical contact being formed by the second via layer V2; a fourth metal sheet 206b in the fourth metal layer M4, which covers and is in electrical contact with the third metal sheet 205b in the third metal layer M3, the electrical contact being formed by the third via layer V3; and a fifth metal sheet 207b in the fifth metal layer M5, which covers and is in electrical contact with the fourth metal sheet 206b in the fourth metal layer M4, the electrical contact being formed by the fourth via layer V4.

[0161] The midpoint of the gap 210 between the disconnected conductive stack portions 204a and 204b and in the very center of the conductive stack 201 can be considered as node N2. The central conductive stack portion 212 is located at this midpoint of the gap 210 and extends to the “lower” portion BB1 of the output bump. The central conductive stack portion 212 is stacked on and carried by a portion of the continuous conductive stack 201 extending from node N2 to BB1.

[0162] The central conductive stack portion 212 includes a third metal layer M3 that covers and is electrically connected to the metal sheet 203 in the notch 210, the electrical contact being formed by the second via layer V2. The third metal layer M3 in the central conductive stack portion 212 includes n individual metal sheets, denoted as 205c(1), ..., 205c(n).

[0163] The central conductive stack portion 212 also includes a fourth metal layer M4, which covers and is in electrical contact with the third metal layer M3, and this electrical contact is formed by the third via layer V3. The fourth metal layer M4 in the central conductive stack portion 212 is divided into n individual metal sheets, denoted as 206c(1), ..., 206c(n).

[0164] The central conductive stack portion 212 also includes a fifth metal layer M5, which covers and is in electrical contact with the fourth metal layer M4, the electrical contact being formed by a fourth via layer V4. The fifth metal layer M5 in the central conductive stack portion 212 is formed by a continuous metal sheet 207c.

[0165] Because the conductive stack portions 204a and 204b are disconnected, the current from transistor S2 or transistor S3 to node N2 flows only in the first metal layer M1 and the second metal layer M2. In other words, the current flowing through metal layers M3, M4, and M5 in the disconnected conductive stack portions 204a and 204b flows downward into metal layers M2 and M1 before reaching node N2. The current from node N2 flows through metal layers M1 and M2 and the various metal layers M3, M4, and M5 of the central conductive stack portion 212, and flows upward through metal sheet 207c into the "lower" portion BB1 of the output bump BB.

[0166] The metal sheets of the first and second metal layers M1, M2, and M5 are designed to have significantly lower resistance than the metal sheets of metal layers M3 and M4. Therefore, the resistance of the metal sheets of metal layers M1, M2, and M5 can be essentially ignored, and the metal sheets 205c(1), ..., 205c(n) and 206c(1), ..., 206c(n) of metal layers M3 and M4 in the central conductive stack portion 212 can be considered to form resistive pillars together with the electrical contact V2 from M2 to M3, the electrical contact V3 from M3 to M4, and the electrical contact V4 from M4 to M5. It is the resistance provided by these resistive pillars that provides the resistance of the conductive path between node N2 and the “lower” portion BB1 of the output bump BB. By carefully selecting the materials for forming the metal sheets 205c(1), ..., 205c(n) and 206c(1), ..., 206c(n), and by carefully selecting the size and geometry of the metal sheets 205c(1), ..., 205c(n) and 206c(1), ..., 206c(n), the resistance of the conductive path between node N2 and the “lower” portion BB1 of the output bump BB can be carefully selected.

[0167] Along the conductive path between node N2 and the “lower” portion BB1 of the output bump BB, there may be approximately 1000 such resistor posts, each with a resistance of approximately 4Ω.

[0168] exist Figures 30-32 In the example shown, the resistor columns are connected in parallel to achieve a total resistance Rs of 4mΩ (4Ω / 1000) (or reference). Figure 14 (Rsense). It should be understood that, conversely, the resistor columns can be connected in series to achieve a total resistance R1 of 4kΩ (4Ω*1000) (reference). Figure 14 ).

[0169] Figure 33 The diagram illustrates an alternative series version of this design. Here, metal layer M1 is also broken into separate metal sheets 202(1), ..., 202(m) spaced apart from each other and each having a resistance RM1, and metal layer M2 is similarly broken into separate metal sheets 203(1), ..., 203(m) spaced apart from each other and each having a resistance RM2. The resistances RM1 and RM2 are both on the order of milliohms (e.g., 3mΩ). Metal layer M5 is also broken into separate metal sheets 207c(1), ..., 207c(o), each metal sheet having a resistance RM5 on the order of milliohms (e.g., 3mΩ), while the resistance Rpillar of each pillar formed by metal sheets 205c(1), ..., 205c(n) and 206c(1), ..., 206c(n) is on the order of ohms (e.g., 3Ω).

[0170] Therefore, current flows into terminal 1 formed by the metal sheet 202(1) of metal layer M1 and the metal sheet 203(1) of metal layer M2, flows upward through the metal sheet 205c(1) of metal layer M3 and the metal sheet 206c(1) of metal layer M4, enters the metal sheet 207c(1) of metal layer M5, flows downward through the metal sheet 206c(2) of metal layer M4 and the metal sheet 205c(2) of metal layer M3, and enters the metal sheets 203(2) and 202(2) of metal layers M2 and M1. This completes the current traversal through a resistor column. The current continues to flow into the next resistor column of metal layers M1 and M2 in the same manner as described above and flows through the resistor column until the current flows upward out of terminal 2. Looking between terminals 1 and 2, assuming the metal layers M1 / M2 / M5 are large enough that their sheet resistance is negligible compared to the resistance of the pillars formed by the stack of V2 / M3 / V3 / M4 / V4, then... Figure 33 The resistance R1 is equal to m * Rpillar. Similarly, when repeating for n pillars, Figure 32 The resistance is equal to Rpillar / n.

[0171] By using a combination of series and parallel arrangements, a ratio metric R1 / Rsense can be generated to provide a process- and temperature-independent scaling factor, which is used for, for example... Figure 14 The current sensor circuit shown.

[0172] It should be understood that process design rules and constraints may include: the metal sheets for metal layers M3 and M4 must be larger than a certain size. Therefore, if Figures 30-33 If the dimensions of the central conductive stack portions 212, 212' shown exceed the process design rules and constraints, then their structure may not be able to be formed. In this case, an alternative design can be used.

[0173] exist Figures 34-35In the design shown, metal layers M3 and M4 of the central stack portion 212 are continuous. Therefore: the third metal layer M3 is formed by a metal sheet 205c extending from node N2 to the lower portion BB1 of the output bump BB, thereby covering the metal sheet 203 of the second metal layer M2 and electrically connected to the metal sheet 203 through via layer V2; and the fourth metal sheet M4 is formed by a metal sheet 206c extending from node N2 to the lower portion BB1 of the output bump BB, covering the metal sheet 205c of the third metal layer M3 and electrically connected to the metal sheet 205c through via layer V3. Due to the gap 210 between the conductive stack portions 204a and 204b, current flows upward from the first metal layer M1 and the second metal layer M2. In fact, because the vias of via layers V2 and V3 physically separate metal layers M2, M3, and M4, current flows upward from the first metal layer M1 and the second metal layer M2 to the fifth metal layer M5, rather than flowing horizontally. Therefore, Figures 34-35 The effective resistance of the resistor column in the design is maintained with Figures 30-33 Same as above.

[0174] Due to the specific design of the conductive path between the source of transistor S2 and the drain of transistor S3 (where notch 210 is between the disconnected conductive stack portions 204a, 204b), the current flow from node N2 to the lower portion BB1 of the output bump BB is restricted to the central conductive stack portion 212, which includes the aforementioned resistor pillars connected in parallel to create a resistor for current sensing. Because the structure and geometry of the resistor pillars are carefully controlled, the sensing is controlled. Therefore, the design disclosed herein provides controlled sensing of the current from the converter 200' output to the loads RL, CL, utilizing the conductive path between node N2 and the lower portion BB1 of the output bump BB, thereby saving area by eliminating the need for a specific planar resistor that would otherwise be required.

[0175] Although the above description, within the context of converter 200', outlines the use of a notch 210 and the addition of a central conductive stack portion 212 in the conductive path from node N2 to the lower portion BB1 of the output bump BB, it should be understood that this design can be used in any conductive path to create a sensing resistor Rs for current or voltage sensing. Therefore, this design of Rs can be used to create a sensing resistor Rs for use with reference to the above. Figure 9 , Figure 12 , Figure 13 , Figure 14 , Figure 21 , Figure 23 , Figure 24 , Figure 25 The resistors used in any of the circuits described above can be arranged in a ratiometric arrangement with alternative series versions of the design described above to provide consistent performance across temperature.

[0176] Obviously, modifications and changes can be made to the descriptions and illustrations herein without departing from the scope of this disclosure as defined in the appended claims.

[0177] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure disclosed herein. Therefore, the scope of this disclosure is limited only by the appended claims.

Claims

1. A circuit comprising: First switching element; Second switching element; Output bump; The interconnection region includes a first sub-region extending from the first switching element to the first node, a second sub-region extending from the second switching element to the first node, and a third sub-region extending from the first node to the output bump; The first sub-region includes: The first plurality of metallization levels are interconnected via vias, each of the first plurality of metallization levels including a metal sheet that extends fully from the first switching element to the first node to directly electrically connect the first switching element to the first node. A plurality of second metallization levels are interconnected via vias, the plurality of second metallization levels covering and interconnected to the plurality of first metallization levels via vias, each of the plurality of second metallization levels including a metal sheet extending partially from the first switching element toward the first node; The second sub-region includes: The first plurality of metallization levels interconnected by vias, each of the first plurality of metallization levels in the second sub-region includes a metal sheet extending fully from the second switching element to the first node to directly electrically connect the second switching element to the first node; The second plurality of metallization levels of the second sub-region are interconnected via vias, the second plurality of metallization levels of the second sub-region covering the first plurality of metallization levels of the second sub-region and interconnected via vias to the first plurality of metallization levels of the second sub-region, each of the second plurality of metallization levels of the second sub-region including a metal sheet extending partially from the second switching element toward the first node, and defining a gap between the second plurality of metallization levels of the second sub-region and the second plurality of metallization levels of the first sub-region. The third sub-region includes: A plurality of metallization levels are interconnected via vias and extend from the first node to the output bump to directly electrically connect the first node to the output bump; and The second plurality of metallization levels of the third sub-region are interconnected via vias, and the second plurality of metallization levels of the third sub-region cover the first plurality of metallization levels of the third sub-region and are interconnected to the first plurality of metallization levels of the third sub-region via vias; The second plurality of metallization levels in the third sub-region include: A top metallization stage having a metal sheet extending fully from the first node to the output bump to directly electrically connect the first node to the output bump; and At least one lower metallization stage has a plurality of spaced metal sheets for directly electrically connecting the top metallization stage to a first plurality of metallization stages in the third sub-region.

2. The circuit of claim 1, wherein the resistance of the plurality of spaced-apart metal sheets of the at least one lower metallization level is greater than the resistance of the top metallization level and the first plurality of metallization levels of the third sub-region.

3. The circuit of claim 1, wherein each of the first plurality of metallization levels in the third sub-region includes a metal sheet extending fully from the first node to the output bump to directly electrically connect the first node to the output bump.

4. The circuit of claim 3, wherein the at least one lower metallization level of the second plurality of metallization levels of the third sub-region comprises: A first lower metallization level covers a first plurality of metallization levels in the third sub-region and is interconnected to the first plurality of metallization levels in the third sub-region via vias. The first lower metallization level includes a plurality of spaced metal sheets connected to the first plurality of metallization levels in the third sub-region via the vias. as well as A second lower metallization stage covers the first lower metallization stage and is interconnected to the first lower metallization stage via vias. The second lower metallization stage includes a plurality of spaced-spaced metal sheets that connect spaced-spaced metal sheets of the first lower metallization stage to metal sheets of the top metallization stage. The corresponding metal sheets of the plurality of spaced-apart metal sheets in the first lower metallization stage and the plurality of spaced-apart metal sheets in the second lower metallization stage are connected by vias to define a plurality of spaced-apart conductive posts, which are connected in parallel between the top metallization stage and the first lower metallization stage.

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