Communication apparatus and communication encryption and decryption method

Abstract

The application relates to a communication device and a communication encryption and decryption method, and belongs to the technical field of data security. By acquiring data to be encrypted, the data to be encrypted is grouped in groups with a set number of bytes, bits of each byte in each group are extracted, the data bits are rearranged in a set order, the rearranged data bits are sequentially cut into corresponding bytes, first layer encryption is completed, the number of bit0 and the number of bit1 after the first layer encryption are counted, whether the current bit output is inverted is judged according to the number of 0 bits and 1 bits in the data bits before the current data bit, and encrypted data is obtained. The decryption method is based on the encryption method to complete decryption. The application completes data encryption in a relatively simple method on the basis of not affecting original time sequence and occupying very few processor resources, greatly improves the security of data transmission, and has very little influence on data real-time performance.

Description

Technical Field

[0001] This invention relates to a communication device and a communication encryption and decryption method, belonging to the field of data security technology. Background Technology

[0002] In fields such as power engineering and industrial control, the use of FPGAs for encoding and decoding communication data is widespread. Traditional device-to-device communication uses protocol-based communication, with real-time communication implemented using FPGAs. The physical layer employs CMI, NRZ, Manchester encoding, etc., while the application layer uses custom protocols or industry-standard protocols. Most communication data in this approach is unencrypted, transmitted in plaintext, lacking any security or privacy. However, this transmission carries critical data; if maliciously intercepted or disguised, and tampered data conforming to the application protocol is sent to control or protection equipment, it could lead to catastrophic consequences. Therefore, encryption of communication data is necessary.

[0003] Currently, patent document CN112367310A discloses an FPGA-based SRIO bus encrypted transmission device. This method is based on FPGA programming logic, combined with the SRIO protocol, and requires the effective data payload transmitted by the user to be an integer multiple of 256 bytes. It achieves high-speed data transmission through a built-in encryption / decryption module. However, this method is only applicable to SRIO and requires the user to transmit data in multiples of 256 bytes, making it highly targeted and subject to many limitations. Patent document CN113037390B discloses an FPGA-based fiber optic encryption method. This method uses the obtained plaintext PT, the FPE encryption mode key KT, and the encrypted plaintext to obtain ciphertext, and completes encryption by converting the bit width of the ciphertext data. This method is designed for high-speed fiber optic large-scale data communication, but the encryption complexity is high, and the need to obtain all data in advance increases the latency of real-time communication. Summary of the Invention

[0004] The purpose of this invention is to provide a communication device and a communication encryption and decryption method to solve the problems of long real-time latency and high implementation complexity of FPGA-based communication encryption.

[0005] To achieve the above objectives, the present invention includes:

[0006] A communication encryption method according to the present invention includes the following steps:

[0007] 1) Obtain the data to be encrypted, group the data to be encrypted into groups of a set number of bytes, and group the remaining data into groups of actual bytes if the data is less than the set number of bytes.

[0008] 2) Extract the bits of each byte in each group, rearrange them in a set order, and truncate the rearranged data bits into corresponding bytes to complete the first layer of encryption;

[0009] 3) Count the number of bit0 and bit1 after the first layer of encryption. Determine whether the current bit output is inverted based on the number of 0 and 1 bits in the data bits before the current data bit, and obtain the encrypted data.

[0010] Beneficial Effects: The communication encryption method of this invention improves the security of data transmission through a two-layer encryption approach. The first layer of encryption is achieved by rearranging the data bits of each group of data bytes and sequentially arranging the resulting new bytes, without consuming excessive processor resources or processing time. The second layer of encryption is performed based on the number of 0 and 1 bits in the preceding data bits. This second layer adds some bitstream encryption logic, which does not cause delay for bitstream output and consumes minimal processing hardware resources. This invention encrypts data in a relatively simple way without affecting the original timing and with minimal processor resource consumption, greatly improving the security of data transmission while having minimal impact on the real-time performance of data transmission.

[0011] Furthermore, the order is set so that the first byte to the first bit of the last byte of the data to be encrypted in each group are sorted sequentially, the second bit of the first byte to the last byte is placed after the first bit of the last byte, and so on until the eighth bit of the first byte to the last byte is arranged sequentially, and the data to be encrypted in each group is arranged sequentially.

[0012] Beneficial effects: When performing the first layer of encryption, this invention sorts the first bit of each group of data to be encrypted from the first byte to the last byte in sequence, and so on, until the 8th bit of each group of data to be encrypted is arranged in sequence. The data to be encrypted in each group is arranged in sequence. This encryption method only requires that the number of encrypted data is an integer multiple of bytes. Encryption can be completed by processing the bits of the data. The processing speed is fast and does not consume too much processor resources, which can well ensure the security of encrypted data.

[0013] Furthermore, if the number of 0s and 1s in the preceding data bits of the current data bit is equal and not zero, then the current bit is inverted; otherwise, the current bit is kept. If the number of 0s and 1s in the preceding data bits of the current data bit is not equal, and the number of 0s and 1s in the preceding data bits is greater and odd, then the current bit is inverted; otherwise, the current bit is kept.

[0014] Beneficial effects: The second-layer encryption method of the present invention determines whether the current bit should be inverted based on the number of 0s and 1s in the previous data bits in the current data bit. This encryption logic is simple and can ensure the security of encrypted data, while not occupying processor resources and ensuring the real-time transmission of data.

[0015] Furthermore, the set byte is 8 bytes.

[0016] Beneficial effects: Each group consists of 8 bytes, and each byte has 8 bits. During encryption, in the first layer of encryption, the first bit of the first byte to the eighth byte forms the first byte, the second bit of the first byte to the eighth byte forms the second byte, and so on, with the eighth bit of the first byte to the eighth byte forming the eighth byte. This results in fast processing speed and ensures data security.

[0017] Furthermore, when the data set contains only 1 byte, the data set is not encrypted using the first layer of encryption.

[0018] Beneficial effect: When a set of data consists of only 1 byte, there is no need to perform encryption.

[0019] A communication decryption method according to the present invention includes the following steps:

[0020] A) Count the number of bit 0 and bit 1 in the encrypted data, and determine whether the current bit of the output should be inverted based on the number of 0 and 1 bits in the data bits before the current data bit, so as to obtain the data after the first layer of decryption;

[0021] B) Based on the length of the data after the first layer of decryption, group the data after the first layer of decryption into groups of M bytes. If the remaining data is less than the set number of bytes, group it into a group of actual bytes. Arrange the bytes in each group sequentially. Starting from the lowest bit of the first byte of each group or the highest bit of the Mth byte of each group, extract 1 bit every M-1 bits. Combine 8 extracted bits into a new byte. Arrange the new bytes formed by each group sequentially. Arrange the data in each group sequentially to complete the second layer of decryption of the encrypted data and restore it to the unencrypted state, where M>1.

[0022] Beneficial Effects: The communication decryption method of this invention is based on the above-mentioned encryption method and decrypts two layers of encrypted data. The first layer of decryption is performed based on the number of 0 and 1 bits in the data bits preceding the current data bit. The second layer of decryption is completed by rearranging the data bits of each group of data bytes and sequentially arranging the resulting new bytes, without consuming excessive processor resources or processing time. The first layer of decryption is based on additional bitstream encryption logic, which does not cause delay for bitstream output, and the added encryption logic consumes very few processing hardware resources. This invention completes data decryption in a relatively simple way without affecting the original timing, consuming very few processing resources, and having minimal impact on real-time performance.

[0023] Furthermore, if the number of 0s and 1s in the preceding data bits of the current data bit is equal and not zero, then the current bit is inverted; otherwise, the current bit is kept. If the number of 0s and 1s in the preceding data bits of the current data bit is not equal, and the number of 0s and 1s is greater and odd, then the current bit is inverted; otherwise, the current bit is kept.

[0024] Beneficial effects: The first-level decryption method of this invention is based on the number of 0s and 1s in the previous data bits in the current data bit to determine whether the current bit should be inverted. This encryption logic is simple, can decrypt quickly, and does not occupy processor resources, thus ensuring the real-time performance of data transmission.

[0025] Furthermore, if the block of data formed after the first decryption is only 1 byte, then the block of data will not be decrypted.

[0026] Furthermore, the data during decryption is stored in a FIFO, RAM, or register.

[0027] Beneficial effects: This decryption method consumes relatively few processor resources, as the data during decryption can be stored in a FIFO, RAM, or register.

[0028] A communication device according to the present invention includes a processor, a register, a FIFO, and a counter. The processor executes control instructions to implement the communication encryption method as described above and the communication decryption method as described in any of the preceding claims. The memory is used to store data to be encrypted, encrypted data, and decrypted data. The counter is used to count the number of bits 0 and bits 1 in the encrypted data.

[0029] Beneficial effects: The communication device of the present invention can realize the communication encryption method and the communication decryption method as described above by executing control instructions through the processor. It stores the data to be encrypted, the encrypted data and the decrypted data through the memory, and counts the number of bit0 and bit1 in the encrypted data through the counter. The communication device has a simple structure, fast parallel processing speed and high real-time performance when processing data. Attached Figure Description

[0030] Figure 1 This is a flowchart of data encryption and decryption based on FPGA communication in the embodiments of the decryption and decryption method of the present invention;

[0031] Figure 2(a) is a schematic diagram of the data before the first encryption in an embodiment of the method of the present invention;

[0032] Figure 2(b) is a schematic diagram of the data after the first encryption in an embodiment of the method of the present invention;

[0033] Figure 3(a) is a schematic diagram of the data before the second encryption in an embodiment of the method of the present invention;

[0034] Figure 3(b) is a schematic diagram of the data after the second encryption in an embodiment of the method of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings.

[0036] Example of a communication encryption method:

[0037] like Figure 1 The communication encryption method shown first obtains the data to be encrypted, groups the data into sets of a predetermined number of bytes, reorders the bits in each byte of each set, and truncates them into corresponding bytes to complete the first layer of encryption. The number of bit 0s and bit 1s after the first layer of encryption is counted. Based on the number of 0s and 1s in the data preceding the current data bit, it is determined whether the current bit should be inverted to obtain the encrypted data, thus completing the second layer of encryption. The specific implementation is as follows:

[0038] S1) First layer of encryption: Obtain the data to be encrypted, group the data to be encrypted into groups of a set number of bytes, and group the remaining data into groups of actual bytes. Extract the bits of each byte in each group, rearrange them in a set order, and truncate the rearranged data bits into corresponding bytes in sequence to complete the first layer of encryption.

[0039] This embodiment is based on a communication encryption method formed by FPGA real-time communication. The data frame format adopts the form of frame header + data + frame trailer. In this embodiment, only the data is encrypted, and the frame header, frame trailer and idle code in the channel are not involved in the encryption.

[0040] First, a register is designed in the FPGA to store the setting byte. This register can store all the bits of the setting byte and is configured with a FIFO (First-In-First-Out) queue. The FPGA also includes a high-frequency clock. In this embodiment, the setting byte is 8 bytes. Based on the setting byte, the FPGA is designed with an 8-byte register, an 8-byte FIFO, a total data byte count register cnt_all, a counter register cnt_8 with a total count of 8, and a suitable encryption state machine using a high-frequency clock. The implementation principle steps are as follows:

[0041] S11) First, obtain the quantity N of user data to be encrypted (i.e., data to be sent). The start code is not involved in the encryption.

[0042] S12) Based on the number N of the acquired data to be encrypted, group the data into sets of 8 bytes each, with any remaining data less than 8 bytes grouped together. For example, if the user data to be sent is 2 bytes, it is grouped into 1 group; if the user data to be sent is 9 bytes, it is grouped into 2 groups. To facilitate hardware processing, the set number of bytes in this embodiment is 8. In other embodiments, the set number of bytes per group is not limited to 8.

[0043] S13) Create an 8-byte register and an 8-byte FIFO, read each set of data from the FIFO, RAM or register where the data is stored and store it into the created register in sequence.

[0044] After writing the data to be encrypted into the transmit RAM, obtain the length len of the data to be encrypted. Clear the two counter registers and the 8-byte register to 0.

[0045] S131) ​​If this group of data consists of 8 bytes, the encryption method is as follows: extract the first bit of the 8 bytes to form a new word, use the first bit of the first byte as the least significant bit, and the first bit of the eighth byte as the most significant bit, and sort them in order. Use this as the first byte of the encrypted data. Then, extract the second to eighth bits of the 8 bytes to form the encrypted byte. After the group of data is encrypted, determine whether the data stored in the FIFO last time has been completely retrieved. If not, the encrypted data waits to be stored in the FIFO. During the waiting period, no new data is retrieved for encryption until the FIFO is empty and data is stored. Then, new data is retrieved and encryption continues until all data processing is completed.

[0046] S132) If the data in this group is 1 byte, the data is not encrypted. Check if the data stored in the FIFO last time has been completely retrieved. If not, encrypt the data and wait to store it in the FIFO. During the waiting period, no new data will be retrieved for encryption until the FIFO is empty and data is stored. Then new data will be retrieved and encrypted again until all data processing is completed.

[0047] S133) If the number of bytes in this group of data is greater than 1 and less than 8 bytes (if it is N bytes, 1 < N < 8), the encryption method is as follows: allocate a register space corresponding to the number of bytes in the FPGA, extract the 1st bit to the 8th bit of the N bytes, arrange the 1st bit of the first word at the 1st bit of the new register space, the 1st bit of the second word at the 2nd bit of the new register space, until the 1st bit of the last byte, and arrange them in sequence. Then, arrange the 2nd bit of the first word to the last word immediately following the 1st bit of the last word in sequence, and so on until the register space of N words is filled. Then, cut the register space into corresponding bytes in order, and determine whether the data stored in the FIFO last time has been fetched. If not, the encrypted data waits to be stored in the FIFO, and no new data is fetched for encryption during the waiting period until the FIFO is empty and the data is stored. After that, new data is fetched and encryption continues until all data is processed. The example of 2 bytes is shown in Figures 2(a) and (b). The 1st bit (bit7) of bite1 is arranged at the 1st bit of the new register, the 1st bit (bit7) of bite0 is arranged at the 2nd bit of the new register. The 2nd bit (bit6) of bite1 is arranged at the 3rd bit, the 2nd bit (bit6) of bite0 is arranged at the 4th bit of the new register, and so on until the encryption of 2-byte data is completed.

[0048] In this embodiment, to ensure real-time data transmission, a state machine used for encryption is adopted. When encryption is started, the encryption state machine monitors the current data state in real time. First, read the RAM byte by byte, store one byte in the register, increment the total byte count register cnt_all and the count register cnt_8 by 1 respectively, and then compare the count register cnt_8 with 8 (the total number of bytes in this group) and compare cnt_all with the length len to be encrypted. The implementation steps are as follows:

[0049] If the count of the count register cnt_8 is less than 8 and cnt_all is equal to the length len to be encrypted, it is necessary to determine the size of cnt_8. When the count of cnt_8 is 1, the data in this group is 1 byte and the data is not encrypted. Then, determine whether the data stored in the FIFO last time has been fetched. If not, the encrypted data waits to be stored in the FIFO, and no new data is fetched for encryption during the waiting period until the FIFO is empty and the data is stored. After that, new data is fetched and encryption continues until all data is processed, and the counter cnt_8, the counter cnt_all, and the data register are cleared.

[0050] When the count of cnt_8 is greater than 1 and less than 8 bytes, the encryption method in the above step S133) is executed.

[0051] If the count in the counter register cnt_8 is less than 8 and cnt_all is less than the length to be encrypted len, it means that the data to be encrypted has not been encrypted. Continue to read RAM byte by byte and store one byte in the register. The total number of bytes register cnt_all and the counter register cnt_8 are incremented by 1. Then, the counter register cnt_8 is compared with the total number of bytes in the group (8), and cnt_all is compared with the length to be encrypted len.

[0052] If the counter cnt_8 counts to 8 and the counter cnt_all is equal to the length len of the data to be encrypted, then the encryption method described in step S131) ​​above will be executed.

[0053] If the counter cnt_8 counts to 8 and the counter cnt_all is less than the length len of the data to be encrypted, it means that the current 8-byte count register is full and needs to be sent, but the entire data to be encrypted has not been encrypted. In this case, step S133) is selected to execute the encryption method, and it is determined whether the FIFO is empty. If it is not empty, it waits in this state. If it is empty, the encrypted data is stored in the FIFO, and the counter cnt_8 is cleared to 0. The RAM is read byte by byte, and one byte is read and stored in the register. The total number of bytes register cnt_all and the counter register cnt_8 are incremented by 1 respectively. Then, the counter register cnt_8 is compared with the total number of bytes 8, and cnt_all is compared with the length len to be encrypted.

[0054] S2) Second layer encryption: Count the number of bit 0 and bit 1 after the first layer encryption, and determine whether the current bit output is inverted based on the number of 0 and 1 bits in the data bits before the current data bit, so as to obtain the encrypted data.

[0055] Create a counter cnt0_en that counts to 0 and a counter cnt1_en that counts to 1 in the existing transmit state machine. After the transmit state machine has sent the start code, start counting cnt0_en and cnt1_en. Clear both counters to 0 before data transmission begins.

[0056] Once data transmission begins and the start code is sent, two counters are started. If the number of 0s and 1s in the preceding data bits is equal and not zero, the current bit is inverted; otherwise, the current bit is retained. If the number of 0s and 1s in the preceding data bits is not equal, and the number of 0s and 1s in the larger number of bits is odd, the current bit is inverted; otherwise, the current bit is retained. In other words, the encryption method is as follows:

[0057] If the number of 0s in the data bits preceding the current data bit is greater than the number of 1s, and the number of 0s is odd, then the current bit is inverted; otherwise, it remains unchanged.

[0058] If the number of 1s in the data bits preceding the current data bit is greater than the number of 0s, and the number of 1s is odd, then the current bit is inverted; otherwise, it remains unchanged.

[0059] If the number of 0s and 1s in the data bits preceding the current data bit is equal and not zero, then the current bit is inverted. If the number of 0s and 1s in the data bits preceding the current data bit is equal and zero, then the current bit is left unchanged. As shown in Figures 3(a) and (b), the data stream 01110001 becomes 00011111 after secondary encryption.

[0060] Example of a communication decryption method:

[0061] like Figure 1 The method described above involves decrypting the second-layer encrypted data. First, counters are created to accumulate the number of bits 0 and 1 respectively. Upon receiving the start code number, the counters are started and cleared. The current bit is inverted based on the number of 0s and 1s in the preceding data bits to obtain the first-layer decrypted data. This decrypted data is then stored. Based on the length of the first-layer decrypted data, it is grouped into sets of 8 bytes. The M bytes of the first-layer decrypted data are sequentially arranged into a register. Starting from the least significant bit in the register, one bit is extracted every M-1 bits, and every 8 extracted bits form a new byte. These new bytes are then sorted sequentially, and the decrypted data is stored in the register. The specific implementation is as follows:

[0062] This embodiment is based on a communication decryption method formed by FPGA real-time communication. The data frame format is frame header + data + frame trailer. In this embodiment, only the data is decrypted, and the frame header, frame trailer and idle code in the channel are not involved in encryption.

[0063] S3) First layer decryption: Count the number of bit0 and bit1, and determine whether the current bit of the output should be inverted based on the number of 0 and 1 in the data bits before the current data bit, so as to obtain the data after the first layer decryption.

[0064] Specifically, a counter cnt0_de that counts 0 and a counter cnt1_de that counts 1 are added to the original transmitting state machine. After receiving the start code, cnt0_de and cnt1_de are started to count, and both counters are cleared to 0.

[0065] If the number of 0s in the data bits preceding the current data bit is greater than the number of 1s, and the number of 0s is odd, then the current bit is inverted; otherwise, it remains unchanged.

[0066] If the number of 1s in the data bits preceding the current data bit is greater than the number of 0s, and the number of 1s is odd, then the current bit is inverted; otherwise, it remains unchanged.

[0067] If the number of 0s and 1s in the data bits preceding the current data bit is equal and not zero, then the current bit is inverted; if the number of 0s and 1s in the data bits preceding the current data bit is equal and zero, then the current bit is left unchanged.

[0068] After data is decrypted, it is stored in a FIFO, RAM, or register, and the length of the decoded data bytes is stored in a length register. For example, as shown in Figures 3(b) and (a), the data stream 00011111 becomes 01110001 after secondary decryption.

[0069] S4) Second-level decryption: Based on the length of the data after the first-level decryption, the data is grouped into M (M=8 in this embodiment) bytes. The bytes in each group are arranged sequentially. Starting from the lowest bit of the first byte of each group or the highest bit of the Mth byte of each group, one bit is extracted every M-1 bits. Every 8 extracted bits form a new byte. The new bytes formed by each group are arranged sequentially, and the data in each group is arranged sequentially to complete the second-level decryption of the encrypted data, restoring it to the unencrypted data. Here, M>1. For ease of hardware processing, M is 8 in this embodiment. In other embodiments, M for each group is not limited to 8.

[0070] The second-layer decryption is similar to the first-layer encryption in communication encryption methods. The decryption method also incorporates a register + FIFO structure and a high-frequency clock to process data and reduce reception latency. When the decoded daily data set fills the 8-byte FIFO or decoding is complete, the high-frequency clock domain decryption state machine quickly reads the empty FIFO and stores it in the decryption register, avoiding data write conflicts. Therefore, the reception latency is at most the decryption time of one data set, effectively ensuring data real-time performance.

[0071] S41) The FPGA design includes 8-byte registers, an 8-byte FIFO, a counter register cnt_8_r with a total count of 8, a receive end register r_fns, a complete decryption end register all_de_fns, a total received data length register r_len, and a suitable decryption state machine using a high-frequency clock. After the data receiving state machine finishes receiving data, register r_fns is set to 1, held for a period of time, then cleared to 0, and the data length register r_len is updated.

[0072] S42) First, obtain the total length N1 of the data to be decrypted based on the data after the first layer of decryption. The start code is not involved in the decryption. Based on the total length N1 of the data to be decrypted, group the data into groups of 8 bytes each. Group the remaining data that is less than 8 bytes into another group.

[0073] S43) First, read the corresponding first set of data from the FIFO, RAM, or register storing the data and store it in a new register:

[0074] S431) When the data set consists of 8 bytes, the decryption method is as follows: extract the first bit of the 8 bytes to form a new word, use the first bit of the first byte as the least significant bit, and the first bit of the eighth byte as the most significant bit, and sort them in sequence. The word formed is the first byte of the decrypted data. Then, arrange the second bits of the 8 bytes in sequence to form the second byte of the decrypted data, and so on, until the eighth bit of the 8 bytes forms the eighth byte of the decrypted data. After the data set is decrypted, store the data in a new FIFO, a new RAM, or a new register to wait for the next step of processing.

[0075] S432) If the data in this group is 1 byte, the data will not be decrypted and will be stored in the next level new FIFO, new RAM or new register for further processing;

[0076] S433) If the number of data bytes M in this group is greater than 1 and less than 8 bytes, the decryption method is as follows: Allocate an M-byte register space in the FPGA, arrange the M bytes sequentially into the newly allocated M-byte register, and then extract 1 bit every M-1 bits starting from the lowest bit in the register. Extract 8 bits to form a byte, and extract them sequentially to form M new bytes. After decrypting the group of data, store the data in a new FIFO, a new RAM, or a new register to await the next step of processing. The current encrypted data is now decrypted. As shown in Figure 2(b), the 2-byte encrypted data is decrypted by extracting 1 bit every 1 bit and then arranging them in order to restore the initial unencrypted data in Figure 2(a).

[0077] In another implementation, when there are M bytes in each group of data (M>1), the highest bit of the Mth byte is extracted from the extraction register as the highest bit of the new byte. Then, one low bit is extracted every M-1 bits and arranged sequentially. Every 8 bits extracted form a new byte. The new bytes formed by each group are arranged sequentially, starting from the Mth byte and proceeding forward until the first byte is arranged. The data groups are arranged sequentially to complete the second layer of decryption of the encrypted data and restore the unencrypted data.

[0078] If the FIFO is full and the receive end register r_fns is 0, it means that the current FIFO group of decrypted data is 8 bytes, and the decryption is not yet complete. The FIFO is read into empty, and the data is stored in the decryption register. Decryption is performed according to the method in step S431), and the FIFO's fullness and r_fns are used to confirm whether to read data and the status transition. If the FIFO is full and the receive end register r_fns is 1, it means that the current FIFO group of decrypted data is 8 bytes, and this is the last group of data. The FIFO is read into empty, and the data is stored in the decryption register. Decryption is performed according to the method in step S431), and the data is stored in the receive RAM. The complete decryption end register all_de_fns is set to 1, and the counter cnt_8_r (total of 8 bytes), the complete decryption end register all_de_fns, and the 8-byte register are cleared to 0.

[0079] If the FIFO is not full and the receive end register r_fns is 1, it means that the decrypted data is less than 8 bytes, and this is the last group of data. The FIFO is read into empty, and the data is stored in the decryption register. The counter cnt_8_r (total of 8 bytes) calculates the number of bytes in this group of data: if the group of data has only 1 byte, it is decrypted according to the decryption method in step S432), and the data is stored in the receive RAM. If the group of data has more than 1 byte, it is decrypted according to the decryption method in step S433), and the data is stored in the receive RAM. The complete decryption end register all_de_fns is set to 1, and the counter cnt_8_r (total of 8 bytes), the complete decryption end register all_de_fns, and the 8-byte register are cleared to 0.

[0080] Communication device example:

[0081] The communication device in this embodiment includes a processor, a memory, a counter, and an internal bus. The processor and memory communicate and exchange data with each other via the internal bus, and the processor and counter also communicate and exchange data with each other via the internal bus. The memory includes at least two storage spaces for storing data to be encrypted, encrypted data, decrypted data, and software programs for encrypting and decrypting the data. The processor processes data by running the software programs stored in the memory, implementing a communication encryption method and a communication decryption method described in the method embodiment of this invention.

[0082] The processor can be a microprocessor (MCU), a programmable logic device (FPGA), or other processing devices. In this embodiment, communication data encryption and decryption are performed based on the FPGA. The FPGA performs both encryption and decryption simultaneously. The data communication method is not limited to electrical or optical media transmission.

[0083] The memory may include RAM, registers, and FIFO. Registers include registers for storing the data to be encrypted, registers for setting the number of bytes during encryption, total number of bytes registers, and decoding registers. The FIFO, with a set length in bytes, stores the encrypted buffered data.

[0084] The counter can count the number of bits 0 and bits 1 in the encrypted data. In this embodiment, an additional counter is added to count the number of bits 0 and the number of bits 1.

[0085] To ensure real-time data transmission, the communication device also includes a state machine, which monitors the current data status in real time when encryption or decryption is initiated. In this embodiment, the state machine is a high-frequency clock domain decryption state machine.

[0086] Specific implementation methods have been given above, but the present invention is not limited to the described implementation methods. The basic idea of ​​the present invention lies in the above basic scheme. For those skilled in the art, designing various modified models, formulas, and parameters based on the teachings of the present invention does not require creative effort. Changes, modifications, substitutions, and variations made to the implementation methods without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A communication encryption method based on FPGA, characterized in that, In the FPGA, a register is set up to store the set byte, which is used to register all the bits of the set byte. A FIFO for the set byte, a total byte count register, and a counter register are also set up, including the following steps: The system acquires the data to be encrypted in real time, groups the data into sets of bytes, and groups the remaining data into sets of actual bytes. Each time a byte is read, it is stored in a register, and the counts in the counter register and the total number of bytes register are incremented by 1. When the count in the counter register equals the set number of bytes, or when 1 byte < the count in the counter register < the set number of bytes and the count in the total number of bytes register equals the length of the data to be encrypted, encryption is performed, and the system checks whether the FIFO is empty. If it is not empty, the system waits; if it is empty, the encrypted data is stored in the FIFO, the counter register is cleared, and the system continues to acquire the data to be encrypted until all the data to be encrypted is encrypted. The encryption method is as follows: Extract the bits of each byte in each group, rearrange them in a set order, and truncate the rearranged data bits into corresponding bytes to complete the first layer of encryption; count the number of bit 0 and bit 1 after the first layer of encryption. If the number of 0 and 1 in the data bits before the current data bit is equal and not zero, then the current bit is inverted; if the number of 0 and 1 in the data bits before the current data bit is equal and zero, then the current bit is kept. If the number of 0 and 1 in the data bits before the current data bit is not equal, and the number of the bit with the larger number is odd, then the current bit is inverted; if the number of the bit with the larger number is even, then the current bit is kept, thus obtaining the encrypted data.

2. The FPGA-based communication encryption method according to claim 1, characterized in that, The order is set so that the first byte to the first bit of the last byte of the data to be encrypted in each group is sorted sequentially, and the second bit of the first byte to the last byte is placed after the first bit of the last byte, until the eighth bit of the first byte to the last byte is sorted sequentially. The data to be encrypted in each group is arranged sequentially.

3. The FPGA-based communication encryption method according to claim 2, characterized in that, When the data frame format adopts the form of frame header + data + frame trailer, only the data in the data frame format is encrypted.

4. The FPGA-based communication encryption method according to claim 2, characterized in that, The specified byte is 8 bytes.

5. The FPGA-based communication encryption method according to any one of claims 1-4, characterized in that, If the data packet is only 1 byte and the total number of bytes register is equal to the length of the data to be encrypted, then the data packet will not be encrypted at the first layer.

6. A communication decryption method based on FPGA, characterized in that, The encrypted data is obtained by encrypting the FPGA-based communication encryption method described in claim 1. The communication decryption method includes the following steps: A) Count the number of bits 0 and 1 in the encrypted data. If the number of 0s and 1s in the data bits preceding the current data bit is equal and not zero, then invert the current bit. If the number of 0s and 1s in the data bits preceding the current data bit is equal and not zero, then keep the current bit. If the number of 0s and 1s in the data bits preceding the current data bit is not equal, and the number of the bit with the larger number of 0s and 1s is odd, then invert the current bit. If the number of the bit with the larger number of 0s and 1s is even, then keep the current bit. This yields the data after the first layer of decryption. B) Based on the length of the data after the first layer of decryption, group the data after the first layer of decryption into groups of M bytes. If the remaining data is less than the set number of bytes, group it into actual bytes. Arrange the bytes in each group sequentially. Starting from the lowest bit of the first byte of each group or the highest bit of the last byte of each group, extract 1 bit every interval of the number of bytes in that group - 1 bit. Combine 8 extracted bits into a new byte. Arrange the new bytes formed by each group sequentially. Arrange the data in each group sequentially to complete the second layer of decryption of the encrypted data and restore it to the unencrypted state, where M > 1.

7. The FPGA-based communication decryption method according to claim 6, characterized in that, M=8。 8. The FPGA-based communication decryption method according to claim 6 or 7, characterized in that, If the packet data formed after the first decryption is only 1 byte, then the packet data will not be decrypted.

9. The FPGA-based communication decryption method according to claim 7, characterized in that, The data during decryption is stored in a FIFO, RAM, or register.

10. A communication device based on an FPGA, comprising an FPGA, a memory, and a counter, characterized in that, The FPGA is used to execute control instructions to implement the communication encryption method as described in claims 1-5 and the communication decryption method as described in any one of claims 6-9. The memory is used to store the data to be encrypted, the encrypted data, and the decrypted data. The counter is used to count the number of bit 0 and bit 1 in the encrypted data.

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