Image processing circuit and electronic device

Abstract

The present disclosure provides an image processing circuit and an electronic device, wherein the image processing circuit comprises a delay module, an identification module and an adjustment module. Firstly, the image processing circuit is used to identify the pixel value change of each pixel point in each row, so as to determine the change identification sequence corresponding to each row of pixel points. Since the change identification sequence includes the change identification corresponding to each pixel point, each row of pixel points can be divided into different segments (such as high-frequency change segment or low-frequency change segment) according to the change condition based on the change identification sequence, and then different processing methods can be adopted for different segments. Thus, the problem that the low-frequency region is not obvious enough after being processed or the visual effect is too messy after the high-frequency region is processed can be avoided when the same image processing algorithm is applied to the whole row.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more particularly to an image processing circuit and electronic device. Background Technology

[0002] Currently, video image processing is often performed on a line-by-line basis. However, applying the same image processing algorithm to an entire line can lead to poor image processing results. Summary of the Invention

[0003] This disclosure proposes an image processing circuit and electronic device. The specific solution is as follows:

[0004] The first aspect of this disclosure provides an image processing circuit, comprising:

[0005] Delay module, recognition module, and adjustment module;

[0006] The input terminal of the delay module is connected to the first input terminal of the recognition module, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed;

[0007] The delay module is used to delay each received pixel value for a first duration before outputting it to the second input terminal of the recognition module;

[0008] The identification module is used to determine the change identifier corresponding to the first pixel value based on the relationship between the difference between the first pixel value received by the first input terminal and the second pixel value received by the second input terminal and the difference threshold, and output the change identifier to the adjustment module;

[0009] The adjustment module is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition.

[0010] Another embodiment of this disclosure provides an electronic device including the image processing circuit described above.

[0011] The image processing circuit and electronic device of this disclosure include a delay module, a recognition module, and an adjustment module. First, the image processing circuit identifies the pixel value changes of each pixel on a row-by-row basis to determine the change identifier sequence corresponding to each row of pixels. Since the change identifier sequence includes the change identifier corresponding to each pixel, each row of pixels can be divided into different segments (e.g., high-frequency change segments or low-frequency change segments) based on the change identifier sequence. Different processing methods can then be applied to different segments. This avoids the problem that when the same image processing algorithm is applied to an entire row, the effect may be insufficient after processing low-frequency areas, or the visual effect may be too cluttered after processing high-frequency areas. Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a schematic diagram of the structure of an image processing circuit provided in an embodiment of the present disclosure;

[0014] Figure 2 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure;

[0015] Figure 3 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure;

[0016] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0017] The embodiments disclosed herein are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0018] In related technologies, image processing is performed on a line-by-line basis when processing video images. However, using the same image processing algorithm for an entire line may result in insufficient effect after processing low-frequency areas, or excessive visual clutter after processing high-frequency areas.

[0019] This disclosure addresses the above-mentioned problems by proposing an image processing circuit that, during the processing of a video image, identifies the pixel value sequence corresponding to each row of pixels in the image, classifying each row of pixels into low-frequency and high-frequency pixels. This allows for the application of different processing methods to different pixels. Consequently, this provides the means to process images with finer granularity and improve image processing results.

[0020] The image processing circuit provided in this disclosure will now be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the structure of an image processing circuit provided in an embodiment of the present disclosure.

[0022] like Figure 1 As shown, the image processing circuit includes: a delay module 101, a recognition module 102, and an adjustment module 103.

[0023] The input terminal of the delay module 101 is connected to the first input terminal of the recognition module 102, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed;

[0024] The delay module 101 is used to delay each received pixel value for a first duration and then output it to the second input terminal of the recognition module 102.

[0025] The identification module 102 is used to determine the change identifier corresponding to the first pixel value based on the relationship between the difference between the first pixel value received by the first input terminal and the second pixel value received by the second input terminal and the difference threshold, and output the change identifier to the adjustment module 103.

[0026] The adjustment module 103 is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition.

[0027] A pixel value sequence is a sequence of pixel values ​​corresponding to each row of pixels in an image. For example, if an image consists of 100 rows of pixels, then it will form 100 pixel value sequences.

[0028] The first duration can be any preset time length. In some possible implementations, the first duration can be the length of one cycle of the clock signal in the image processing circuit, or the length of several clock signal cycles.

[0029] Furthermore, the first pixel value is the pixel value in the pixel value sequence input to the first input terminal of the recognition module 102 in the image to be processed. The second pixel value is the pixel value in the pixel value sequence input to the second input terminal of the recognition module 102 after a delay of the first duration by the delay module 101. The difference threshold is a preset critical value used to determine the different change indicators corresponding to the first pixel value, and can be 5, 6, 7, etc., which is not limited in this disclosure.

[0030] The change flag is used to identify the change in the value of the first pixel relative to the value of the second pixel. For example, if the difference between the first pixel value and the second pixel value is greater than or equal to a difference threshold, the change flag is set to 0, indicating that the change in the first pixel value is relatively large compared to the second pixel value; if the difference between the first pixel value and the second pixel value is less than the difference threshold, the change flag is set to 1, indicating that the change in the first pixel value is relatively small, and so on. This disclosure does not limit the specific implementation of the change flag.

[0031] It should be noted that, in order to divide the image into finer granularities in this disclosure, the delay module 101 can delay each pixel value by the transmission time of each pixel value in the pixel value sequence, so that the first pixel value and the second pixel value processed by the recognition module 102 are two adjacent pixel values ​​in the same row of pixel values.

[0032] The first preset condition is a pre-defined condition used to determine whether the change identifier corresponding to each pixel needs to be adjusted. In this disclosure, the change identifier corresponding to each pixel is used to identify the change of that pixel relative to its adjacent preceding pixel. Simultaneously (except for the last pixel), each pixel is also the basis for determining the change identifier of the next adjacent pixel. If the change identifiers corresponding to multiple consecutive pixels are inconsistent, the change identifier determined by the pixel difference between a certain pixel and its preceding pixel will differ from the change identifier determined by the pixel difference between its adjacent following pixel. If the image is divided into high-frequency and low-frequency regions at the pixel granularity, it will not only reduce the accuracy of region division but also increase the complexity of the overdrive compensation process. Therefore, in this disclosure, the consistency of the changes of multiple consecutive pixels can be used to determine whether the consecutive pixels are high-frequency or low-frequency pixels. Therefore, the first preset condition can be a set distance threshold. That is, based on the first preset condition, if the change identifiers corresponding to multiple pixels within any distance threshold range in the change identifier sequence are inconsistent, the change identifier corresponding to the pixel that needs adjustment can be adjusted.

[0033] For example, if the distance threshold corresponding to the first preset condition is 4, a change identifier of 0 for a pixel indicates a significant change in pixel value compared to the previous pixel value, while a change identifier of 1 indicates a relatively small change. In this case, if a segment of the change identifier sequence contains "010101111", this segment contains both "1" and "0". Although the first four change identifiers contain both "1" and "0", the consecutive repetitions of 1 and 0 are less than 4, meaning the first preset condition is not met. Since the change of identifier 1 is relatively small, the adjustment module 103 can adjust identifier "1" to 0 before outputting this segment of change identifiers. The adjusted output change sequence identifier might be "000001111", which divides this part of the pixels into pixels with larger changes (high-frequency region) and pixels with smaller changes (low-frequency region).

[0034] In this disclosure, by utilizing an image processing circuit, the pixel value changes of each pixel are first identified on a row-by-row basis to determine the change identifier sequence corresponding to each row of pixels. Then, based on the change identifier sequence and a first preset condition, change identifiers that do not meet the first preset condition are adjusted before being output. This allows each row of pixels to be directly divided into different segments (such as high-frequency change segments or low-frequency change segments) based on the adjusted change identifier sequence, enabling different processing methods to be applied to different segments. This avoids the problem that when the same image processing algorithm is applied to an entire row, the effect of processing low-frequency areas may be insufficient, or the visual effect of processing high-frequency areas may be too cluttered.

[0035] In some possible implementations, the image processing circuit may include a clock module 104 connected to the delay module 101. The delay module is used to determine the first duration based on the period of the clock signal output by the received clock module.

[0036] In this disclosure, the delay module 101 determines a first duration by receiving a clock cycle signal input from the clock module 104, for example, the first duration being the length of one clock cycle signal. During the first clock cycle, the first pixel value in the pixel value sequence is input to both the recognition module 102 and the delay module 101; during the second clock cycle, the second pixel value in the pixel value sequence is input to both the recognition module 102 and the delay module 101, while the delay module 101 inputs the first pixel value to the recognition module 102; during the third clock cycle, the third pixel value in the pixel value sequence is input to both the recognition module 102 and the delay module 101, while the delay module 101 inputs the second pixel value to the recognition module 102, and so on. In each clock cycle, a new pixel value in the pixel value sequence is input to the recognition module 102. At the same time, the delay module 101 inputs the previous pixel value adjacent to the new pixel value to the recognition module 102, thereby ensuring that the recognition module 102 can obtain two adjacent pixel values ​​in the pixel value sequence. Then, the recognition module 102 can determine the change identifier of the new pixel value based on the change value between the new pixel value and the adjacent previous pixel value.

[0037] In some possible implementations, the identification module 102 can be used to determine the change identifier corresponding to the first pixel value as a first identifier when the difference between the first pixel value and the second pixel value is greater than a difference threshold; or, when the difference between the first pixel value and the second pixel value is less than or equal to a difference threshold, determine the change identifier corresponding to the first pixel value as a second identifier.

[0038] The specific forms of the first and second identifiers can be set as needed, such as the first identifier being "0" and the second identifier being "1", or the first identifier being "1" and the second identifier being "0", etc. This disclosure does not limit this.

[0039] In this disclosure, the identification module 102 performs a difference operation on the received first pixel value and the second pixel value, compares the difference result with the difference threshold, and then determines the change identifier corresponding to the first pixel value based on the relationship between the two, providing conditions for the subsequent adjustment module 103 to perform further operations on the sequence.

[0040] For example, the difference threshold is 5. The pixel value sequence of the input recognition module 102 contains pixel values ​​of 60. That is, the difference between each first pixel value and the second pixel value obtained by the recognition module 102 is 0, which is less than the difference threshold. Therefore, the recognition module 102 can determine that the identifier of the pixel point corresponding to each pixel value in the pixel value sequence is the second identifier.

[0041] In some possible implementations, the image processing circuit may further include a setting module 105 connected to both the recognition module 102 and the adjustment module 103. This setting module 105 is used to determine the difference threshold and the first preset condition based on the acquired configuration information, and to synchronize the difference threshold to the recognition module 102 and the first preset condition to the adjustment module 103.

[0042] The configuration information can be parameters that the user configures as needed, or parameters that the setting module determines based on historical data from the image processing circuit. This disclosure does not limit this.

[0043] For example, the setting module 105 determines the difference threshold to be 5 based on the acquired configuration information, and the distance threshold corresponding to the first preset condition is 4. The setting module 105 can then send the difference threshold of 5 to the recognition module 102, so the recognition module 102 can determine the change identifier corresponding to each pixel value based on this difference threshold and the difference between each pixel value and its adjacent previous pixel value. Simultaneously, the adjustment module 103 receives the distance threshold of 4 corresponding to the first preset condition from the setting module 105. Therefore, the adjustment module 103 can determine whether each change identifier in the change identifier sequence received from the recognition module 102 needs adjustment based on this first preset condition, and adjust the change identifiers that need adjustment before outputting them.

[0044] In some possible implementations, the image processing circuit may further include an overdrive compensation module 106 connected to the adjustment module 103, which is used to determine the first set of pixels and the second set of pixels contained in each row of pixels according to the change identifier sequence corresponding to each row of pixels output by the adjustment module 103, and to perform overdrive compensation on the pixels in the first set of pixels based on a first compensation algorithm, and to perform overdrive compensation on the pixels in the second set of pixels based on a second compensation algorithm.

[0045] Overdrive compensation is an image quality compensation algorithm. The first set of pixels represents the set of pixels with low-frequency changes. The second set of pixels represents the set of pixels with high-frequency changes.

[0046] The first compensation algorithm is for the first set of pixels. The second compensation algorithm is for the second set of pixels.

[0047] For example, in the change identifier sequence adjusted by adjustment module 103, a segment of the change identifier is "00001111". Here, a change identifier of 0 for a pixel indicates a significant change in pixel value compared to the previous pixel, while a change identifier of 1 indicates a relatively small change. After obtaining this change identifier sequence, overdrive compensation module 106 can determine that the first four digits "0000" represent pixels with significant changes (i.e., the first four digits form the second set of pixels), and the last four digits "1111" represent pixels with smaller changes (i.e., the first set of pixels). Therefore, the second compensation algorithm is used to compensate for overdrive in the first four pixels corresponding to this change identifier, and the first compensation algorithm is used for the last four pixels. This allows different algorithms to be used to process different parts of the same row of pixels, further refining the granularity of image processing and improving the image processing effect.

[0048] Figure 2 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure.

[0049] like Figure 2 As shown, the adjustment module 103 in the image processing circuit provided in this disclosure includes an N-bit shift register 201, a data selector 202, and a logic gate processing component 203, wherein N is an integer greater than 1.

[0050] like Figure 2 As shown, the output of each shift register in the N-shift register 201 is connected to one input of the logic gate processing component 203, and the output of the Nth shift register in the N-shift register 201 is connected to one input of the data selector 202.

[0051] The output terminal of the logic gate processing component 203 is connected to the control terminal of the data selector 202;

[0052] Another input terminal of the data selector 202 is used to receive a preset level value;

[0053] The logic gate processing component 203 is used to determine whether the change flag in the Nth register is a flag that satisfies the first preset condition based on the output value of each register in the Nth shift register 201, and based on the determination result, control the data selector 202 to output the value output by the shift register 201 or output the preset level value.

[0054] The preset level value is the level value that the adjustment module 103 needs to adjust to when adjusting the change indicator. For example, the preset level value can be 0, and this disclosure does not limit it.

[0055] In this disclosure, after receiving the change identifier sequence, the adjustment module 103 retains and outputs the change identifiers that meet the first preset conditions based on the change identifier sequence and according to the different changes of each row of pixels, and adjusts and outputs the change identifiers that do not meet the conditions.

[0056] In some possible implementations, the logic gate processing component 203 includes N AND gates (such as...). Figure 2 The module indicated by the "&" symbol in the diagram), and three NOT gates (such as... Figure 2 The "!" symbol in the text indicates a module, and an OR gate circuit (such as...). Figure 2 (The module indicated by the "≥1" symbol), a shifter 203a and a counter 203b.

[0057] The first input terminal of the first AND gate is connected to the output terminal of the second shift register, and the second input terminal is connected to the output terminal of the first shift register;

[0058] The first input of the i-th AND gate is connected to the output of the (i+1)-th shift register, and the second input of the i-th AND gate is connected to the output of the (i-1)-th AND gate, where i is a value greater than 1 and less than N.

[0059] The first input of the (N-1)th AND gate is connected to the output of the Nth shift register through the first NOT gate, and the second input is connected to the output of the (N-2)th AND gate. The output of the (N-1)th AND gate is connected to the first input of the OR gate.

[0060] The first input terminal of the Nth AND gate is connected to the output terminal of the Nth shift register, the second input terminal is connected to the output terminal of the (N-2)th AND gate through the second NOT gate, and the output terminal of the Nth AND gate is connected to the second input terminal of the OR gate.

[0061] The other output of the first NOT gate is connected to the third input of the OR gate;

[0062] The output of the OR gate is connected to the third input of the Nth AND gate through the shifter, and to the input of the counter through the third NOT gate.

[0063] The maximum count value of the counter 203b is N, where N is a first preset condition value.

[0064] The first input is the right-hand input of the AND gate. The second input is the left-hand input of the AND gate.

[0065] For example, such as Figure 3As shown, if the change sequence of the input adjustment module 103 is "01011111", N is 4, the value of the shifter 203a is the value output by the OR gate after the previous logic calculation, for example, 1.

[0066] The following is combined Figure 3 Taking N=4 as an example, the structure of the adjustment module provided in this disclosure will be further explained. Figure 3As shown, if the identifier sequence input to the adjustment module 103 is "01011111", the value stored in shifter 203a is the value output by the OR gate after the previous logic calculation, for example, 1. The currently received change identifiers in the 4-bit shift registers FF1, FF2, FF3, and FF4 of the adjustment module 103 are 1, 0, 1, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 1, and shifter 203a is updated, storing the value output by the OR gate. After the OR gate output value of 1 is processed by the NOT gate, the output is 0, meaning that rst_n is 0, the counter is reset to 0, and the data selector 202 outputs the preset level value "0". In the next cycle, the values ​​of the 4-bit shift registers FF1, FF2, and FF3 are all shifted forward by one bit, and a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 1, 1, 0, and 1 respectively, and the value of shifter 203a is 1. After calculation by the logic circuit, the OR gate outputs 1, shifter 203a is updated, storing the value output by the OR gate. rst_n remains 0, the counter remains in the reset state, and the output is 0. Data selector 202 still outputs the preset level value "0". Next, the values ​​of shift registers FF1, FF2, and FF3 are shifted forward by one bit, and a new sequence flag "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 1, 1, 1, and 0 respectively, and the value of shifter 203a remains 1. After calculation by the logic circuit, the OR gate outputs 1, shifter 203a is updated, storing the value output by the OR gate. rst_n remains 0, the counter remains in the reset state, and the output is 0. Data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of shift registers FF1, FF2, and FF3 are all shifted forward by one bit, and a new sequence flag "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 1, 1, 1, and 1 respectively, and the value of shifter 203a is 1. After calculation by the logic circuit, the OR gate outputs 0, shifter 203a is updated, storing the value output by the OR gate, rst_n is 1, the counter value is incremented by 1, the output count value is 1, and data selector 202 selects the value in shift register FF4 for output, that is, the output value of data selector 202 is "1". Through the above analysis, it can be seen that "0101" in the change flag sequence "01011111" input to adjustment module 103 is processed and the output becomes 0001.

[0067] If the identifier sequence input to adjustment module 103 is "01011100", the value stored in shifter 203a is the value output by the OR gate after the previous logic calculation, for example, 1. The currently received change identifiers in the 4-bit shift registers FF1, FF2, FF3, and FF4 of adjustment module 103 are 1, 0, 1, and 0 respectively. After logic circuit calculation, the OR gate outputs 1, and shifter 203a is updated, storing the value output by the OR gate. The OR gate output value of 1 is processed by the NOT gate, resulting in an output of 0. This means that rst_n is 0, the counter is reset to 0, and data selector 202 outputs the preset level value "0". In the next cycle, the values ​​of shift registers FF1, FF2, and FF3 are all shifted forward by one bit, and a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 1, 1, 0, and 1 respectively, and the value of shifter 203a is 1. After calculation by the logic circuit, the OR gate outputs 1, shifter 203a is updated, storing the value output by the OR gate. rst_n remains 0, the counter remains in the reset state, and the output is 0. Data selector 202 still outputs the preset level value "0". Next, the values ​​of shift registers FF1, FF2, and FF3 are shifted forward by one bit, and a new sequence flag "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 1, 1, 1, and 0 respectively, and the value of shifter 203a remains 1. After calculation by the logic circuit, the OR gate outputs 1, shifter 203a is updated, storing the value output by the OR gate. rst_n remains 0, the counter remains in the reset state, and the output is 0. Data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of shift registers FF1, FF2, and FF3 are all shifted forward by one bit, and a new sequence flag "0" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, and FF4 are 0, 1, 1, and 1 respectively, and the value of shifter 203a is 1. After calculation by the logic circuit, the OR gate outputs 1, shifter 203a is updated, storing the value output by the OR gate, rst_n remains 0, the counter remains in the reset state, the output bit is 0, and the data selector 202 still outputs the preset level value "0". Through the above analysis, it can be seen that "0101" in the change flag sequence "01011100" input to the adjustment module 103 is processed and the output becomes 0000.

[0068] As the above analysis shows, whether each change flag (the value in shift register FF4 within each cycle) will be output by data selector 202 depends not only on the current value in each shift register, but also on the value stored in shifter 203a, which stores the output value of the OR gate in the previous cycle. In other words, whether each change flag will be adjusted depends not only on its adjacent next few change flags, but also on its adjacent first few change flags.

[0069] In summary, when the adjustment module 103 receives the change identifier sequence, it directly outputs the corresponding change identifier for pixels that meet the first preset condition. For pixels that do not meet the first preset condition, the corresponding change identifier is adjusted to "0" before output. For example, if the distance threshold set for the first preset condition is 4, in the change identifier sequence "01011100", the number of consecutive repetitions of the first four "0" and "1" is less than 4, and the number of pixels with a change identifier of "1" in the consecutive pixels after the fourth pixel does not meet the distance threshold, therefore, the identifier "1" in the first four bits will be adjusted to "0".

[0070] In some possible implementations, the adjustment module 103 further includes a data adjustment unit 204 connected to the output of the data selector 202, which is used to adjust the first identifier in the identifier sequence output by the data selector 202 that meets the second preset condition to the second identifier before outputting it.

[0071] The second preset condition is a pre-defined condition used to determine whether the change identifier corresponding to each pixel needs further adjustment. Since each change identifier in the identifier sequence output by the data selector 202 is an identifier adjusted according to the distance threshold configured by the first preset condition, each change identifier in the identifier sequence output by the data selector 202 must be the same as its several adjacent change identifiers. In this case, if the change identifier corresponding to a certain pixel in the identifier sequence output by the data selector 202 is 0, and the change identifier corresponding to its adjacent next pixel is 1, it means that the change of the next pixel relative to the previous pixel is not significant. Therefore, the change of the previous pixel relative to the next pixel can also be considered not significant. In this case, to avoid visual clutter after processing the previous pixel as a high-frequency pixel, in this disclosure, its corresponding change identifier can be adjusted to "1" to perform overdrive compensation on the previous pixel as a low-frequency pixel. That is, the second preset condition can be that the first identifier is "0", and the change identifier corresponding to its adjacent next pixel is "1", and the corresponding second identifier after adjusting the first identifier is "1".

[0072] For example, if the change identifier sequence output by data selector 202 to data adjustment unit 204 is "00001111", the change identifier corresponding to the fourth pixel is "0", and the change identifiers of subsequent pixels are all "1". That is, in this sequence, the fourth pixel has little change compared to the third pixel, and therefore little change compared to the fifth pixel. Thus, using subsequent pixels as a reference, the third pixel can be considered a pixel with little change, and its corresponding change identifier "0" can be adjusted to "1". Therefore, the change identifier sequence "00001111" input to data adjustment unit 204, after adjustment, outputs as "00011111".

[0073] In this disclosure, when the data adjustment unit 204 adjusts the change identifier sequence, for a pixel with a change identifier of "0", if multiple consecutive pixels following it that meet the second preset condition all have change identifiers of "1", the pixel can be considered to meet the requirement, and its corresponding change identifier is adjusted to "1". If the number of consecutive pixels following the pixel with a corresponding change identifier of "1" does not meet the second preset condition, the pixel can be considered to not meet the requirement, and its corresponding change identifier is not adjusted. Thus, the data adjustment unit 204 further adjusts the division of pixels in each row, further improving the accuracy of pixel division in each row, thereby providing conditions for more accurate image processing.

[0074] In the image processing circuit provided in this embodiment, the pixel value changes of each pixel are identified on a row-by-row basis to determine the change identifier sequence corresponding to each row of pixels. Based on preset conditions, the change identifiers in the change identifier sequence that meet the conditions are adjusted to divide each row of pixels into different segments (such as high-frequency change segments or low-frequency change segments). Different processing methods can then be applied to different segments. This further refines the granularity of image processing and improves the quality and effect of the processed image.

[0075] Based on the image processing circuit provided in the above embodiments, this disclosure also provides an electronic device, including the image processing circuit provided in the above embodiments.

[0076] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0077] like Figure 4 As shown, the electronic device 400 may include an image processing circuit 401 and a display component 402.

[0078] The structure of the image processing circuit 401 and the image processing process can be described in detail in other embodiments of this disclosure, and will not be repeated here.

[0079] In this disclosure, the image processing circuit 401 can process the image to be displayed, and then display it through the display component 402, thereby improving the quality and effect of the image displayed by the display component 402.

[0080] In some possible implementations, the electronic device 400 may also include a transceiver, a processor, a memory, etc.

[0081] The transceiver can be used to obtain the task to be run and its configuration information.

[0082] The processor executes computer instructions stored in memory. A processor can be a general-purpose processor, including a Central Processing Unit (CPU) and a network processor (NP); it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0083] The memory is connected to the processor via the system bus and communicates with it. The memory is used to store computer program instructions.

[0084] The system bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus. Transceivers are used to enable communication between database access devices and other computers (e.g., clients, read-write libraries, and read-only libraries). Memory may include random access memory (RAM) and may also include non-volatile memory.

[0085] The electronic device provided in this disclosure can be the terminal device described in the above embodiments.

[0086] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

[0087] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An image processing circuit, characterized in that, include: Delay module, recognition module, and adjustment module; The input terminal of the delay module is connected to the first input terminal of the recognition module, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed; The delay module is used to delay each received pixel value for a first duration before outputting it to the second input terminal of the recognition module; The identification module is used to determine the change identifier corresponding to the first pixel value based on the relationship between the difference between the first pixel value received by the first input terminal and the second pixel value received by the second input terminal and the difference threshold, and output the change identifier to the adjustment module; The adjustment module is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition. The first preset condition is a set distance threshold. When the change identifiers corresponding to multiple pixels within the distance threshold range in the change identifier sequence are inconsistent, the change identifiers corresponding to the pixels that need to be adjusted are adjusted. The adjustment module includes: an N-bit shift register, a data selector, and a logic gate processing component, where N is an integer greater than 1; The output of each shift register in the N-bit shift register is connected to one input of the logic gate processing component, and the output of the Nth shift register in the N-bit shift register is connected to one input of the data selector. The output of the logic gate processing component is connected to the control terminal of the data selector. Another input terminal of the data selector is used to receive a preset level value; The logic gate processing component is used to determine whether the change flag in the Nth register is a flag that satisfies the first preset condition based on the output value of each register in the Nth shift register, and based on the determination result, control the data selector to output the value output by the shift register or output the preset level value.

2. The circuit as described in claim 1, characterized in that, Also includes: The clock module connected to the delay module; The delay module is used to determine the first duration based on the period of the clock signal output by the received clock module.

3. The circuit as described in claim 1, characterized in that, Also includes: A setting module that is connected to both the identification module and the adjustment module; The setting module is used to determine the difference threshold and the first preset condition based on the acquired configuration information, and synchronize the difference threshold to the identification module and the first preset condition to the adjustment module.

4. The circuit as described in claim 1, characterized in that, The identification module is specifically used for: If the difference between the first pixel value and the second pixel value is greater than the difference threshold, the change identifier corresponding to the first pixel value is determined to be the first identifier; or... If the difference between the first pixel value and the second pixel value is less than or equal to the difference threshold, the change identifier corresponding to the first pixel value is determined to be the second identifier.

5. The circuit as described in claim 1, characterized in that, The adjustment module also includes a data adjustment unit connected to the output of the data selector; The data adjustment unit is used to adjust the first identifier in the identifier sequence output by the data selector that meets the second preset condition to the second identifier before outputting it.

6. The circuit as described in claim 1, characterized in that, The logic gate processing component includes N AND gates, three NOT gates, one OR gate, one shifter, and a counter. The first input terminal of the first AND gate is connected to the output terminal of the second shift register, and the second input terminal is connected to the output terminal of the first shift register; The first input of the i-th AND gate is connected to the output of the (i+1)-th shift register, and the second input of the i-th AND gate is connected to the output of the (i-1)-th AND gate, where i is a value greater than 1 and less than N. The first input of the (N-1)th AND gate is connected to the output of the Nth shift register through the first NOT gate, and the second input is connected to the output of the (N-2)th AND gate. The output of the (N-1)th AND gate is connected to the first input of the OR gate. The first input terminal of the Nth AND gate is connected to the output terminal of the Nth shift register, the second input terminal is connected to the output terminal of the (N-2)th AND gate through the second NOT gate, and the output terminal of the Nth AND gate is connected to the second input terminal of the OR gate. The other output of the first NOT gate is connected to the third input of the OR gate; The output of the OR gate is connected to the third input of the Nth AND gate through the shifter, and to the input of the counter through the third NOT gate.

7. The circuit as described in claim 6, characterized in that, The maximum count value of the counter is N.

8. The circuit as described in any one of claims 1-6, characterized in that, It also includes: an overdrive compensation module connected to the adjustment module; The overdrive compensation module is used to determine the first set of pixels and the second set of pixels contained in each row of pixels according to the change identifier sequence corresponding to each row of pixels output by the adjustment module, and to perform overdrive compensation on the pixels in the first set of pixels based on the first compensation algorithm, and to perform overdrive compensation on the pixels in the second set of pixels based on the second compensation algorithm.

9. An electronic device, characterized in that, Includes the image processing circuit as described in any one of claims 1-8.

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