Driving method, driving circuit and display device

Abstract

The application discloses a driving method, a driving circuit and a display device. The driving method comprises the following steps: sequentially dividing the display area into a first display area and a second display area along the transmission direction of a data signal; continuously inputting a first scanning voltage and a second scanning voltage to the conduction of a thin film transistor corresponding to a scanning line in the first display area in one scanning period of the scanning line in the first display area; continuously inputting a third scanning voltage and a fourth scanning voltage to the conduction of a thin film transistor corresponding to a scanning line in the second display area in one scanning period of the scanning line in the second display area; the voltage value of the first scanning voltage is greater than the voltage value of the second scanning voltage, and the voltage value of the third scanning voltage is less than the voltage value of the fourth scanning voltage. The application changes the charging capacity of the pixels at the far end and the near end of the data signal input end, reduces the brightness difference between the pixels, and makes the brightness of the whole display area uniform.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method, driving circuit and display device. Background Technology

[0002] LCD monitors are the mainstream products in the LCD display field today. The display effects of LCD monitors, such as brightness, contrast, color, and viewing angle, are mainly determined by the display panel. 80% of the cost of an LCD monitor is also concentrated in the display panel. Therefore, the display panel is the main factor that determines the quality and cost of an LCD monitor.

[0003] With the development of science and technology and the needs of daily life, TV sizes are getting larger and larger, and resolutions are getting higher and higher. New driving architectures are also emerging one after another. Taking a 55-inch 4K dual-gate drive as an example, the number of data lines is reduced by increasing the number of scan lines, thereby reducing the number of COFs and reducing costs. However, the disadvantage is that the charging time of each pixel is reduced by half. In addition, due to the impedance of the wiring and parasitic capacitance, the pixels in the display area far from the data signal input end are not charged enough, resulting in uneven display of the entire display area and unsatisfactory display effect, which greatly affects the viewing experience. Summary of the Invention

[0004] The purpose of this application is to provide a driving method, driving circuit, and display device, which aims to solve the problem of uneven display in the display area of ​​the display panel at the near end and far end of the data signal input terminal.

[0005] This application discloses a driving method for a display panel, the display panel including a display area and a non-display area, the non-display area being disposed around the display area, the driving method including the following steps:

[0006] Along the direction of data signal transmission, the display area is sequentially divided into a first display area and a second display area;

[0007] During one scan cycle of a scan line within the first display area, a first scan voltage and a second scan voltage are continuously input to the scan line within the first display area to control the conduction of the thin-film transistor corresponding to the scan line; and

[0008] During one scan cycle of the scan line in the second display area, a third scan voltage and a fourth scan voltage are continuously input to the scan line in the second display area to control the conduction of the thin-film transistor corresponding to the scan line;

[0009] Wherein, the voltage value of the first scanning voltage is greater than the voltage value of the second scanning voltage, and the voltage value of the third scanning voltage is less than the voltage value of the fourth scanning voltage.

[0010] Optionally, the input of the data signal is controlled by a latch signal, and the step of continuously inputting a third scan voltage and a fourth scan voltage to the scan line in the second display area within one scan cycle to control the conduction of the thin-film transistor corresponding to the scan line includes:

[0011] A target latch signal is generated based on the original latch signal, and the output of the data signal is controlled by the target latch signal.

[0012] The pixels connected to the thin-film transistors corresponding to the scan lines are charged according to the third scan voltage, the fourth scan voltage, and the voltage of the data signal.

[0013] In this display area, the output of the data signal is controlled by the original latch signal, and the output of the data signal is controlled by the target latch signal. For the same pixel, the charging end time corresponding to the target latch signal is later than the charging end time corresponding to the original latch signal.

[0014] Optionally, the voltage value of the first scanning voltage is equal to the voltage value of the fourth scanning voltage, and the voltage value of the second scanning voltage is equal to the voltage value of the third scanning voltage; the input duration of the first scanning voltage is equal to the input duration of the third scanning voltage, and the input duration of the second scanning voltage is equal to the input duration of the fourth scanning voltage.

[0015] Optionally, the duration between the charging start times of the latch signals corresponding to the last scan line of the first display area and the first scan line of the second display area is greater than the duration between the charging start times of the original latch signals or target latch signals corresponding to two adjacent scan lines.

[0016] Optionally, the display area has m scan lines, and the step of dividing the display area into a first display area and a second display area sequentially along the data signal transmission direction includes:

[0017] The detection frame start signal is calculated sequentially according to the scanning order of the scan lines. The first scan line is counted as 1. When the count is n, the counting stops. The display area corresponding to the first n scan lines is divided into the first display area, and the display area corresponding to the scan lines after n lines is divided into the second display area.

[0018] Where m / 2-a≤n≤m / 2+a, a<n<m, and m, n, and a are natural numbers.

[0019] Optionally, within the second display area, in any two adjacent rows of scan lines, the third scan voltage corresponding to the scan line closer to the first display area is different from the third scan voltage corresponding to the scan line farther from the first display area, and the fourth scan voltage corresponding to the scan line closer to the first display area is the same as the fourth scan voltage corresponding to the scan line farther from the first display area.

[0020] The absolute value of the difference between the third and fourth scan voltages corresponding to the scan lines closer to the first display area is greater than the absolute value of the difference between the third and fourth scan voltages corresponding to the scan lines farther from the first display area.

[0021] Optionally, the display panel has gate driving chips on both sides of the display area, namely a first gate driving chip and a second gate driving chip, and the scan line is divided into a continuous first scan line and a second scan line.

[0022] The step of continuously inputting a first scan voltage and a second scan voltage to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line within one scan cycle of the scan line in the first display area includes:

[0023] During one scan cycle of the scan line in the first display area, the first gate driving chip and the second gate driving chip simultaneously and continuously input a first scan voltage and a second scan voltage to the first segment of the scan line and the second segment of the scan line in the first display area, respectively, to control the conduction of the thin film transistors corresponding to the first segment of the scan line and the second segment of the scan line.

[0024] The step of continuously inputting a third scan voltage and a fourth scan voltage to the scan line in the second display area within one scan cycle to control the conduction of the thin-film transistor corresponding to the scan line includes:

[0025] During one scan cycle of the scan line in the second display area, the first gate driver chip and the second gate driver chip simultaneously and continuously input a third scan voltage and a fourth scan voltage to the first scan line and the second scan line in the second display area, respectively, to control the conduction of the thin film transistors corresponding to the first scan line and the second scan line.

[0026] This application also discloses a driving circuit for driving the display panel using any of the driving methods described above. The driving circuit includes a timing control module, a data driving module, and a gate driving module. The timing control module outputs a clock signal and a latch signal. The data driving module is connected to the timing control module and outputs a data signal to a data line. The gate driving module is connected to the timing control module and outputs a scan signal to a scan line. The gate driving module generates a scan signal based on the clock signal output by the timing control module to control the turn-off of the thin-film transistor corresponding to the scan line. The data driving module outputs a data signal to the data line based on the latch signal. The data lines are described above. During one scan cycle of the scan signal for the scan line in the first display area, the gate driving module continuously inputs a first scan voltage and a second scan voltage to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line. During one scan cycle of the scan signal for the scan line in the second display area, the gate driving module continuously inputs a third scan voltage and a fourth scan voltage to the scan line in the second display area to control the conduction of the thin-film transistor corresponding to the scan line. The voltage value of the first scan voltage is greater than the voltage value of the second scan voltage, and the voltage value of the third scan voltage is less than the voltage value of the fourth scan voltage.

[0027] Optionally, the timing control module includes a timing control chip, a pulse width modulation chip, and a level conversion chip. The pulse width modulation chip operates according to the voltage enable signal output by the timing control chip. The level conversion chip is connected to both the pulse width modulation chip and the timing control chip. The pulse width modulation chip has a first voltage output unit and a second voltage output unit. The first voltage output unit outputs a first scan voltage and a fourth scan voltage, and the second low-voltage output unit outputs a second scan voltage and a third scan voltage. The level conversion chip outputs different scan voltages to the gate driver chip within one scan cycle according to the scan duration signal output by the timing control chip.

[0028] This application also discloses a display device, which includes a driving circuit as described above and a display panel, wherein the driving circuit is used to drive the display panel.

[0029] Compared to schemes that do not divide the display area and use different scanning voltages for driving, this application divides the display area into a first display area and a second display area. Within one scan cycle, the scan lines in the near-end first display area are continuously fed with different magnitudes of first and second scanning voltages to control the conduction of the corresponding thin-film transistors. Similarly, the scan lines in the far-end second display area are continuously fed with different magnitudes of third and fourth scanning voltages to control the conduction of the corresponding thin-film transistors. By increasing the voltage in the latter half of the scan cycle of the scan lines in the far-end second display area and increasing the voltage in the first half of the scan cycle of the scan lines in the near-end first display area, the pixel charging amounts in the two areas are made closer, reducing brightness differences and resulting in uniform brightness across the entire display area, thus improving the display effect. Attached Figure Description

[0030] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0031] Figure 1 This is a flowchart illustrating a driving method according to the first embodiment of this application;

[0032] Figure 2 This is a schematic diagram of the display panel structure in the first embodiment of this application;

[0033] Figure 3 This is a schematic diagram of the scanning signal waveforms corresponding to the first display area and the second display area in the first embodiment of this application;

[0034] Figure 4 This is a flowchart illustrating the driving method in the second embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the driving signal waveforms corresponding to the first display area and the second display area in the second embodiment of this application;

[0036] Figure 6 This is a schematic diagram of the actual drive signals within the display area of ​​this application;

[0037] Figure 7 This is a schematic diagram of the actual driving signals for the display area in the second embodiment of this application;

[0038] Figure 8This is a flowchart illustrating the driving method in the third embodiment of this application;

[0039] Figure 9 This is a schematic diagram of the scanning signal waveform corresponding to the second display area in the fourth embodiment of this application;

[0040] Figure 10 This is a flowchart illustrating the driving method in the fifth embodiment of this application;

[0041] Figure 11 This is a schematic diagram of the display panel structure in the fifth embodiment of this application;

[0042] Figure 12 This is a schematic diagram of the driving circuit in the sixth embodiment of this application;

[0043] Figure 13 This is a schematic diagram of the display device according to the seventh embodiment of this application;

[0044] Figure 14 This is a schematic diagram of the clock signal waveforms corresponding to the first and second display areas of this application.

[0045] Among them, 100 is a driving circuit; 110 is a timing control module; 120 is a timing control chip; 121 is a counter; 130 is a pulse width modulation chip; 131 is a first voltage output unit; 132 is a second voltage output unit; 140 is a level conversion chip; 150 is a gate driving module; 151 is a first gate driving chip; 152 is a second gate driving chip; 160 is a data driving module; 200 is a display panel; 210 is a display area; 211 is a first display area; 212 is a second display area; 220 is a non-display area; 230 is a scan line; 240 is a data line; and 300 is a display device. Detailed Implementation

[0046] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0047] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0048] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0049] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0050] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0051] like Figure 1 As shown, in the first embodiment of this application, a driving method is disclosed. The driving method is used to drive a display panel, the display panel including a display area and a non-display area, the non-display area being disposed around the display area, and the driving method including the steps of:

[0052] S1: Along the transmission direction of the data signal, the display area is sequentially divided into a first display area and a second display area;

[0053] S2: Within one scan cycle of a scan line in the first display area, a first scan voltage and a second scan voltage are continuously input to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line; and

[0054] S3: During one scan cycle of the scan line in the second display area, the third scan voltage and the fourth scan voltage are continuously input to the scan line in the second display area to control the conduction of the thin film transistor corresponding to the scan line;

[0055] Wherein, the voltage value of the first scanning voltage is greater than the voltage value of the second scanning voltage, and the voltage value of the third scanning voltage is less than the voltage value of the fourth scanning voltage.

[0056] refer to Figures 1 to 3As shown, the driving method of this embodiment is mainly used in a dual-gate driven display panel 200, that is, two scan lines 230 simultaneously receive the same scan signal (G1, ..., Gn, ... Gm); of course, it is not limited to dual-gate driven display panels 200. The driving method of this embodiment can be used when there is a large difference in brightness between the display areas at the far end and near end of the data signal input terminal; of course, in particular, in a dual-gate driven display panel, since the number of scan lines is twice that of a normal display panel, the length of the data line is longer than that of a normal display panel, which results in a very obvious difference in brightness between the first display area 211 at the near end and the second display area 212 at the far end, and the display effect of the entire display area 210 is poor; Therefore, within one scan cycle H of the scan line 230 in the first display area 211, the first scan voltage VGH1 and the second scan voltage VGH2 are continuously input to the scan line 230 in the first display area 211 to control the conduction of the thin-film transistor corresponding to the scan line 230; while within one scan cycle H of the scan line in the second display area 212, the third scan voltage VGH3 and the fourth scan voltage VGH4 are continuously input to the scan line 230 in the second display area 212 to control the conduction of the thin-film transistor corresponding to the scan line 230, and the fifth input voltage VGH5 is input to the scan line 230 in the first display area 211 and the second display area 212 to control the turn-off of the thin-film transistor corresponding to the scan line 230.

[0057] It should be noted that the voltage value of the first scanning voltage VGH1 is greater than that of the second scanning voltage VGH2, and the voltage value of the third scanning voltage VGH3 is less than that of the fourth scanning voltage VGH4. The scanning voltage of the scanning line 230 in the near-end first display area 211 decreases from high to low, meaning that the charging amount of the corresponding pixel is reduced relative to the pixel continuously charged by the first scanning voltage VGH1 during the scanning cycle H. Conversely, the scanning voltage of the scanning line 230 in the far-end second display area 212 increases from low to high. This results in an increase in charging voltage and charging amount during the latter half of the charging time in the scanning cycle H. In other words, by reducing the charging amount of the near-end pixels and appropriately increasing the charging amount of the far-end pixels, the brightness difference between the near and far-end pixels is reduced, resulting in more uniform brightness across the entire display area and improved display performance.

[0058] Generally, before the display panel 200 is improved, the voltage of the scan line 230 of the display panel 200 is the original scan voltage VGH. The first scan voltage VGH1 and the fourth scan voltage VGH4 can be directly obtained from the original scan voltage. Correspondingly, the second scan voltage VGH2 and the third scan voltage VGH3 are obtained by pulling down the original scan voltage. Of course, the first scan voltage VGH1 can also be obtained by pulling up or pulling down the original scan voltage. Correspondingly, if the first scan voltage VGH1 is obtained by pulling up the original scan voltage VGH, then the second scan voltage VGH2 and the third scan voltage VGH3 are obtained by pulling up the original scan voltage VGH. The scanning voltage VGH2 can be directly used as the original scanning voltage; or the first scanning voltage VGH1 can be used as the original scanning voltage, the second scanning voltage VGH2 can be obtained by pulling down the original scanning voltage VGH, the third scanning voltage VGH3 can be used as the original scanning voltage VGH, and the fourth scanning voltage VGH4 can be obtained by pulling up the original scanning voltage VGH. The scanning voltages can be selected to be pulled down or pulled up according to the actual situation. The scanning voltage VGH can also be equivalent to the clock signal voltage CKV. That is, after changing the clock signal voltage in the above way, the corresponding scanning voltage is generated according to the changed clock signal voltage.

[0059] Furthermore, the voltage value of the first scanning voltage VGH1 is equal to the voltage value of the fourth scanning voltage VGH4, and the voltage value of the second scanning voltage VGH2 is equal to the voltage value of the third scanning voltage VGH3; the input duration T1 of the first scanning voltage VGH1 is equal to the input duration T1 of the third scanning voltage VGH3, and the input duration T2 of the second scanning voltage VGH2 is equal to the input duration T2 of the fourth scanning voltage VGH4. A set of scanning voltages in the first display area 211 and a set of scanning voltages in the second display area 212 can be shared at different times.

[0060] like Figure 4 As shown, as a second embodiment of this application, it is a further improvement on the first embodiment described above. The input of data signals is controlled by latch signals. During the low-level time between two high levels of the latch signal, data voltage is input to the thin-film transistor corresponding to a row of scan lines. Step S3 includes:

[0061] S341: Generate a target latch signal based on the original latch signal, and use the target latch signal to control the output of the data signal; and

[0062] S342: Charge the pixels connected to the thin-film transistors corresponding to the scan lines according to the third scan voltage, the fourth scan voltage, and the voltage of the data signal.

[0063] in, Figure 5The waveforms of the scan signal Gn, data signal Data, and latch signal TP under ideal conditions are shown. Figure 6 The waveforms of the actual scan and latch signals before this solution was implemented are shown. Figure 7 For the actual scan signal and latch signal waveforms after implementing this scheme, please refer to... Figures 2 to 7 As shown, the first display area 211 uses the original latch signal TP1 to control the output of the data signal data, and the second display area 212 uses the target latch signal TP2 to control the output of the data signal data. For the same pixel, the charging end time corresponding to the target latch signal TP2 is later than the charging end time corresponding to the original latch signal. The duration between the charging start time of the latch signal TP corresponding to the last scan line 230 of the first display area 211 and the first scan line 230 of the second display area 212 is greater than the duration between the charging start times of the original latch signal TP1 or the target latch signal TP2 corresponding to two adjacent scan lines 230.

[0064] Taking the pixel corresponding to a scan line 230 in the first display area 211 as an example for charging, the scan voltage first enters the scan line and charges the gate of the thin-film transistor on the scan line. The data signal voltage on the data line charges the source of the thin-film transistor. After charging for a period of time, the thin-film transistor turns on. The low level time of the latch signal is the actual charging time of the pixel. Considering that the waveform of the scan voltage in the second display area 212 will have a serious trailing, this application delays the latch signal TP corresponding to the scan line 230 in the second display area 212 to obtain the target latch signal TP2.

[0065] refer to Figure 6 As shown, the actual charging time of the scan signal Gn in the first display area near the edge is t1. Because the signal loss is small at the near end, the waveform remains unchanged. However, the scan signal Gm in the second display area at the far end has a large loss, and the waveform has been distorted, resulting in severe trailing in the later stages. The charging time of the pixel corresponding to the current scan line is t2. However, due to the trailing, the next row of pixels still uses the data voltage of the previous row for charging, and the charging time is t3, thus causing incorrect charging. (Reference) Figure 7As shown, to avoid incorrect charging of pixels corresponding to scan lines in the far-end second display area, the TP time corresponding to the far-end scan line is generally delayed by a time t, which is the incorrect charging time t3. The range of t is 2H≤t≤4H, where H is the turn-on time of the thin-film transistor corresponding to one scan line. For this scheme, the Dual Gate UD model is 1H=1 / 60 / 2250 / 2=3.7us. By delaying the latch signal of the second display area, even if there is trailing, it will not affect the charging of pixels corresponding to the next scan line.

[0066] like Figure 8 As shown, this third embodiment of the present application is a further refinement of the above embodiments. This embodiment mainly refines how the display area is divided, wherein the display area is provided with m scan lines, and step S1 includes:

[0067] S181: Detect frame start signal. Calculate sequentially according to the scanning order of the scan lines. The first scan line count is 1. When the count is n, stop counting. Divide the display area corresponding to the first n scan lines into the first display area, and divide the display area corresponding to the scan lines after n into the second display area.

[0068] Where m / 2-a≤n≤m / 2+a, a<n<m, and m, n, and a are natural numbers.

[0069] The number of scan lines is calculated by a counter. When the number of scan lines reaches the preset number n, the calculation stops. During subsequent scan drives, the voltage of the scan signal changes. Specifically, during the scan signal period used for the first n scan lines (including the nth scan line), the first scan voltage and the second scan voltage are continuously input to the scan lines in the first display area to control the conduction of the thin-film transistors corresponding to the scan lines. During the scan signal period used for the scan lines after the nth scan line, the third scan voltage and the fourth scan voltage are continuously input to the scan lines in the first display area to control the conduction of the thin-film transistors corresponding to the scan lines. The reason for this calculation is to ensure that the scan voltage can be generated in advance when scanning into the second display area, so as to avoid the scan lines in the second display area still using the scan voltage of the scan lines in the first display area.

[0070] The display area is generally divided into equal sections, meaning the number of scan lines in the first display area is the same as in the second display area, and the changes usually occur in the middle. This variation is not easily noticeable to the naked eye and has certain advantages. However, it is not always equal. The loss of data signals on the data lines does not necessarily change regularly with distance. The loss may be greater after four or five scan lines from the center line, while the loss is smaller before that. In this case, if the division is directly based on the center line, there may still be a large difference in voltage between the scan lines above and below the center line, resulting in a poor improvement effect. Therefore, the division can be performed after detecting the data voltage on the data lines.

[0071] As a fourth embodiment of this application, it is an improvement on any of the above embodiments, referring to... Figure 2 and Figure 9 As shown, considering that the distance between the scan line 230 and the data signal input terminal varies within the second display area 212, the voltage of the data signal Data received by the corresponding pixels also varies. This results in the scan line 230 at the far end potentially having a lower charging voltage, and the final charging amount being less than that of the pixel corresponding to the scan line at the near end. Therefore, within the second display area 212, in any two adjacent rows of scan lines 230, the third scan voltage VGH3 corresponding to the scan line 230 closer to the first display area is different from the third scan voltage VGH3' corresponding to the scan line 230 farther from the first display area, while the fourth scan voltage VGH4 corresponding to the scan line 230 closer to the first display area 211 is the same as the fourth scan voltage VGH4' corresponding to the scan line 230 farther from the first display area 211. The absolute value of the difference between the third scan voltage VGH3 and the fourth scan voltage VGH4 corresponding to the scan line 230 closer to the first display area 211 is greater than the absolute value of the difference between the third scan voltage VGH3' and the fourth scan voltage VGH3' corresponding to the scan line 230 farther from the first display area.

[0072] like Figure 10 As shown, as the fifth embodiment of this application, the driving method of the first embodiment is used for a dual-side driven display panel. Specifically, gate driving chips are provided on both sides of the display area of ​​the display panel, namely a first gate driving chip and a second gate driving chip, and the scan line is divided into a continuous first scan line and a second scan line.

[0073] Step S2 includes:

[0074] S21: During one scan cycle of the scan line in the first display area, the first gate driving chip and the second gate driving chip simultaneously and continuously input the first scan voltage and the second scan voltage to the first segment of the scan line and the second segment of the scan line in the first display area, respectively, to control the conduction of the thin film transistors corresponding to the first segment of the scan line and the second segment of the scan line.

[0075] Step S3 includes:

[0076] S31: During one scan cycle of the scan line in the second display area, the first gate driving chip and the second gate driving chip simultaneously and continuously input a third scan voltage and a fourth scan voltage to the first scan line and the second scan line in the second display area, respectively, to control the conduction of the thin film transistors corresponding to the first scan line and the second scan line.

[0077] refer to Figure 5 , Figure 10 and Figure 11 As shown, the display panel adopts dual-sided driving, so the driving method of this application can be applied to larger-sized display panels without worrying about voltage loss after the scan signal is input to the scan line, resulting in different opening degrees of the thin-film transistors before and after. Specifically, a scan line is equally divided into two scan lines, namely the first scan line 231 and the second scan line 232. Within one scan cycle H of the scan line in the first display area, the first gate driving chip 151 and the second gate driving chip 152 simultaneously and continuously input the first scan voltage VGH1 and the second scan voltage VGH2 to the first scan line 231 and the second scan line 232 of the scan line 230 in the first display area 211, respectively, to control the first scan line 231 and the second scan line 232. The thin-film transistor corresponding to the scan line 232 is turned on; within one scan cycle of the scan line in the second display area 212, the first gate driver chip 151 and the second gate driver chip 152 simultaneously and continuously input the third scan voltage VGH3 and the fourth scan voltage VGH4 to the first segment of scan line 231 and the second segment of scan line 232 in the second display area 212, respectively, to control the turn-on of the thin-film transistors corresponding to the first segment of scan line 231 and the second segment of scan line 232; finally, the fifth input voltage VGH5 is input to the scan line 230 in the first display area 211 and the second display area 212 through any one or two gate driver chips to control the turn-off of the thin-film transistors corresponding to the scan line 230.

[0078] like Figure 12As shown in the sixth embodiment of this application, a driving circuit 100 is also disclosed. The driving circuit 100 drives the display panel using the driving method described in any of the above embodiments. The driving circuit 100 includes: a timing control module 110, a data driving module 160, and a gate driving module 150; the timing control module 110 outputs a clock signal CLK and a latch signal TP; the data driving module 160 is connected to the timing control module 110 and outputs a data signal data to a data line 240; the gate driving module 150 is connected to the timing control module 110 and outputs a scan signal Gn to a scan line 230; wherein, the gate driving module 150 generates a scan signal Gn according to the clock signal CLK output by the timing control module 110 to control the turn-off of the thin-film transistor corresponding to the scan line 230, and the data driving module 160 outputs a data signal data to the data line 240 according to the latch signal TP.

[0079] refer to Figure 2 , Figure 3 and Figure 12 As shown, within one scan cycle H of the scan signal of the scan line 230 in the first display area 211, the gate driving module 150 continuously inputs a first scan voltage VGH1 and a second scan voltage VGH2 to the scan line in the first display area 211 to control the conduction of the thin-film transistor corresponding to the scan line; within one scan cycle of the scan signal of the scan line 230 in the second display area 212, the gate driving module continuously inputs a third scan voltage VGH3 and a fourth scan voltage VGH4 to the scan line 230 in the second display area 212 to control the conduction of the thin-film transistor corresponding to the scan line 230; wherein, the voltage value of the first scan voltage VGH1 is greater than the voltage value of the second scan voltage VGH2, and the voltage value of the third scan voltage VGH3 is less than the voltage value of the fourth scan voltage VGH4.

[0080] Furthermore, the timing control module 110 includes a timing control chip 120, a pulse width modulation chip 130, and a level conversion chip 140. The pulse width modulation chip 130 operates according to the voltage enable signal VGH_EN output by the timing control chip 120. The level conversion chip 140 is connected to both the pulse width modulation chip 130 and the timing control chip 120. The pulse width modulation chip 130 has a first voltage output unit 131 and a second voltage output unit 132. The first voltage output unit 131 outputs a first scan voltage VGH1 and a fourth scan voltage, and the second low-voltage output unit 132 outputs a second scan voltage VGH2 and a third scan voltage. The level conversion chip 140 outputs different scan voltages VGH to the gate drive module 150 within one scan cycle according to the scan duration signal output by the timing control chip 120.

[0081] For details, please refer to Figure 2 , Figure 3 , Figure 6 , Figure 7 and Figure 12As shown, the timing control chip 120 has an internal row counter 121 to detect the row number and determine whether it belongs to the first or second display area of ​​the display panel. The pulse width modulation chip has two areas, a first voltage output unit 131 and a second voltage output unit 132, to store the values ​​of VGH1 and VGH2 respectively. When the row counter 121 inside the timing control chip 120 detects the frame start signal STV, it starts counting upon receiving the start signal. The count is 1 when the first scan signal or CKV arrives, and so on. Assuming the count reaches 1000, and considering the range of 1 to 1000 as the far end, the timing control chip... The internal control register of chip 120 is set to 1000. When the count reaches 1000, the timing control chip outputs VGH_EN and TP_EN as High. The VGH_EN signal is sent to the pulse width modulation chip 130. When the pulse width modulation chip 130 receives the instruction, the VGH voltage values ​​of the first voltage output unit 131 and the second voltage output unit 132 are exchanged. That is, the first voltage output unit 131 outputs VGH2, and the second voltage output unit 132 BankB outputs VGH1. At the same time, the TP_EN high-level signal is sent to the data drive module 160. The data drive can adjust the latch signal delay (TP). When the Delay function is enabled, the timing control chip 120 outputs the TP_Delay_CMD instruction to the data driver module to obtain the latch signal TP2. The Delay T time can be adjusted through the internal register according to the actual situation in the plane. When the row counter is greater than 1000, it is judged as near end, and the VGH_EN and TP_EN signals are low level. The TP Delay function of the data driver module is disabled, and TP1 is output normally. The VGH voltages of the two Bank areas in the pulse width modulation chip 130 are swapped back. At the same time, combined with the T1 and T2 times given by the timing control chip 120 to the level conversion chip 140, the level conversion chip 140 outputs a complete CK signal to the data driver module 160 and then to the data line in the display panel.

[0082] like Figure 13 As shown, as the eighth embodiment of this application, a display device 300 is disclosed. The display device 300 includes a driving circuit 100 as described in any of the above embodiments and a display panel 200. The driving circuit 100 is used to drive the display panel 200.

[0083] This application uses scanning voltage to drive the display panel, but the waveform change is not limited to the voltage waveform of the scanning signal; it can also be the waveform of the clock signal that generates the scanning signal. (See reference...) Figure 14As shown, when corresponding to the first display area, within one clock signal cycle H of the clock signal line, a first clock signal voltage VGH1 and a second clock signal voltage VGH2 are continuously input to the clock signal line. The clock signal line is connected to the gate driving module, and the voltage of the clock signal line generates a scan signal through the gate driving module, which is output to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line. When corresponding to the second display area, within one clock signal cycle of the clock signal line, a third clock signal voltage VGH3 and a fourth clock signal voltage VGH4 are continuously input to the clock signal line. The clock signal line is connected to the gate driving module. The voltage of the clock signal line generates a scan signal through the gate driving module, which is output to the scan line in the second display area to control the conduction of the thin-film transistor corresponding to the scan line; wherein, the voltage value of the first clock signal voltage VGH1 is greater than the voltage value of the second clock signal voltage VGH2, the voltage value of the third clock signal voltage VGH3 is less than the voltage value of the fourth clock signal voltage VGH4, and the voltage value of the first clock signal voltage VGH1 is equal to the voltage value of the fourth clock signal voltage VGH4, and the voltage value of the second clock signal voltage VGH2 is equal to the voltage value of the third clock signal voltage VGH3.

[0084] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0085] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0086] The technical solution of this application can be widely used in various driving methods, such as TN (Twisted Nematic) driving method, IPS (In-Plane Switching) driving method, VA (Vertical Alignment) driving method, MVA (Multi-Domain Vertical Alignment) driving method, and of course, other types of driving methods, such as OLED (Organic Light-Emitting Diode) driving method, are also applicable to the above solution.

[0087] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A driving method for a display panel, the display panel comprising a display area and a non-display area, the non-display area being disposed around the display area, characterized in that, The driving method includes the following steps: Along the direction of data signal transmission, the display area is sequentially divided into a first display area and a second display area; During one scan cycle of a scan line within the first display area, a first scan voltage and a second scan voltage are continuously input to the scan line within the first display area to control the conduction of the thin-film transistor corresponding to the scan line; and During one scan cycle of the scan line in the second display area, a third scan voltage and a fourth scan voltage are continuously input to the scan line in the second display area to control the conduction of the thin-film transistor corresponding to the scan line; Wherein, the voltage value of the first scanning voltage is greater than the voltage value of the second scanning voltage, and the voltage value of the third scanning voltage is less than the voltage value of the fourth scanning voltage.

2. The driving method as described in claim 1, characterized in that, The input of the data signal is controlled by a latch signal. The step of continuously inputting a third scan voltage and a fourth scan voltage to the scan line in the second display area within one scan cycle to control the conduction of the thin-film transistor corresponding to the scan line includes: A target latch signal is generated based on the original latch signal, and the output of the data signal is controlled using the target latch signal; and The pixels connected to the thin-film transistors corresponding to the scan lines are charged according to the third scan voltage, the fourth scan voltage, and the voltage of the data signal. In this display area, the output of the data signal is controlled by the original latch signal, and the output of the data signal is controlled by the target latch signal. For the same pixel, the charging end time corresponding to the target latch signal is later than the charging end time corresponding to the original latch signal.

3. The driving method as described in claim 1 or 2, characterized in that, The voltage value of the first scan voltage is equal to the voltage value of the fourth scan voltage, and the voltage value of the second scan voltage is equal to the voltage value of the third scan voltage; the input duration of the first scan voltage is equal to the input duration of the third scan voltage, and the input duration of the second scan voltage is equal to the input duration of the fourth scan voltage.

4. The driving method as described in claim 2, characterized in that, The duration between the charging start times of the latch signals corresponding to the last scan line of the first display area and the first scan line of the second display area is greater than the duration between the charging start times of the original latch signals or target latch signals corresponding to two adjacent scan lines.

5. The driving method as described in claim 1, characterized in that, The display area has m scan lines. The step of dividing the display area into a first display area and a second display area sequentially along the data signal transmission direction includes: The detection frame start signal is calculated sequentially according to the scanning order of the scan lines. The first scan line is counted as 1. When the count is n, the counting stops. The display area corresponding to the first n scan lines is divided into the first display area, and the display area corresponding to the scan lines after n lines is divided into the second display area. Where m / 2-a≤n≤m / 2+a, a<n<m, and m, n, and a are natural numbers.

6. The driving method as described in claim 1, characterized in that, Within the second display area, in any two adjacent rows of scan lines, the third scan voltage corresponding to the scan line closer to the first display area is different from the third scan voltage corresponding to the scan line farther from the first display area, while the fourth scan voltage corresponding to the scan line closer to the first display area is the same as the fourth scan voltage corresponding to the scan line farther from the first display area. The absolute value of the difference between the third and fourth scan voltages corresponding to the scan lines closer to the first display area is greater than the absolute value of the difference between the third and fourth scan voltages corresponding to the scan lines farther from the first display area.

7. The driving method as described in claim 1, characterized in that, The display panel has gate driving chips on both sides of the display area, namely a first gate driving chip and a second gate driving chip, and the scan line is divided into a continuous first scan line and a second scan line. The step of continuously inputting a first scan voltage and a second scan voltage to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line within one scan cycle of the scan line in the first display area includes: During one scan cycle of the scan line in the first display area, the first gate driving chip and the second gate driving chip simultaneously and continuously input a first scan voltage and a second scan voltage to the first segment of the scan line and the second segment of the scan line in the first display area, respectively, to control the conduction of the thin film transistors corresponding to the first segment of the scan line and the second segment of the scan line. The step of continuously inputting a third scan voltage and a fourth scan voltage to the scan line in the second display area within one scan cycle to control the conduction of the thin-film transistor corresponding to the scan line includes: During one scan cycle of the scan line in the second display area, the first gate driver chip and the second gate driver chip simultaneously and continuously input a third scan voltage and a fourth scan voltage to the first scan line and the second scan line in the second display area, respectively, to control the conduction of the thin film transistors corresponding to the first scan line and the second scan line.

8. A driving circuit that drives the display panel using the driving method as described in any one of claims 1-7, characterized in that, The driving circuit includes: The timing control module outputs clock signals and latch signals; The data driving module, connected to the timing control module, outputs data signals to the data line; and A gate driving module, connected to the timing control module, outputs a scan signal to the scan line; The gate driving module generates a scan signal based on the clock signal output by the timing control module to control the turn-off of the thin-film transistor corresponding to the scan line, and the data driving module outputs a data signal to the data line based on the latch signal. During one scan cycle of the scan signal of the scan line in the first display area, the gate driving module continuously inputs a first scan voltage and a second scan voltage to the scan line in the first display area to control the conduction of the thin-film transistor corresponding to the scan line; during one scan cycle of the scan signal of the scan line in the second display area, the gate driving module continuously inputs a third scan voltage and a fourth scan voltage to the scan line in the second display area to control the conduction of the thin-film transistor corresponding to the scan line. Wherein, the voltage value of the first scanning voltage is greater than the voltage value of the second scanning voltage, and the voltage value of the third scanning voltage is less than the voltage value of the fourth scanning voltage.

9. The driving circuit as described in claim 8, characterized in that, The timing control module includes a timing control chip, a pulse width modulation chip, and a level conversion chip. The pulse width modulation chip operates according to the voltage turn-on signal output by the timing control chip, and the level conversion chip is connected to both the pulse width modulation chip and the timing control chip. The pulse width modulation chip includes a first voltage output unit and a second voltage output unit. The voltages output by the first voltage output unit are a first scan voltage and a fourth scan voltage, and the voltages output by the second voltage output unit are a second scan voltage and a third scan voltage. The level conversion chip outputs different scan voltages to the gate driver chip within one scan cycle according to the scan duration signal output by the timing control chip.

10. A display device, characterized in that, The display device includes a driving circuit as described in any one of claims 8-9 and a display panel, wherein the driving circuit is used to drive the display panel.

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