Cache memory and method for managing cache memory

Abstract

A cache memory and a management method of the cache memory are disclosed. The cache memory includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in-first-out manner. The control circuit is coupled to the storage circuit and the buffer circuit, and is used to find a storage space in the storage circuit and write the data into the storage space.

Description

[0001] This invention is a divisional application of the invention application filed on January 30, 2019, with application number 2019100936283 and titled "Cache Memory and Cache Memory Management Method". Technical Field

[0002] This invention relates to cache memory, and more particularly to multilevel cache memory. Background Technology

[0003] Figure 1 This is an architecture diagram of an existing electronic device. Electronic device 100 includes a processor 110, a first-level (L1) cache 120, a second-level (L2) cache 130, and a system memory 140. The L1 cache 120 and L2 cache 130 are typically Static Random-Access Memory (SRAM), while the system memory 140 is typically Dynamic Random-Access Memory (DRAM). The L2 cache 130 includes control circuitry 132 and storage circuitry 136. Control circuitry 132 writes data to or reads data from storage circuitry 136. The data structure of storage circuitry 136 and the algorithms used by control circuitry 132 to access storage circuitry 136 are well known to those skilled in the art and will not be described further. The following discusses the problems encountered by electronic device 100 in the inclusive mode and exclusive mode of the cache. The inclusive and proprietary modes are well known to those skilled in the art, and will not be elaborated upon further.

[0004] Figure 2This is a partial flowchart of the electronic device 100 operating in containment mode. During data access, when data is missed in the L1 cache 120, the L1 cache 120 requests data from the L2 cache 130 (step S210). In step S220, the control circuit 132 checks whether the data requested by the L1 cache 120 is stored in the storage circuit 136. Assuming that the data requested by the L1 cache 120 is not stored in the storage circuit 136 (i.e., the L2 cache missed), the control circuit 132 requests data from the system memory 140 (step S230). Next, the L2 cache 130 retrieves the data from the system memory 140 (step S240), and then the L2 cache 130 replies the data to the L1 cache 120 (step S250). After receiving the data replied by the L2 cache 130, the L1 cache 120 stores the data. Finally, L1 cache 120 broadcasts data to L2 cache 130 (step S260). In step S260, control circuit 132 needs to check the tag of storage circuit 136 and write the data into storage circuit 136. Because the capacity of L2 cache 130 is usually larger than that of L1 cache 120, accessing storage circuit 136 is relatively time-consuming. For example, if accessing L1 cache 120 requires one system clock cycle, accessing storage circuit 136 may require two to three cycles. Because step S260 is relatively time-consuming, control circuit 132 cannot immediately process the next access command, causing processor 110 to stall.

[0005] Figure 3This is a partial flowchart of the electronic device 100 operating in proprietary mode. During data access, when data is not found in the L1 cache 120, the L1 cache 120 requests data from the L2 cache 130 (step S310). In step S320, the control circuit 132 checks whether the requested data from the L1 cache 120 is stored in the storage circuit 136. Assuming that the requested data from the L1 cache 120 is stored in the storage circuit 136 (i.e., the L2 cache is hit), the control circuit 132 replies the data to the L1 cache 120 (step S330). Next, the L1 cache 120 evicts a line of data to the L2 cache 130 (step S340). In step S340, the control circuit 132 checks the tag of the storage circuit 136 and writes the line of data to the appropriate location in the storage circuit 136. Since the access memory circuit 136 is relatively time-consuming, step S340 may prevent the control circuit 132 from processing the next access command immediately, causing the processor 110 to stall. Summary of the Invention

[0006] In view of the shortcomings of the prior art, one object of this disclosure is to provide a cache memory and a cache memory management method to improve the performance of electronic devices.

[0007] This application discloses a cache memory, comprising a storage circuit, a buffer circuit, and a control circuit. The buffer circuit stores data in a first-in, first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit, and is used to locate a storage space in the storage circuit and write the data into that storage space.

[0008] This application also discloses a method for managing a cache memory, the cache memory including a storage circuit and a buffer circuit, the buffer circuit storing data in a first-in-first-out manner, the method including: when a target data is written to the cache memory, writing the target data to the buffer circuit without checking the storage circuit; and finding a storage space in the storage circuit and writing the target data to the storage space.

[0009] This application also discloses a cache memory, comprising a first-level cache memory, a second-level cache memory, and a temporary register. The first-level cache memory includes a first control circuit. The second-level cache memory includes a second control circuit. The temporary register is coupled to the first control circuit and the second control circuit. The first control circuit and the second control circuit reference a temporary value in the temporary register to control the first-level cache memory and the second-level cache memory to operate in an inclusive mode or an exclusive mode, respectively.

[0010] By incorporating buffer circuitry into the cache memory, the access speed of the cache memory is improved. Compared to conventional technologies, electronic devices employing the cache memory of this disclosure can reduce the probability of processor stagnation. Furthermore, the cache memory of this disclosure is easy to switch between containment mode and proprietary mode.

[0011] The features, implementation, and technical effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 A diagram of the architecture of an existing electronic device;

[0013] Figure 2 A partial flowchart of existing electronic devices operating in containment mode;

[0014] Figure 3 A partial flowchart of existing electronic devices operating in proprietary mode;

[0015] Figure 4 This is an architectural diagram of an embodiment of the electronic device disclosed herein;

[0016] Figure 5 A flowchart illustrating an embodiment of the cache memory management method of this disclosure;

[0017] Figure 6 for Figure 5 A flowchart of an embodiment of step S540; and

[0018] Figure 7 This is an architectural diagram of another embodiment of the electronic device disclosed herein.

[0019] Symbol Explanation

[0020] 100, 400, 70 electronic devices

[0021] 110, 410, 72 processors

[0022] 120, 420, 724, 734 L1 cache memory

[0023] 130, 430, 74 L2 cache memory

[0024] 140, 440 system memory

[0025] 132, 432, 7241, 7341, 742 control circuits

[0026] 136, 436, 7242, 7342, 746 storage circuits

[0027] 434, 744 buffer circuits

[0028] 720, 730 cores

[0029] 722 and 732 processing units

[0030] 76 temporary registers

[0031] Steps S210~S260, S310~S340, S510~S580, S610~S640 Detailed Implementation

[0032] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0033] This disclosure includes cache memory and methods for managing cache memory. Since some components of the cache memory may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device embodiments. Furthermore, some or all of the processes of the cache memory management method of this disclosure may be in the form of software and / or firmware, and may be executed by the cache memory of this disclosure or its equivalent. Without affecting the full disclosure and implementability of the method embodiments, the following description of the method embodiments will focus on the steps rather than the hardware.

[0034] Figure 4 This is an architectural diagram of an embodiment of the electronic device disclosed herein. The electronic device 400 includes a processor 410, an L1 cache 420, an L2 cache 430, and a system memory 440. The L2 cache 430 includes a control circuit 432, a buffer circuit 434, and a storage circuit 436. The buffer circuit 434 stores data in a first-in-first-out (FIFO) manner, while the storage circuit 436 stores data in a non-FIFO manner. In some embodiments, the capacity of the buffer circuit 434 is smaller than the capacity of the storage circuit 436, so that the access speed of the control circuit 432 to the buffer circuit 434 can be greater than the access speed to the storage circuit 436. The storage circuit 436 stores multiple tags and multiple data corresponding to the tags. The data structure of the storage circuit 436 is well known to those skilled in the art and will not be described in detail here. The buffer circuit 434 can be implemented as SRAM or as a temporary register (e.g., a flip-flop), and the storage circuit 436 is implemented as SRAM. L1 cache 420 and L2 cache 430 can operate in either containment mode or proprietary mode.

[0035] Figure 5This is a flowchart of an embodiment of the cache management method of this disclosure. Figure 5 The process applies to both containment mode and proprietary mode. When the control circuit 432 obtains target data from the L1 cache 420 or system memory 440 and needs to store the target data, the control circuit 432 writes the target data to the buffer circuit 434 without checking the tag of the storage circuit 436 (step S510). Next, the control circuit 432 determines whether the L2 cache 430 is in an idle state (step S520). If step S520 is negative, the control circuit 432 further determines whether there is another target data that needs to be written to the L2 cache 430 (step S530). If step S530 is positive, the control circuit 432 writes the other target data to the buffer circuit 434 (step S510); if step S530 is negative, the control circuit 432 searches for and / or retrieves data (including accessing the buffer circuit 434 and / or the storage circuit 436) (step S540). After step S540, the process returns to step S520.

[0036] When the L2 cache 430 is idle (yes in step S520), the control circuit 432 determines whether the buffer circuit 434 is empty (step S550). If the buffer circuit 434 does not store any data (i.e., yes in step S550), the process returns to step S520. If the buffer circuit 434 is not empty (i.e., no in step S550), the control circuit 432 searches for storage space in the storage circuit 436 (step S560), and then reads the target data from the buffer circuit 434 and writes it to the storage circuit 436 (step S570). In other words, the purpose of steps S560 and S570 is to move the target data from the buffer circuit 434 to the storage circuit 436. After the move, the target data exists only in the storage circuit 436 and not in the buffer circuit 434. In other words, the buffer circuit 434 and the storage circuit 436 do not store the same line of data simultaneously. After step S570 is completed, the control circuit 432 completes the writing of the target data into the L2 cache memory 430 (step S580), and then the process returns to step S520.

[0037] In step S560, the storage space can be unoccupied space or space occupied by data that is about to be evicted. The control circuit 432 can find the data that is about to be evicted based on an algorithm (e.g., Least Recently Used (LRU)) and the tags in the storage circuit 436.

[0038] Depend on Figure 5As can be seen from the process, the buffer circuit 434 may store multiple target data simultaneously, while the control circuit 432 reads the target data sequentially and writes it into the storage circuit 436 in a first-in-first-out manner. In some embodiments, the data in the buffer circuit 434 has the same format as the data in the storage circuit 436 (e.g., both are row data format) to simplify step S570.

[0039] Because the control circuit 432 does not need to check the tag of the storage circuit 436 to find a suitable storage space (whether it is an empty storage space or the space occupied by data about to be evicted) in step S510, theoretically step S510 can be completed in only one system clock cycle. In comparison, because the control circuit 432 needs to check the tag before writing the target data to the storage circuit 436, directly writing the target data to the storage circuit 436 requires at least two system clock cycles (depending on the size of the storage circuit 436). In other words, the buffer circuit 434 can improve the speed of the L2 cache 430.

[0040] The idle state of step S520 includes: (1) when the control circuit 432 has no read / write operations to be processed; and (2) when the L2 cache 430 is not hit, the period from when the control circuit 432 requests data from the system memory 440 to when it receives a reply from the system memory 440. Because the number of system clock cycles required for one access to the system memory 440 is usually much greater than the number of system clock cycles required for the control circuit 432 to write data to the storage circuit 436, the control circuit 432 has ample time to execute steps S560 and S570 in case (2).

[0041] In summary, since the L2 cache 430 misses in encompass mode or hits in proprietary mode, from the perspective of the processor 410, the operation of the L2 cache 430 only requires one system clock cycle, so the processor 410 will not be stalled, thus greatly increasing the performance of the electronic device 400.

[0042] Figure 6 for Figure 5The flowchart shows an embodiment of step S540. When the L1 cache 420 misses and requests data from the L2 cache 430, the control circuit 432 checks whether the buffer circuit 434 and the storage circuit 436 store the target data (step S610). If there is a hit (i.e., the buffer circuit 434 or the storage circuit 436 stores the target data, step S620 is yes), the control circuit 432 reads the target data and replies the target data to the L1 cache 420 (step S630). If there is a miss (i.e., neither the buffer circuit 434 nor the storage circuit 436 stores the target data, step S620 is no), the control circuit 432 requests data from the system memory 440 (step S640).

[0043] Figure 7 This is an architectural diagram of another embodiment of the electronic device disclosed herein. The electronic device 70 includes a processor 72, an L2 cache 74, and a temporary register 76. The processor 72 includes a core 720 and a core 730. The core 720 includes a processing unit 722 and an L1 cache 724. The L1 cache 724 includes control circuitry 7241 and storage circuitry 7242. The core 730 includes a processing unit 732 and an L1 cache 734. The L1 cache 734 includes control circuitry 7341 and storage circuitry 7342. In short, the processor 72 is a multi-core architecture, with cores 720 and 730 having their own L1 caches (724 and 734 respectively), and sharing the L2 cache 74. The L2 cache 74 includes control circuitry 742, buffer circuitry 744, and storage circuitry 746. The functions of control circuit 742, buffer circuit 744, and storage circuit 746 are similar to those of control circuit 432, buffer circuit 434, and storage circuit 436, respectively, and will not be described again. Control circuits 7241, 7341, and 742 are coupled to temporary register 76 and can read the temporary value stored in temporary register 76.

[0044] The control circuits 7241 of L1 cache 724, 7341 of L1 cache 734, and 742 of L2 cache 74 control the operation of L1 cache 724, L1 cache 734, and L2 cache 74 respectively in containment mode or proprietary mode by referring to the temporary value stored in register 76. In other words, the L1 cache and L2 cache can be programmably switched between containment mode and proprietary mode. In this way, the electronic device 70 does not need to determine the operating modes of L1 cache 724, L1 cache 734, and L2 cache 74 during the design phase; instead, the user can set the temporary value of register 76 according to the actual application (i.e., dynamic adjustment) after the circuit is completed. In some embodiments, register 76 may be a control register of processor 72.

[0045] The following are application examples of electronic device 70.

[0046] Example 1: When cores 720 and 730 are processing in parallel (i.e., executing the same program), the temporary value of register 76 can be set to a first value (e.g., 1), so that L1 cache 724, L1 cache 734 and L2 cache 74 operate in containment mode.

[0047] Example 2: When core 720 and core 730 execute the first program and the second program respectively, and the first program and the second program share instructions and / or data, the temporary value of temporary register 76 can be set to a first value (e.g., 1), so that L1 cache 724, L1 cache 734 and L2 cache 74 operate in containment mode.

[0048] Example 3: When core 720 and core 730 execute the first program and the second program respectively, and the first program and the second program do not share instructions and / or data (that is, the first program and the second program are independent programs), the temporary value of the register 76 can be set to a second value (e.g., 0), so that L1 cache 724, L1 cache 734 and L2 cache 74 operate in proprietary mode.

[0049] In Examples 1 and 2, the containment mode helps reduce the number of data moves (i.e., improves the hit rate), thus improving the performance of electronic device 70. In Example 3, the proprietary mode helps L1 cache 724, L1 cache 734, and L2 cache 74 store more instructions and / or data, thus improving the performance of electronic device 70.

[0050] In some embodiments, the aforementioned control circuits 432, 7241, 7341 and 742 can be implemented by a finite state machine (containing multiple logic circuits).

[0051] Since those skilled in the art can understand the implementation details and variations of the method embodiments of this disclosure through the disclosed device embodiments, repeated descriptions are omitted here to avoid redundancy, without affecting the disclosure requirements and implementability of the method embodiments. Please note that the shapes, sizes, proportions, and order of steps of the components in the foregoing drawings are merely illustrative and are intended for those skilled in the art to understand this disclosure, and are not intended to limit this disclosure.

[0052] Although the embodiments of this disclosure are described above, they are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims of this specification.

Claims

1. A cache memory, comprising: A first-level cache memory, including a first control circuit; A second-level cache memory, including a second control circuit; and A temporary register is coupled to the first control circuit and the second control circuit; The first control circuit and the second control circuit refer to a temporary value of the register to control the operation of the first-level cache and the second-level cache in an inclusive mode or to control the operation of the first-level cache and the second-level cache in a proprietary mode, respectively.

2. The cache memory as claimed in claim 1, wherein the second-level cache memory is shared by a first core and a second core of a processor, the first core executing a first program and the second core executing a second program, wherein when the first program and the second program are programs that share instructions or data, the temporary value corresponds to the containment mode.

3. The cache memory as claimed in claim 1, wherein the second-level cache memory is shared by a first core and a second core of a processor, the first core executing a first program and the second core executing a second program, wherein when the first program and the second program are not programs that share instructions or data, the temporary value corresponds to the proprietary mode.

4. The cache memory as claimed in claim 1, wherein the second-level cache memory further comprises: A storage circuit; and A buffer circuit is used to store data in a first-in, first-out manner. in, The second control circuit is used to locate a storage space in the storage circuit and write the data into that storage space.

5. The cache memory as claimed in claim 4, wherein when the second control circuit checks whether the second-level cache memory contains target data, the second control circuit checks whether the storage circuit and the buffer circuit store the target data.

6. The cache memory as claimed in claim 4, wherein when target data is written to the second-level cache memory, the second control circuit writes the target data to the buffer circuit without checking the storage circuit.

7. The cache memory as claimed in claim 4, wherein the capacity of the buffer circuit is smaller than the capacity of the storage circuit.

8. A method for managing a cache memory, used in a cache memory comprising a first-level cache memory, a second-level cache memory, and a temporary register. in, This management method includes: Read a temporary value from the register; The operation of the first-level cache and the second-level cache is controlled in an inclusive mode or in a proprietary mode based on the temporary value.

9. The cache memory management method as described in claim 8, wherein the second-level cache memory is shared by a first core and a second core of a processor, the first core executes a first program and the second core executes a second program, and when the first program and the second program are programs that share instructions or data, the temporary value corresponds to the containment mode.

10. The cache memory management method as described in claim 8, wherein the second-level cache memory is shared by a first core and a second core of a processor, the first core executes a first program and the second core executes a second program, and when the first program and the second program are not programs that share instructions or data, the temporary value corresponds to the proprietary mode.

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