Semiconductor memory device and memory system

Abstract

This disclosure provides a semiconductor memory device and a memory system. The semiconductor memory device includes: a chip module comprising multiple memory chips connected to adjacent memory chips via connectors; each memory chip includes an electrical connection portion; the connector includes a first conductive structure electrically connected to the electrical connection portions of adjacent memory chips; and a control unit connected to each memory chip and configured to control the opening or closing of the signal transmission channels of each memory chip in response to a chip selection signal. The memory capacity can be expanded via the connector connection, which is simple and easy to implement. The control unit can control the opening or closing of the signal transmission channels of each memory chip according to the received chip selection signal. Thus, the expansion function of the semiconductor memory device can be conveniently opened or closed according to actual needs, and the number of available memory chips can be adjusted, thereby flexibly controlling the memory capacity and better balancing memory capacity and power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor memory device and memory system. Background Technology

[0002] Semiconductor memory refers to memory devices implemented using semiconductors (such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc.). Dynamic random access memory (DRAM) is small in size, highly integrated, and consumes little power. It is also faster than read-only memory (ROM) and can be widely used in the memory of devices such as servers and computers.

[0003] Expanding memory capacity is an effective way to improve system performance and stability. However, existing methods for expanding memory have problems such as high implementation difficulty and low flexibility. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] A first aspect of this disclosure provides a semiconductor memory device, the semiconductor memory device comprising:

[0006] A chip module, comprising multiple memory chips, adjacent memory chips being connected by connectors, each memory chip including an electrical connection portion, and each connector including a first conductive structure, the first conductive structure being electrically connected to the electrical connection portions of adjacent memory chips respectively;

[0007] The control unit, connected to each of the memory chips, is configured to control the opening or closing of the signal transmission channel of each of the memory chips in response to a chip selection signal.

[0008] According to some embodiments of this disclosure, the chip module includes at least one stacked structure, and each stacked structure includes a plurality of the memory chips stacked together.

[0009] According to some embodiments of this disclosure, the connector includes a substrate, a plurality of first slot structures disposed on one side of the substrate, and a plurality of second slot structures disposed on the other side of the substrate, wherein the plurality of first slot structures correspond one-to-one with the plurality of second slot structures;

[0010] The first conductive structure is disposed in the substrate. The first conductive structure includes a plurality of first conductive portions disposed in one-to-one correspondence with the plurality of first slot structures. One end of the first conductive portion is electrically connected to the corresponding first slot structure, and the other end of the first conductive portion is electrically connected to the corresponding second slot structure.

[0011] The first slot structure is used to engage with the electrical connection portion on the corresponding memory chip, and the second slot structure is used to engage with the electrical connection portion on the corresponding memory chip.

[0012] According to some embodiments of this disclosure, the electrical connection portion includes a plurality of first electrical connection terminals that are respectively engaged with a plurality of first slot structures, and a plurality of second electrical connection terminals that are respectively engaged with a plurality of second slot structures.

[0013] The plurality of first electrical connection terminals and the plurality of second electrical connection terminals are electrically connected through a second conductive structure.

[0014] According to some embodiments of this disclosure, the second conductive structure includes a plurality of second conductive portions disposed in a one-to-one correspondence with the plurality of first electrical connection terminals, one end of the second conductive portion being electrically connected to the corresponding first electrical connection terminal, and the other end of the second conductive portion being electrically connected to the corresponding second electrical connection terminal.

[0015] According to some embodiments of this disclosure, the first electrical connection terminal and / or the second electrical connection terminal include ball-planted particles.

[0016] According to some embodiments of this disclosure, the first electrical connection terminal includes ball-shaped particles, the groove wall of the first slot structure forms part of a spherical surface, the groove wall adapts to and at least covers the middle and lower part of the first electrical connection terminal, and the diameter of the opening formed by the groove wall is smaller than the diameter of the spherical surface; and / or,

[0017] The second electrical connection terminal includes ball-shaped particles, and the groove wall of the second slot structure forms part of a spherical surface. The groove wall is adapted to the second electrical connection terminal and at least covers the upper and middle parts of the second electrical connection terminal, and the diameter of the opening formed by the groove wall is smaller than the diameter of the spherical surface.

[0018] According to some embodiments of this disclosure, each of the memory chips includes an enable port, and the control unit is connected to the enable port of each of the memory chips;

[0019] The control unit is configured to, in response to a chip select signal, selectively send a first enable signal to an enable port of at least one of the memory chips to control the signal transmission channel of the memory chip receiving the first enable signal to open, and / or selectively send a second enable signal to an enable port of at least one of the memory chips to control the signal transmission channel of the memory chip receiving the second enable signal to close.

[0020] According to some embodiments of this disclosure, the chip module includes multiple stacked structures, each stacked structure includes multiple memory chips stacked on top of each other, the memory chips in each stacked structure are arranged in a one-to-one correspondence, the enable ports of the corresponding memory chips in each stacked structure are connected to the same signal line, and the control unit is configured to send a first enable signal or a second enable signal to each signal line in response to a chip selection signal.

[0021] According to some embodiments of this disclosure, the semiconductor memory device includes:

[0022] A signal register, electrically connected to each of the memory chips, is configured to store signals to be sent to each of the memory chips.

[0023] According to some embodiments of this disclosure, the signals include address signals, data masking signals, clock signals, control signals, and / or data signals.

[0024] According to some embodiments of this disclosure, the semiconductor memory device includes:

[0025] A serial presence detection chip is configured to store chip information for each of the memory chips, the chip information including the operating frequency, operating voltage, speed, row address bandwidth, column address bandwidth, capacity and / or timing information of the memory chip.

[0026] A second aspect of this disclosure provides a memory system including a semiconductor memory device as described above and a control module connected to the semiconductor memory device, the control module being configured to send a chip selection signal to the control unit.

[0027] According to some embodiments of this disclosure, the memory system further includes a central processing module connected to the control module. The control module is connected to a serial presence detection chip of the semiconductor memory device. The control module is configured to read chip information stored in the serial presence detection chip and send the chip information to the central processing module. The central processing module is configured to determine a chip selection signal based on the chip information and send the chip selection signal to the control module.

[0028] According to some embodiments of this disclosure, the control module is integrated into the central processing module.

[0029] In the semiconductor memory device provided in this embodiment, a chip module is provided with multiple memory chips. The multiple memory chips are connected by connectors, and signal conduction between the memory chips is realized through a first conductive structure on the connector. In this way, the memory capacity can be expanded by connecting with connectors. The expansion method is simple and easy to implement. The control unit can control the signal transmission channel of each memory chip to open or close according to the received chip selection signal. In this way, the expansion function of the semiconductor memory device can be conveniently opened or closed according to actual needs, and the number of available memory chips can be adjusted, thereby flexibly controlling the memory capacity and better balancing memory capacity and power consumption.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor memory device according to an exemplary embodiment;

[0033] Figure 2 This is a schematic diagram of the structure of a chip module according to an exemplary embodiment;

[0034] Figure 3 This is an exploded view of a stacked structure provided according to an exemplary embodiment;

[0035] Figure 4 This is a cross-sectional view of a stacked structure provided according to an exemplary embodiment;

[0036] Figure 5 This is a schematic diagram of the structure of a semiconductor memory device according to an exemplary embodiment;

[0037] Figure 6 It is a memory system provided according to an exemplary embodiment.

[0038] In the figure, 10 is a chip module; 20 is a control unit; 100 is a memory chip; 110 is an electrical connection part; 111 is a first electrical connection terminal; 112 is a second electrical connection terminal; 120 is a first surface; 130 is a second surface; 140 is a second conductive structure; 141 is a second conductive part; 200 is a connector; 210 is a first conductive structure; 211 is a first conductive part; 220 is a substrate; 230 is a first slot structure; 240 is a second slot structure; 300 is a stacked structure; 400 is a signal register; 500 is a serial presence detection chip; 1 is a semiconductor memory device; 2 is a control module; and 3 is a central processing module. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0040] There are several common ways to expand memory capacity:

[0041] Method 1: Configure a large-capacity dynamic random access memory in the system;

[0042] Method 2: Increase the number of dynamic random access memory modules on the DRAM memory modules;

[0043] Method 3: Increase the number of channels.

[0044] Of the three methods mentioned above, Method 1 has high requirements for process technology and design, and is limited by the current technological level, making it difficult to further increase the capacity of dynamic random access memory. Method 2 is limited by the transmission bit width of the CPU (central processing unit), and the number of dynamic random access memories on the DRAM memory module is limited, making it difficult to increase further. Method 3 is limited by the design of the system motherboard, making it difficult to implement and lacking in flexibility.

[0045] As mentioned above, the methods for expanding memory capacity have significant limitations and are difficult to meet higher system performance and stability requirements.

[0046] Based on this, the present disclosure provides a semiconductor memory device. A chip module is provided with multiple memory chips, which are connected by connectors. Signal conduction between the memory chips is achieved through a first conductive structure on the connector. In this way, the memory capacity can be expanded by connecting the chips. The expansion method is simple and easy to implement. The control unit can control the signal transmission channel of each memory chip to open or close according to the received chip selection signal. Thus, the expansion function of the semiconductor memory device can be conveniently opened or closed according to actual needs, and the number of available memory chips can be adjusted, thereby flexibly controlling the memory capacity and better balancing memory capacity and power consumption.

[0047] An exemplary embodiment of this disclosure provides a semiconductor memory device, which can be implemented as a Single Inline Memory Module (SIMM), a Dual-Inline Memory Module (DIMM), a Small Outline Dual-Inline Memory Module (SODIMM), an Unbuffered Dual-Inline Memory Module (UDDIMM), a Fully Buffered Dual-Inline Memory Module (FBDIMM), a Rank-Buffered Dual-Inline Memory Module (RBDIMM), a Registered Dual-Inline Memory Module (RDIMM), or a Load Dual-Inline Memory Module (LRDIMM), etc. Figure 1 As shown, the semiconductor memory device 1 includes a chip module 10 and a control unit 20 connected to the chip module 10. The chip module 10 is used to implement the data storage function of the semiconductor memory device 1, and the control unit 20 is used to control the operating state of the chip module 10.

[0048] The chip module 10 includes multiple memory chips 100, each of which is a storage structure capable of data writing, data reading, and / or data deletion. Exemplarily, each memory chip 100 may include a semiconductor substrate. The semiconductor substrate may be made of one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. Multiple transistors may be disposed on the semiconductor substrate. The transistors may be covered by an interlayer dielectric layer. The interlayer dielectric layer may have a single-layer or multi-layer structure including a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a porous dielectric layer. The interlayer dielectric layer may have multiple internal chip lines therein. The internal chip lines may be electrically connected to the transistors. The transistors and the internal chip lines may constitute an internal integrated circuit.

[0049] like Figure 2 As shown, adjacent memory chips 100 are connected by connectors 200, that is, adjacent memory chips 100 are mechanically connected by connectors 200 to form a single integral structure. In some embodiments, adjacent memory chips 100 are non-detachable connected by connectors 200, for example, the memory chips 100 and connectors 200 are fixedly connected by welding, bonding, or other methods. In other embodiments, adjacent memory chips 100 are detachable connected by connectors 200, for example, the memory chips 100 and connectors 200 are connected by a snap-fit ​​structure.

[0050] The memory chip 100 also includes an electrical connection portion 110. For example, the electrical connection portion 110 can be connected to the internal wires of the memory chip 100. The connector 200 is provided with a first conductive structure 210. The first conductive structure 210 is electrically connected to the electrical connection portions 110 of adjacent memory chips 100 respectively. That is, the connector 200 has a first side and a second side. Memory chips 100 are arranged on both the first side and the second side of the connector 200. The first conductive structure 210 is electrically connected to the electrical connection portion 110 on the memory chip 100 located on the first side on the first side, and the first conductive structure 210 is electrically connected to the electrical connection portion 110 on the memory chip 100 located on the second side on the second side. In this way, the connector 200 realizes both the mechanical connection and the electrical connection of adjacent memory chips 100, thereby enabling adjacent memory chips 100 to transmit signals through the first conductive structure 210 on the connector 200.

[0051] The control unit 20 is connected to each memory chip 100 and is configured to control the opening or closing of the signal transmission channel of each memory chip 100 in response to a chip selection signal, which can be sent by an external host. For example, the control unit 20 is a CS_mux chip (i.e., a multiplexer) connected to an external host such as a processor.

[0052] In the semiconductor storage device 1 provided in this embodiment, the storage chips 100 are connected by connectors 200, and the signal conduction between the storage chips 100 is realized through the first conduction structure 210 on the connectors 200. In this way, the memory capacity can be expanded by connecting through the connectors 200. The expansion method is simple and easy to implement. The control unit 20 can control the signal transmission channel of each storage chip 100 to open or close according to the received chip selection signal. In this way, the expansion function of the semiconductor storage device 1 can be conveniently opened or closed according to actual needs, and the number of available storage chips 100 can be adjusted, thereby flexibly controlling the memory capacity and better balancing the memory capacity and power consumption.

[0053] The semiconductor memory device 1 also includes a driving circuit for driving each memory chip 100. Multiple driving circuits can be configured to ensure that driving of each memory chip 100 can still be guaranteed after memory expansion. It is understood that the memory chips 100 in the chip module 10 can be arranged side-by-side, for example, multiple memory chips 100 can be arranged side-by-side on a substrate. For example, as... Figure 3 As shown, the memory chip 100 has opposing first surfaces 120 and second surfaces 130, as well as semiconductor side surfaces connecting the first surfaces 120 and the second surfaces 130. Electrical connection portions 110 are provided on opposing semiconductor side surfaces of adjacent memory chips 100 to connect adjacent memory chips 100 via connectors 200. The connectors 200 can be a single integral structure, connecting multiple memory chips 100 into a single integral structure. Alternatively, there can be multiple connectors 200, with one connector 200 provided between every two adjacent memory chips 100.

[0054] The memory chips 100 in the chip module 10 can be stacked, for example, as Figure 3 and Figure 4 As shown, the chip module includes a stacked structure 300, which comprises multiple memory chips 100 stacked together. This allows for full utilization of vertical space, resulting in a more compact structure for the chip module 10. The stacked structure 300 can be a single unit, or it can be... Figure 5 Multiple options are shown, and the specific settings can be configured according to specific needs. This disclosure does not impose any restrictions on this.

[0055] In one exemplary embodiment, the connector 200 is connected to the memory chip 100 via a snap-fit ​​connection, which ensures both the reliability of the connection between the connector 200 and the memory chip 100 and facilitates the assembly and disassembly of the connector 200 and the memory chip 100. Thus, a desired number of memory chips 100 can be combined to form a chip module 10 according to actual needs, and the number of memory chips 100 in the chip module 10 can be flexibly increased or decreased later by assembling and disassembling the connector 200 and the memory chip 100. For example, the chip module 10 on the initial DRAM memory module is connected by the connector 200 to form a stacked structure 300 with 10 memory chips 100. During later use, some memory chips 100 can be removed from the stacked structure 300 to reduce the number of memory chips 100 in the stacked structure 300. For example, two memory chips 100 and two connectors 200 can be removed, resulting in a stacked structure 300 with eight memory chips 100. Alternatively, new connectors 200 and memory chips 100 can be snapped onto the existing stacked structure 300 to increase the number of memory chips 100 in the stacked structure 300. For example, one connector 200 can be snapped onto the existing stacked structure 300, and one memory chip 100 can be snapped onto the connector 200 to obtain a stacked structure 300 with 11 memory chips 100.

[0056] For example, such as Figure 4 As shown, the connector 200 includes a substrate 220, a plurality of first slot structures 230 disposed on one side of the substrate 220 (e.g., located on a first side), and a plurality of second slot structures 240 disposed on the other side of the substrate 220 (e.g., located on a second side). The substrate 220 is made of an insulating material. The plurality of first slot structures 230 and the plurality of second slot structures 240 correspond one-to-one. The first slot structures 230 are used to engage with the electrical connection portions 110 on the corresponding memory chip 100, and the second slot structures 240 are used to engage with the electrical connection portions 110 on the corresponding memory chip 100.

[0057] like Figure 3 and Figure 4 As shown, the first slot structure 230 can protrude from the surface of the substrate 220. For example, the first slot structure 230 is soldered to the surface of the substrate 220, and the opening of the first slot structure 230 faces the memory chip 100 on the first side of the connector 200. In this way, the electrical connection portion 110 on the memory chip 100 on the first side can be inserted into the first slot structure 230 through the opening of the first slot structure 230 to realize the snap-fit ​​fixation between the connector 200 and the memory chip 100 on the first side.

[0058] In one exemplary embodiment, the electrical connection portion 110 includes a plurality of first electrical connection terminals 111 that respectively engage with a plurality of first slot structures 230. In some embodiments, the cross-sectional shape of the first slot structure 230 is, for example, inverted T-shaped, and the first electrical connection terminals 111 have claws adapted to the shape of the first slot structure 230. The engagement is achieved by the claws engaging with the inverted T-shaped first slot structure 230. In other embodiments, such as... Figure 3 and Figure 4 As shown, the first electrical connection terminal 111 is spherical. Exemplarily, the first electrical connection terminal 111 includes ball-planted particles, i.e., spherical particles formed by a ball-planting process. The groove wall surface of the first slot structure 230 forms part of a spherical surface. The groove wall surface adapts to and at least covers the middle and lower part of the first electrical connection terminal 111, and the diameter of the opening formed by the groove wall surface is smaller than the diameter of the spherical surface. That is, the groove wall surface of the first slot structure 230 is formed as a spherical surface with an opening, the diameter of the first electrical connection terminal 111 matches the diameter of the groove wall surface of the first slot structure 230, for example, the diameter of the first electrical connection terminal 111 is equal to or slightly smaller than the diameter of the groove wall surface of the first slot structure 230, and at least one of the first slot structure 230 and the first electrical connection terminal 111 is elastic, thereby allowing the first electrical connection terminal 111 to be inserted into the first slot structure 230 through the opening. Understandably, the "lower part" mentioned here refers to the portion of the structure on the side of the first electrical connection terminal 111 closest to the connector 200, and the "middle part" refers to the portion of the structure closest to the centerline of the first electrical connection terminal 111. After the snap-fit ​​is completed, because the diameter of the opening is smaller than the diameter of the first electrical connection terminal 111, the connection between the first slot structure 230 and the first electrical connection terminal 111 is reliable. In addition, because the groove wall of the first slot structure 230 covers most of the outer surface of the first electrical connection terminal 111, the relative positional reliability of the connector 200 and the memory chip 100 after connection is ensured.

[0059] The first slot structure 230 can also be a recessed portion formed on the surface of the substrate 220. The first electrical connection terminal 111 is inserted into the recessed portion to realize the snap-fit ​​connection between the memory chip 100 and the connector 200.

[0060] Similarly, the second slot structure 240 can protrude from the surface of the substrate 220. For example, the second slot structure 240 is soldered to the surface of the substrate 220, and the opening of the second slot structure 240 faces the memory chip 100 on the second side of the connector 200. In this way, the electrical connection portion 110 on the memory chip 100 on the second side can be inserted into the second slot structure 240 through the opening of the second slot structure 240 to realize the snap-fit ​​fixation between the connector 200 and the memory chip 100 on the second side.

[0061] In one exemplary embodiment, the electrical connection portion 110 includes a plurality of second electrical connection terminals 112 that respectively engage with a plurality of second slot structures 240. In some embodiments, the cross-sectional shape of the second slot structure 240 is, for example, inverted T-shaped, and the second electrical connection terminals 112 have claws adapted to the shape of the second slot structure 240. The engagement is achieved by the claws engaging with the inverted T-shaped second slot structure 240. In other embodiments, such as... Figure 3 and Figure 4 As shown, the second electrical connection terminal 112 is spherical. Exemplarily, the second electrical connection terminal 112 includes ball-planted particles, i.e., spherical particles formed by a ball-planting process. The groove wall surface of the second slot structure 240 forms part of a spherical surface. The groove wall surface adapts to and at least covers the middle and upper parts of the second electrical connection terminal 112, and the diameter of the opening formed by the groove wall surface is smaller than the diameter of the spherical surface. That is, the groove wall surface of the second slot structure 240 is formed as a spherical surface with an opening, and the diameter of the second electrical connection terminal 112 matches the diameter of the groove wall surface of the second slot structure 240. For example, the diameter of the second electrical connection terminal 112 is equal to or slightly smaller than the diameter of the groove wall surface of the second slot structure 240. At least one of the second slot structure 240 and the second electrical connection terminal 112 is elastic, thereby allowing the second electrical connection terminal 112 to be inserted into the second slot structure 240 through the opening. Understandably, the "upper part" mentioned here refers to the portion of the structure on the second electrical connection terminal 112 near the connector 200, and the "middle part" refers to the portion of the structure near the centerline of the second electrical connection terminal 112. After the snap-fit ​​is completed, because the diameter of the opening is smaller than the diameter of the second electrical connection terminal 112, the connection between the second slot structure 240 and the second electrical connection terminal 112 is reliable. In addition, because the groove wall of the second slot structure 240 covers most of the outer surface of the second electrical connection terminal 112, the relative positional reliability of the connector 200 and the memory chip 100 after connection is ensured. The second slot structure 240 can also be a recessed portion formed on the surface of the substrate 220, into which the second electrical connection terminal 112 snaps into the recessed portion to achieve the snap-fit ​​connection between the memory chip 100 and the connector 200.

[0062] Continue to refer to Figure 4A first conductive structure 210 is disposed in the substrate 220. The first conductive structure 210 includes a plurality of first conductive portions 211 corresponding to a plurality of first slot structures 230. One end of the first conductive portion 211 is electrically connected to the corresponding first slot structure 230, and the other end of the first conductive portion 211 is electrically connected to the corresponding second slot structure 240. In this way, both the mechanical connection between the connector 200 and the memory chip 100 and the electrical connection between the memory chips 100 can be realized through the first slot structure 230 and the second slot structure 240. Specifically, when the memory chip 100 on one side of the connector 200 is engaged with the first slot structure 230, and the memory chip 100 on the other side of the connector 200 is engaged with the second slot structure 240, the connector 200 and the memory chip 100 are fixedly connected to form an integral stacked structure 300. The memory chip 100 on one side of the connector 200 is electrically connected to the memory chip 100 on the other side of the connector 200 through its first electrical connection terminal 111, the first slot structure 230, the first conductive structure 210, the second slot structure 240, and the second electrical connection terminal 112.

[0063] On a memory chip 100, a plurality of first electrical connection terminals 111 are disposed on a first surface 120, for example, a plurality of ball-mounted particles are disposed on the first surface 120. A plurality of second electrical connection terminals 112 are disposed on a second surface 130 of the memory chip 100, for example, a plurality of ball-mounted particles are disposed on the second surface 130. The plurality of first electrical connection terminals 111 and the plurality of second electrical connection terminals 112 are electrically connected through a second conductive structure 140, thereby enabling signal transmission between each memory chip 100 in the stacked structure 300, allowing each memory chip 100 in the stacked structure 300 to share the same signal trace.

[0064] In an exemplary embodiment, such as Figure 4 As shown, the positions of multiple first electrical connection terminals 111 and multiple second electrical connection terminals 112 correspond one-to-one. The second conductive structure 140 includes multiple second conductive portions 141 corresponding one-to-one with the multiple first electrical connection terminals 111. One end of the second conductive portion 141 is electrically connected to the corresponding first electrical connection terminal 111, and the other end of the second conductive portion 141 is electrically connected to the corresponding second electrical connection terminal 112. By providing second conductive portions 141 corresponding one-to-one with the multiple first electrical connection terminals 111 and second electrical connection terminals 112, each first electrical connection terminal 111 is connected to a second electrical connection terminal 112 through a second conductive portion 141, thereby improving the flexibility of signal transmission between the memory chips 100.

[0065] Of course, it is understandable that the multiple memory chips 100 in the chip module 10 can be arranged side by side or stacked, depending on the specific space requirements, and there are no restrictions on this.

[0066] In one exemplary embodiment, each memory chip 100 includes an enable port. A control unit 20 is connected to the enable port of each memory chip 100. The control unit 20 can send an enable signal to the enable port based on a received chip selection signal to control the opening and closing of the signal transmission channel of the memory chip 100. For example, the chip selection signal includes the address information of the memory chip 100 and the corresponding control switch information. The control unit 20 receives the chip selection signal and, based on the address information of each memory chip 100, sends an enable signal to the corresponding memory chip 100. The control switch information corresponds to the enable signal. For example, when the control switch information of a certain memory chip 100 is open, the control unit 20 responds to the chip selection signal and sends a first enable signal to the enable port of the memory chip 100 to control the signal transmission channel of the memory chip 100 receiving the first enable signal to open. When the control switch information of a certain memory chip 100 is closed, the control unit 20 responds to the chip selection signal and sends a second enable signal to the enable port of the memory chip 100 to control the signal transmission channel of the memory chip 100 receiving the second enable signal to close.

[0067] For example, the enable port of the memory chip 100 is provided with a PMOS transistor. The PMOS transistor is located on the signal transmission channel. The PMOS transistor is configured to be turned off when the gate receives a high level and turned on when the gate receives a low level. Then, the first enable signal is a low-level signal sent to the gate of the PMOS transistor, and the second enable signal is a high-level signal sent to the gate of the PMOS transistor.

[0068] In this embodiment, the opening and closing of the signal transmission channel is controlled by sending an enable signal to the enable port of the memory chip 100. The control method is simple, easy to implement, and provides precise control over each memory chip 100.

[0069] In an embodiment where the chip module 10 includes multiple stacked structures 300, and each stacked structure 300 includes multiple memory chips 100 stacked in layers, the enable ports of corresponding memory chips 100 in each stacked structure 300 are connected to the same signal line. For example, the multiple stacked structures 300 include a first stacked structure and a second stacked structure. The first stacked structure includes a first memory chip, a second memory chip, and a third memory chip stacked in sequence, and the second stacked structure includes a fourth memory chip, a fifth memory chip, and a sixth memory chip stacked in sequence. The first memory chip corresponds to the fourth memory chip, the second memory chip corresponds to the fifth memory chip, and the third memory chip corresponds to the sixth memory chip. The enable terminals of the first and fourth memory chips are connected to the same signal line (e.g., the first signal line), the enable terminals of the second and fifth memory chips are connected to the same signal line (e.g., the second signal line), and the enable terminals of the third and sixth memory chips are connected to the same signal line (e.g., the third signal line).

[0070] The control unit 20 is configured to send a first enable signal or a second enable signal to each signal line in response to a chip selection signal. Thus, a single signal line can control multiple corresponding memory chips 100 of each stacked structure 300, improving the control efficiency of the memory chips 100 and consequently increasing the response speed of the semiconductor memory device 1. For example, the control unit 20 can send a first enable signal to the first signal line, thereby simultaneously opening the signal transmission channels of the first and fourth memory chips. As another example, the control unit 20 can send a second enable signal to the second signal line, thereby simultaneously closing the signal transmission channels of the second and fifth memory chips.

[0071] In one exemplary embodiment, such as Figure 5 As shown, the semiconductor memory device 1 includes a signal register 400, which is electrically connected to each memory chip 100. The signal register 400 is configured to store signals to be sent to each memory chip 100. These signals can be, for example, address signals (ADD), data masking signals (CMD), clock signals (CLOCK), control signals (CTRL), and / or data signals (DQ). By storing the signals to be sent to each memory chip 100 through the signal register 400, signal loss is prevented even when there are many signals, thus ensuring control accuracy.

[0072] In one embodiment, the semiconductor memory device 1 includes a serial presence detector (SPD) chip 500 configured to store chip information of each memory chip 100. The chip information includes the operating frequency, operating voltage, speed, row address bandwidth, column address bandwidth, capacity, and / or timing information of each memory chip 100. The SPD chip 500 may be, for example, a programmable read-only memory (e.g., an EEPROM). The chip information may also include device information of the semiconductor memory device 1. When the memory system including the semiconductor memory device 1 provided in this disclosure is started, an external host can read the device information from the SPD chip 500 and identify the semiconductor memory device 1 based on the device information. Furthermore, the external host can determine the operating state of each memory chip 100 based on the current system operating status and the information of each memory chip 100 in the SPD chip 500, so that the operating state of the memory chip 100 better matches the current system operating status.

[0073] An exemplary embodiment of this disclosure also provides a memory system, such as Figure 6 As shown, the memory system includes a semiconductor memory device 1 and a control module 2 connected to the semiconductor memory device 1. The control module 2 is configured to send a chip selection signal to the control unit 20 to control the working state of each memory chip 100 in the semiconductor memory device 1, thereby flexibly controlling the memory capacity and better balancing the memory capacity and power consumption.

[0074] The control unit 20, such as the CS_mux chip, can communicate with the control module 2 through at least one of the following interface protocols: Universal Serial Bus (USB), MultiMedia Card (MMC), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Serial SCSI (SAS), Enhanced Small Drive Interface (ESDI), or Integrated Development Environment (IDE).

[0075] In one embodiment, the memory system further includes a central processing module 3 connected to the control module 2. The control module 2 is connected to the serial presence detection chip 500 of the semiconductor memory device 1. The control module 2 is configured to read chip information stored in the serial presence detection chip 500 and send the chip information to the central processing module 3. The central processing module 3 is configured to determine a chip selection signal based on the chip information and send the chip selection signal to the control module 2. Thus, the central processing module 3 can comprehensively manage the operating status of each memory chip 100 according to the overall operating status of the current memory system, achieving a relative balance between memory capacity and power consumption. The control module 2 can be a separately configured controller or integrated into the central processing module 3, thereby further improving the integration of the module.

[0076] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0077] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0079] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0080] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0081] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A semiconductor memory device, characterized in that, The semiconductor memory device includes: A chip module, comprising multiple memory chips, adjacent memory chips being connected by connectors, each memory chip including an electrical connection portion, and each connector including a first conductive structure, the first conductive structure being electrically connected to the electrical connection portions of adjacent memory chips respectively; A control unit, connected to each of the memory chips, is configured to control the opening or closing of the signal transmission channel of each of the memory chips in response to a chip selection signal; The chip module includes at least one stacked structure, and each stacked structure includes a plurality of the memory chips stacked together. The connector includes a substrate, a plurality of first slot structures disposed on one side of the substrate, and a plurality of second slot structures disposed on the other side of the substrate, wherein the plurality of first slot structures correspond one-to-one with the plurality of second slot structures. The first conductive structure is disposed in the substrate. The first conductive structure includes a plurality of first conductive portions disposed in one-to-one correspondence with the plurality of first slot structures. One end of the first conductive portion is electrically connected to the corresponding first slot structure, and the other end of the first conductive portion is electrically connected to the corresponding second slot structure. The first slot structure is used to engage with the electrical connection portion on the corresponding memory chip, and the second slot structure is used to engage with the electrical connection portion on the corresponding memory chip. The electrical connection portion includes a plurality of first electrical connection terminals that are respectively engaged with a plurality of first slot structures, and a plurality of second electrical connection terminals that are respectively engaged with a plurality of second slot structures. The plurality of first electrical connection terminals and the plurality of second electrical connection terminals are electrically connected through a second conductive structure; The first electrical connection terminal includes ball-shaped particles, the groove wall of the first slot structure forms part of a spherical surface, the groove wall adapts to the first electrical connection terminal and at least covers the middle and lower part of the first electrical connection terminal, and the diameter of the opening formed by the groove wall is smaller than the diameter of the spherical surface; and / or, The second electrical connection terminal includes ball-shaped particles, and the groove wall of the second slot structure forms part of a spherical surface. The groove wall is adapted to the second electrical connection terminal and at least covers the upper and middle parts of the second electrical connection terminal, and the diameter of the opening formed by the groove wall is smaller than the diameter of the spherical surface.

2. The semiconductor memory device according to claim 1, characterized in that, The second conductive structure includes a plurality of second conductive portions that are disposed in a one-to-one correspondence with the plurality of first electrical connection terminals. One end of the second conductive portion is electrically connected to the corresponding first electrical connection terminal, and the other end of the second conductive portion is electrically connected to the corresponding second electrical connection terminal.

3. The semiconductor memory device according to any one of claims 1 to 2, characterized in that, Each of the aforementioned memory chips includes an enable port, and the control unit is connected to the enable port of each of the aforementioned memory chips; The control unit is configured to, in response to a chip select signal, selectively send a first enable signal to an enable port of at least one of the memory chips to control the signal transmission channel of the memory chip receiving the first enable signal to open, and / or selectively send a second enable signal to an enable port of at least one of the memory chips to control the signal transmission channel of the memory chip receiving the second enable signal to close.

4. The semiconductor memory device according to claim 3, characterized in that, The chip module includes multiple stacked structures, each stacked structure including multiple memory chips stacked on top of each other, and the memory chips in each stacked structure are arranged in a one-to-one correspondence. The enable ports of the corresponding memory chips in each stacked structure are connected to the same signal line. The control unit is configured to send the first enable signal or the second enable signal to each signal line in response to the chip selection signal.

5. The semiconductor storage device according to any one of claims 1 to 2, characterized by, The semiconductor memory device includes: A signal register, electrically connected to each of the memory chips, is configured to store signals to be sent to each of the memory chips.

6. The semiconductor storage device according to claim 5, wherein The signals include address signals, data masking signals, clock signals, control signals, and / or data signals.

7. The semiconductor memory device according to any one of claims 1 to 2, characterized in that, The semiconductor memory device includes: A serial presence detection chip is configured to store chip information for each of the memory chips, the chip information including the operating frequency, operating voltage, speed, row address bandwidth, column address bandwidth, capacity and / or timing information of the memory chip.

8. A memory system, characterized in that, The device includes a semiconductor memory device as described in any one of claims 1 to 7 and a control module connected to the semiconductor memory device, the control module being configured to send a chip selection signal to the control unit.

9. The memory system of claim 8, wherein, The memory system further includes a central processing module connected to the control module. The control module is connected to a serial presence detection chip of the semiconductor memory device. The control module is configured to read chip information stored in the serial presence detection chip and send the chip information to the central processing module. The central processing module is configured to determine a chip selection signal based on the chip information and send the chip selection signal to the control module.

10. The memory system of claim 9, wherein, The control module is integrated into the central processing module.

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