Memory fault injection apparatus, method and related devices

Abstract

This disclosure provides a memory fault injection device, method, and related apparatus, relating to the field of computer technology, particularly to the fields of autonomous driving, data processing, and memory fault injection. The specific implementation scheme includes: at least one fault injection module, which establishes an electrical connection with the fault injection point of the memory under test via a probe module. The fault injection point is a physical contact point located on the signal transmission path between the memory controller and the memory chip of the memory under test; and a controller, which responds to an injection signal and controls the fault injection module to perform fault injection on the memory under test.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of autonomous driving, data processing, and memory fault injection. Background Technology

[0002] Memory fault injection is a testing technique that artificially introduces errors or anomalies into system memory to verify the system's fault tolerance, error detection mechanism, and recovery behavior under memory fault scenarios.

[0003] Unlike memory stress testing or address testing, which are primarily used to discover hardware defects, memory fault injection is the deliberate creation of faults to verify the completeness of error handling logic at the software level.

[0004] Memory is used in many electronic devices. Especially in the emerging field of autonomous driving, onboard memory plays a crucial role in storing perception data, decision instructions, control signals and system firmware in real time. Its operational stability directly determines the driving safety of autonomous vehicles. Summary of the Invention

[0005] This disclosure provides a memory fault injection device, method, and related apparatus.

[0006] According to one aspect of this disclosure, a fault injection device is provided, comprising: At least one fault injection module, wherein the fault injection module establishes an electrical connection with the fault injection point of the memory under test through a probe module, wherein the fault injection point is a physical contact point located on the signal transmission path between the memory controller and the memory chip of the memory under test; A controller is configured to control the fault injection module to inject faults into the memory under test in response to an injection signal.

[0007] According to another aspect of this disclosure, a memory fault injection method is provided, applied to the controller of a fault injection device, comprising: In response to an injection signal for a memory fault, the fault injection module is controlled to inject a fault into the memory under test. Obtain memory status data from the memory controller of the memory under test.

[0008] According to another aspect of this disclosure, a fault injection device is provided, and a controller applied to the fault injection device includes: The response module is used to control the fault injection module to inject faults into the memory under test in response to the injection signal for memory faults. The acquisition module is used to acquire memory status data from the memory controller of the memory under test.

[0009] According to another aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and The memory is communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the methods described in the present disclosure.

[0010] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform any of the methods according to embodiments of this disclosure.

[0011] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods according to embodiments of this disclosure.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic diagram of the structure of a memory fault injection device according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of another memory fault injection device according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the circuit structure corresponding to the first injection unit according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the circuit structure corresponding to the second injection unit according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the circuit structure corresponding to the third injection unit according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the circuit structure corresponding to a self-test unit according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the overall structure of a memory fault injection device according to an embodiment of the present disclosure; Figure 8 This is a schematic flowchart of a memory fault injection method according to an embodiment of the present disclosure; Figure 9This is a schematic diagram of the specific process of a memory fault injection method according to an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the structure of a memory fault injection device according to an embodiment of the present disclosure; Figure 11 This is a block diagram of an electronic device used to implement the memory fault injection method of the embodiments of this disclosure. Detailed Implementation

[0014] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0015] The terms “first,” “second,” etc., used in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0016] It should be noted that, unless it is explicitly stated that there is a sequential order of execution between different operations, or that there is a sequential order of execution between different operations in terms of technical implementation, the execution order between multiple operations may not be significant, and multiple operations may be executed simultaneously.

[0017] Traditional memory fault injection devices are typically designed for DIMM (Dual In-line Memory Module) memory modules used in fixed environments such as servers. The core design of traditional memory fault injection is aimed at stable operating environments such as data centers and office equipment, focusing on verifying the memory's fault response and fault tolerance capabilities under normal loads.

[0018] In view of this, this embodiment provides a memory fault injection device, which is suitable for data centers, office equipment, etc., operating in stable environments, and also suitable for electronic devices in vehicles that generate unstable environments during movement. Figure 1 As shown, the memory fault injection device 100 provided in this embodiment includes: At least one fault injection module 101 establishes an electrical connection with the fault injection point of the memory under test 200 via a probe module 102. The fault injection point is a physical contact point located on the signal transmission path between the memory controller 103 and the memory chip 104 of the memory under test 200. As an example, Figure 1 The diagram shows that this physical contact point is a fault injection point on the signal transmission path.

[0019] The controller 105 is used to control the fault injection module 101 to inject faults into the memory 200 under test in response to the injection signal.

[0020] The controller 105 can connect to at least one fault injection module 101, and each fault injection module 101 has its own probe module 102. The probe module 102 serves as a bridge for communication between the fault injection module 101 and the memory under test 200. When the memory fault injection device has multiple fault injection modules 101, each fault injection module 101 can inject faults into one memory under test 200. The same controller 105 can simultaneously control multiple fault injection modules 101 to inject faults into multiple contents under test.

[0021] Each fault injection module 101 has the same structure. The following description will use one fault injection module 101 as an example.

[0022] Among them, the probe module 102 of the fault injection module 101 refers to the physical interface component between the memory fault injection device 100 and the memory under test 200. Through elastic probes, test needles or conductive contacts, it forms a low-impedance and reliable electrical connection with the fault injection point to realize the injection of fault signals and the acquisition of memory status signals without damaging the original hardware structure of the memory under test 200.

[0023] The electrical connection between the probe module 102 and the memory under test 200 refers to the connection relationship between two or more conductive components formed through direct contact or a conductive medium, which is capable of stably transmitting electrical signals or carrying current.

[0024] In this embodiment of the present disclosure, by establishing an electrical connection between the probe module 102 and the fault injection point of the memory under test 200, it can be ensured that the fault signal of the fault injection module 101 can be transmitted to the signal link of the memory under test 200 without abnormality.

[0025] The memory under test 200 is a storage device that is subjected to faults and has its performance verified. It includes memory chip 104, memory controller 103, and DQ (Data Quadrature, memory data line) series resistor 106.

[0026] Among them, the memory controller 103 is the core control chip used to initiate memory read and write operations, control memory timing, process data transmission, monitor memory operating status, and collect and report error information. It is the control core of the memory system.

[0027] The 104 memory chip is the core memory chip that enables data storage and is a basic component of memory.

[0028] The fault injection point is the physical contact point on the signal transmission path between the memory controller 103 and the memory chip 104 of the memory under test 200. It is the access point for the fault signal to enter the memory signal link from the fault injection module 101.

[0029] The signal transmission path refers to the physical link between the memory controller 103 and the memory chip 104 used for transmitting information. In the memory fault injection device 100, it specifically refers to the DQ data signal link of the memory under test 200, which is the core transmission channel for memory read and write data and also the target path for fault injection.

[0030] Physical contact points refer to conductive points that can be reliably contacted by the probes in probe module 102.

[0031] It is understandable that if testing the memory status after a memory fault injection requires the cooperation of other electronic devices, such as other processors and sensors in an autonomous vehicle, then these other electronic devices can interact with the memory under test by referring to the existing processing flow. This disclosure will not elaborate on this.

[0032] In this embodiment of the present disclosure, the fault injection device sets up at least one fault injection module 101, and establishes an electrical connection between it and the fault injection point on the signal transmission path between the memory controller 103 and the memory chip 104 of the memory under test 200 via the probe module 102. Then, the controller 105 responds to the injection signal and controls the fault injection module 101 to perform fault injection. This can simulate different types of faults of the memory under test 200, not limited to operational faults under stable conditions, but also including other types of faults, thereby comprehensively evaluating the design performance of the memory under test 200.

[0033] like Figure 2 As shown, the memory fault injection device 100 provided in this embodiment further includes a host computer module 107, which is used to send test signals to the controller 105. The controller 105 is used to receive the test signals sent by the host computer module 107 in order to perform fault injection on the memory 200 under test.

[0034] The host computer module 107 is a functional module used to realize human-computer interaction, test control and data management. It can be composed of a terminal with a visual operation interface and supporting control software. It communicates bidirectionally with the controller 105 through a communication protocol to issue test configuration commands, control the test process, and receive and parse the memory status data returned by the controller 105, so as to realize the full control of fault simulation test.

[0035] In response to the user's configuration, the host computer module 107 sends a test signal to the controller 105. The controller 105 can execute the test procedure based on the test signal. Furthermore, it can send the test results back to the host computer module 107, or, according to the test procedure, back to other storage devices.

[0036] In this embodiment of the disclosure, the controller 105 receives the test signal sent by the host computer module 107, which can realize the closed-loop control of the entire process of fault simulation test of the DQ of the memory under test 200 from parameter configuration to instruction execution, status feedback and data management, ensuring the convenience of test operation, the accuracy of test control and the traceability of the test process.

[0037] like Figure 2 As shown, the memory fault injection device 100 provided in this embodiment of the present disclosure further includes a power supply unit 108. The power supply unit 108 is used to supply power to the memory under test 200; the controller 105 is also used to control the power supply unit 108 to power on the memory under test 200 again in the event that an unrecoverable error occurs in the memory under test 200.

[0038] Among these, unrecoverable errors, such as system crashes or freezes determined by memory status data obtained through memory controller 103, prevent further testing. Therefore, the memory under test 200 can be powered back on via power supply unit 108 to allow the fault injection test to continue.

[0039] In this embodiment, the power supply unit 108 independently provides a stable power supply to the memory under test 200, ensuring the normal operation of the memory under test 200 and the independence of the test environment. When the controller 105 detects that the memory under test 200 has an unrecoverable error that cannot be repaired by conventional methods due to fault injection, it sends a control command to the power supply unit 108, controlling the power supply unit 108 to perform a power-off and power-on re-energization operation on the memory under test 200, so that the memory under test 200 returns to its initial normal working state, ensuring that the test process can be automatically and continuously executed, while avoiding hardware damage to the memory under test 200 due to prolonged abnormal state, thus improving the safety and stability of the test system.

[0040] In this embodiment of the disclosure, for each fault injection module 101, the fault injection module 101 includes at least one of the following units: (1) The first injection unit is used to simulate the short-circuit fault to ground of the DQ of the memory under test 200; A short circuit to ground fault refers to an abnormal connection between DQ and ground (GND, Ground), forming a low-impedance or even near-zero-impedance conduction path. This causes the DQ signal level to be forcibly pulled to ground potential, preventing normal signal transmission and leading to abnormalities such as data errors and communication interruptions.

[0041] (2) The second injection unit is used to simulate the ground impedance change fault of DQ; A ground impedance variation fault refers to a fault in which the equivalent impedance between DQ and ground deviates from the normal operating standard value, exhibiting abnormal increases, decreases, or continuous fluctuations. This can lead to problems such as transmission delays and signal attenuation in the signal transmitted through the memory data line DQ, resulting in abnormalities such as memory data read / write errors.

[0042] (3) The third injection unit is used to simulate the fault caused by interference signals to DQ.

[0043] Interference signal-induced faults refer to the distortion of the level, edge, and timing of normal data signals caused by external or internal interference signals coupled to the memory data line DQ, which prevents the memory controller 103 from correctly sampling and identifying data, thus causing data transmission errors and other faults.

[0044] In this embodiment, three types of faults are specifically simulated in the DQ of the memory under test 200: short circuit to ground, change in impedance to ground, and interference signal. This allows for flexible selection of single or multiple fault combinations based on testing needs, reproducing various fault scenarios encountered during actual operation of the memory under test 200. This enables a comprehensive and multi-dimensional evaluation of the memory under test 200's fault tolerance. In particular, it can reproduce electromagnetic interference during the operation of autonomous driving strategies, thus better testing the corresponding memory in autonomous vehicles.

[0045] Each fault injection module 101 has a probe module 102, and each probe module 102 is as follows: Figure 2 As shown, it includes at least one of the following probes: (1) The first probe 1021 is used for electrical connection with the first injection point; The first probe 1021 refers to the component in the probe module 102 used to establish an electrical connection with the first injection point. The first injection point is located along the signal transmission direction and is relatively close to the memory controller 103.

[0046] The signal transmission direction can be understood as the signal transmission direction from memory chip 104 to memory controller 103.

[0047] (2) The second probe 1022 is used for electrical connection with the second injection point; The second probe 1022 is similar to the first probe 1021 and is also a component used to establish an electrical connection. The second injection point is also located on the signal transmission path between the memory controller 103 and the memory chip 104, but compared with the first injection point, it is farther away from the memory controller 103 and relatively closer to the memory chip 104 along the signal transmission direction.

[0048] In this embodiment, the probe module 102 is equipped with at least one of a first probe 1021 and a second probe 1022 and is correspondingly connected to the first injection point and the second injection point. This enables the electrical connection between the fault injection module 101 and the memory under test 200, allowing the fault signal to be accurately applied to the core data transmission path between the memory controller 103 and the memory chip 104, ensuring the targeting and effectiveness of the fault injection. At the same time, it adapts to the point access requirements of different fault injection modules 101, providing stable and reliable physical interface support for the accurate simulation of various faults.

[0049] Wherein, the first injection point and the second injection point satisfy any of the following requirements: (1) Set across the two ends of the DQ series resistor 106; The DQ series resistor 106 is a standard matching resistor connected in series with DQ. It has the functions of current limiting, anti-interference, and signal impedance matching. It is directly soldered to the conductive line of the memory data line DQ, and the metal pads / lines at both ends of it are directly connected to the 200 data line DQ of the memory under test.

[0050] By setting the first and second injection points at the two ends of the resistor, the fault signal can be directly applied to the main circuit of the memory data line DQ. Furthermore, by utilizing the series characteristics of the resistor, the transmission of the fault signal in different segments of the memory data line DQ can be flexibly controlled, thereby ensuring the accuracy and repeatability of fault injection.

[0051] In practice, if the memory under test 200 has a DQ series resistor 106, the two ends of the DQ series resistor 106 can be selected as the first injection point and the second injection point. If the memory under test 200 does not have a DQ series resistor 106, the following scheme (2) or (3) can be selected.

[0052] (2) Reserved flying wire access points for testing; Reserved flying lead access points for testing refer to test points specifically reserved in advance for subsequent testing or debugging of the DQ. They are usually metal pads, pin headers, or reserved solder holes on the PCB (Printed Circuit Board), which are directly connected to the conductive lines of the memory data lines DQ. There are no actual components soldered on them; they are only used for temporary access to test flying leads / probes.

[0053] (3) Welding points of DQ.

[0054] DQ solder joints refer to the solder joints inherent to DQ components on the PCB, including solder joints such as the 103-pin pad of the memory controller and the 104-pin pad of the memory chip, which have extremely strong hardware compatibility.

[0055] In this embodiment, the first injection point and the second injection point are set to any of the following locations: the two ends of the DQ series terminal block, the reserved test flying wire access point, or the DQ solder point. This allows for adaptation to different hardware designs and testing scenarios of the memory under test 200, providing flexible, diverse, and practical fault injection point selection. Electrical connection between the fault injection module 101 and the memory data line DQ can be achieved without additional complex modifications to the original circuitry of the memory under test 200, ensuring the effectiveness and accuracy of the fault signal application. Simultaneously, it makes fault injection operations more convenient and adaptable, meeting the memory fault injection needs under different testing environments.

[0056] In some embodiments, to simulate a short-circuit fault to ground in the data line DQ of the memory under test 200, such as Figure 3 As shown, the first injection unit includes a first switch 109.

[0057] like Figure 3 The circuit structure shown simulates a short-to-ground fault in the DQ of the memory under test 200. One end of the first switch 109 is connected to the second probe 1022, and the other end is grounded. Figure 3 The diagram also shows a switch driver 120 disposed between the first switch 109 and the controller 105, so that the controller 105 can control the first switch 109 to be turned on and off through the switch driver 120.

[0058] The circuit connection state can be changed by controlling the first switch 109 to be turned on and off. When the switch is turned on, it is equivalent to connecting the DQ of the memory under test 200 to ground, simulating a short circuit to ground fault.

[0059] In this embodiment of the present disclosure, when the first switch 109 is turned on, the second probe 1022 is used to connect the DQ data line of the memory under test 200 to ground, thereby simulating the ground short circuit fault of the DQ data line of the memory under test 200. This enables the controllable start and stop of the ground short circuit fault and can flexibly simulate the instantaneous or continuous DQ ground short circuit scenario of the memory under test 200.

[0060] like Figure 3 As shown, in the circuit structure simulating a short-circuit fault to ground in the DQ of the memory under test 200, the controller 105 is used to control the duration of the first switch 109 being turned on in response to the injection signal of the short-circuit fault to ground, so as to inject the short-circuit fault to ground into the memory under test 200; and reads the memory status data after the injection of the short-circuit fault to ground from the memory controller 103.

[0061] Specifically, after receiving the injection signal for a short-circuit fault to ground sent by the host computer module 107, the controller 105 executes a switch control action. By adjusting the on-time of the first switch 109, a short-circuit fault to ground for a corresponding duration is injected into the data line DQ of the memory under test 200. During the injection of the short-circuit fault to ground, the controller 105 communicates synchronously with the memory controller 103 of the memory under test 200 to actively obtain memory operating status data after the fault injection, including but not limited to: whether there are read / write errors in the memory, whether there are single-bit / multi-bit errors, whether the communication link is abnormal, and whether the ECC (Error-Correcting Code) error correction mechanism is triggered.

[0062] The duration of the switch's on / off state affects the degree of short-circuit-to-ground fault to varying degrees. For example, when the first switch 109 is continuously on, it is equivalent to connecting the data line DQ of the memory under test 200 to ground through a low-impedance path, simulating a prolonged short-circuit-to-ground fault in the DQ line of the memory under test 200. By controlling the first switch 109 to be on briefly and then off quickly, the instantaneous connection state of the circuit can be changed. When the switch is pulsed on for a very short time, it is equivalent to momentarily connecting the data line DQ of the memory under test 200 to ground, simulating a brief pulse-type short-circuit-to-ground fault in the DQ line of the memory under test 200.

[0063] In this embodiment, the controller 105 responds to the injection signal of the short-circuit fault to ground and controls the on-time of the first switch 109 to inject a DQ short-circuit fault of the corresponding duration into the memory under test 200. It can also read relevant memory status data from the memory controller 103 after the fault injection. This not only achieves precise control of the short-circuit fault injection time, but also flexibly simulates different types of short-circuit fault scenarios such as instantaneous pulse type and continuous type. Furthermore, it can intuitively reflect the memory operation status after the fault injection through the acquired status data.

[0064] The pulse width supported by the first switch 109 is within a first width range; the controller 105 controls the test memory 200 to generate different bit errors by controlling the pulse width of the first switch 109. The controllable pulse width is located between the first width and the second width; the first width is less than a preset picosecond, and the second width is greater than a preset nanosecond.

[0065] The controller 105 outputs a drive signal to the first switch 109 to adjust its conduction duration, i.e., pulse width, thereby controlling the duration of the DQ signal short-circuited to ground, which in turn causes the memory under test 200 to generate different bit errors. The correspondence between pulse width and the number of error bits is based on the unit time UI of memory data transmission (UI = 1 / data transmission rate (MT / s)). For example, when the pulse width is ≤ the first reference value, which is less than 1, such as 0.8UI, the memory under test 200 may generate a 1-bit error. When it is between the second and third reference values, where both the second and third reference values ​​are greater than 1 and less than 2, such as 1.2UI ≤ pulse width ≤ 1.8UI, the memory under test 200 may generate a 2-bit error. When it is greater than the fourth reference value, which is greater than 2, such as pulse width ≥ 2.2UI, the memory under test 200 may generate more than 2 bit errors. During the control process, the controller 105 avoids fuzzy intervals in different ranges, such as the transition ranges from 0.8UI to 1.2UI and from 1.8UI to 2.2UI, which can improve the accuracy of memory fault injection.

[0066] In this embodiment of the disclosure, the pulse width adjustable by the controller 105 is within the range of a first width to a second width, wherein the first width is the minimum adjustable pulse width of the controller 105, and its value is less than a preset picosecond threshold. For example, this threshold is not less than the minimum on-time of the first switch 109, which is 500 ps. The second width is the maximum adjustable pulse width of the controller 105, and its value is greater than a preset nanosecond threshold, for example, this threshold is not greater than the maximum on-time of the first switch 109, which is 10 ns.

[0067] In this embodiment, by limiting the pulse width supported by the first switch 109 to a corresponding first width range, and the pulse width adjustable by the controller 105 to fall between a first width less than a preset picosecond and a second width greater than a preset nanosecond, the controller 105 can precisely control the pulse width to trigger different bit error faults of the memory under test 200. This allows matching the pulse width thresholds corresponding to different bit errors, accurately simulating different degrees of bit error faults such as single-bit and multi-bit faults of the memory under test 200, improving the accuracy of testing the memory under test 200 for short-circuit faults with different pulse widths, and protecting the memory under test 200.

[0068] In some embodiments, the second injection unit used to simulate the ground impedance variation fault of DQ is as follows: Figure 4 The diagram shows a second switch 110 and a variable resistor 111; like Figure 4The diagram shows a circuit structure for simulating a ground impedance variation fault in a DQ circuit. One end of the second switch 110 is connected to the first probe 1021, and the other end is connected to a variable resistor 111. The first end (not shown in the figure) of the variable resistor 111 is connected to the second switch 110, the second end (not shown in the figure) is grounded, and the third end (not shown in the figure) is connected to the controller 105.

[0069] The variable resistor 111 may include a digitally controlled variable resistor or a programmable resistor device, which refers to an electronic device that receives control signals through a digital interface and adjusts the position of the vernier contact to change the effective resistance value. It may include a resistor string, a switch array and digital control logic, and can achieve the same electronic adjustment function as a mechanical potentiometer or rheostat.

[0070] In this embodiment, one end of the second switch 110 is connected to the first probe 1021 and the other end is connected to the variable resistor 111. The variable resistor 111 is connected to the second switch 110, grounded, and communicated with the controller 105. This structure can controllably switch on and off the impedance change fault branch through the second switch 110. At the same time, the controller 105 precisely adjusts the resistance value of the variable resistor 111 through the third terminal. With the help of the first probe 1021, different preset impedances are coupled between the DQ data line and ground, which can flexibly and accurately simulate the fault caused by the abnormal change of the impedance to ground of the DQ data line.

[0071] like Figure 4 As shown, in the circuit structure simulating the ground impedance change fault of DQ, the controller 105 responds to the injected signal of the change impedance by turning on the second switch 110 through the switch driver 120; controls the variable resistor 111 through the third terminal to generate a preset impedance; and reads the memory status data after the injected impedance change fault from the memory controller 103.

[0072] After receiving the impedance change injection signal sent by the host computer module 107, the controller 105 executes a switch control action to turn on the second switch 110, so that the variable resistor 111 is connected to the impedance adjustment branch between the data line DQ of the memory under test 200 and ground. After the second switch 110 is turned on and the impedance adjustment branch is connected, the controller 105 sends a control command through the third terminal of the variable resistor 111 to adjust the resistance value of the variable resistor 111 so that it generates and outputs a preset impedance that matches the injection signal, thereby injecting a ground impedance change fault of the corresponding impedance value into the DQ data line of the memory under test 200. After each impedance change fault injection, the controller 105 communicates with the memory controller 103 of the memory under test 200 to actively obtain the memory operating status data after the fault injection, including but not limited to: whether memory read and write are abnormal, whether there are data sampling errors, whether signal transmission is stable, and whether the error detection mechanism is triggered. The controller 105 analyzes and judges the received memory status data. It can evaluate the tolerance and fault resistance of the memory under test 200 to different degrees of ground impedance abnormality through the memory status data under different preset impedances. If the memory under a certain preset impedance has a continuous abnormality, it can accurately locate the sensitive threshold of the memory under test 200 for that impedance fault.

[0073] In this embodiment, the controller 105 responds to the injection signal of the change in ground impedance to complete the connection of the second switch 110 and the adjustment of the preset impedance of the variable resistor 111, so as to realize the controllable injection of the DQ ground impedance change fault of the memory under test 200. Then, by reading the memory status data after the fault injection, it can flexibly simulate the abnormal ground impedance fault scenario under different resistance values, and can intuitively reflect the operating status of the memory under various impedance faults through the acquired status data, so as to ensure the accuracy of the test process.

[0074] The variable resistor 111 supports a resistance range between the first ohm and the second ohm; the first ohm is less than the second ohm, and the difference between the first ohm and the second ohm is greater than kiloohms.

[0075] In this embodiment, the supported resistance range of the variable resistor 111 is set between the first ohm and the second ohm, and it is clearly stated that the first ohm is less than the second ohm and the difference between the two is greater than 1,000 ohms. This provides a wide range of resistance adjustment space with sufficient span for simulating the ground impedance change fault of the DQ of the memory under test 200. It can accurately reproduce various ground impedance abnormality scenarios from low resistance to high resistance, match the different impedance fault types in actual memory operation, and make the fault simulation more in line with the real working conditions.

[0076] In some embodiments, such as Figure 5 As shown, the third injection unit for simulating a fault caused by interference signals in the DQ includes: interference signal generator 112, first resistor 113 and third switch 114; like Figure 5 The circuit structure shown is used to simulate a fault caused by interference signals in the DQ. The first terminal of the interference signal generator 112 is connected to the controller 105; the second terminal of the interference signal generator 112 is connected to the second probe 1022; the third terminal of the interference signal generator 112 is connected to the first resistor 113; the first resistor 113 is connected to the third switch 114; and the third switch 114 is connected to the first probe 1021.

[0077] In this embodiment, the controller 105 regulates the interference signal generator 112 to generate a target interference waveform. The first resistor 113 limits the interference intensity, and the third switch 114 controls the on / off state of the interference branch. The interference signal is then coupled to the DQ of the memory under test 200 via the first probe 1021 and the second probe 1022. This allows for flexible and accurate simulation of faults caused by various interference signals, such as internal crosstalk, power supply noise, and external electromagnetic radiation, affecting the DQ of the memory under test 200. Simultaneously, through the coordinated operation of various devices, flexible generation, precise control, and safe injection of interference signals are achieved, ensuring the realism, controllability, and adaptability of the DQ interference fault simulation of the memory under test 200. For autonomous vehicles, this method can adapt to the testing requirements of special scenarios, namely electromagnetic interference scenarios.

[0078] like Figure 5 As shown, in the circuit structure simulating a fault caused by interference signal in the DQ, the controller 105 responds to the injection signal of the injected interference fault by turning on the third switch 114; the first terminal of the interference signal generator 112 controls the interference signal generator 112 to generate interference information, so as to apply the interference signal to the memory under test 200 through the first probe 1021 and the second probe 1022; and reads the memory status data after the injected interference fault from the memory controller 103.

[0079] After receiving the injection signal for the injected interference fault, the controller 105 can execute a switch control action through the switch driver 120 to turn on the third switch 114, thus fully connecting the interference fault injection branch between the interference signal generator 112, the first resistor 113, the first probe 1021, and the second probe 1022. After the third switch 114 is turned on and the interference fault injection branch is connected, the controller 105 sends a control command through the first terminal of the interference signal generator 112 to regulate the interference signal generator 112 to generate and output interference information matching the test requirements. In this way, the interference signal is applied to the series resistor of the DQ of the memory under test 200 through the first probe 1021 and the second probe 1022. After the interference fault injection is completed, the controller 105 communicates with the memory controller 103 of the memory under test 200 to actively obtain the memory operating status data after the injection of the interference fault, including but not limited to: whether memory read and write are abnormal, whether there are data transmission errors, whether signal sampling is stable, and whether error detection and correction mechanisms are triggered.

[0080] In this embodiment, the controller 105 responds to the injection signal by activating the third switch 114, regulating the interference signal generator 112 to generate corresponding interference information, which is then applied to the memory under test 200 via a probe. The controller then reads the memory status data after the fault, thus achieving controllable start / stop of interference fault injection and precise control of the interference signal. This allows for flexible simulation of various interference scenarios encountered by the memory under test 200 during actual operation. The acquired status data provides intuitive feedback on the memory's operating status after interference, ensuring the controllability of the testing process and the authenticity and traceability of the test results.

[0081] Specifically, the interference signal may include radiated interference; the controller 105 is used to control the interference signal generator 112 to generate at least one of the following interferences: (1) Interference signals of different amplitudes; In this embodiment of the disclosure, the interference signals of different amplitudes refer to the various interference waveforms with different voltage amplitudes generated by the controller 105 by configuring the output voltage parameters of the interference signal generator 112, which are coupled and superimposed on the series resistor of the DQ of the memory under test 200 through the coupler, and finally applied to the DQ of the memory under test 200.

[0082] (2) Interference signals of different frequencies.

[0083] The interference signals of different frequencies are generated by the controller 105 through configuring the sampling rate, waveform period, and spectrum parameters of the interference signal generator 112, generating interference waveforms with different time-domain change rates and frequency-domain energy distributions, and then applied to the DQ of the memory under test 200 via a coupler.

[0084] In this embodiment, the controller 105 responds to the interference fault injection signal to turn on the third switch 114 and adjust the parameters of the interference signal generator 112. With the help of the first probe 1021 and the second probe 1022, the interference signal is accurately applied to the DQ of the memory under test 200. The memory status data after the fault injection is read simultaneously. This not only enables the controllable start and stop of interference injection and signal adjustment, but also provides intuitive feedback on the operating status of the memory under interference fault through the acquired status data. This provides real and effective data support for analyzing the anti-interference performance, signal stability and interference fault response mechanism of the memory under test 200.

[0085] Wherein, the resistance value of the first resistor 113 is a preset multiple of the target resistance value; the target resistance value is the resistance value between the first access point and the second access point; the preset multiple is greater than or equal to the first multiple and less than or equal to the second multiple.

[0086] like Figure 5 As shown, the first access point and the second access point are nodes directly connected across the two ends of the DQ series resistor 106. The only component between these two points is the DQ series resistor 106. Therefore, the resistance value in this range is the resistance value of the DQ series resistor 106 itself, which serves as the reference for the resistance value of the first resistor 113.

[0087] In simulating a fault caused by interference signals in the DQ bus, the first resistor 113 used for interference coupling has a resistance value selected as a fixed multiple of the resistance value of the DQ series resistor 106. For example, the fixed multiple can be limited to between 10 and 100 times, ensuring that the interference signal can be effectively coupled to the DQ bus to achieve the expected fault simulation effect, without affecting the original normal signal transmission of the DQ bus.

[0088] In this embodiment, the resistance value of the first resistor 113 is set to a preset multiple of the target resistance value between the first and second access points, and the multiple is limited to between the first and second multiples. This can match the impedance characteristics of the interference signal application link, realize the impedance matching of the link and the signal impedance adjustment, and ensure that the interference signal is accurately applied to the data line DQ of the memory under test 200 through the first probe 1021 and the second probe 1022 with a stable amplitude and frequency. This makes the simulation of interference faults more accurate and closer to the actual working conditions, and at the same time provides suitable impedance support for the stable transmission of interference signals of different intensities, ensuring the accuracy and reliability of interference fault injection testing.

[0089] In this embodiment of the disclosure, in order to improve the accuracy of fault injection testing, before the aforementioned fault injection module injects a fault, a self-test can be performed to confirm that the access of the memory fault injection device 100 will not bring additional uncontrollable interference or fault simulation signals to the memory under test, such as... Figure 6As shown, the memory fault injection device 100 of this embodiment also provides a self-test unit to perform a fault-free injection self-test before fault injection, confirming that the test device does not interfere with the normal operation of the memory. Figure 6 As shown, the self-test unit includes a fourth switch 115 and a second resistor 116.

[0090] like Figure 6 The circuit structure for self-test is shown. The first probe 1021, the fourth switch 115, the second resistor 116, and the second probe 1022 are connected in series.

[0091] In this embodiment, a self-test unit consisting of a fourth switch 115, a second resistor 116, and a first probe 1021 and a second probe 1022 connected in series performs a fault-free injection self-test before fault injection. This verifies in advance that the fault injection device itself has not introduced any interference signals or falsely triggered fault simulation signals into the test link, thereby confirming that the hardware and connection links of the memory under test 200 are in a normal fault-free injection state. This avoids interference to the memory under test 200 caused by the access of the memory fault injection device 100, which could lead to the memory under test 200 failing to operate normally. This embodiment can eliminate other interference factors from the source of testing as much as possible, ensuring that all kinds of errors that occur in the memory during subsequent fault injection testing are caused by faults accurately simulated by the device, thus ensuring the authenticity, accuracy, and effectiveness of the fault injection test results.

[0092] like Figure 6 As shown, in the circuit structure used for self-test, the controller 105 is used to respond to the test signal of self-test by controlling the fourth switch 115 to connect the second resistor 116 and the first probe 1021 through the switch driver 120; read memory status data from the memory controller 103; and output the self-test result when it is determined that the memory status data indicates that the memory under test 200 is in a correct state.

[0093] After receiving the trigger signal to start the self-test, controller 105 executes a switch control action, turning on the fourth switch 115, thus fully connecting the self-test series branch between the second resistor 116, the first probe 1021, and the second probe 1022. With the fourth switch 115 on and the self-test branch connected, controller 105 communicates with the memory controller 103 of the memory under test 200, actively acquiring the memory's current operating status data, including but not limited to: whether memory read / write is normal, and whether there are ECC errors. The controller parses and judges the received memory status data. Only when the data clearly shows that memory read / write is normal, there are no errors, and communication is stable, is the self-test considered successful, and a self-test pass result is output. If a memory error or abnormality occurs, it indicates that the memory under test may have a problem, and the hardware connections of probe module 102, the fourth switch 115, and the coupler need to be checked for proper functioning.

[0094] In this embodiment, the controller 105 uses the self-test control logic described above, triggering a self-test signal, to verify in a standardized manner whether the memory under test 200 maintains normal operation after the self-test path is established. When the communication status of the memory under test 200 is confirmed to be normal, the controller outputs the self-test result, effectively identifying equipment faults such as poor probe contact or broken links. This ensures that the hardware of the testing device is in a normal and usable state before fault injection, avoiding distortion of subsequent fault injection test results due to device problems, and guaranteeing the accuracy, reliability, and automated continuity of the entire memory fault injection test process.

[0095] In summary, taking the memory under test 200 having a DQ series resistor as an example, the structural schematic diagram of the memory fault injection device 100 provided in this embodiment of the disclosure is as follows: Figure 7 As shown, it includes: At least one fault injection module 101, taking one of the fault injection modules 101 as an example, the fault injection module 101 establishes an electrical connection with the fault injection point of the memory under test 200 through the probe module 102.

[0096] The probe module 102 is used to establish an electrical connection with the fault injection point of the memory under test 200, ensuring that the fault signal of the fault injection module 101 can be transmitted to the signal link of the memory under test 200 without abnormality. The probe module 102 includes a first probe 1021 for electrical connection with a first injection point and a second probe 1022 for electrical connection with a second injection point.

[0097] The memory controller 103 is a core control chip used to initiate memory read and write operations, control memory timing, process data transmission, monitor memory operating status, and collect and report error information.

[0098] The 104 memory chip is the core memory chip used to implement data storage functions.

[0099] The controller 105 is used to control the fault injection module 101 to inject faults into the memory under test 200 in response to the injection signal.

[0100] like Figure 7 The DQ series resistor 106 of the memory under test 200 shown is used to achieve impedance matching of the DQ signal transmission path, eliminate signal reflection caused by impedance discontinuity during signal transmission between the memory controller 103, the transmission line and the memory chip, avoid signal distortion and jitter caused by the superposition of reflected signal and original signal, and ensure the integrity of signal waveform during high-speed data transmission.

[0101] The host computer module 107 is used to send test signals to the controller 105 and receive and parse the memory status data returned by the controller 105, so as to realize the full control of the fault simulation test.

[0102] The power supply unit 108 is used to supply power to the memory under test 200 and to ensure that the memory under test 200 is powered on again in the event of an unrecoverable error.

[0103] The first switch 109, with one end connected to the second probe 1022 and the other end grounded, forms the first injection unit, which is used to simulate the short circuit to ground fault of the data line DQ of the memory under test 200.

[0104] The second switch 110 is connected to the first probe 1021 at one end and to the variable resistor 111 at the other end. The first end of the variable resistor 111 is connected to the second switch 110, the second end is grounded, and the third end is connected to the controller 105, thus forming a second injection unit, which is used to simulate the ground impedance change fault of DQ.

[0105] The variable resistor 111 is used to adjust the resistance in the case of a fault with varying impedance to ground in the simulated DQ.

[0106] The interference signal generator 112 includes a DAC data converter 1121, a primary coupler coil 1122, a coupling magnetic core 1123, and a secondary coupler coil 1124. In a specific implementation, after the DAC chip generates interference signals of different amplitudes and frequencies, these signals are coupled to the DQ series resistor through the coupler composed of the primary coupler coil 1122, the coupling magnetic core 1123, and the secondary coupler coil 1124.

[0107] The first resistor 113 is used to achieve impedance matching and signal impedance adjustment of the link, ensuring that the interference signal is accurately applied to the data line DQ of the memory under test 200 through the first probe 1021 and the second probe 1022 with a stable amplitude and frequency.

[0108] The third switch 114, together with the interference signal generator 112, the second probe 1022, and the first resistor 113, forms a third injection unit, which is used to simulate the circuit of DQ suffering from a fault caused by an interference signal.

[0109] The fourth switch 115, connected in series with the first probe 1021, the second resistor 116, and the second probe 1022, forms a self-test unit to confirm that the test equipment does not interfere with the normal operation of the memory.

[0110] The aforementioned switches can be implemented as MOS (Metal-Oxide-Semiconductor) switches, and the switching on and off are controlled by the switch driver 120. In this embodiment, when the controller 105 and the MOS driver (i.e., switch driver 120) simulate a short-circuit fault to ground, the MOS switch supports the generation of ultra-short pulses. The MOS switch conduction time is 500ps~10ns, which can induce single-bit and multi-bit errors in the memory. When simulating a fault caused by a change in impedance to ground, the controller 105 communicates with the digital potentiometer (i.e., variable resistor 111) via SPI (Serial Peripheral Interface), IIC (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), etc., to set the conduction resistance and simulate a fault caused by a change in the impedance to ground of the memory DQ harness. The adjustable range of the variable resistor is 0Ω~10kΩ. The implementation sequence requires setting the resistor first and then turning on the MOS switch. Due to the influence of the digital potentiometer, the extremely short pulse fault injection of path 2 cannot be achieved, but different resistors can be adjusted to observe the system performance of the memory under test. The controller 105 also simulates a fault caused by interference to the memory DQ (which may include internal crosstalk of the scenario). Interference signals, including periodic pulse signals, sawtooth signals, white noise, and power switch-like signals, are applied to the DQ harness. To control the coupling signal strength and interference effect, the first resistor is 10 to 100 times the resistance of the DQ series resistor.

[0111] The second resistor 116 is used to match the impedance characteristics of the DQ signal transmission link between the self-test branch and the memory under test 200, so as to avoid signal reflection, crosstalk and other problems caused by impedance mismatch after the self-test branch is connected, and ensure that the signal transmission of the memory under test 200 is not affected during the self-test, and ensure that the memory can maintain normal operation during the self-test.

[0112] Based on the same technical concept, this disclosure also provides a memory fault injection method, applied to the controller 105 of the memory fault injection device 100, such as... Figure 8 As shown, it includes the following: S801, in response to an injection signal for memory faults, controls the fault injection module 101 to inject a fault into the memory under test 200.

[0113] S802 obtains memory status data from the memory controller 103 of the memory under test 200.

[0114] In this embodiment, the standardized execution of memory fault injection and status acquisition is achieved through the controller 105. First, a simulated injection of the corresponding fault type is triggered based on the injection signal. Then, memory status data is directly obtained from the memory controller 103 of the memory under test 200. This ensures that the acquired data can truly reflect the actual operating status and fault response results of the memory after fault injection. In this way, a test closed loop of fault injection-real-time status acquisition is established, which provides real and effective test data support for subsequent analysis of the fault tolerance and anti-interference capabilities of memory and autonomous driving system for various faults. At the same time, it can simplify the operation process of fault testing and improve the efficiency and accuracy of memory fault injection testing.

[0115] In summary Figure 7 and Figure 8 After connecting the fault injection module 101 of the memory fault injection device to the memory under test 200 via the probe module 102, this disclosure provides a specific process for a memory fault injection method as follows: Figure 9 As shown, it includes the following: S901, the host computer module 107 responds to user operation to set up the test channel.

[0116] The test channels provided for configuration include a first injection unit, a second injection unit, and a third injection unit. The appropriate test channel can be selected based on testing requirements to perform fault injection and testing on the memory 200 under test.

[0117] S902, Controller 105 initiates the device self-test process.

[0118] In other words, controller 105 responds to the set test channel and performs a self-test via the self-test unit. Controller 105 connects the fourth switch 115 via the MOS driver, and controller 105 assesses the impact of the relevant link corresponding to the probe module 102 on memory communication. According to the test procedure set by the host computer module 107, when the fourth switch 115 is turned on, controller 105 reads memory status data from memory controller 103. If the memory status data indicates that the memory is working normally and there are no errors, the self-test is considered passed, and subsequent fault injection operations can be performed. If the self-test fails, the device fault needs to be checked.

[0119] S903, controller 105 determines whether the self-test has passed. If the self-test passes, continue to step S905; otherwise, proceed to step S704.

[0120] S904, Controller 105 indicates a device malfunction requiring inspection.

[0121] S905, the controller 105 selects the fault injection mode according to the test procedure set by the host computer module 107.

[0122] The fault injection mode selects which type of fault to inject. During implementation, the first injection unit, the second injection unit, and the third injection unit each correspond to a fault type. The fault injection of these fault types can be implemented sequentially according to the process set by the host computer module 107.

[0123] S906, the controller 105 injects the corresponding fault into the memory 200 under test through the corresponding fault injection unit.

[0124] As described above, fault injection includes at least one of the following: (1) Used to simulate a short circuit to ground fault in the memory data line DQ of the memory under test 200; (2) Used to simulate the ground impedance variation fault of the DQ; (3) Used to simulate the fault caused by interference signals to the DQ.

[0125] S907, after the controller 105 is injected, it reads memory status data from the memory controller 103 in order to record memory error information and record the fault performance of the memory controller 103.

[0126] The memory error information includes memory errors such as ECC error correction, multi-bit errors, and chipkill (ChipkillCorrect, single-chip complete failure error correction); system errors caused by memory errors, such as system crash files and uncorrectable errors, etc., to evaluate the system performance after the error is injected.

[0127] S908, the controller 105 determines whether an unrecoverable error has occurred, such as a system crash or a CPU (Central Processing Unit) stagnation. If yes, proceed to step S909; otherwise, proceed to step S910.

[0128] S909, controller 105 controls power supply unit 108 to power on and restore the memory under test 200, and records one restart.

[0129] S910, controller 105 starts the next test and returns to continue execution S902.

[0130] S911, the controller 105 confirms the end of the test and sends the test results and log files temporarily stored in the storage device back to the host computer module 107.

[0131] In summary, this disclosure provides a memory fault injection method designed for memory usage scenarios in autonomous vehicles. It can meet various fault scenarios, simulating rapid short-circuit faults to ground in memory data lines, impedance variation faults to ground in memory data lines, and interference from the complex electromagnetic environment in a vehicle on memory data line communication. It achieves excellent memory fault injection results and comprehensively evaluates memory design and system design performance. Faults are injected into the system to evaluate system robustness, fault correction capabilities, fault isolation capabilities, and fault recovery capabilities after a fault occurs.

[0132] Furthermore, during the design phase, fault injection can enhance design robustness, optimize hardware, software, and system design to address faults, and proactively avoid or respond to potential faults. During the product phase, this equipment and method can be used to simulate field faults in the laboratory, enhancing understanding of field faults and aiding in field problem analysis. During the after-sales phase, fault injection methods can be used to reproduce problems, quickly check changes in memory fault detection / correction / recovery mechanisms of faulty components, and can also be used for product inspection.

[0133] The memory fault injection method provided in this disclosure can be applied to memory usage scenarios in autonomous vehicles to improve the verification effect of memory fault injection in autonomous vehicles. For example, it can simulate rapid short-circuit faults to ground in memory data lines, impedance change faults to ground in memory data lines, and interference from complex electromagnetic environments in automobiles on memory data line communication. This can achieve excellent memory fault injection results and comprehensively evaluate the performance of memory design and system design.

[0134] Based on the same technical concept, this disclosure also provides a memory fault injection device 1000 and a memory fault injection equipment 100, such as... Figure 10 As shown, it includes: The response module 1001 is used to control the fault injection module to inject a fault into the memory under test 200 in response to an injection signal for memory fault. The acquisition module 1002 is used to acquire memory status data from the memory controller of the memory under test 200.

[0135] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.

[0136] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0137] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0138] Figure 11 A schematic block diagram of an example electronic device 1100 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0139] like Figure 11 As shown, device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1102 or a computer program loaded into random access memory (RAM) 1103 from storage unit 1108. The RAM 1103 may also store various programs and data required for the operation of device 1100. The computing unit 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0140] Multiple components in device 1100 are connected to I / O interface 1105, including: input unit 1106, such as keyboard, mouse, etc.; output unit 1107, such as various types of monitors, speakers, etc.; storage unit 1108, such as disk, optical disk, etc.; and communication unit 1109, such as network card, modem, wireless transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0141] The computing unit 1101 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1101 performs the various methods and processes described above, such as memory fault injection methods. For example, in some embodiments, the memory fault injection method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by the computing unit 1101, one or more steps of the memory fault injection method described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured to perform a memory fault injection method by any other suitable means (e.g., by means of firmware).

[0142] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0143] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0144] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0145] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0146] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0147] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0148] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0149] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory fault injection device, comprising: At least one fault injection module, wherein the fault injection module establishes an electrical connection with the fault injection point of the memory under test through a probe module, wherein the fault injection point is a physical contact point located on the signal transmission path between the memory controller and the memory chip of the memory under test; A controller is configured to control the fault injection module to inject faults into the memory under test in response to an injection signal.

2. The device according to claim 1, wherein, Each of the fault injection modules includes at least one of the following units: The first injection unit is used to simulate a short-circuit fault to ground in the memory data line DQ of the memory under test. The second injection unit is used to simulate the ground impedance variation fault of the DQ; The third injection unit is used to simulate the fault caused by interference signals to the DQ.

3. The device according to claim 2, wherein the probe module comprises at least one of the following probes: The first probe is used for electrical connection with the first injection point. The second probe is used for electrical connection to the second injection point; Along the signal transmission direction, the first injection point is closer to the memory controller than the second injection point.

4. The device according to claim 3, wherein the first injection unit includes a first switch; One end of the first switch is connected to the second probe, and the other end is grounded.

5. The device according to claim 4, wherein, The controller is specifically used for: In response to the injection signal of a short circuit to ground fault, the duration of the first switch being turned on is controlled to inject a short circuit to ground fault into the memory under test. Read memory status data after a short-circuit fault to ground from the memory controller.

6. The device according to claim 4 or 5, wherein the pulse width supported by the first switch is within a first width range; The controller controls the pulse width of the first switch to generate different bit errors in the memory under test. The controllable pulse width is located between a first width and a second width; the first width is less than a preset picosecond, and the second width is greater than a preset nanosecond.

7. The device according to claim 3, wherein the second injection unit comprises a second switch and a variable resistor; One end of the second switch is connected to the first probe, and the other end is connected to the variable resistor; The first end of the variable resistor is connected to the second switch, the second end is grounded, and the third end is connected to the controller.

8. The device according to claim 7, wherein, The controller is specifically used for: In response to the injected signal that changes the impedance, the second switch is turned on; The variable resistor is controlled by the third terminal to generate a preset impedance; Read memory status data after an injection impedance change fault from the memory controller.

9. The device according to claim 7 or 8, wherein the variable resistor supports a resistance range between a first ohm and a second ohm; The first ohm is less than the second ohm, and the difference between the first ohm and the second ohm is greater than kiloohms.

10. The device according to claim 3, wherein the third injection unit comprises: Interference signal generator, first resistor and third switch; The first end of the interference signal generator is connected to the controller; The second end of the interference signal generator is connected to the second probe; The third terminal of the interference signal generator is connected to the first resistor; The first resistor is connected to the third switch; The third switch is connected to the first probe.

11. The device according to claim 9, wherein, The controller is specifically used for: In response to the injection signal of the injection interference fault, the third switch is turned on; The interference signal generator is controlled by the first terminal to generate interference information, so as to apply the interference signal to the memory under test through the first probe and the second probe; Read memory status data after the injection interference fault from the memory controller.

12. The device according to claim 10 or 11, wherein the interference signal includes radiated interference; The controller is used to control the interference signal generator to generate at least one of the following interferences: Interference signals of different amplitudes; Interference signals of different frequencies.

13. The device according to claim 10, wherein the resistance value of the first resistor is a preset multiple of the target resistance value; The target resistance value is the resistance value between the first access point and the second access point; The preset multiple is greater than or equal to the first multiple, and less than or equal to the second multiple.

14. The device according to any one of claims 3-13, further comprising a self-testing unit: The self-test unit includes a fourth switch and a second resistor; The first probe, the fourth switch, the second resistor, and the second probe are connected in series.

15. The device according to claim 14, wherein the controller is further configured to: In response to the self-test signal, the fourth switch is controlled to connect the second resistor and the first probe; Read memory status data from the memory controller; If the memory status data indicates that the memory under test is in a correct state, the self-test result is output.

16. The device according to claim 1, wherein the controller is configured to receive the test signal sent by the host computer module.

17. The device according to claim 3, wherein, The first injection point and the second injection point satisfy either of the following requirements: It is set across the series resistor DQ; Reserved connection points for flying wires used for testing; DQ's solder joints.

18. The device according to claim 1, further comprising a power supply unit; The power supply unit is used to supply power to the memory under test; The controller is also configured to control the power supply unit to repower the memory under test in the event that an unrecoverable error occurs in the memory under test.

19. A memory fault injection method, applied to the controller of the device according to any one of claims 1-17, comprising: In response to an injection signal for a memory fault, the fault injection module is controlled to inject a fault into the memory under test. Obtain memory status data from the memory controller of the memory under test.

20. A memory fault injection device, applied to the controller of the device according to any one of claims 1-17, comprising: The response module is used to control the fault injection module to inject faults into the memory under test in response to the injection signal for memory faults. The acquisition module is used to acquire memory status data from the memory controller of the memory under test.

21. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of claim 19.

22. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to claim 19.

23. A computer program product comprising a computer program that, when executed by a processor, implements the method according to claim 19.

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