memory chip

Abstract

The application discloses a storage chip, which comprises a non-volatile state register and a control circuit. The non-volatile state register comprises a plurality of register groups, each register group comprising a flag register and at least one register. The control circuit is connected with the non-volatile state register and is used for controlling the number of write operations of the non-volatile state register to be greater than the number of erase operations of the non-volatile state register. Through the control of the control circuit, each register group in the non-volatile state register is controlled to perform at least one write operation and then perform one erase operation, so that the number of write operations of the plurality of register groups is greater than the number of erase operations. In this way, the number of erase operations can be reduced under the condition that the number of write operations is unchanged, and the reliability of the non-volatile state register can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a storage chip. BACKGROUND

[0002] The non-volatile status register in the storage chip is an important block indispensable in application, and the non-volatile status bit therein needs to have high reliability, that is, it can still be used normally after repeated erasing and writing for many times (such as 6K times).

[0003] However, the conventional scheme is to perform erasing before writing, that is, each writing operation needs to be accompanied by an erasing operation, and in this way, most storage units reach the upper limit of service life after being erased for several hundred K times. SUMMARY

[0004] The present application provides a storage chip to alleviate the technical problem of low reliability of the non-volatile status register.

[0005] In a first aspect, the present application provides a storage chip, which comprises a non-volatile status register and a control circuit, the non-volatile status register comprises a plurality of register groups, each register group comprises a flag register and at least one register; the control circuit is connected with the non-volatile status register, and the control circuit is used for controlling that the number of writing times of the non-volatile status register is greater than the number of erasing times of the non-volatile status register.

[0006] In some embodiments, the control circuit is connected with the plurality of register groups, and the control circuit controls that each register group performs a writing operation for multiple times and then performs an erasing operation.

[0007] In some embodiments, the number of register groups in the non-volatile status register is equal to the number of writing operations performed between two adjacent erasing operations.

[0008] In some embodiments, in the same register group, the flag register is used for identifying the storage state of the at least one register, and the storage state comprises a writable state and a written state.

[0009] In a second aspect, the present application provides a storage chip, which comprises a plurality of register groups, each register group comprises a flag register and at least one register, and the number of registers in different register groups is equal; wherein, before each erasing operation, at least two of the plurality of register groups each perform a writing operation.

[0010] In some embodiments, after each register group each performs a writing operation, the plurality of register groups perform an erasing operation.

[0011] In some implementations, a flag register is used to identify the storage state of the register group in which the flag register resides, including a writable state and a written state.

[0012] In some implementations, the multiple register groups include the first register group to the last register group arranged sequentially in address order; the storage status of each register group is read one by one in address order; and it is determined whether the storage status of the current register group is writable; if the storage status of the current register group is writable, it is determined whether the current register group is the first register group; if the current register group is the first register group, the data to be written is directly written to the current register group.

[0013] In some implementations, if the current register group is not the first register group, the stored data of each register in the previous register group of the current register group is recorded to the buffer; and the data to be written is written to the current register group. The data to be written includes flag data, the part of the data stored in the buffer group that does not need to be updated, and the data to be updated. The flag data is written to the flag register in the current register group, the part of the data stored in the buffer group that does not need to be updated is written to the data bits in the current register group that do not need to be updated, and the data to be updated is written to the data bits in the current register group that need to be updated.

[0014] In some implementations, if the storage state of the current register group is not writable, it is determined whether the current register group is the last register group; if the current register group is not the last register group, the storage state of the next register group is read in address order.

[0015] In some implementations, if the current register group is the last register group, then after recording the stored data of each register in the last register group to the buffer, an erase operation is performed on multiple register groups.

[0016] In some implementations, data to be written is written to the first register group. The data to be written includes flag data, the portion of data stored in the buffer that does not need to be updated, and the data to be updated. The flag data is written to the flag register in the first register group. The portion of data stored in the buffer that does not need to be updated is written to the data bits in the first register group that do not need to be updated. The data to be updated is written to the data bits in the first register group that need to be updated.

[0017] In some implementations, flag data is used to identify the storage state as written.

[0018] Thirdly, this application provides a memory chip that includes N register groups, each register group including a flag register and M registers, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1.

[0019] The memory chip provided in this application controls each register group in the non-volatile status register to perform at least one write operation followed by one erase operation through a control circuit. This allows the number of write operations for multiple register groups to be greater than the number of erase operations. In this way, the number of erase operations can be reduced without changing the number of write operations, thereby improving the reliability of the non-volatile status register.

[0020] Furthermore, before each erase operation, at least two of the multiple register groups each perform a write operation. This also ensures that the number of write operations for multiple register groups is greater than the number of erase operations. In this way, the number of erase operations can be reduced without changing the number of write operations, thereby improving the reliability of non-volatile status registers. Attached Figure Description

[0021] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0022] Figure 1 This is a schematic diagram of a memory chip provided in an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of another structure of the memory chip provided in an embodiment of this application.

[0024] Figure 3 This is a schematic diagram of the first structure of the register provided in an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of a second structure of the register provided in an embodiment of this application.

[0026] Figure 5 This is a schematic diagram of a third structure of the register provided in an embodiment of this application.

[0027] Figure 6 This is a schematic diagram illustrating the operation of the memory chip provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] This embodiment provides a memory chip; please refer to [link / reference]. Figures 1 to 6 ,like Figure 1 , Figure 2As shown, the memory chip includes a non-volatile status register 100 and a control circuit 200. The non-volatile status register 100 includes multiple register groups, each register group including a flag register and at least one register. The control circuit 200 is connected to the non-volatile status register 100 and is used to control the number of writes to the non-volatile status register 100 to be greater than the number of erases to the non-volatile status register 100.

[0030] It is understood that the memory chip provided in this embodiment controls each register group in the non-volatile status register 100 to perform at least one write operation and then one erase operation through the control circuit 200. This can achieve that the number of write operations for multiple register groups is greater than the number of erase operations. In this way, the number of erase operations can be reduced without changing the number of write operations, thereby improving the reliability of the non-volatile status register 100.

[0031] It should be noted that, such as Figure 1 , Figure 2 As shown, multiple register groups may include a first register group 10 and a second register group 20. After each register group 10 and the second register group 20 is written once, the first register group 10 and the second register group 20 are erased at the same time. In this way, the number of writes to the non-volatile status register 100 is 2, and the number of erases to the non-volatile status register 100 is 1. This can make the number of writes to the non-volatile status register 100 greater than the number of erases to the non-volatile status register 100, thereby improving the reliability of the non-volatile status register 100.

[0032] In this application, "multiple" refers to two or more.

[0033] Multiple register groups may also include a third register group 30. After each of the first register group 10, the second register group 20, and the third register group 30 is written once, the first register group 10, the second register group 20, and the third register group 30 are erased all at once. In this way, the number of writes to the non-volatile status register 100 is 3, and the number of erases to the non-volatile status register 100 is 1. This also enables the number of writes to the non-volatile status register 100 to be greater than the number of erases to the non-volatile status register 100, thereby further improving the reliability of the non-volatile status register 100.

[0034] Understandably, multiple register groups can include even more register groups. Assuming that the maximum number of erasures for each flag register or each register is 300K, if the same non-volatile status register 100 is configured with 32 register groups, each erase can perform at least 32 write operations. Correspondingly, the equivalent erase / write lifetime of the same non-volatile status register 100 is 9.6KK = 32 * 300K times, which far exceeds the actual erase / write lifetime of the non-volatile status register 100 before the improvement, which is 300K times.

[0035] Each register group may include a flag register and at least one register, for example, in Figure 1 In this configuration, the first register group 10 includes a flag register 11, a first register 12, a second register 13, and a third register 14; the second register group 20 includes a flag register 21, a first register 22, a second register 23, and a third register 24; and the third register group 30 includes a flag register 31, a first register 32, a second register 33, and a third register 34. Therefore, the number of registers in different register groups can be equal.

[0036] When register groups 10, 20, 30, and so on are arranged in address order, the number of registers in a later register group can be greater than the number of registers in an earlier register group. For example, in... Figure 2 In this configuration, the first register group 10 may include flag register 11 and first register 12, etc.; the second register group 20 may include flag register 21, first register 22, and second register 23, etc.; and the third register group 30 may include flag register 31, first register 32, second register 33, and third register 34, etc. Therefore, it can be seen that the number of registers in each register group arranged sequentially in address order can also increase.

[0037] It should be noted that both of the above configurations of the number of registers in the register group can achieve the same amount of data migration between different register groups.

[0038] Each flag register or register can have a storage capacity of one or more bits or one or more bytes. Flag registers are used to store flag data.

[0039] The aforementioned memory chip may be, but is not limited to, NOR Flash, or other applicable memory.

[0040] It should be noted that each write operation can be performed once on a register group, and only one write operation can be performed on the same register group after each erase. Each erase operation can be performed once on the non-volatile status register 100, which means erasing all stored data in the memory area where the non-volatile status register 100 is located.

[0041] One of the registers can be like Figure 3 As shown, the register has a storage capacity of one byte, or 8 bits S0-S7. Each bit S0-S7 is a function bit, which can be used to enable or disable the corresponding function, or to indicate the status.

[0042] One of the registers can be as follows Figure 4 As shown, the register's storage capacity is also one byte, or 8 bits S8-S15. Each bit S8-S15 is a function bit, used to enable or disable a corresponding function, or to indicate status. Bit S10 is a reserved bit (R). The function of reserved bits is not defined during the design phase and can be defined later during use.

[0043] One of the registers can be as follows Figure 5 As shown, the storage capacity of this register is also one byte, or 8 bits. Each bit is a function bit or a reserved bit (R), which can be used to enable or disable the corresponding function, or to indicate the status.

[0044] It should be noted that, with Figure 4 Taking the data QE in bit S9 of the register shown as an example, when data QE is 1, it indicates entering four-wire mode; otherwise, it is in single-wire or two-wire mode. During application, data QE is repeatedly updated, meaning it switches between 0 and 1. This implies that... Figure 4 The register shown is repeatedly erased and written.

[0045] In one embodiment, the control circuit 200 is connected to a plurality of register groups, and the control circuit 200 controls the plurality of register groups to perform an erase operation after each set of write operations.

[0046] It should be noted that one erase operation corresponds to one erase count, and one write operation corresponds to one write count. Before each erase operation, one write operation is performed on each register group. Multiple register groups can also be subjected to multiple write operations. This ensures that the number of write operations to the non-volatile status register 100 is greater than the number of erase operations. By keeping the number of write operations constant, the number of erase operations can be reduced, thereby improving the reliability of the non-volatile status register 100.

[0047] In one embodiment, the number of register groups in the nonvolatile status register 100 is equal to the number of write operations performed between two adjacent erase operations.

[0048] It should be noted that each write operation can be performed on one or more register groups. This embodiment uses one register group per write operation as an example. The number of register groups in the non-volatile status register 100 is the number of write operations that can be performed after one erase operation, or the number of write operations that can be performed before one erase operation. In this embodiment, the number of register groups can be configured according to the desired equivalent erase / write lifetime, which is beneficial for accurately predicting the desired equivalent erase / write lifetime.

[0049] In one embodiment, within the same register group, a flag register is used to identify the storage state of at least one register, including a writable state and a written state.

[0050] It should be noted that the different values ​​stored in the flag register of each register set can be used to indicate the storage status of that register set. For example, a value of 0xFF stored in the flag register indicates that the register set is empty and in a writable state; a value of 0x00 stored in the flag register indicates that the register set has been written to and is in a written state. Here, 0xFF represents the "FF" of hexadecimal "0x", which is 11111111 in binary. 0x00 represents the "00" of hexadecimal "0x", which is 00000000 in binary.

[0051] In one embodiment, depending on the type of flag register, the values ​​00 (0x00) and FF (0xFF) stored in the flag register can be defined differently; that is, 00 can also indicate that the register group is writable, and FF can also indicate that the register group is written to. Therefore, simple transformations of the values ​​stored in the flag register should also be included within the scope of protection claimed in this patent.

[0052] In one embodiment, this embodiment provides a memory chip, such as... Figure 1 As shown, the memory chip includes multiple register groups, each register group including a flag register and at least one register, and the number of registers in different register groups is equal; wherein, before each erase operation, at least two of the multiple register groups each perform a write operation once.

[0053] It is understood that the memory chip provided in this embodiment performs a write operation on at least two of the multiple register groups before each erase operation. This also ensures that the number of write operations on multiple register groups is greater than the number of erase operations. In this way, the number of erase operations can be reduced while keeping the number of write operations constant, thereby improving the reliability of the non-volatile status register. Performing a write operation on a register group means performing a write operation on at least one register in that register group.

[0054] It should be noted that flag bits can exist independently, and their number can be one or more, for example, 8; flag bits can also be constructed in a flag register, in which case the number of flag bits in each flag register can be 8, that is, the storage capacity of each flag register can be one or more bytes.

[0055] In one embodiment, this embodiment provides a memory chip including N register groups, each register group including a flag register and M registers.

[0056] It should be noted that N can be an integer greater than or equal to 2. Each register can be written once and then erased once for all registers. This can also achieve a situation where the number of writes for multiple registers is greater than the number of erases. In this way, the number of erase operations can be reduced while keeping the number of write operations the same, thereby improving the reliability of non-volatile status registers.

[0057] Where M can be an integer greater than or equal to 1.

[0058] In one embodiment, after each register group performs a write operation, multiple register groups perform an erase operation.

[0059] It should be noted that in this embodiment, after performing write operations on all registers in all register groups, the erase operation on all registers in all register groups is then performed, which can better extend the lifespan of the registers.

[0060] In one embodiment, the flag register is used to identify the storage state of the register group in which the flag register resides, and the storage state includes a writable state and a written state.

[0061] It should be noted that the above flag data "0xFF" indicates that the storage status is writable, and the above flag data "0x00" indicates that the storage status is written.

[0062] In one embodiment, such as Figure 6As shown, multiple registers include the first register to the last register arranged sequentially in address order; the storage status of each register is read one by one in address order; and it is determined whether the storage status of the current register is writable; if the storage status of the current register is writable, it is determined whether the current register is the first register; if the current register is the first register, the data to be written is directly written to the current register.

[0063] It should be noted that the address order mentioned above can be from the first storage address of the first register group to the last storage address of the last register group. In multiple register groups, the first register group to the last register group corresponds sequentially to the first storage address to the last storage address. Specifically, the first register group corresponds to the first storage address, and so on, with the last register group corresponding to the last storage address. The first storage address to the last storage address can be arranged in ascending order (smallest to largest) or in descending order (largest to smallest).

[0064] by Figure 1 Taking the memory chip shown as an example, since the first register group 10 is the first register group and the storage state of the first register group 10 is writable, the data to be written can be directly written to the first register group 10. For example, the data to be written can be written to at least one of the first, second, and third registers, and "0x00" can be written to the flag register 11 in the first register group 10 to update the storage state of the first register group 10.

[0065] In one embodiment, if the current register group is not the first register group, the stored data of each register in the previous register group is recorded to the buffer. In a preferred embodiment, the stored data of each register in the previous register group that is adjacent to the current register group in address order is recorded to the buffer. It is understood that registers are generally edited in address order in the art, but it is also possible to skip a certain address range. The data to be written is written to the current register group. The data to be written includes flag data, the part of the data stored in the buffer that does not need to be updated, and the data to be updated. The flag data is written to the flag register in the current register group. The part of the data stored in the buffer that does not need to be updated is written to the data bits in the current register group that do not need to be updated. The data to be updated is written to the data bits in the current register group that need to be updated.

[0066] It should be noted that in this embodiment, the flag data can be "0x00" to indicate that the current storage state of the register group is a written state.

[0067] by Figure 1Taking the memory chip shown as an example, the storage state of the second register group 20 is writable. Since the second register group 20 is not the first register group, it is necessary to record the stored data of each register in the first register group 10 to the buffer. Taking the stored data of the first register 12, the second register 13 and the third register 14 in the first register group 10 as 0xFF, 0xFD and 0xFC respectively as an example, if the least significant bit of the stored data (0xFF, binary representation is 11111111) in the first register 12 is changed from 1 to 0, then all the register data in the first register group 10 except for the least significant bit of the first register 12 need to be written from the buffer to the corresponding register in the second register group 20. For example, the flag data 0x00 in the data to be written is written to the flag register 21. The data 1111111, excluding the least significant bit of the data in the first register 12, is written to the first register 22. The data 0xFD stored in the second register 13 is written to the second register 23. The data 0xFC stored in the third register 14 is written to the third register 24. The data currently written to the first register 22, second register 23, and third register 24 can be the portion of the data stored in the buffer that does not need to be updated. Furthermore, 0 needs to be written to the least significant bit of the first register 22; this 0 written to the least significant bit of the first register 22 is the data to be updated in the aforementioned data to be written.

[0068] In one embodiment, such as Figure 6 As shown, if the storage status of the current register group is not writable, then it is determined whether the current register group is the last register group; if the current register group is not the last register group, then the storage status of the next register group is scanned, and the process proceeds to the step "determine whether the storage status of the current register group is writable".

[0069] It should be noted that the current storage state of the register group is not writable; that is, the current storage state of the register group is already written.

[0070] In one embodiment, such as Figure 6 As shown, if the current register group is the last register group, after recording the stored data of each register in the last register group to the buffer, an erase operation is performed on multiple register groups.

[0071] It should be noted that in this embodiment, a single erase operation erases the entire storage area containing multiple register groups.

[0072] In one embodiment, such as Figure 6As shown, the data to be written is written to the first register group. The data to be written includes flag data, the part of the data stored in the buffer that does not need to be updated, and the data to be updated. The flag data is written to the flag register 11 in the first register group. The part of the data stored in the buffer that does not need to be updated is written to the data bits that do not need to be updated in the first register group. The data to be updated is written to the data bits that need to be updated in the first register group.

[0073] It should be noted that in this embodiment, the flag data can be "0x00" to indicate that the storage status of the first register group is in the written state.

[0074] In this embodiment, when the storage state of the last register group is written, it means that the storage state of all current register groups is written. In other words, there is no blank register group that can accommodate the data to be written. Therefore, an erase operation is required to write the data to be written to the first register group.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0076] The memory chip provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory chip, characterized in that, include: A non-volatile status register, the non-volatile status register comprising multiple register groups, each register group comprising a flag register and at least one register; and A control circuit, connected to the non-volatile status register, is used to control the number of writes to the non-volatile status register to be greater than the number of erases to the non-volatile status register.

2. The memory chip according to claim 1, characterized in that, The control circuit is connected to the plurality of register groups, and the control circuit controls the plurality of register groups to perform an erase operation after each of the multiple write operations.

3. The memory chip according to claim 2, characterized in that, The number of register groups in the non-volatile status register is equal to the number of write operations performed between two adjacent erase operations.

4. The memory chip according to claim 1, characterized in that, Within the same register group, the flag register is used to identify the storage state of the at least one register, the storage state including a writable state and a written state.

5. A memory chip, characterized in that, The memory chip includes multiple register groups, each register group including a flag register and at least one register, and the number of registers in different register groups is equal; Prior to each erase operation, at least two of the plurality of register groups each perform a write operation.

6. The memory chip according to claim 5, characterized in that, After each of the register groups performs a write operation, the plurality of register groups perform an erase operation.

7. The memory chip according to claim 5, characterized in that, The flag register is used to identify the storage state of the register group to which the flag register is located, and the storage state includes a writable state and a written state.

8. The memory chip according to claim 7, characterized in that, The plurality of register groups include the first register group to the last register group arranged sequentially in address order; the storage status of each register group is read one by one according to the address order; and it is determined whether the storage status of the current register group is writable; if the storage status of the current register group is writable, it is determined whether the current register group is the first register group; if the current register group is the first register group, the data to be written is directly written to the current register group.

9. The memory chip according to claim 8, characterized in that, If the current register group is not the first register group, then the stored data of each register in the previous register group of the current register group is recorded to the buffer; and the data to be written is written to the current register group. The data to be written includes flag data, the part of the data stored in the buffer group that does not need to be updated, and the data to be updated. The flag data is written to the flag register in the current register group, the part of the data stored in the buffer group that does not need to be updated is written to the data bits in the current register group that do not need to be updated, and the data to be updated is written to the data bits in the current register group that need to be updated.

10. The memory chip according to claim 8, characterized in that, If the storage status of the current register group is not writable, then determine whether the current register group is the last register group; if the current register group is not the last register group, then scan the storage status of the next register group and proceed to the step "determine whether the storage status of the current register group is writable".

11. The memory chip according to claim 10, characterized in that, If the current register group is the last register group, then after recording the stored data of each register in the last register group to the buffer, an erase operation is performed on the multiple register groups.

12. The memory chip according to claim 11, characterized in that, Write the data to be written to the first register group. The data to be written includes flag data, the portion of the data stored in the buffer that does not need to be updated, and the data to be updated. The flag data is written to the flag register in the first register group. The portion of the data stored in the buffer that does not need to be updated is written to the data bits in the first register group that do not need to be updated. The data to be updated is written to the data bits in the first register group that need to be updated.

13. The memory chip according to claim 9 or 12, characterized in that, The flag data is used to identify the storage state as a written state.

14. A memory chip, characterized in that, The memory chip includes N register groups, each register group including a flag register and M registers, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1. After each register group performs a write operation, multiple register groups perform an erase operation.

Images