Method, system and apparatus for testing memory chips
By constructing a mapping table to correspond to logical addresses, the problems of incomplete and inefficient testing of memory chips in existing technologies are solved, achieving full-disk logical address coverage and improving testing efficiency.
CN122245391APending Publication Date: 2026-06-19CHENGDU BIWIN STORAGE TECHNOLOGY CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU BIWIN STORAGE TECHNOLOGY CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-06-19
AI Technical Summary
Technical Problem
Existing driver-level I/O read/write testing solutions cannot achieve full address coverage, have testing blind spots, and have low testing efficiency.
Method used
By constructing a target mapping table to replace the traditional array recording method, the correspondence between table bytes and logical addresses is established, achieving complete coverage of the entire disk's logical addresses. During write testing, only the first N bytes and the last M bytes of the target storage block are written with the identifier value and logical address information.
Benefits of technology
It breaks through the memory capacity limitation of embedded test terminals, achieves complete coverage of the entire logical address of the storage chip, and significantly improves test efficiency.
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Smart Images
Figure CN122245391A_ABST
Abstract
This invention discloses a testing method, system, and apparatus for a memory chip. The method includes: determining the number of logical addresses based on the storage space of the memory chip under test; creating a target mapping table based on the number of addresses and establishing a correspondence between each table byte in the target mapping table and each logical address, wherein each table byte is used to record the data write status of the corresponding logical address; parsing the obtained write test command to obtain the write logical address and a first identifier value; determining the first table byte corresponding to the write logical address in the target mapping table based on the write logical address, and determining the first target storage block corresponding to the write logical address in the storage space of the memory chip under test; writing the first identifier value into the first N bytes of the first target storage block, writing the address value of the write logical address into the last M bytes of the first target storage block, and updating the first status encoding value of the first table byte to a second status encoding value after confirming successful writing.
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