Low-power, high-throughput 5G LDPC decoder implementation method and device

Abstract

This invention discloses a low-power, high-throughput 5G LDPC decoder implementation method, specifically comprising: Step 1, calculating the parameters required for decoding from the input parameters; Step 2, based on the spreading factor Z... c The values ​​are stored in different blocks according to different storage methods; Step 3: Based on the expansion factor Z c The value of determines whether to perform layer splitting transformation on the base matrix and update the required posterior probability information of the variable nodes; Step 4: Update the information of the check nodes and the posterior probability information of the variable nodes within the layer; Step 5: Implement layered iterative decoding; Step 6: After updating the information of all check nodes in each layer and reaching the set number of iterations, the decoding iteration is completed, and the output processing of the decoding result begins. This method significantly reduces the required resources; and by utilizing the orthogonality of adjacent layers of the split matrix, the intra-layer pipelining operation improves the decoder throughput after reducing the decoding parallelism. A low-consumption, high-throughput 5G LDPC decoder implementation device is also disclosed.

Description

Technical Field

[0001] This invention belongs to the field of error correction technology for wireless communication systems, specifically relating to a low-power, high-throughput 5G LDPC decoder implementation method and a low-power, high-throughput 5G LDPC decoder implementation device. Background Technology

[0002] Currently, 5G has entered the commercial stage and is gradually penetrating all aspects of social production and life, inevitably bringing tremendous changes to our lives. Because 5G has higher requirements for information transmission rate, information transmission reliability, and system capacity, and its application scenarios are more diverse, in-depth research on key technologies in the system is necessary, and channel coding and decoding technology is a very important part of this.

[0003] 5G(5 th The New Radio (NR) standard of Generation Mobile Communication Systems has adopted Low Density Parity Check (LDPC) codes as the channel coding and decoding scheme for data transmission in enhanced Mobile Broadband (eMBB) scenarios. Therefore, it is very meaningful to design and implement LDPC decoders with lower resource consumption and higher throughput.

[0004] 5G LDPC belongs to quasi-cyclic LDPC codes. Its basic parity-check matrix BG has two structures, namely BG1 and BG2, and supports 51 spreading factors Z. c Z c The range is from 2 to 384, so there are 102 types of parity-check matrices obtained by expanding BG.

[0005] The decoding algorithm for 5G LDPC is the Belief Propagation (BP) algorithm. This algorithm involves numerous complex nonlinear functions, making it unsuitable for direct use in hardware implementation. In hardware implementation, the most commonly used algorithms are the Normalized Min-Sum (NMS) and Offset Min-Sum (OMS) algorithms. These two algorithms evolved from the BP algorithm, sacrificing some decoding performance but significantly reducing implementation complexity. They simplify numerous nonlinear function operations into simple addition, subtraction, comparison, and XOR operations, making them very suitable for hardware implementation. During the LDPC code decoding process, the scheduling methods between nodes can be divided into flooding and layered approaches. Flooding decoding calculates the information from all variable nodes to the check node in each iteration, and then calculates the information from the check node to the variable nodes, dividing the message iteration into two completely independent processes. Layered decoding, on the other hand, immediately uses the updated check node information to update the variable node information and uses it for updating subsequent check node messages. Layered decoding has lower complexity than flooding decoding and converges faster, therefore, layered decoding is often used in hardware implementations.

[0006] The architecture of LDPC decoders is mainly divided into fully parallel, row-parallel, and block-parallel structures. Among them, the row-parallel and block-parallel structures adopt a hierarchical decoding scheduling method. Currently, most 5G LDPC decoders adopt a hierarchical, block-parallel structure.

[0007] Chongqing University of Posts and Telecommunications disclosed a method for implementing 5G LDPC decoding in its patent application "A High-Throughput LDPC Decoding Algorithm and Architecture for 5G Terminals" (application date: February 25, 2020, application number: 202010122272.4, application publication number: CN 111211790A). The parallelism of the decoding computation is equal to the spread factor Z. c Because the spreading factor Z in the 5G NR standard c The minimum value is 2 and the maximum value is 384. In order to be compatible with all codewords in the 5G NR standard, the decoding framework needs to design the parallelism of block parallel decoding to be 384. This requires 384 computing modules to be pre-configured, resulting in excessive hardware resource consumption and failure to meet project requirements in some scenarios.

[0008] Based on the above analysis, the problems and defects of the existing technology are: in order to ensure the high throughput of 5G communication and be compatible with all 5G LDPC codewords, the decoder needs to reserve a large degree of parallelism, resulting in excessive resource consumption. Summary of the Invention

[0009] The first objective of this invention is to provide a low-consumption, high-throughput 5G LDPC decoder implementation method. It employs a layered minimum sum decoding algorithm, which significantly reduces the required resources by splitting the base matrix. Furthermore, by utilizing the orthogonality between adjacent layers of the split matrix, the throughput of the decoder, which reduces resource consumption, is improved.

[0010] The second objective of this invention is to provide a low-power, high-throughput 5G LDPC decoder implementation device.

[0011] The first technical solution adopted in this invention is a method for implementing a low-power, high-throughput 5G LDPC decoder, specifically as follows:

[0012] Step 1: Based on the 5G NR LDPC code standard, calculate the various decoding-related parameters required for decoding from the input parameters;

[0013] Step 2: Store the received posterior probability information of the variable nodes, based on the expansion factor Z. c The values ​​are stored using different block storage methods;

[0014] Step 3: Based on the expansion factor Z c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix.

[0015] Step 4: Update the verification node information and variable node posterior probability information within the layer;

[0016] Step 5: Control the decoding process of each layer according to the basis matrix splitting to achieve layered iterative decoding;

[0017] Step 6: After updating the information of all verification nodes in each layer and reaching the set number of iterations, the decoding iteration is complete, and the output processing of the decoding results begins.

[0018] The invention is further characterized in that,

[0019] In step 1, the parameters required for decoding include the basis matrix BG and the spread factor Z. c The number of rows M, the number of columns N, the shortened bit length L, and the number of decoding iterations I are all specified.

[0020] Step 2 is as follows:

[0021] Step 2.1: Concatenate the received variable node posterior probability information, that is, concatenate the 0s or 1s in the corresponding bits of the input quantized variable node posterior probability information;

[0022] Where, if the expansion factor Z cIf Z is not greater than 192, then c Each posterior probability information bit is grouped together to concatenate the data. After each group is concatenated, the address addra of the cached concatenated data result is incremented by 1. The initial value of addra is 0.

[0023] If the expansion factor Z c Greater than 192, Z c If it is even, then use Z. c The data is grouped into pairs with a unit length of 2. The posterior probability information of odd-numbered bits is grouped together, and the posterior probability information of even-numbered bits is grouped together. After each group is grouped, the address of the cached odd-numbered data result, addra_odd, and the address of the cached even-numbered data result, addra_even, are both incremented by 1. The initial value of addra_odd is 0, and the initial value of addra_even is 1. The bit width of the data signal temporarily storing the grouped result is set to 192.

[0024] Step 2.2: Classify and store the posterior probability information of the assembled variable nodes:

[0025] Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information in step 2.1.

[0026] Step 3 specifically involves:

[0027] Step 3.1: Based on the base matrix and decoding parameters specified in the 5G NR LDPC standard, obtain the non-zero column index value (index) and the actual cyclic shift coefficient value (offset) corresponding to each non-zero column index for each layer, where index ≥ 0 and 0 ≤ offset. <Z c ;

[0028] Set the following rule: when the expansion factor Z c When the value is not greater than 192, the corresponding posterior probability information block of the variable node in each layer is obtained according to the index, and then the information block is shifted according to the corresponding cyclic shift coefficient value.

[0029] When the expansion factor Z c When Z is greater than 192, c If the number is even, the basis matrix is ​​split into two groups at each level; within each level, the first group Z is processed first. c The update of the information of two check nodes is defined as L1; then the second group of Z within the layer is performed. cThe update of the information of two check nodes is defined as L2. Based on the storage method of the posterior probability information of the variable nodes in step 2, the non-zero column index value L1_index and the actual cyclic shift coefficient value L1_offset in the L1 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L1_index = 2*index, L1_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L1_index = 2*index+1, L1_offset = (offset-1) / 2. The non-zero column index value L2_index and the actual cyclic shift coefficient value L2_offset in the L2 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L2_index = 2*index+1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L2_index = 2*index, L2_offset = (offset+1) / 2.

[0030] Step 3.2: Obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in Step 3.1. The non-zero column index is the address of the posterior probability information of the variable node stored in Step 2.1. After retrieving the posterior probability information of the corresponding variable node, perform the shift operation according to the corresponding cyclic shift coefficient.

[0031] Step 3.3: Concatenate the data in the corresponding bits of each variable node's posterior probability information block after shifting to restore Z. c This provides the actual posterior probability information of the variable nodes that can be used for calculation. At this point, each validation node in the layer has obtained the posterior probability information of the variable nodes needed for updating.

[0032] Step 4 is as follows:

[0033] Step 4.1: Use different methods to ensure compatibility with the expansion factor Z. c All possible values. When the expansion factor Z... c When the value is not greater than 192, the parallelism within the layer is equal to Z. c Using Z c Each decoding module performs parallel computation; when the expansion factor Z... c When Z is greater than 192, c If the number is even, the intra-layer parallelism of the decoding is Z. c / 2, using Z c Two decoding modules perform parallel computation.

[0034] 192 RAM blocks are pre-configured to store the check node information: when Z cWhen Z is not greater than 192, the address (A-1) of the S-th RAM block stores the information of the S-th check node in layer A; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth check node in the first group of the A layer, and the address (2*A-1) of the Sth RAM block stores the information of the Sth check node in the second group of the A layer, where S = 1, 2, ..., 192 and A = 1, 2, ..., 46.

[0035] Step 4.2: Decode and update the posterior probability information of the variable nodes obtained in Step 3 and the corresponding check node information in Step 4.1, and store the updated check node information at the corresponding addresses of the 192 RAM blocks in Step 4.1.

[0036] Step 4.3: The updated variable node posterior probability information is grouped and concatenated according to the grouping rules in Step 2, with 0 and 1 bits at corresponding positions. After reverse cyclic shifting, it is still stored at the address where the variable node posterior probability information data before the update is obtained.

[0037] Step 5 specifically involves:

[0038] If the base matrix is ​​not split in step 3, the update of the next layer begins after the posterior probability information of the verification nodes and variable nodes in the previous layer is updated, and steps 3 and 4 are repeated. For cases where there is a base matrix layer splitting transformation, an intra-layer pipeline operation is performed, that is, in the first group of Z in the layer... c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the Z of the second group within the layer. c After reading the posterior probability information of the relevant variable nodes of the two verification nodes and completing the update of the two groups within the split layer, start the update of the first layer within the next layer, and repeat steps 3 and 4.

[0039] Step 6 specifically involves:

[0040] Step 6.1: Control the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, store it and wait for output;

[0041] Step 6.2: After storing the hard decision information of the variable nodes of a transport block, begin decoding and output.

[0042] The second technical solution adopted in this invention is a low-power, high-throughput 5G LDPC decoder implementation device, comprising:

[0043] The decoding parameter calculation module is used to calculate the parameters required for decoding from the input parameters according to the 5G NR LDPC code standard.

[0044] The input buffer control and variable node posterior probability information storage unit is used to store the received variable node posterior probability information, based on the expansion factor Z. c The values ​​are stored using different block storage methods;

[0045] The cyclic shift coefficient, cyclic shift, and data restoration unit are used to determine the data based on the expansion factor Z. c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix.

[0046] The decoding center, decoding calculation and verification node information storage unit are used to update the verification node information and variable node posterior probability information within the layer, and store the updated verification node information.

[0047] The overall decoding control module is used to control the decoding process of each layer according to the base matrix splitting, so as to realize layered iterative decoding.

[0048] The decoding output control and decoding output buffer unit is used to complete the information update of all verification nodes in each layer and, after reaching the set number of iterations, the decoding iteration is completed and the output processing of the decoding result begins.

[0049] The invention is further characterized in that,

[0050] The input cache control and variable node posterior probability information storage unit includes an input cache control module and a variable node posterior probability information storage module, wherein...

[0051] The input buffer control module is used to concatenate the received variable node posterior probability information, that is, to concatenate the 0s or 1s in the corresponding bits of the quantized variable node posterior probability information.

[0052] Where, if the expansion factor Z c If Z is not greater than 192, then c Each posterior probability information bit is grouped together to concatenate the data. After each group is concatenated, the address addra of the cached concatenated data result is incremented by 1. The initial value of addra is 0.

[0053] If the expansion factor Z c Greater than 192, Z c If it is even, then use Z. cThe data is grouped into pairs with a unit length of / 2, concatenating odd-numbered posterior probability information together and even-numbered posterior probability information together. After each concatenation, the addresses of both the odd-numbered data results cache (addra_odd) and the even-numbered data results cache (addra_even) are incremented by 1. The initial value of addra_odd is 0, and the initial value of addra_even is 1. The bit width of the data signal temporarily storing the concatenation results is set to 192.

[0054] The variable node posterior probability information storage module is used to classify and store the assembled variable node posterior probability information.

[0055] Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information.

[0056] The cyclic shift coefficient, cyclic shift, and data restoration unit includes a cyclic shift coefficient module, a cyclic shift module, and a data restoration module.

[0057] The cyclic shift coefficient module is used to obtain the non-zero column index value (index) and the actual cyclic shift coefficient value (offset) corresponding to each non-zero column index for each layer, based on the base matrix and decoding parameters specified in the 5G NR LDPC standard, where index ≥ 0 and 0 ≤ offset. <Z c ;

[0058] Set the following rule: when the expansion factor Z c When the value is not greater than 192, the corresponding posterior probability information block of the variable node in each layer is obtained according to the index, and then the information block is shifted according to the corresponding cyclic shift coefficient value.

[0059] When the expansion factor Z c When Z is greater than 192, c If the number is even, the basis matrix is ​​split into two groups at each level; within each level, the first group Z is processed first. c The update of the information of two check nodes is defined as L1; then the second group of Z within the layer is performed. cThe update of the information of two check nodes is defined as L2. Based on the storage method of the posterior probability information of the variable nodes in step 2, the non-zero column index value L1_index and the actual cyclic shift coefficient value L1_offset in the L1 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L1_index = 2*index, L1_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L1_index = 2*index + 1, L1_offset = (offset - 1) / 2. The non-zero column index value L2_index and the actual cyclic shift coefficient value L2_offset in the L2 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L2_index = 2*index + 1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L2_index = 2*index, L2_offset = (offset + 1) / 2.

[0060] The cyclic shift module is used to obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in the cyclic shift coefficient module. The non-zero column index is the address of the stored variable node posterior probability information. After retrieving the corresponding variable node posterior probability information, the shift operation is performed according to the corresponding cyclic shift coefficient.

[0061] The data restoration module is used to reconstruct the data from the corresponding bits of the shifted variable node posterior probability information blocks, restoring Z from each variable node posterior probability information block. c This provides the actual posterior probability information of the variable nodes that can be used for calculation. At this point, each validation node in the layer has obtained the posterior probability information of the variable nodes needed for updating.

[0062] The decoding center, decoding calculation, and verification node information storage unit includes a decoding center module, a decoding calculation module, and a verification node information storage module.

[0063] The decoding center module is pre-configured with 192 decoding computation modules. It supports parallel computation and updating of up to 192 check node information and their related variable node posterior probability information within a layer, and uses different methods to be compatible with the expansion factor Z. c All possible values. When the expansion factor Z... c When the value is not greater than 192, the parallelism within the layer is equal to Z. c Using Z c Each decoding module performs parallel computation; when the expansion factor Z... c When Z is greater than 192, c If the number is even, the intra-layer parallelism of the decoding is Z. c / 2, using Z c Two decoding modules perform parallel computation.

[0064] The verification node information storage module has 192 pre-configured RAM blocks for storing verification node information: when Z... c When Z is not greater than 192, the address (A-1) of the S-th RAM block stores the information of the S-th check node in layer A; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth check node in the first group of the A layer, and the address (2*A-1) of the Sth RAM block stores the information of the Sth check node in the second group of the A layer, where S = 1, 2, ..., 192 and A = 1, 2, ..., 46.

[0065] The decoding and calculation module is used to decode and calculate the acquired variable node posterior probability information and corresponding check node information, and to update the updated check node information and store it in the corresponding address of 192 RAM blocks.

[0066] The data splicing and shifting module is used to splice the updated variable node posterior probability information into corresponding positions of 0 and 1 bits according to the grouping rules in the input cache control module, and then perform reverse circular shifting before storing it at the address where the updated variable node posterior probability information data is obtained.

[0067] The overall decoding control module, if the base matrix is ​​not split, updates the next layer's update after the posterior probability information of the check nodes and variable nodes in the previous layer is updated, repeating the work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation, and check node information storage unit. For cases where the base matrix layer is split, intra-layer pipelined operations are performed, i.e., in the first group of Z within the layer... c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the Z of the second group within the layer. c After reading the posterior probability information of the relevant variable nodes of the two verification nodes and completing the update of the two groups within the split layer, the update of the first layer within the next layer begins. The work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation and verification node information storage unit is repeated.

[0068] The decoding output control and decoding output buffer unit includes a decoding output control module and a decoding output buffer module, wherein,

[0069] The decoding output control module is used to control the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, store it and wait for output;

[0070] The decoding output buffer module is used to start decoding output after the hard decision information of the variable node of a transport block has been stored.

[0071] The beneficial effects of this invention are:

[0072] (1) This invention is compatible with all codewords under the 5G NR standard. Compared with the existing traditional architecture, by splitting the base matrix, the parallelism of the block parallel decoding required by the decoding framework is reduced from 384 to 192, which can significantly reduce the resource consumption of 5G LDPC decoding hardware implementation.

[0073] (2) This invention uses the expansion factor Z c As a basis for judgment, for the expansion factor Z c For values ​​not exceeding 192, the resource consumption for decoding implementation can be significantly reduced without decreasing throughput; for the expansion factor Z... c For cases with a value greater than 192, although the throughput is lower than that of the 384 parallel architecture, the decoding throughput under the 192 parallel architecture can be effectively improved by utilizing the orthogonality of the layer after the basis matrix is ​​split and adopting intra-layer pipelining.

[0074] (3) Under the premise of keeping the verification relationship unchanged, the present invention cleverly splits the base matrix and stores the codewords in blocks, reducing the parallelism of decoding and making the decoding implementation less complex.

[0075] (4) The architecture of this invention is highly flexible and can be adapted to different expansion factors Z. c By taking different values ​​and adopting different processing methods, an effective trade-off can be achieved between decoding resources and decoding throughput, realizing 5G NR LDPC decoding with low resource consumption and high throughput, which can meet the needs of different scenarios. Attached Figure Description

[0076] Figure 1 This is a schematic diagram of the structure of the device of the present invention;

[0077] Figure 2 This is a schematic diagram of the block storage method for the posterior probability information of variable nodes in this invention;

[0078] Figure 3 This is a schematic diagram of the decoding iteration process in the method of the present invention;

[0079] Figure 4 This is a schematic diagram of the basis matrix transformation rules in the method of this invention;

[0080] Figure 5 This is a schematic diagram of the relationship between the internal water flow operation process in the method of the present invention. Detailed Implementation

[0081] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0082] This invention provides a low-power, high-throughput 5G LDPC decoder implementation method, such as... Figure 1-5 As shown, the specific steps include the following:

[0083] Step 1: Based on the 5G NR LDPC code standard, calculate the various decoding-related parameters required for decoding from the input parameters; in Step 1, the parameters required for decoding include the basis matrix BG and the spreading factor Z. c The number of rows M, the number of columns N, the shortened bit length L, and the number of decoding iterations I are all specified.

[0084] Setting the iteration count I requires a comprehensive consideration of the requirements for decoding performance and throughput. A larger iteration count results in better decoding performance but lower throughput; conversely, a smaller iteration count results in worse decoding performance but higher throughput.

[0085] Step 2: Store the received posterior probability information of the variable nodes, based on the expansion factor Z. c The values ​​are stored using different block storage methods, such as... Figure 2 As shown, specifically:

[0086] Step 2.1: Concatenate the received variable node posterior probability information info, that is, concatenate the 0s or 1s in the corresponding bits of the input quantized variable node posterior probability information info.

[0087] Where, if the expansion factor Z c If Z is not greater than 192, then c Each posterior probability information bit is grouped together, and the data is concatenated into groups. After each group is concatenated, the address `addra` of the cached concatenated data result is incremented by 1. The initial value of `addra` is 0. The posterior probability information of the variable nodes contained in the g-th group is `info((g-1)*Z`. c ),info((g-1)*Z c +1),…,info(g*Z c -1). Wherein, info((g-1)*Z c ) represents the (g-1)*Zth digit. c +1 posterior probability information for variable nodes, g = 1, 2, ..., N;

[0088] If the expansion factor Z c Greater than 192, Z c If it is even, then use Z. cThe data is grouped into pairs with a unit length of / 2. Odd-numbered posterior probability information (info) is concatenated together, and even-numbered posterior probability information (info) is concatenated together. After each group is concatenated, the addresses of both the cached odd-numbered data results (addra_odd) and the cached even-numbered data results (addra_even) are incremented by 1. The initial value of addra_odd is 0, and the initial value of addra_even is 1. The posterior probability information of the variable nodes contained in the q-th group is info((q-1)*Z). c ),info((q-1)*Z c +2),…,info(q*Z c -2). Wherein, info((q-1)*Z c ) represents the (q-1)*Zth digit. c +1 posterior probability information for variable nodes, q=1,3…,2*N-1; the posterior probability information of variable nodes contained in the r-th group is info((r-2)*Z c +1),info((r-2)*Z c +3),…,info((r-1)*Z c -1). Where, info((r-2)*Z c +1) represents the (r-2)*Zth digit. c +2 posterior probability information for variable nodes, r = 2, 4, ..., 2*N. Because the maximum unit length of the block is 192, the bit width of the data signal temporarily stored in the splicing result is set to 192;

[0089] Step 2.2: Classify and store the posterior probability information of the assembled variable nodes:

[0090] Two sets of RAM are configured to implement the ping-pong operation, ensuring that the decoding of the next code block can begin immediately after the decoding of the previous code block is completed. The number of instantiated RAM blocks in each set of RAM is the same as the quantization bit width of the variable node posterior probability information, and the address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information in step 2.1.

[0091] Step 3: Based on the expansion factor Z c The value of determines whether to perform a layer-by-layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix, such as... Figure 3-4 As shown, the details are as follows:

[0092] Step 3.1: Based on the base matrix and decoding parameters specified in the 5G NR LDPC standard, obtain the non-zero column index value (index) and the actual cyclic shift coefficient value (offset) corresponding to each non-zero column index for each layer, where index ≥ 0 and 0 ≤ offset. <Z c ;

[0093] Set the following rule: when the expansion factor Z c When the value is not greater than 192, the corresponding posterior probability information block of the variable node in each layer is obtained according to the index, and then the information block is shifted according to the corresponding cyclic shift coefficient value.

[0094] When the expansion factor Z c When Z is greater than 192, c If the number is even, it's equivalent to dividing the original single-layer operation into two groups, requiring a split transformation of the basis matrix; within each layer, the first group Z within the layer is processed first. c The update of the information of two check nodes is defined as L1; then the second group of Z within the layer is performed. c The update of the information of two check nodes is defined as L2. Based on the storage method of the posterior probability information of the variable nodes in step 2, the non-zero column index value L1_index and the actual cyclic shift coefficient value L1_offset in the L1 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L1_index = 2*index, L1_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L1_index = 2*index+1, L1_offset = (offset-1) / 2. The non-zero column index value L2_index and the actual cyclic shift coefficient value L2_offset in the L2 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L2_index = 2*index+1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L2_index = 2*index, L2_offset = (offset+1) / 2.

[0095] Step 3.2: Obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in Step 3.1. The non-zero column index is the address of the posterior probability information of the variable node stored in Step 2.1. After retrieving the posterior probability information of the corresponding variable node, perform the shift operation according to the corresponding cyclic shift coefficient.

[0096] Step 3.3: Concatenate the data in the corresponding bits of each variable node's posterior probability information block after shifting to restore Z.c This provides the actual posterior probability information of the variable nodes that can be used for calculation. At this point, each validation node in the layer has obtained the posterior probability information of the variable nodes needed for updating.

[0097] Step 4: Update the verification node information and variable node posterior probability information within the layer.

[0098] Step 4.1: 192 pre-configured decoding calculation modules are provided, supporting parallel calculation and updating of up to 192 check node information and their related variable node posterior probability information within the layer, using different methods to ensure compatibility with the expansion factor Z. c All possible values, when the expansion factor Z c When the value is not greater than 192, the parallelism within the layer is equal to Z. c Z needs to be used c Each decoding module performs parallel computation, when the expansion factor Z... c When Z is greater than 192, c If the number is even, the intra-layer parallelism of the decoding is Z. c / 2, Z must be used c Two decoding modules perform parallel computation.

[0099] A pre-configured 192 RAM blocks are used as a verification node information storage module to store verification node information. The pre-configured 192 RAM blocks are used to store verification node information: when Z... c When Z is not greater than 192, the address (A-1) of the S-th RAM block stores the information of the S-th check node in layer A; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth parity node in the first group of layer A, and the address (2*A-1) of the Sth RAM block stores the information of the Sth parity node in the second group of layer A, where S = 1, 2, ..., 192 and A = 1, 2, ..., 46. For example: when Z... c When the value is not greater than 192, the address 0 of the first RAM stores the information of the first parity node in the first layer, and the address 1 of the first RAM stores the information of the first parity node in the second layer; the address 0 of the second RAM stores the information of the second parity node in the first layer, and the address 1 of the second RAM stores the information of the second parity node in the second layer, and so on.

[0100] Step 4.2: Calculate and update the posterior probability information of the corresponding variable node for each decoding calculation module. Decode and update the posterior probability information of the variable node obtained in Step 3 and the corresponding verification node information in Step 4.1, and store the updated verification node information at the corresponding addresses of the 192 RAM blocks in Step 4.1.

[0101] Step 4.3: The updated variable node posterior probability information is grouped and concatenated according to the grouping rules in Step 2, with 0 and 1 bits at corresponding positions. After reverse cyclic shifting, it is still stored at the address where the variable node posterior probability information data before the update is obtained.

[0102] Step 5: Control the decoding process of each layer according to the basis matrix partitioning, and realize layered iterative decoding, such as... Figure 5 As shown, the details are as follows:

[0103] If the base matrix is ​​not split in step 3, the update of the next layer begins after the posterior probability information of the verification nodes and variable nodes in the previous layer is updated, and steps 3 and 4 are repeated. For cases where there is a base matrix layer splitting transformation, an intra-layer pipeline operation is performed, that is, in the first group of Z in the layer... c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the Z of the second group within the layer. c After reading the posterior probability information of the relevant variable nodes of the two verification nodes and completing the update of the two groups within the split layer, start the update of the first layer within the next layer, and repeat steps 3 and 4.

[0104] Step 6: After updating the information of all verification nodes in each layer and reaching the set number of iterations, the decoding iteration is complete, and the output processing of the decoding results begins.

[0105] Step 6.1: Control the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, store it and wait for output;

[0106] Step 6.2: After storing the hard decision information of the variable nodes of a transport block, begin decoding and output.

[0107] The present invention also provides a low-power, high-throughput 5G LDPC decoder implementation device, comprising: a decoding parameter calculation module, used to calculate the parameters required for decoding from the input parameters according to the 5G NR LDPC code standard;

[0108] The input buffer control and variable node posterior probability information storage unit is used to store the received variable node posterior probability information, based on the expansion factor Z. c The values ​​are stored using different block storage methods;

[0109] The cyclic shift coefficient, cyclic shift, and data restoration unit are used to determine the data based on the expansion factor Z. c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix.

[0110] The decoding center, decoding calculation and verification node information storage unit are used to update the verification node information and variable node posterior probability information within the layer;

[0111] The overall decoding control module is used to control the decoding process of each layer according to the base matrix splitting, so as to realize layered iterative decoding.

[0112] The decoding output control and decoding output buffer unit is used to complete the information update of all verification nodes in each layer and, after reaching the set number of iterations, the decoding iteration is completed and the output processing of the decoding result begins.

[0113] The invention is further characterized in that,

[0114] The input cache control and variable node posterior probability information storage unit includes an input cache control module and a variable node posterior probability information storage module, wherein...

[0115] The input buffer control module is used to concatenate the received variable node posterior probability information, that is, to concatenate the 0s or 1s in the corresponding bits of the quantized variable node posterior probability information.

[0116] Where, if the expansion factor Z c If Z is not greater than 192, then c Each posterior probability information bit is grouped together to concatenate the data. After each group is concatenated, the address addra of the cached concatenated data result is incremented by 1. The initial value of addra is 0.

[0117] If the expansion factor Z c Greater than 192, Z c If it is even, then use Z. c The data is grouped into pairs with a unit length of 2. The posterior probability information of odd-numbered bits is grouped together, and the posterior probability information of even-numbered bits is grouped together. After each group is grouped, the address of the cached odd-numbered data result, addra_odd, and the address of the cached even-numbered data result, addra_even, are both incremented by 1. The initial value of addra_odd is 0, and the initial value of addra_even is 1. The bit width of the data signal temporarily storing the grouped result is set to 192.

[0118] The variable node posterior probability information storage module is used to classify and store the assembled variable node posterior probability information.

[0119] Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information.

[0120] The cyclic shift coefficient, cyclic shift, and data restoration unit includes a cyclic shift coefficient module, a cyclic shift module, and a data restoration module.

[0121] The cyclic shift coefficient module is used to obtain the non-zero column index value (index) and the actual cyclic shift coefficient value (offset) corresponding to each non-zero column index for each layer, based on the base matrix and decoding parameters specified in the 5G NR LDPC standard, where index ≥ 0 and 0 ≤ offset. <Z c ;

[0122] Set the following rule: when the expansion factor Z c When the value is not greater than 192, the corresponding posterior probability information block of the variable node in each layer is obtained according to the index, and then the information block is shifted according to the corresponding cyclic shift coefficient value.

[0123] When the expansion factor Z c When Z is greater than 192, c If the number is even, the basis matrix is ​​split into two groups at each level; within each level, the first group Z is processed first. c The update of the information of two check nodes is defined as L1; then the second group of Z within the layer is performed. c The update of the information of two check nodes is defined as L2. Based on the storage method of the posterior probability information of the variable nodes in step 2, the non-zero column index value L1_index and the actual cyclic shift coefficient value L1_offset in the L1 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L1_index = 2*index, L1_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L1_index = 2*index + 1, L1_offset = (offset - 1) / 2. The non-zero column index value L2_index and the actual cyclic shift coefficient value L2_offset in the L2 process are obtained by the following relationship: if the actual cyclic shift coefficient value offset is even, then L2_index = 2*index + 1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset is odd, then L2_index = 2*index, L2_offset = (offset + 1) / 2.

[0124] The cyclic shift module is used to obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in the cyclic shift coefficient module. The non-zero column index is the address of the stored variable node posterior probability information. After retrieving the corresponding variable node posterior probability information, the shift operation is performed according to the corresponding cyclic shift coefficient.

[0125] The data restoration module is used to reconstruct the data from the corresponding bits of the shifted variable node posterior probability information blocks, restoring Z from each variable node posterior probability information block. c This provides the actual posterior probability information of the variable nodes that can be used for calculation. At this point, each validation node in the layer has obtained the posterior probability information of the variable nodes needed for updating.

[0126] The decoding center, decoding calculation, and verification node information storage unit includes a decoding center module, a decoding calculation module, and a verification node information storage module.

[0127] The decoding center module is pre-configured with 192 decoding computation modules. It supports parallel computation and updating of up to 192 check node information and their related variable node posterior probability information within a layer, and uses different methods to be compatible with the expansion factor Z. c All possible values. When the expansion factor Z... c When the value is not greater than 192, the parallelism within the layer is equal to Z. c Using Z c Each decoding module performs parallel computation; when the expansion factor Z... c When Z is greater than 192, c If the number is even, the intra-layer parallelism of the decoding is Z. c / 2, using Z c Two decoding modules perform parallel computation.

[0128] 192 RAM blocks are pre-configured to store the check node information: when Z c When Z is not greater than 192, the address (A-1) of the S-th RAM block stores the information of the S-th check node in layer A; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth check node in the first group of the A layer, and the address (2*A-1) of the Sth RAM block stores the information of the Sth check node in the second group of the A layer, where S = 1, 2, ..., 192 and A = 1, 2, ..., 46.

[0129] The decoding and calculation module is used to decode and calculate the acquired variable node posterior probability information and corresponding check node information, and to update the updated check node information and store it in the corresponding address of 192 RAM blocks.

[0130] The verification node information storage module is used to store the updated variable node posterior probability information by grouping the corresponding 0 and 1 bits of the variable node posterior probability information according to the grouping rules, and then storing it at the address where the data of the variable node posterior probability information before the update is obtained after reverse cyclic shifting.

[0131] The overall decoding control module, if the base matrix is ​​not split, updates the next layer's update after the posterior probability information of the check nodes and variable nodes in the previous layer is updated, repeating the work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation, and check node information storage unit. For cases where the base matrix layer is split, intra-layer pipelined operations are performed, i.e., in the first group of Z within the layer... c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the Z of the second group within the layer. c After reading the posterior probability information of the relevant variable nodes of the two verification nodes and completing the update of the two groups within the split layer, the update of the first layer within the next layer begins. The work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation and verification node information storage unit is repeated.

[0132] The decoding output control and decoding output buffer unit includes a decoding output control module and a decoding output buffer module;

[0133] The decoding output control module is used to control the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, store it and wait for output;

[0134] The decoding output buffer module is used to start decoding output after the hard decision information of the variable node of a transport block has been stored.

[0135] Example 1

[0136] After implementing the functions of a traditional decoder architecture with a parallelism of 384, a decoder architecture with a parallelism of 192, and a decoder architecture with a parallelism of 192 and intra-layer pipelining, respectively, we synthesized the implementation and obtained the resource consumption results, as shown in Table 1.

[0137] Table 1

[0138] LUT BRAM FF 384 parallelism 124530 310.5 117380 192 parallelism 70654 210 67822 192 parallelism + intra-layer pipelining 80189 210 75599

[0139] In the table, LUT represents lookup table, BRAM represents block RAM, and FF represents trigger.

[0140] The following results can be obtained from the data analysis in the table:

[0141] The 192-parallelism architecture consumes significantly fewer resources than the 384-parallelism architecture, with LUTs decreasing by approximately 43.3%, BRAMs by approximately 32.3%, and FFs by approximately 42.2%.

[0142] The architecture with 192 parallelism and intra-layer pipelining also consumes significantly fewer resources than the architecture with 384 parallelism. Specifically, LUTs are reduced by about 35.6%, BRAMs by about 32.3%, and FFs by about 35.6%.

[0143] Compared to the architecture with 192 parallelism, the architecture with intra-layer pipelining has a slight increase in resource consumption. Specifically, LUTs increase by about 13.4%, BRAM remains unchanged, and FF increases by about 11.5%.

[0144] Functional simulation of throughput was performed by selecting codewords:

[0145] Codeword a: Qm=4, rate=658 / 1024, TBS=2216, G=3456, Z c =224

[0146] Codeword b: Qm=4, rate=873 / 1024, TBS=5888, G=6912, Z c =288

[0147] Codeword c: Qm=1, rate=198 / 1024, TBS=2664, G=13824, Z c =288

[0148] Codeword d: Qm=4, rate=873 / 1024, TBS=47112, G=55296, Z c =384 where Qm is the modulation order, rate is the code rate, TBS is the length of the information bits without CRC check, G is the length of the input codeword, and Z is the input codeword length. c This is the expansion factor.

[0149] This example operates at a clock speed of 180MHz, with 10 iterations per iteration. The throughput of each codeword under the three architectures was obtained through simulation, as shown in Table 2, in MHz.

[0150] Table 2

[0151] Code word a Code b Code c Coded words d 384 parallelism 252.68 514.69 80.85 685.96 192 parallelism 126.34 257.34 40.42 342.98 192 parallelism + intra-layer pipelining 178.29 354.70 57.96 472.68

[0152] The results can be obtained from the data in the table:

[0153] For codeword 'a', based on an architecture with 192 parallelism, by adopting intra-layer pipelining, the throughput can be improved by approximately 41.1% compared to the 192 parallelism architecture.

[0154] For codeword b, based on an architecture with 192 parallelism, by adopting intra-layer pipelining, the throughput can be improved by approximately 37.8% compared to the 192 parallelism architecture.

[0155] For codeword c, based on an architecture with 192 parallelism, by adopting intra-layer pipelining, the throughput can be improved by approximately 43.4% compared to 192 parallelism.

[0156] For codeword d, based on the architecture with 192 parallelism, after adopting intra-layer pipelining, the throughput can be improved by about 37.8% compared to 192 parallelism.

[0157] In summary, this invention achieves compatibility with all codewords of 5G NR LDPC, significantly reduces resource consumption, and improves the throughput of the 192-parallelism architecture through intra-layer pipelining. This invention is highly applicable to different needs in various scenarios, achieving an effective trade-off between decoding resources and decoding throughput, realizing low-resource-consumption, high-throughput 5G NR LDPC decoding, which is of great significance for practical applications.

[0158] Example 2

[0159] A low-power, high-throughput 5G LDPC decoder implementation device includes: a decoding parameter calculation module, used to calculate the parameters required for decoding from the input parameters according to the 5G NR LDPC code standard;

[0160] The input buffer control and variable node posterior probability information storage unit is used to store the received variable node posterior probability information, based on the expansion factor Z. c The values ​​are stored using different block storage methods;

[0161] The cyclic shift coefficient, cyclic shift, and data restoration unit are used to determine the data based on the expansion factor Z. c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix.

[0162] The decoding center, decoding calculation and verification node information storage unit are used to update the verification node information and variable node posterior probability information within the layer;

[0163] The overall decoding control module is used to control the decoding process of each layer according to the base matrix splitting, so as to realize layered iterative decoding.

[0164] The decoding output control and decoding output buffer unit is used to complete the information update of all verification nodes in each layer and, after reaching the set number of iterations, the decoding iteration is completed and the output processing of the decoding result begins.

[0165] Example 3

[0166] A low-power, high-throughput 5G LDPC decoder implementation device includes: a decoding parameter calculation module, used to calculate the parameters required for decoding from the input parameters according to the 5G NR LDPC code standard;

[0167] The input buffer control and variable node posterior probability information storage unit is used to store the received variable node posterior probability information, based on the expansion factor Z. c The values ​​are stored using different block storage methods;

[0168] The cyclic shift coefficient, cyclic shift, and data restoration unit are used to determine the data based on the expansion factor Z. c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix.

[0169] The decoding center, decoding calculation and verification node information storage unit are used to update the verification node information and variable node posterior probability information within the layer;

[0170] The overall decoding control module is used to control the decoding process of each layer according to the base matrix splitting, so as to realize layered iterative decoding.

[0171] The decoding output control and decoding output buffer unit is used to complete the information update of all verification nodes in each layer and, after reaching the set number of iterations, the decoding iteration is completed and the output processing of the decoding result begins.

[0172] The input cache control and variable node posterior probability information storage unit includes an input cache control module and a variable node posterior probability information storage module, wherein...

[0173] The input buffer control module is used to concatenate the received variable node posterior probability information, that is, to concatenate the 0s or 1s in the corresponding bits of the quantized variable node posterior probability information.

[0174] Where, if the expansion factor Z c If Z is not greater than 192, then c Each posterior probability information bit is grouped together to concatenate the data. After each group is concatenated, the address addra of the cached concatenated data result is incremented by 1. The initial value of addra is 0.

[0175] If the expansion factor Z c Greater than 192, Z c If it is even, then use Z. cThe data is grouped into pairs with a unit length of 2. The posterior probability information of odd-numbered bits is grouped together, and the posterior probability information of even-numbered bits is grouped together. After each group is grouped, the address of the cached odd-numbered data result, addra_odd, and the address of the cached even-numbered data result, addra_even, are both incremented by 1. The initial value of addra_odd is 0, and the initial value of addra_even is 1. The bit width of the data signal temporarily storing the grouped result is set to 192.

[0176] The variable node posterior probability information storage module is used to classify and store the assembled variable node posterior probability information.

[0177] Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information.

Claims

1. A method for implementing a low-complexity, high-throughput 5G LDPC decoder, characterized in that, Specifically: Step 1: Based on the 5G NR LDPC code standard, calculate the various decoding-related parameters required for decoding from the input parameters; Step 2: Store the received posterior probability information of the variable nodes, and then adjust the data according to the expansion factor. Z c The values ​​are stored in different blocks according to different storage methods; Step 2 is as follows: Step 2.1: Concatenate the received variable node posterior probability information, that is, concatenate the 0s or 1s in the corresponding bits of the input quantized variable node posterior probability information; Where, if the expansion factor Z c If not greater than 192, then Z c The data is grouped into sets of posterior probability information bits. After each group is concatenated, the address of the concatenated data result is cached. addra Then increase by 1, addra The initial value is 0; If the expansion factor Z c Greater than 192, Z c If it is even, then use Z c The data is grouped into pairs with a unit length of / 2. Odd-numbered posterior probability information is grouped together, and even-numbered posterior probability information is grouped together. After each group is grouped, the address of the odd-numbered data result is cached. addra_odd and the address of the cached even-numbered data results addra_even All increase by 1, addra_odd The initial value is 0. addra_eve The initial value of n is 1, and the bit width of the data signal temporarily stored in the splicing result is set to 192; Step 2.2: Classify and store the posterior probability information of the assembled variable nodes: Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the variable node posterior probability information grouped and concatenated in step 2.

1. Step 3: Based on the expansion factor Z c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix. Step 4: Update the verification node information and variable node posterior probability information within the layer; Step 5: Control the decoding process of each layer according to the basis matrix splitting to achieve layered iterative decoding; Step 6: After updating the information of all verification nodes in each layer and reaching the set number of iterations, the decoding iteration is complete, and the output processing of the decoding results begins.

2. The method for implementing a low-power, high-throughput 5G LDPC decoder according to claim 1, characterized in that, In step 1, the parameters required for decoding include the basis matrix BG and the spread factor. Z c The number of rows M, the number of columns N, the shortened bit length L, and the number of decoding iterations in the parity check matrix. I .

3. The method for implementing a low-power, high-throughput 5G LDPC decoder according to claim 1, characterized in that, Step 3 specifically involves: Step 3.1: Based on the base matrix and decoding parameters specified in the 5G NR LDPC standard, obtain the non-zero column index values ​​for each layer. index and the actual circular shift coefficient value corresponding to each non-zero column index. offset ,in index≥ 0, 0 ≤offset <Z c ; Set the following rule: when the expansion factor Z c When not greater than 192, according to index Obtain the corresponding posterior probability information block of the variable node in each layer, and then shift the information block according to the corresponding cyclic shift coefficient value; When expansion factor Z c When it is greater than 192, Z c If the number is even, the basis matrix is ​​split into two groups at each level; within each level, the first group is processed first. Z c The information of two verification nodes is updated; this process is defined as L1. Then, the second set of information within the layer is performed. Z c The update of two check node information is defined as L2, based on the storage method of the posterior probability information of the variable nodes in step 2, and the non-zero column index value in the L1 process. L1_index Compared with the actual cyclic shift coefficient value L1_offset It is obtained from the following relationship: if the actual cyclic shift coefficient value offset If it is even, then L1_index = 2* index , L1_offset = offset / 2; if the actual cyclic shift coefficient value offset If it is an odd number, then L1_index = 2* index +1, L1_offset =( offset -1) / 2, non-zero column index value in L2 process L2_index Compared with the actual cyclic shift coefficient value L2_offset It is obtained from the following relationship: if the actual cyclic shift coefficient value offset If it is even, then L2_index = 2* index +1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset If it is an odd number, then L2_index = 2* index , L2_offset =( offset +1) / 2; Step 3.2: Obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in Step 3.

1. The non-zero column index is the address of the posterior probability information of the variable node stored in Step 2.

1. After retrieving the posterior probability information of the corresponding variable node, perform the shift operation according to the corresponding cyclic shift coefficient. Step 3.3: Concatenate and reconstruct the data in the corresponding bits of each variable node's posterior probability information block after shifting. The reconstructed posterior probability information block of each variable node will then... Z c Each actual variable node has its own posterior probability information that can be used for calculation; at this point, each verification node in the layer has the posterior probability information of the variable nodes required for updating.

4. The method for implementing a low-power, high-throughput 5G LDPC decoder according to claim 3, characterized in that, Step 4 is as follows: Step 4.1: Use different methods to ensure compatibility with expansion factors. Z c All possible values, when the expansion factor Z c When the value is not greater than 192, the intra-layer parallelism is equal to Z c ,use Z c Each decoding module performs parallel computation; when the expansion factor... Z c When it is greater than 192, Z c If the number is even, the intra-layer parallelism of the decoding is... Z c / 2, use Z c Two decoding modules perform parallel computation. 192 RAM blocks are pre-configured to store the check node information: when Z c When the value is not greater than 192, the address A of the Sth RAM block stores the information of the Sth check node in the Ath layer; when Z c When the value is not greater than 192, the address A-1 of the S-th RAM block stores the information of the S-th check node in the A-th layer; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth check node in the first group of the A layer, and the address 2*A-1 of the Sth RAM block stores the information of the Sth check node in the second group of the A layer, S=1, 2, …, 192, A=1, 2, …, 46; Step 4.2: Decode and update the posterior probability information of the variable nodes obtained in Step 3 and the corresponding check node information in Step 4.1, and store the updated check node information at the corresponding addresses of the 192 RAM blocks in Step 4.

1. Step 4.3: The updated variable node posterior probability information is grouped and concatenated according to the grouping rules in Step 2, with 0 and 1 bits at corresponding positions. After reverse cyclic shifting, it is still stored at the address where the variable node posterior probability information data before the update is obtained.

5. The method for implementing a low-power, high-throughput 5G LDPC decoder according to claim 4, characterized in that, Step 5 specifically involves: If the base matrix is ​​not split in step 3, the update of the next layer begins after the posterior probability information of the verification nodes and variable nodes in the previous layer is updated, and steps 3 and 4 are repeated. For cases where there is a base matrix layer splitting transformation, an intra-layer pipeline operation is performed, that is, in the first group within the layer... Z c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the second group within the layer. Z c After reading the posterior probability information of the relevant variable nodes of the two verification nodes, and completing the update of the two groups within the split layer, start the update of the first layer within the next layer, and repeat steps 3 and 4. Step 6 specifically involves: Step 6.1: Control the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, store it and wait for output; Step 6.2: After storing the hard decision information of the variable nodes of a transport block, begin decoding and output.

6. A low-power, high-throughput 5G LDPC decoder implementation device, characterized in that, It includes: a decoding parameter calculation module, which is used to calculate the parameters required for decoding from the input parameters according to the 5G NR LDPC code standard; The input buffer control and variable node posterior probability information storage unit is used to store the received variable node posterior probability information, based on the expansion factor. Z c The values ​​are stored in different blocks according to different storage methods; The cyclic shift coefficient, cyclic shift, and data restoration unit are used to determine the data based on the expansion factor. Z c The value of determines whether to perform a layer split transformation on the basis matrix, and obtains the posterior probability information of the variable nodes required for updating the verification nodes of each layer based on the basis matrix. The decoding center, decoding calculation and verification node information storage unit are used to update the verification node information and variable node posterior probability information within the layer; The overall decoding control module is used to control the decoding process of each layer according to the base matrix splitting, realize the hierarchical iterative decoding output control and decoding output buffer unit, and complete the information update of all verification nodes in each layer. After the set number of iterations is reached, the decoding iteration is completed and the output processing of the decoding result begins. The input cache control and variable node posterior probability information storage unit includes an input cache control module and a variable node posterior probability information storage module, wherein... The input buffer control module is used to concatenate the received variable node posterior probability information, that is, to concatenate the 0s or 1s in the corresponding bits of the quantized variable node posterior probability information. Where, if the expansion factor Z c If not greater than 192, then Z c The data is grouped into sets of posterior probability information bits. After each group is concatenated, the address of the concatenated data result is cached. addra Then increase by 1, addra The initial value is 0; If the expansion factor Z c Greater than 192, Z c If it is even, then use Z c The data is grouped into pairs with a unit length of / 2. Odd-numbered posterior probability information is grouped together, and even-numbered posterior probability information is grouped together. After each group is grouped, the address of the odd-numbered data result is cached. addra_odd and the address of the cached even-numbered data results addra_even All increase by 1, addra_odd The initial value is 0. addra_eve The initial value of n is 1, and the bit width of the data signal temporarily stored in the splicing result is set to 192; The variable node posterior probability information storage module is used to classify and store the assembled variable node posterior probability information. Two sets of RAM are set up to implement the ping-pong operation. The number of RAM blocks instantiated in each set of RAM is the same as the quantization bit width of the variable node posterior probability information. The address where the variable node posterior probability information is stored is the address corresponding to the grouped concatenation of the variable node posterior probability information.

7. The low-power, high-throughput 5G LDPC decoder implementation apparatus according to claim 6, characterized in that, The cyclic shift coefficient, cyclic shift, and data restoration unit includes a cyclic shift coefficient module, a cyclic shift module, and a data restoration module. The cyclic shift coefficient module is used to obtain the non-zero column index value of each layer according to the base matrix and various decoding parameters specified in the 5G NR LDPC standard. index and the actual circular shift coefficient value corresponding to each non-zero column index. offset ,in index≥ 0, 0≤offset <Z c ; Set the following rule: when the expansion factor Z c When not greater than 192, according to index Obtain the corresponding posterior probability information block of the variable node in each layer, and then shift the information block according to the corresponding cyclic shift coefficient value; When expansion factor Z c When it is greater than 192, Z c If the number is even, the basis matrix is ​​split into two groups at each level; within each level, the first group is processed first. Z c The information of two verification nodes is updated; this process is defined as L1. Then, the second set of information within the layer is performed. Z c The update of two check node information is defined as L2, based on the storage method of the posterior probability information of the variable nodes in step 2, and the non-zero column index value in the L1 process. L1_index Compared with the actual cyclic shift coefficient value L1_offset It is obtained from the following relationship: if the actual cyclic shift coefficient value offset If it is even, then L1_index = 2* index , L1_offset = offset / 2; if the actual cyclic shift coefficient value offset If it is an odd number, then L1_index = 2* index +1, L1_offset =( offset -1) / 2, non-zero column index value in L2 process L2_index Compared with the actual cyclic shift coefficient value L2_offset It is obtained from the following relationship: if the actual cyclic shift coefficient value offset If it is even, then L2_index = 2* index +1, L2_offset = offset / 2; if the actual cyclic shift coefficient value offset If it is an odd number, then L2_index = 2* index , L2_offset =( offset +1) / 2; The cyclic shift module is used to obtain the non-zero column index and the corresponding cyclic shift coefficient of the first layer according to the rules in the cyclic shift coefficient module. The non-zero column index is the address of the stored variable node posterior probability information. After retrieving the corresponding variable node posterior probability information, the shift operation is performed according to the corresponding cyclic shift coefficient. The data restoration module is used to reconstruct the data from the corresponding bits of the shifted variable node posterior probability information blocks, restoring the data from each variable node posterior probability information block. Z c Each actual variable node has its own posterior probability information that can be used for calculation; at this point, each verification node in the layer has the posterior probability information of the variable nodes required for updating.

8. The low-power, high-throughput 5G LDPC decoder implementation apparatus according to claim 6, characterized in that, The decoding center, decoding calculation, and verification node information storage unit includes a decoding center module, a decoding calculation module, and a verification node information storage module. The decoding center module is pre-configured with 192 decoding computation modules. It supports parallel computation and updating of up to 192 check node information and their related variable node posterior probability information within a layer, and uses different methods to be compatible with the expansion factor. Z c All possible values, when the expansion factor Z c When the value is not greater than 192, the intra-layer parallelism is equal to Z c ,use Z c Each decoding module performs parallel computation; when the expansion factor... Z c When it is greater than 192, Z c If the number is even, the intra-layer parallelism of the decoding is... Z c / 2, use Z c Two decoding modules perform parallel computation. 192 RAM blocks are pre-configured to store the check node information: when Z c When the value is not greater than 192, the address A-1 of the S-th RAM block stores the information of the S-th check node in layer A; when Z c When the value is greater than 192, the address 2*(A-1) of the Sth RAM block stores the information of the Sth check node in the first group of the A layer, and the address 2*A-1 of the Sth RAM block stores the information of the Sth check node in the second group of the A layer, S=1, 2, …, 192, A=1, 2, …, 46; The decoding and calculation module is used to decode and calculate the acquired variable node posterior probability information and corresponding check node information, and to update the updated check node information and store it in the corresponding address of 192 RAM blocks. The verification node information storage module is used to store the updated variable node posterior probability information by grouping the 0 and 1 bits at corresponding positions according to the grouping rules, and then storing it at the address where the data of the variable node posterior probability information before the update is obtained after reverse cyclic shifting. The overall decoding control module, if the base matrix is ​​not split, updates the next layer's update after the posterior probability information of the check nodes and variable nodes in the previous layer is updated, repeating the work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation, and check node information storage unit. For cases where the base matrix layer is split, intra-layer pipelined operations are performed, i.e., in the first group within the layer... Z c After the posterior probability information of the two verification nodes and their corresponding variable nodes is updated, and before the write-back storage is completed, it will be used to calculate the second group within the layer. Z c After reading the posterior probability information of the relevant variable nodes of the two verification nodes and completing the update of the two groups within the split layer, the update of the first layer within the next layer begins. The work of the cyclic shift coefficient, cyclic shift and data restoration unit, decoding center, decoding calculation and verification node information storage unit is repeated. The decoding output control and decoding output buffer unit includes a decoding output control module and a decoding output buffer module; Among them, the decoding output control module controls the reading of the sign bit information in the posterior probability information of the variable node, that is, the hard decision information of the variable node, stores it and waits for output; The decoding output buffer module is used to start decoding output after the hard decision information of the variable node of a transport block has been stored.

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