Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate has a display area and a non-display area, the display area is provided with a plurality of first signal lines arranged in an array and a plurality of sub-pixels, the non-display area is provided with a first power supply line to an Nth power supply line, the first signal lines extend at least partially along a first direction, any one of the first power supply line to the Nth power supply line extends at least partially along a second direction, the first signal lines are electrically connected to the sub-pixels and are configured to provide initial signals to the sub-pixels; the display area is divided into M display sub-areas arranged along the second direction, the first signal lines located in the same display sub-area are connected to the same power supply line, and the first signal lines in at least two display sub-areas are connected to different power supply lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a display substrate having a display area and a non-display area. The display area is provided with sub-pixels arranged in an array and a plurality of first signal lines. The non-display area is provided with a first power supply line to an Nth power supply line. The first signal lines extend at least partially along a first direction, and any one of the first to Nth power supply lines extends at least partially along a second direction. The first direction and the second direction intersect.

[0005] The first signal line is electrically connected to the sub-pixel and is configured to provide an initial signal to the sub-pixel;

[0006] The display area is divided into M display sub-areas arranged along the second direction. The first signal line in the same display sub-area is connected to the same power supply line, and the first signal lines in at least two display sub-areas are connected to different power supply lines, where M and N ≥ 2.

[0007] In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines and a plurality of second initial signal lines extending along the first direction. The sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to drive the light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The light-emitting device includes a first electrode. The first initial signal lines are configured to provide an initial signal to one of the source and drain electrodes of the driving transistor. The second initial signal lines are configured to provide an initial signal to the first electrode of the light-emitting device.

[0008] The first signal line includes either the first initial signal line or the second initial signal line.

[0009] In an exemplary embodiment, the display area is further provided with a plurality of third initial signal lines extending along the first direction, the third initial signal lines being configured to provide an initial signal to another electrode in the source and drain electrodes of the driving transistor;

[0010] The first signal line includes any one of the first initial signal line, the second initial signal line, and the third initial signal line.

[0011] In an exemplary embodiment, when the first signal line is the second initial signal line, M = K or 2K-1, where K is the number of times the second initial signal line effectively initializes the first electrode of the light-emitting device within the target duration. The effective initialization refers to the second initial signal line adjusting the first electrode of the light-emitting device from the first signal to the second signal. The voltage value of the first signal is different from the voltage value of the second signal. The second signal is the signal transmitted by the second initial signal line, and the target duration is equal to the duration of one display frame.

[0012] In an exemplary embodiment, when M = K, the m-th display sub-area includes: sub-pixels from row (m-1)*X / K+1 to row m*X / K, where 1 ≤ m ≤ M, and X is the total number of rows of sub-pixels included in the display area.

[0013] In an exemplary embodiment, N = M, the second initial signal line of the nth display sub-region is electrically connected to the nth power supply line, and 1 ≤ n ≤ N;

[0014] The voltage values ​​of the signals from the first power supply line to the Nth power supply line are the same.

[0015] In an exemplary embodiment, when M = 2K-1, a blanking region is included between two adjacent display frames; the a-th sub-pixel group includes: sub-pixels in rows (X*a / K)-Y+1 to rows (X*a / K)+Y, where X is the total number of rows of sub-pixels included in the display area, and Y is the ratio of the duration in the blanking region to the duration of display of a row of sub-pixels.

[0016] The first sub-pixel group to the (K-1)th sub-pixel group are located in different display sub-regions.

[0017] In an exemplary embodiment, when M = 2K-1, the 2a display sub-area includes: the a-th sub-pixel group, the first display sub-area includes: the first row of sub-pixels to the (X / K)-Y+1th row of sub-pixels, the 2K-1 display sub-area includes: the (X*(K-1) / K)+Y+1th row of sub-pixels and the Xth row of sub-pixels, and the b display sub-area includes: the (X*(b-1) / 2*K)+Y+1th row of sub-pixels to the (X*(b+1) / 2*K)-Yth row of sub-pixels.

[0018] In an exemplary embodiment, when M = 2K-1, the second initial signal line of the odd-numbered display sub-area is electrically connected to the first power supply line, and the second initial signal line of the even-numbered display sub-area is electrically connected to the second power supply line.

[0019] The voltage value of the signal on the first power supply line is less than the voltage value of the signal on the second power supply line.

[0020] In an exemplary embodiment, the number of any one of the first power supply lines to the Nth power supply line is two, and they are respectively located on opposite sides of the display area.

[0021] In an exemplary embodiment, the display area is further provided with a plurality of first initial connection lines, a plurality of second initial connection lines, and a plurality of third initial connection lines; any one of the first initial connection lines, the second initial connection lines, and the third initial connection lines extends at least partially along the second direction;

[0022] The first initial connection lines located in different display sub-areas are spaced apart, the second initial connection lines located in different display sub-areas are spaced apart, the third initial connection lines located in different display sub-areas are spaced apart, the first initial connection lines and the first initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other, the second initial connection lines and the second initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other, and the third initial connection lines and the third initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other;

[0023] The non-display area is further provided with: a first initial power supply line and a third initial power supply line extending at least partially along the second direction, wherein the first initial power supply line is connected to a first initial signal line located in all sub-display areas, and the third initial power supply line is connected to a third initial signal line located in all sub-display areas;

[0024] The number of the first initial power supply lines is two, and they are respectively located on opposite sides of the display area. The number of the third initial power supply lines is two, and they are respectively located on opposite sides of the display area. The first power supply lines to the Nth power supply line, the first initial power supply line and the third initial power supply line located on the same side of the display area are arranged along the first direction.

[0025] In an exemplary embodiment, the system includes: a substrate and a driving structure layer disposed on the substrate, the driving structure layer including: a pixel driving circuit, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line to an Nth power supply line, a first initial power supply line and a third initial power supply line;

[0026] Any one of the first power supply lines to the Nth power supply line is disposed on the same layer as the first initial power supply line and the third initial power supply line, and is located on the side of any one of the first initial signal line, the second initial signal line and the third initial signal line away from the substrate.

[0027] In an exemplary embodiment, the non-display area includes: a binding area located on one side of the display area and a border area located on the other side of the display area; the non-display area is also provided with at least one second signal line.

[0028] The second signal line is electrically connected to two first initial power supply lines located on both sides of the display area and a first initial connection line located in the display area, or to two third initial power supply lines located on both sides of the display area and a third initial connection line located in the display area.

[0029] Any one of the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line is located in the border area and the bonding area, and the second signal line is located in the bonding area.

[0030] In an exemplary embodiment, the non-display area further includes a test pin group disposed on the side of the bonding area away from the display area;

[0031] The second signal line includes: a first connecting segment, a second connecting segment, a third connecting segment, a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, and a seventh connecting segment, wherein any one of the first connecting segment, the third connecting segment, and the seventh connecting segment extends at least partially along the first direction, and any one of the second connecting segment, the fourth connecting segment, the fifth connecting segment, and the sixth connecting segment extends at least partially along the second direction;

[0032] With the second signal line electrically connected to two first initial power supply lines located on both sides of the display area and a first initial connection line located in the display area, one end of the first connection segment is electrically connected to one end of one of the first initial power supply lines, the other end of the first connection segment is electrically connected to the middle section of the second connection segment, one end of the second connection segment is electrically connected to one end of the third connection segment, the other end of the third connection segment is electrically connected to one end of the fifth connection segment, one end of the fourth connection segment is electrically connected to the middle section of the third connection segment, the other end of the fourth connection segment is electrically connected to the first initial connection line, the other end of the fifth connection segment is electrically connected to one end of the sixth connection segment, the other end of the sixth connection segment is electrically connected to the test pin group, one end of the seventh connection segment is electrically connected to the middle section of the fifth connection segment, and the other end of the seventh connection segment is electrically connected to another first initial power supply line.

[0033] With the second signal line electrically connected to two third initial power supply lines located on both sides of the display area and a third initial connection line located in the display area, one end of the first connection segment is electrically connected to one end of one of the third initial power supply lines, the other end of the first connection segment is electrically connected to the middle section of the second connection segment, one end of the second connection segment is electrically connected to one end of the third connection segment, the other end of the third connection segment is electrically connected to one end of the fifth connection segment, one end of the fourth connection segment is electrically connected to the middle section of the third connection segment, the other end of the fourth connection segment is electrically connected to the third initial connection line, the other end of the fifth connection segment is electrically connected to one end of the sixth connection segment, the other end of the sixth connection segment is electrically connected to the test pin group, one end of the seventh connection segment is electrically connected to the middle section of the fifth connection segment, and the other end of the seventh connection segment is electrically connected to another third initial power supply line.

[0034] In an exemplary embodiment, the non-display area further includes: a first power line and a second power line, wherein the first power line is electrically connected to the pixel driving circuit and configured to provide a power signal to the pixel driving circuit, and the second power line is electrically connected to the second electrode of the light-emitting device and configured to provide a power signal to the second electrode of the light-emitting device; the bonding area includes: a first fan-out area, a bending area, a second fan-out area, a first circuit area, a third fan-out area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area; the first power line and the second power line are located in the bonding area and the border area;

[0035] The first connecting segment, the second connecting segment, the third connecting segment, the fifth connecting segment, the sixth connecting segment, and the seventh connecting segment are all located on the side of the second fan-out area away from the display area. The first connecting segment and the seventh connecting segment are located on the side of the third connecting segment away from the display area and are located in any one of the first circuit area, the third fan-out area, and the driver chip area. Any one of the second connecting segment and the fifth connecting segment is at least partially located in the first circuit area, the third fan-out area, the driver chip area, and the bonding pin area. The sixth connecting segment is located in the bonding pin area. The fourth connecting segment is located on the side of the first circuit area closer to the display area and is at least partially located in the first fan-out area, the bending area, and the second fan-out area.

[0036] The orthographic projections of the first connecting segment and the seventh connecting segment on the substrate at least partially overlap with the orthographic projections of the first power line and the second power line on the substrate, respectively; the orthographic projection of the fourth connecting segment on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0037] In an exemplary embodiment, the fourth connection segment includes: a first sub-segment, a second sub-segment, and a third sub-segment sequentially arranged along a direction close to the display area, wherein the third signal line is located in the display area;

[0038] The first sub-segment is electrically connected to both the third connecting segment and the second sub-segment, and the third sub-segment is electrically connected to the second sub-segment.

[0039] The first segment is at least partially located in the second fan-out region, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate. The second segment is at least partially located in the bending region, and the third segment is at least partially located in the first fan-out region.

[0040] In an exemplary embodiment, the first connecting segment and the seventh connecting segment are located on the side of the first power line or the second power line closer to the substrate, the second connecting segment, the third connecting segment, the fifth connecting segment and the sixth connecting segment are located on the side of the first connecting segment away from the substrate, the first sub-segment is located on the side of the third connecting segment closer to the substrate, the second sub-segment is located on the side of the first sub-segment away from the substrate, the third sub-segment is located on the side of the second sub-segment closer to the substrate, and the sixth connecting segment is located on the side of the fifth connecting segment away from the substrate.

[0041] In an exemplary embodiment, the display area is further provided with a signal connection line, which is electrically connected to the initial connection line connected to the third sub-segment and the second signal line, respectively. The signal connection line has a single-layer structure and is located on the side of the second sub-segment close to the substrate.

[0042] In an exemplary embodiment, the first power line located in the bonding area has an opening on the side near the display area, and the second segment extends to the opening of the first power line.

[0043] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0044] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0045] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0046] Figure 1 This is a schematic diagram of the structure of a display device;

[0047] Figure 2 This is a planar schematic diagram of a display substrate;

[0048] Figure 3A This is a schematic diagram of a pixel driving circuit.

[0049] Figure 3B As a kind Figure 3A The working process of the provided pixel driving circuit;

[0050] Figure 4 This is a timing diagram of the signals within a display frame;

[0051] Figure 5 A schematic diagram illustrating the activation of the signal to achieve effective anode reset;

[0052] Figure 6 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0053] Figure 7 A schematic diagram of the structure of a display substrate provided in an exemplary embodiment. Figure 1 ;

[0054] Figure 8 A schematic diagram of the structure of a display substrate provided in an exemplary embodiment. Figure 2 ;

[0055] Figure 9 for Figure 7 A schematic diagram of the load of any power supply line in the provided display substrate on the display frame;

[0056] Figure 10for Figure 7 A schematic diagram of the load of any power supply line in the blanking region of the provided display substrate;

[0057] Figure 11 for Figure 7 A schematic diagram showing the connection between the first display sub-area and the first power supply line in the provided display substrate;

[0058] Figure 12 for Figure 7 A schematic diagram showing the connection between the second display sub-area and the second power supply line in the provided display substrate;

[0059] Figure 13 for Figure 7 A schematic diagram showing the connection between the third display sub-area and the third power supply line in the provided display substrate;

[0060] Figure 14 for Figure 8 A schematic diagram showing the connection between the odd-numbered display sub-area and the first power supply line in the provided display substrate;

[0061] Figure 15 for Figure 8 A schematic diagram showing the connection between the even-numbered display sub-area and the second power supply line in the provided display substrate;

[0062] Figure 16 A schematic diagram of the structure of a display substrate provided in an exemplary embodiment;

[0063] Figure 17 A schematic diagram of the binding area provided in an exemplary embodiment;

[0064] Figure 18 for Figure 17 A magnified view of the central region A1;

[0065] Figure 19 for Figure 17 A magnified view of the central area A2;

[0066] Figure 20 for Figure 17 A magnified view of the central area A3;

[0067] Figure 21 This is a partial schematic diagram of the binding area. Detailed Implementation

[0068] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0069] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0070] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0071] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0072] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0073] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0074] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0075] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0076] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0077] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0078] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0079] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0080] Figure 1 This is a schematic diagram of the structure of a display device. In some examples, such as... Figure 1 As shown, the display device may include: a timing controller 21, a data driver 22, a scan driving circuit 23, a light-emitting driving circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driving circuit 23 may be configured to provide a scan signal to the sub-pixels PX along a scan signal line; the data driver 22 may be configured to provide a data voltage to the sub-pixels PX along a data line; the light-emitting driving circuit 24 may be configured to provide a light-emitting control signal to the sub-pixels PX along a light-emitting control line; and the timing controller 21 may be configured to control the scan driving circuit 23, the light-emitting driving circuit 24, and the data driver 22.

[0081] In some examples, such as Figure 1 As shown, timing controller 21 can provide grayscale values ​​and control signals of specifications suitable for data driver 22 to data driver 22; timing controller 21 can provide scan clock signals, scan start signals, etc. of specifications suitable for scan driver 23 to scan driver circuit 23; timing controller 21 can provide light emission clock signals, light emission start signals, etc. of specifications suitable for light emission driver circuit 24 to light emission driver circuit 24. Data driver 22 can use the grayscale values ​​and control signals received from timing controller 21 to generate data voltages to be provided to data lines D1 to Di. For example, data driver 22 can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data lines D1 to Di on a sub-pixel line basis. Scan driver circuit 23 can use the scan clock signals, scan start signals, etc. received from timing controller 21 to generate scan signals to be provided to scan lines S1 to Sj. For example, scan driver circuit 23 can sequentially provide scan signals with conduction level pulses to scan lines. In some examples, the scan driver 23 may include a shift register to generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a scan clock signal. The light-emitting driver circuit 24 can generate light-emitting control signals to be provided to the light-emitting control lines E1 to Eo using the light-emitting clock signal, light-emitting start signal, etc., received from the timing controller 21. For example, the light-emitting driver circuit 24 can sequentially provide light-emitting control signals with off-level pulses to the light-emitting control lines. The light-emitting driver circuit 24 may include a shift register to generate light-emitting control signals by sequentially transmitting light-emitting start signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal. Here, i, j, and o are all natural numbers.

[0082] In some examples, the display device may include a display substrate. The subpixel array, scan driving circuitry, and light-emitting driving circuitry may be directly disposed on the display substrate. For example, the scan driving circuitry may be disposed on the left bezel of the display substrate, and the light-emitting driving circuitry may be disposed on the right bezel; alternatively, both the left and right bezels of the display substrate may contain the scan driving circuitry and the light-emitting driving circuitry. In some examples, the scan driving circuitry and the light-emitting driving circuitry may be formed together with the subpixels during the subpixel formation process.

[0083] In some examples, the data driver can be located on a separate chip or printed circuit board. For example, the data driver can be formed on the lower bezel of the display substrate using chip-on-glass, chip-on-plastic, or chip-on-film methods to connect to the driver chip pins. The timing controller can be located separately from the data driver or integrated with it. However, this embodiment is not limited to this.

[0084] Figure 2 This is a planar schematic diagram of a display substrate. In some examples, such as... Figure 2 As shown, the display substrate may include: a display area AA, a bonding area B1 located on one side of the display area AA, and a border area B2 located on the other sides of the display area AA. The bonding area B1 may be, for example, the bottom border of the display substrate, and the border area B2 may include the top border, left border, and right border of the display substrate. In some examples, the display area AA may be a flat area comprising multiple sub-pixels PX that make up a pixel array, and these sub-pixels PX are configured to display moving or still images. The display area may be referred to as the effective area. In some examples, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0085] In some examples, the border area B2 may include a circuit area, a power line area, a crack dam area, and a dicing area arranged sequentially along the direction of the display area AA. The circuit area may be connected to the display area AA and may include at least multiple cascaded gate drive circuits electrically connected to multiple gate lines in the display area AA. The power line area is connected to the circuit area and may include at least low-level power lines extending parallel to the edge of the display area and connected to the cathode of the display area. The crack dam area may be connected to the power line area and may include at least multiple cracks formed on the composite insulating layer. The dicing area is connected to the crack dam area and may include at least dicing grooves formed on the composite insulating layer. These dicing grooves can be configured to allow cutting along the dicing grooves after all film layers of the display substrate have been prepared.

[0086] In some examples, the binding area B1 and the border area B2 can be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam can extend along a direction parallel to the edge of the display area to form a ring structure around the display area AA. The edge of the display area is the edge of the display area closer to the binding area B1 or the border area B2.

[0087] In some examples, such as Figure 2 As shown, the display area AA may include at least multiple sub-pixels PX, multiple gate lines, and multiple data lines Data. The multiple gate lines may extend along a first direction X, and the multiple data lines Data may extend along a second direction Y. The orthogonal projections of the multiple gate lines and the multiple data lines Data on the substrate intersect to form multiple sub-pixel regions, each sub-pixel region containing one sub-pixel PX. The multiple data lines Data are electrically connected to the multiple sub-pixels PX and can be configured to provide data signals to the multiple sub-pixels PX. The multiple data lines Data may extend to the bonding area B1. The multiple gate lines are electrically connected to the multiple sub-pixels PX and can be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals.

[0088] In some examples, such as Figure 2 As shown, the first direction X can be the extension direction of the gate line in the display area AA (row direction), and the second direction Y can be the extension direction of the data line in the display area AA (column direction). The first direction X and the second direction Y can intersect, and for example, the first direction X and the second direction Y can be perpendicular to each other.

[0089] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0090] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0091] In some examples, a sub-pixel may include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0092] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include a first electrode, a second electrode, and an organic light-emitting layer located between the first and second electrodes. The first electrode of the light-emitting element can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited in this respect.

[0093] Figure 3A This is a schematic diagram of a pixel driving circuit. Figure 3A This explanation uses 8T1C as an example. Figure 3A As shown, the pixel driving circuit can be connected to 11 signal lines (Data line, first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, light emission line E, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). The gate lines include: first scan line Gate1, second scan line Gate2, first reset line Reset1, second reset line Reset2, and light emission line E.

[0094] In an exemplary implementation, such as Figure 3AAs shown, the control electrode of the first transistor M1 is connected to the first reset line Reset1, the first terminal of the first transistor M1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the third node N3. The control electrode of the second transistor M2 is connected to the second scan line Gate2, the first terminal of the second transistor M2 is connected to the first node N1, and the second terminal of the second transistor M2 is connected to the third node N3. The control electrode of the third transistor M3 is connected to the first node N1, the first terminal of the third transistor M3 is connected to the second node N2, and the second terminal of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the first scan line Gate1, the first terminal of the fourth transistor M4 is connected to the data line Data, and the second terminal of the fourth transistor M4 is connected to the second node N2. The control electrode of the fifth transistor M5 is connected to the light-emitting line E, the first terminal of the fifth transistor M5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light-emitting line E, the first terminal of the sixth transistor M6 is connected to the third node N3, and the second terminal of the sixth transistor M6 is connected to the fourth node N4. The control electrode of the seventh transistor M7 is connected to the second reset line Reset2, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the fourth node N4. The control electrode of the eighth transistor M8 is connected to the second reset line Reset2, the first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor M8 is connected to the second node N2. The first terminal of capacitor C is connected to the first power supply line VDD, and the second terminal of capacitor C is connected to the first node N1.

[0095] In an exemplary embodiment, the first electrode of the light-emitting device is electrically connected to the fourth node N4, and the second electrode of the light-emitting device is connected to the second power line VSS.

[0096] In an exemplary embodiment, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0097] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0098] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the eighth transistor M8 may include both P-type and N-type transistors.

[0099] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0100] In an exemplary implementation, such as Figure 3A As shown, the second transistor M2 can be an N-type transistor, and the first transistor M1, the third transistor M3 to the eighth transistor M8 can be P-type transistors.

[0101] Figure 3B As a kind Figure 3A The operation process of the provided pixel driving circuit. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0102] In the first stage P1, also known as the first reset stage, the signal of the second reset line Reset2 is low, while the signals of the first reset line Reset1, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are high. The low signal of the second reset line Reset2 turns on the seventh transistor M7 and the eighth transistor M8. The signal of the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L, clearing the original charge from the first electrode. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2, clearing the original charge from the second node N2. During this stage, the third transistor M3 is turned on. The high signal of the second scan line Gate2 turns on the second transistor M2. The signal from the second node N2 is supplied to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The signals of the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high-level signals. The first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are disconnected. During this stage, the light-emitting device L does not emit light.

[0103] The second stage, P2, is called the second reset stage. The signal on the first reset line, Reset1, is low, while the signals on the second reset line, Reset2, the first scan line, Gate1, the second scan line, Gate2, and the light-emitting line E are high. The low signal on Reset1 causes the first transistor M1 and the first initial signal line, INIT1, to provide signals to the third node N3, re-initializing (resetting) N3 and clearing its existing charge. During this stage, the third transistor M3 remains on. The high signal on Gate2 turns on the second transistor M2. The signal from the third node N3 is supplied to the first node N1, continuously initializing it. The high signals on Reset2, Gate1, and the light-emitting line E turn on the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. During this stage, the light-emitting device L does not emit light.

[0104] The third stage, P3, is called the data writing stage or threshold compensation stage. The signal on the first scan line Gate1 is low, while the signals on the first reset line Reset1, the second reset line Reset2, the second scan line Gate2, and the light-emitting line E are high. The data line Data outputs a data voltage. During this stage, the third transistor M3 remains on. The low signal on the first scan line Gate1 turns on the fourth transistor M4. The high signal on the second scan line Gate2 turns on the second transistor M2. The data voltage output from the data line Data is supplied to the first node N1 via the on-state fourth transistor M4, the second node N2, the on-state third transistor M3, the third node N3, and the on-state second transistor M2. The difference between the data voltage output from the data line Data and the threshold voltage of the third transistor M3 is charged into capacitor C. The voltage at the second terminal of capacitor C (first node N1) is Vd - |Vth|, where Vd is the data voltage output from the data line Data, and Vth is the threshold voltage of the third transistor M3. The signals of the first reset line Reset1, the second reset line Reset2, and the light-emitting line E are at a high level, and the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are disconnected. During this stage, the light-emitting device L does not emit light.

[0105] In the fourth stage, P4, known as the continuous compensation stage, the signals of the first reset line Reset1, the second reset line Reset2, the first scan line Gate1, the second scan line Gate2, and the light-emitting line E are all high-level signals. The signal of the second scan line Gate2 is also high-level, and the second transistor M2 remains continuously conducting. Meanwhile, the signals of the first scan line Gate1, the first reset line Reset1, the second reset line Reset2, and the light-emitting line E remain high-level, while the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are de-energized. Although the data line Data stops writing, the second node N2 still supplies power to the first node N1 through the conducting third transistor M3, the third node N3, and the conducting second transistor M2, continuously compensating for the threshold voltage of the third transistor M3.

[0106] In the fifth stage, P5, also known as the bias stage, the signals of the second scan line Gate2 and the second reset line Reset2 are low-level signals, while the signals of the first reset line Reset1, the first scan line Gate1, and the light-emitting line E are high-level signals. When the signal of the second scan line Gate2 is low, and the signals of the first scan line Gate1, the first reset line Reset1, and the light-emitting line E are high, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all off. When the signal of the second reset line Reset2 is low, the seventh transistor M7 and the eighth transistor M8 are turned on. The signal of the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal of the second initial signal line INIT2 is written to the fourth node N3. During this stage, the third transistor M3 is in a biased state, and the light-emitting device L does not emit light.

[0107] The sixth stage, P6, is called the light-emitting stage. The signals of the light-emitting line E and the second scan line Gate2 are low-level signals, while the signals of the first reset line Reset1, the second reset line Reset2, and the first scan line Gate1 are high-level signals. The low-level signal of the light-emitting signal line E turns on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0108] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor M3 is:

[0109] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0110] Where I is the driving current flowing through the third transistor M3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power line VDD.

[0111] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product, and improving the overall display effect of the display product.

[0112] With the maturity of display technology, more and more display products are using LTPO display substrates, especially gaming displays. The market's demand for high refresh rates and variable frequency displays is becoming increasingly urgent.

[0113] Figure 4 This is a timing diagram of signals within a display frame. For example... Figure 4 As shown, a display frame includes multiple frequency conversion units. Within each frequency conversion unit, the pixel driving circuit drives the light-emitting device to emit light once. The display product can switch between different frequencies by increasing the number of frequency conversion units contained in each display frame. Figure 4 This explanation uses an example of a display frame containing three frequency conversion units. Figure 4 As shown, the light-emitting duty cycle and the number of effective anode resets are the same in each frequency conversion unit. The number of effective anode resets refers to the number of times the signal at the first electrode of the light-emitting device is changed from the first signal to the signal of the second initial signal line. Although... Figure 4 In a frequency converter unit, the second reset signal line Reset2 has two valid level signals, that is, the second initial signal line INIT2 resets the first electrode of the light-emitting device twice. However, when the second initial signal line INIT2 resets the first electrode of the light-emitting device for the first time, the signal of the first electrode of the light-emitting device changes from the first signal to the signal of the second initial signal line, which can be called a valid anode reset. However, when the second initial signal line INIT2 resets the first electrode of the light-emitting device for the second time, the signal of the first electrode of the light-emitting device does not change and remains the signal of the second initial signal line. This time, it cannot be called a valid anode reset. Therefore, in each frequency converter unit, there is only one valid anode reset.

[0114] In an exemplary embodiment, taking an effective anode reset frequency of 360Hz as an example, when each display frame includes three frequency conversion units, the refresh rate of the display frame can meet 120Hz; when each display frame includes four frequency conversion units, the refresh rate of the display frame can meet 90Hz. Therefore, refresh rates divisible by 360 (e.g., 120Hz / 90Hz / 72Hz / 60Hz / 45Hz / 40Hz / 36Hz / 30Hz / 20Hz / 10Hz / 1Hz) can be switched. Similarly, when the effective anode reset frequency is 240Hz, refresh rates divisible by 240 can be switched. This disclosure does not impose any limitations in this regard.

[0115] Figure 5 A schematic diagram illustrating the activation of the signal to achieve effective anode reset. Figure 5 The explanation is based on the first to third display frames, with each display frame including three frequency conversion units. Figure 5 The horizontal axis in the figure represents the scan time, where ti refers to the moment when the second reset signal line is at an active level. Figure 5 The vertical axis represents the number of the second reset signal lines. Figure 5 This is illustrated using 18 second reset signal lines G1 to G18 as an example. Figure 5 In the table, 1, 2, and 3 represent the signal pulses when the second reset signal line Reset2 is first active in the first, second, and third frequency conversion units within a display frame, respectively. Hereinafter, 1 is referred to as the first pulse signal, 2 as the second pulse signal, and 3 as the third pulse signal. Figure 5 As shown, there is a blanking region between two adjacent display frames. Figure 5 This explanation is based on the example of a hidden region with a duration of 2t, where the first hidden region includes t19 and t20, and the second hidden region includes t39 and t40.

[0116] In an exemplary implementation, the blanking region refers to a virtual time period used to accommodate display driving timing and signal transmission. The blanking region is also referred to as the "pre- and post-cycloidal time period" or the "synchronization pulse time period".

[0117] like Figure 5 As shown, from a horizontal perspective, the signals of the first second reset signal line G1 at t1, t21, and t41 are the first pulse signals, the signals at t7, t27, and t47 are the second pulse signals, and the signals at t13, t33, and t53 are the third pulse signals. The other second reset signal lines follow the same pattern.

[0118] like Figure 5 As shown, from a vertical perspective, taking t13 as an example, at t13, the signal of the first second reset signal line is the third pulse signal, the signal of the seventh second reset signal line is the second pulse signal, and the signal of the thirteenth reset signal line is the first pulse signal. That is, at t13, the first, seventh, and thirteenth reset signal lines are simultaneously turned on. When the second reset signal line is turned on, the second initial signal line provides an initial signal to the fourth node. In other words, at t13, the second initial signal lines in the sub-pixels connected to the first, seventh, and thirteenth reset signal lines provide an initial signal to the fourth node to effectively reset the fourth node. The same logic applies to the remaining times.

[0119] like Figure 5As shown, after the first pulse signal completes its first scan, the display substrate enters the first blanking region (t19 and t20). In t19, the seventh second reset signal line G7 and the thirteenth second reset signal line G13 are simultaneously turned on. In t20, the eighth second reset signal line G8 and the fourteenth second reset signal line G14 are simultaneously turned on. After the first scan of the second pulse signal is completed, at t25, the fifth second reset signal line G5 and the thirteenth second reset signal line G13 are simultaneously turned on; at t26, the sixth second reset signal line G6 and the fourteenth second reset signal line G14 are simultaneously turned on. After the first scan of the third pulse signal is completed, at t31, the fifth second reset signal line G5 and the eleventh second reset signal line G11 are simultaneously turned on; at t32, the sixth second reset signal line G6 and the twelfth second reset signal line G12 are simultaneously turned on, and so on. After the second scan of the first pulse signal is completed, the display substrate enters the second blanking zone (t39 and t40). At t39, the seventh second reset signal line G7 and the thirteenth second reset signal line G13 are simultaneously turned on; at t40, the eighth second reset signal line G8 and the fourteenth second reset signal line G14 are simultaneously turned on. After the second scan of the second pulse signal is completed, at t45, the fifth second reset signal line G5 and the thirteenth second reset signal line G13 are simultaneously turned on. At t46, the sixth second reset signal line G6 and the fourteenth second reset signal line G14 are simultaneously turned on. After the second scan of the third pulse signal is completed, at t51, the fifth second reset signal line G5 and the eleventh second reset signal line G11 are simultaneously turned on. At t52, the sixth second reset signal line G6 and the twelfth second reset signal line G12 are simultaneously turned on.

[0120] like Figure 5 As shown, on the display substrate, except for the first display frame and the above few times, three second reset signal lines are simultaneously turned on for all other times of the display frame. Figure 4 The timing of the signals will cause a difference in the number of rows of the second reset signal line that is simultaneously turned on in the blanking zone and the display frame. Specifically, the number of rows of the second reset signal line that is simultaneously turned on in the display frame is three, while the number of rows of the second reset signal line that is simultaneously turned on in the blanking zone is two.

[0121] like Figure 5As shown, when the three second reset signal lines are simultaneously turned on, the number of the three turned-on second reset signals, K1, K2, and K3, respectively satisfy 1≤K1≤6, 7≤K2≤12, and 13≤K3≤18. If the display area of ​​the display substrate is uniformly divided into three regions along the column direction, including the first display sub-region to the third display sub-region, where the first display sub-region includes the first row of sub-pixels to the sixth row, the second display sub-region includes the seventh row of sub-pixels to the twelfth row, and the third display sub-region includes the thirteenth row of sub-pixels to the eighteenth row, then the three turned-on second reset signal lines are located in the first, second, and third display sub-regions, respectively. In other words, the three second initial signal lines that simultaneously perform effective anode reset are located in the first, second, and third display sub-regions, respectively.

[0122] like Figure 5 As shown, when the two second reset signal lines are simultaneously turned on, the two turned-on second reset signal lines are located in the first display sub-area and the second display sub-area, or in the second display sub-area and the third display sub-area, respectively. In other words, the two second initial signal lines that simultaneously perform effective anode reset are located in the first display sub-area and the second display sub-area, or in the second display sub-area and the third display sub-area, or in the first display sub-area and the third display sub-area, respectively.

[0123] A display substrate further includes a second initial power supply line, which is electrically connected to all second initial signal lines located in the display area and configured to provide initial signals to the second initial signal lines. Figure 4 and Figure 5 It is known that the number of rows of the second reset signal lines simultaneously conducting during a portion of the display frame is three, meaning the load on the second initial power supply line is the sum of the capacitances of the fourth nodes of the three rows of sub-pixels. In the blanking region, the number of rows of the second reset signal lines simultaneously conducting is two, meaning the load on the second initial power supply line is the sum of the capacitances of the fourth nodes of the two rows of sub-pixels. Because the load on the second initial power supply line differs between the display frame and the blanking region, the potential of the fourth node of the sub-pixel displayed in the display frame is higher than that of the fourth node of the sub-pixel displayed in the blanking region. This results in a slower turn-on speed for the light-emitting devices of the sub-pixels displayed in the blanking region, leading to a darker display effect. And according to... Figure 5 Analysis shows that when the number of rows of the second reset signal line that is simultaneously turned on is two, the sub-pixels displayed are roughly located at one-third and two-thirds of the display substrate. That is, the one-third and two-thirds of the display substrate are darker than other parts of the display substrate, while the remaining areas are brighter, thus forming a split display and causing poor display effect of the display substrate. Figure 4 and Figure 5The analysis is based on the example of a display frame containing three frequency conversion units, with the display screen effect being a three-part screen. When a display frame contains four frequency conversion units, the display substrate is darker at one-quarter, two-quarters, and three-quarters, with the display screen effect being a four-part screen.

[0124] Figure 6 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. Figure 6 As shown, the display substrate provided in this embodiment has a display area AA and a non-display area. The display area AA is provided with sub-pixels PX arranged in an array and multiple first signal lines S1. Each sub-pixel includes a pixel driving circuit and a light-emitting device. The non-display area is provided with first power supply lines SL-1 to Nth power supply lines SL-N. The first signal lines extend at least partially along a first direction X, and any one of the first power supply lines SL-1 to Nth power supply lines SL-N extends at least partially along a second direction Y. The first direction X and the second direction Y intersect. The first signal lines are electrically connected to the pixel driving circuit or the light-emitting device and are configured to provide an initial signal to the pixel driving circuit or the light-emitting device.

[0125] like Figure 6 As shown, the display area AA is divided into M display sub-areas R1 to RM arranged along the second direction. The first signal line in the same display sub-area is connected to the same power supply line, and the first signal line in at least two display sub-areas is connected to different power supply lines, M, N≥2.

[0126] In an exemplary embodiment, the pixel driving circuit can be Figure 3A The provided pixel driving circuit.

[0127] In an exemplary implementation, such as Figure 6 As shown, the non-display area includes: a binding area B1 located on one side of the display area and a border area B2 located on the other sides of the display area AA.

[0128] The display substrate provided in this embodiment has a display area and a non-display area. The display area is provided with sub-pixels arranged in an array and multiple first signal lines. The non-display area is provided with a first power supply line to an Nth power supply line. The first signal lines extend at least partially along a first direction, and any one of the first to Nth power supply lines extends at least partially along a second direction. The first signal lines are electrically connected to the sub-pixels and are configured to provide an initial signal to the sub-pixels. The display area is divided into M display sub-regions arranged along the second direction. The first signal lines in the same display sub-region are connected to the same power supply line, and the first signal lines in at least two display sub-regions are connected to different power supply lines, where M, N≥2. By setting the first to Nth power supply lines, connecting the first signal lines in the same display sub-region to the same power supply line, and connecting the first signal lines in at least two display sub-regions to different power supply lines, this disclosure can reduce the load difference of any power supply line in the display frame and blanking area, thereby improving the display effect of the display substrate.

[0129] In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction. The sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a driving transistor, and the light-emitting device includes a first electrode. The first initial signal lines are configured to provide an initial signal to one of the source and drain electrodes of the driving transistor, and the second initial signal lines are configured to provide an initial signal to the first electrode of the light-emitting device. The first signal lines include any one of the first initial signal lines and the second initial signal lines.

[0130] In an exemplary embodiment, the display area is provided with a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines extending along a first direction. The pixel driving circuit includes a driving transistor, and the light-emitting device includes a first electrode. The first initial signal lines are configured to provide an initial signal to one of the source and drain electrodes of the driving transistor. The second initial signal lines are configured to provide an initial signal to the first electrode of the light-emitting device, and the third initial signal lines are configured to provide an initial signal to the other electrode of the source and drain electrodes of the driving transistor. The first signal lines include any one of the first initial signal lines, the second initial signal lines, and the third initial signal lines.

[0131] Figure 7 A schematic diagram of the structure of a display substrate provided in an exemplary embodiment. Figure 1 , Figure 8 A schematic diagram of the structure of a display substrate provided in an exemplary embodiment. Figure 2 . Figure 7 and Figure 8 This explanation uses the first signal line as the second initial signal line INIT2 as an example.

[0132] In an exemplary implementation, such as Figure 7 and Figure 8 As shown, M = K or 2K-1, where K is the number of times the second initial signal line effectively initializes the first electrode of the light-emitting device within the target duration. Effective initialization refers to the second initial signal line adjusting the first electrode of the light-emitting device from the first signal to the second signal. The voltage value of the first signal is different from the voltage value of the second signal. The second signal is the signal transmitted by the second initial signal line. The target duration is equal to the duration of one display frame. Figure 7 Taking M=K=3 as an example, Figure 8 This explanation is based on the example of K=3 and M=2K-1=5.

[0133] In an exemplary implementation, such as Figure 7 As shown, when M = K, the m-th display sub-region includes sub-pixels from row (m-1)*X / K+1 to row m*X / K, where 1 ≤ m ≤ M, and X is the total number of rows of sub-pixels in the display area, i.e., the display area is evenly divided. For example, with X = 18 and K = 3, the display area includes three sub-regions: the first sub-region includes sub-pixels from row 1 to row 6; the second sub-region includes sub-pixels from row 7 to row 12; and the third sub-region includes sub-pixels from row 13 to row 18.

[0134] In an exemplary implementation, such as Figure 7 As shown, when M=K, N=M, the second initial signal line of the nth display sub-area is electrically connected to the nth power supply line, 1≤n≤N; the voltage values ​​of the signals from the first power supply line to the Nth power supply line are the same. For example, the second initial signal line INIT2 of the first display sub-area R1 is electrically connected to the first power supply line SL-1, the second initial signal line INIT2 of the second display sub-area R2 is electrically connected to the second power supply line SL-2, and the second initial signal line INIT2 of the third display sub-area R3 is electrically connected to the third power supply line SL-3.

[0135] according to Figure 4 and Figure 5 Analysis shows that at any given time, the multiple second reset signal lines that are simultaneously activated are located in different display sub-regions, meaning that the multiple second initial signal lines that are simultaneously performing effective anode reset are located in different display sub-regions. Figure 7 By setting the second initial signal lines of different display sub-areas to connect to different power supply lines, multiple second initial signal lines that are simultaneously turned on at any given time can be connected to different power supply lines respectively. That is, the load of any power supply line at any given time is a second initial signal line.

[0136] In an exemplary embodiment, Figure 9 for Figure 7 A schematic diagram of the load of any power supply line in the provided display substrate on the display frame. Figure 10 for Figure 7A schematic diagram of the load of any power supply line in the blanking region of the provided display substrate. (Example) Figure 9 and Figure 10 As shown, Figure 7 In the display substrate shown, the second power supply line SL-2 and the third power supply line SL-3 are both loaded with a second initial signal line INIT2 at any time in the display frame and the blanking zone. The first power supply line SL-1 is loaded with a second initial signal line INIT2 at any time in the display frame, but has no load at any time in the blanking zone. That is to say, in the first display sub-region of the blanking zone, no second initial signal line will reset the first electrode of the light-emitting device in the sub-pixel. Therefore, the difference in the first power supply line SL-1 between the display frame and the blanking zone will not affect the display effect. Figure 7 The provided display substrate ensures that the signal of the fourth node of any sub-pixel in all sub-pixel rows is approximately the same, and the reset degree of the first electrode of any light-emitting device is consistent, thereby eliminating dark bands at the split screen, eliminating poor split screen performance, and improving the display effect of the display substrate.

[0137] In an exemplary embodiment, the second initial signal lines located in different display sub-regions are independent of each other and do not affect each other. The first power supply line to the Nth power supply line can be merged into a single bus in the bonding area of ​​the display substrate, which can save the number of chip pins, or they can be three independent signal lines.

[0138] In an exemplary implementation, such as Figure 8 As shown, a blanking region is included between two adjacent display frames. The first subpixel group to the (K-1)th subpixel group are located in different display sub-regions. The a-th subpixel group includes: subpixels in rows (X*a / K)-Y+1 to (X*a / K)+Y, where X is the total number of rows of subpixels included in the display area, and Y is the ratio of the duration in the blanking region to the duration of displaying one row of subpixels. For example, taking X=18, Y=2, and K=3 as an example, the first subpixel group includes: subpixels in rows 5 to 8, and the second subpixel group includes: subpixels in rows 11 to 14. The first subpixel group is approximately located at one-third of the display substrate, and the second subpixel group is approximately located at two-thirds of the display substrate. The subpixels included in the first to the (K-1)th subpixel groups are as follows... Figure 4 and Figure 5 The number of rows of the second reset signal lines that are simultaneously turned on is the combination of the sub-pixels connected to the second reset signal lines (G5 to G8, G11 to G14) whose signals are valid at all times in both rows.

[0139] In an exemplary embodiment, when M = 2K-1, the 2a display sub-area includes: the a-th sub-pixel group, the first display sub-area includes: the first row of sub-pixels to the (X / K)-Y+1th row of sub-pixels, the 2K-1 display sub-area includes: the (X*(K-1) / K)+Y+1th row of sub-pixels and the Xth row of sub-pixels, and the b display sub-area includes: the (X*(b-1) / 2*K)+Y+1th row of sub-pixels to the (X*(b+1) / 2*K)-Yth row of sub-pixels. For example, when X=18, K=3, Y=2, the display area includes five display sub-areas. The first display sub-area includes: the first row of sub-pixels to the fourth row of sub-pixels; the second display sub-area includes: the fifth row of sub-pixels to the eighth row of sub-pixels; the third display sub-area includes: the ninth row of sub-pixels to the tenth row of sub-pixels; the fourth display sub-area includes: the eleventh row of sub-pixels to the fourteenth row of sub-pixels; and the fifth display sub-area includes: the fifteenth row of sub-pixels to the eighteenth row of sub-pixels.

[0140] In an exemplary implementation, such as Figure 8 As shown, when M = 2K-1, the second initial signal line INIT2 of the odd-numbered display sub-area is electrically connected to the first power supply line SL-1, and the second initial signal line INIT2 of the even-numbered display sub-area is electrically connected to the second power supply line SL-1; the voltage value of the signal of the first power supply line SL-1 is less than the voltage value of the signal of the second power supply line SL-1.

[0141] Figure 8 The provided display substrate can compensate for the reset degree of the fourth node of the sub-pixel in the even-numbered display sub-region by differentiating the voltage values ​​of the signal of the first power supply line SL-1 and the signal of the second power supply line SL-2. This makes the signal of the fourth node of the sub-pixel in the even-numbered display sub-region after resetting the fourth node the same as the signal of the fourth node of the sub-pixel in the odd-numbered display sub-region after resetting the fourth node, thereby eliminating dark bands at the split screen, avoiding poor split screen performance, and improving the display effect of the display substrate.

[0142] In an exemplary implementation, such as Figures 6 to 8 As shown, there are two power supply lines in any of the first power supply line SL-1 to the Nth power supply line SL-N, and they are located on opposite sides of the display area.

[0143] In an exemplary implementation, such as Figures 6 to 8 As shown, the display area is also provided with multiple first initial connection lines (not shown in the figure), multiple second initial connection lines CL2 and multiple third initial connection lines (not shown in the figure); any one of the first initial connection lines, second initial connection lines CL2 and third initial connection lines extends at least partially along the second direction Y.

[0144] In an exemplary embodiment, the first initial connection line spacing is set in different display sub-areas, the second initial connection line CL2 spacing is set in different display sub-areas, and the third initial connection line spacing is set in different display sub-areas.

[0145] In an exemplary embodiment, the first initial connection line and the first initial signal line located in the same display sub-region are arranged in a mesh structure and are electrically connected to each other. The mesh structure of the first initial connection line and the first initial signal line located in the same display sub-region can ensure the display uniformity of the display substrate.

[0146] In an exemplary embodiment, the second initial connection line and the second initial signal line located in the same display sub-region are arranged in a mesh structure and are electrically connected to each other. This mesh structure ensures the display uniformity of the display substrate.

[0147] In an exemplary embodiment, the third initial connection line and the third initial signal line located in the same display sub-region are arranged in a mesh structure and are electrically connected to each other. The mesh structure of the second initial connection line and the second initial signal line located in the same display sub-region can ensure the display uniformity of the display substrate.

[0148] Figure 11 for Figure 7 A schematic diagram showing the connection between the first display sub-area and the first power supply line in the provided display substrate. Figure 12 for Figure 7 A schematic diagram showing the connection between the second display sub-area and the second power supply line in the provided display substrate. Figure 13 for Figure 7 A schematic diagram showing the connection between the third display sub-area and the third power supply line in the provided display substrate. Figure 14 for Figure 8 A schematic diagram showing the connection between the odd-numbered display sub-area and the first power supply line in the provided display substrate. Figure 15 for Figure 8 A schematic diagram showing the connection between the even-numbered display sub-area and the second power supply line in the provided display substrate. (See diagram below.) Figures 11 to 15 As shown, the non-display area is further provided with: a first initial power supply line INITL1 and a third initial power supply line INITL3 extending at least partially along the second direction Y. The first initial power supply line INITL1 is connected to the first initial signal line INIT1 located in all sub-display areas, and the third initial power supply line INITL3 is connected to the third initial signal line INIT3 located in all sub-display areas.

[0149] In an exemplary embodiment, any one of the power supply lines from the first power supply line to the Nth power supply line, the first initial power supply line, and the third initial power supply line can be located in the border area and the binding area.

[0150] In an exemplary embodiment, there are two first initial power supply lines INITL1, which are located on opposite sides of the display area.

[0151] In an exemplary embodiment, there are two third initial power supply lines INITL3, which are located on opposite sides of the display area.

[0152] In an exemplary implementation, such as Figures 11 to 15 As shown, the first power supply lines SL-1 to Nth power supply lines SL-N, the first initial power supply line INITL1, and the third initial power supply line INITL3, located on the same side of the display area, are arranged along the first direction X. The order in which the first power supply lines SL-1 to Nth power supply lines SL-N, the first initial power supply line INITL1, and the third initial power supply line INITL3 are arranged can be arbitrary, and this disclosure does not impose any limitation on this.

[0153] In an exemplary embodiment, the display substrate may include: a substrate and a driving structure layer disposed on the substrate. The driving structure layer includes: a pixel driving circuit, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line to an Nth power supply line, a first initial power supply line, and a third initial power supply line.

[0154] In an exemplary embodiment, any one of the first power supply lines to the Nth power supply line is disposed on the same layer as the first initial power supply line and the third initial power supply line, and is located on the side of any one of the first initial signal line, the second initial signal line and the third initial signal line away from the substrate.

[0155] When the display substrate is an LTPO display substrate, the driving structure layer may include: a light-shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, a seventh insulating layer, and a planarization layer, which are sequentially stacked on the substrate.

[0156] The pixel driving circuit includes at least one low-temperature polysilicon transistor (LTP) and at least one metal-oxide-semiconductor (MODS). The signal line connected to the control electrode of the LTP is called the first gate line. Figure 3A For example, the first gate line may include a first scan line, a first reset line, a second reset line, and a light-emitting line. The signal line connected to the control electrode of the metal-oxide-semiconductor transistor is called the second gate line. Figure 3A For example, the second gate line may include a second scan line. The first gate line can be a single-layer structure, and the second gate line can be a double-layer structure.

[0157] In an exemplary embodiment, any one of the first initial signal line, the second initial signal line, and the third initial signal line may be located in any one of the light-shielding layer, the third conductive layer, or the fourth conductive layer.

[0158] In an exemplary embodiment, the active layer of the low-temperature polysilicon transistor may be located in the first semiconductor layer.

[0159] In an exemplary embodiment, the first gate line and one of the plates of the capacitor may be located in the first conductive layer.

[0160] In an exemplary embodiment, the other plate of the capacitor and one of the film layers of the second gate line may be located in the second conductive layer.

[0161] In an exemplary embodiment, another film layer of the second gate line may be located in the third conductive layer.

[0162] In an exemplary embodiment, the first and second terminals of all transistors in the pixel driving circuit can be located in the fourth conductive layer.

[0163] In an exemplary embodiment, any one of the data signal line, the first power line, the first initial connection line, the second initial connection line, and the third initial connection line may be located in at least one film layer of the fourth conductive layer and the fifth conductive layer.

[0164] In some examples, the substrate can be a rigid substrate, such as a glass substrate. However, this embodiment is not limited to this. For example, the substrate can be a flexible substrate, such as one made of an insulating material like resin. Additionally, the substrate can be a single-layer or multi-layer structure. When the substrate is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be disposed in single or multiple layers between the layers.

[0165] In an exemplary implementation, such as Figures 11 to 15 As shown, any one of the power supply lines from the first power supply line to the Nth power supply line can be located in the fifth conductive layer along with the first initial power supply line and the third initial power supply line.

[0166] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer, an encapsulation structure layer, and an encapsulation cover. In some possible implementations, the display substrate may include other film layers, such as spacer pillars, touch structure layers, etc., which are not limited herein.

[0167] In an exemplary embodiment, the light-emitting structure layer may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a second electrode. The anode layer may include a first electrode of a light-emitting element, and the anode may be disposed on a planarization layer of the driving structure layer, electrically connected to a transistor of a pixel driving circuit through a via formed in the planarization layer; the pixel definition layer is disposed on the anode layer and the planarization layer, and has a pixel opening that exposes at least a portion of the surface of the first electrode; the organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the first electrode; the second electrode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer; the organic light-emitting layer emits light of a corresponding color under the drive of the first and second electrodes.

[0168] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0169] In an exemplary embodiment, the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the hole blocking layers may be a common layer connected together. However, this embodiment is not limited in this respect.

[0170] In an exemplary embodiment, Figure 16 This is a schematic diagram of a display substrate provided in an exemplary embodiment. The non-display area is further provided with at least one second signal line S2; the second signal line S2 is electrically connected to two first initial power supply lines INITL1 located on both sides of the display area and a first initial connection line CL1 located in the display area, or to two third initial power supply lines INITL3 located on both sides of the display area and a third initial connection line CL3 located in the display area. The second signal line S2 is located in the bonding area B1.

[0171] like Figure 3BAs shown, the signal of the third initial signal line INIT3 is written to the third node N3 before the light-emitting stage. After the light-emitting stage, the third node N3 rapidly pulls up the potential of the fourth node N4, causing the light-emitting device to emit light. Therefore, when the display substrate displays a low grayscale and low brightness image, the voltage value of the third initial signal line INIT3 directly affects the lighting speed of the light-emitting device. The higher the voltage value of the third initial signal line INIT3, the faster the light-emitting device lights up; conversely, the lower the voltage value of the third initial signal line INIT3, the slower the light-emitting device lights up. Therefore, if the third initial signal line INIT3 fluctuates, it can easily cause deviations in the low grayscale brightness. For a display substrate without a second signal line S2, the third initial signal of the third initial signal line is input to the display area from both sides of the display substrate. Due to the coupling effects of other signals within the display substrate, the reset degree of the third node N3 of the sub-pixels located in the middle and on both sides of the display substrate may differ. The reset degree of the third node N3 of the sub-pixels in the middle of the display substrate is smaller, while the reset degree of the third node N3 of the sub-pixels on both sides of the display substrate is larger. This results in a problem where the display substrate is brighter in the middle and darker on the sides, leading to poor display quality. The inclusion of the second signal line S2 in this disclosure allows the third initial signal to be input not only from both sides of the display substrate but also output from the middle of the display substrate. This improves the load capacity and stability of the third initial power supply line, reduces the difference in the reset degree of the third nodes of the sub-pixels located on both sides and in the middle of the display substrate, eliminates the brightness difference problem between the sides and the middle of the display substrate, and improves the display effect of the display substrate.

[0172] In an exemplary embodiment, Figure 17 A schematic diagram of the binding area provided in an exemplary embodiment, such as Figure 17 As shown, the non-display area also includes a test pin group 51 located on the side of the bonding area away from the display area.

[0173] like Figure 17 As shown, the second signal line may include: a first connecting segment L1, a second connecting segment L2, a third connecting segment L3, a fourth connecting segment L4, a fifth connecting segment L5, a sixth connecting segment L6, and a seventh connecting segment L7. Any one of the first connecting segments L1, the third connecting segment L3, and the seventh connecting segment L7 extends at least partially along a first direction X, and any one of the second connecting segments L2, the fourth connecting segment L4, the fifth connecting segment L5, and the sixth connecting segment L6 extends at least partially along a second direction Y. Figure 18 The following explanation is based on the example of the second signal line being electrically connected to two third initial power supply lines INITL3 located on both sides of the display area and the third initial connection line CL3 located in the display area.

[0174] With the second signal line electrically connected to the two first initial power supply lines located on both sides of the display area and the first initial connection line located in the display area, one end of the first connection segment L1 is electrically connected to one end of one of the first initial power supply lines, the other end of the first connection segment L1 is electrically connected to the middle section of the second connection segment L2, one end of the second connection segment L2 is electrically connected to one end of the third connection segment L3, the other end of the third connection segment L3 is electrically connected to one end of the fifth connection segment L5, one end of the fourth connection segment L4 is electrically connected to the middle section of the third connection segment L3, the other end of the fourth connection segment L4 is electrically connected to the first initial connection line, the other end of the fifth connection segment L5 is electrically connected to one end of the sixth connection segment L6, the other end of the sixth connection segment L6 is electrically connected to the test pin group, one end of the seventh connection segment L7 is electrically connected to the middle section of the fifth connection segment L5, and the other end of the seventh connection segment L7 is electrically connected to another first initial power supply line.

[0175] In an exemplary implementation, such as Figure 17 As shown, with the second signal line electrically connected to the two third initial power supply lines located on both sides of the display area AA and the third initial connection line INITL3 located in the display area, one end of the first connection segment L1 is electrically connected to one end of one of the third initial power supply lines, the other end of the first connection segment L1 is electrically connected to the middle section of the second connection segment L2, one end of the second connection segment L2 is electrically connected to one end of the third connection segment L3, the other end of the third connection segment L3 is electrically connected to one end of the fifth connection segment L5, one end of the fourth connection segment L4 is electrically connected to the middle section of the third connection segment L3, the other end of the fourth connection segment L4 is electrically connected to the third initial connection line (not shown in the figure), the other end of the fifth connection segment L5 is electrically connected to one end of the sixth connection segment L6, the other end of the sixth connection segment L6 is electrically connected to the test pin group, one end of the seventh connection segment L7 is electrically connected to the middle section of the fifth connection segment L5, and the other end of the seventh connection segment L7 is electrically connected to another third initial power supply line INITL3.

[0176] In an exemplary embodiment, the non-display area further includes: a first power line PL1 and a second power line PL2. The first power line is electrically connected to the pixel driving circuit and is configured to provide a power signal to the pixel driving circuit. The second power line is electrically connected to the second electrode of the light-emitting device and is configured to provide a power signal to the second electrode of the light-emitting device.

[0177] In an exemplary implementation, such as Figure 17 As shown, the bonding area B1 may include: a first fan-out area B111, a bending area B112, a second fan-out area B113, a first circuit area B114, a third fan-out area B115, a driver chip area B116, and a bonding pin area B10, arranged sequentially along the direction away from the display area.

[0178] In an exemplary implementation, such as Figure 17 As shown, the first fan-out area B111 can be connected to the display area AA. The bending area B112 connects the first fan-out area B111 and the second fan-out area B112, and can be configured such that the bonding area B1 bends to the back of the display area AA. The first circuit area B114 can include at least a test circuit group 42. The test circuit group can include multiple test circuits, which can be configured to be electrically connected to multiple data lines of the display area, providing test data signals to the multiple data lines of the display area. The driver chip area B116 includes a driver chip pin group 61. The driver chip pin group can be electrically connected to multiple data lines and is configured to be bonded to at least one driver chip. For example, each driver chip pin group can be configured to be bonded to one driver chip. Figure 17 The diagram omits the fan-out routing within the first fan-out area B111, the second fan-out area B113, and the third fan-out area B115. Figure 17 The diagram illustrates several connection lines between the test circuit group and the bonding pin group, and between the bonding pin group and the test pin group. This embodiment does not limit the number of these connection lines.

[0179] In an exemplary embodiment, the first fan-out area B111 further includes: multiple sets of first fan-out traces. These multiple sets of first fan-out traces can be arranged along a first direction X. Each set of first fan-out traces may include multiple first fan-out traces, and these first fan-out traces may include: data extensions of multiple data lines within the display area to the binding area.

[0180] In an exemplary implementation, such as Figure 17 As shown, the bonding area B1 may include multiple first power lines PL1 and multiple second power lines PL2. The bonding pin group 41 within the bonding pin area B10 can be electrically connected to two second power lines PL2 and one first power line PL1. The first power line PL1 can be located between the two second power lines PL2 in the first direction X. The first power line PL1 can be electrically connected to the second power pin of the bonding pin group within the bonding pin area B10, and the second power lines PL2 can be electrically connected to the first power pin within the bonding pin group.

[0181] In some examples, the number of driver chip pin groups in driver chip area B116 may be the same as the number of bonding pin groups in bonding pin area B10. Multiple driver chip pin groups and multiple bonding pin groups can be connected in a one-to-one correspondence. Pins within a driver chip pin group can be electrically connected to pins within a corresponding bonding pin group via pin connection lines 600. Pin connection lines 600 can extend generally along the second direction Y and can be arranged sequentially along the first direction X. For example, driver chip pin group 61 is connected to bonding pin group 41. This embodiment is not limited in this respect.

[0182] In an exemplary embodiment, the first power line PL1 and the second power line PL2 may be located in the bonding area B1 and the border area B2.

[0183] Figure 18 for Figure 17 A magnified view of region A1 in the middle. Figure 19 for Figure 17 A magnified view of region A2 in the middle. Figure 20 for Figure 17 A magnified view of region A3 in the middle. In an exemplary embodiment, as shown... Figures 17 to 20 As shown, the first connecting segment L1, the second connecting segment L2, the third connecting segment L3, the fifth connecting segment L5, the sixth connecting segment L6, and the seventh connecting segment L7 are all located on the side of the second fan-out area B113 away from the display area AA. The first connecting segment L1 and the seventh connecting segment L7 are located on the side of the third connecting segment L3 away from the display area, and are located in any one of the first circuit area B114, the third fan-out area B115, and the driver chip area B116. Any one of the second connecting segments L2 and the fifth connecting segment L5 is at least partially located in the first circuit area B114, the third fan-out area B115, the driver chip area B116, and the bonding pin area B10. The sixth connecting segment L6 is located in the bonding pin area B10. The fourth connecting segment L4 is located on the side of the first circuit area B114 closer to the display area AA, and is at least partially located in the first fan-out area B111, the bending area B112, and the second fan-out area B113.

[0184] In an exemplary implementation, such as Figures 18 to 20 As shown, the orthographic projections of the first connecting segment L1 and the seventh connecting segment L7 on the substrate at least partially overlap with the orthographic projections of the first power line PL1 and the second power line PL2 on the substrate, respectively; the orthographic projection of the fourth connecting segment L4 on the substrate at least partially overlaps with the orthographic projection of the first power line PL1 on the substrate.

[0185] In an exemplary implementation, such as Figure 20 As shown, the fourth connecting segment L4 may include: a first sub-segment L41, a second sub-segment L42, and a third sub-segment L43 arranged sequentially along the direction close to the display area AA. The first sub-segment L41 is electrically connected to the third connecting segment L3 and the second sub-segment L42, respectively, and the third sub-segment L43 is electrically connected to the second sub-segment L42. The first sub-segment L41 is at least partially located in the second fan-out area B113, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first power line PL1 on the substrate. The second sub-segment L42 is at least partially located in the bending area B112, and the third sub-segment L43 is at least partially located in the first fan-out area B111.

[0186] In some examples, the first power line PL1 and the second power line PL2 can be single-layer traces, for example, located on the fourth or fifth conductive layer; or, the first power line PL1 and the second power line PL2 can be double-layer traces, for example, a stacked structure of the fourth and fifth conductive layers. This embodiment is not limited in this respect. Figure 18 and Figure 19 The following explanation uses a stacked trace structure with the first power line PL1 and the second power line PL2 as the fourth and fifth conductive layers as an example.

[0187] In an exemplary implementation, such as Figure 18 and Figure 19 As shown, the first connection segment L1 and the seventh connection segment L7 are located on the side of the first power line PL1 or the second power line PL2 near the substrate. Exemplarily, the first connection segment L1 and the seventh connection segment L7 may be located in at least one of the first conductive layer, the second conductive layer, and the third conductive layer.

[0188] In an exemplary implementation, such as Figure 18 and Figure 19 As shown, the second connecting segment L2, the third connecting segment L3, the fifth connecting segment L5, and the sixth connecting segment L6 are located on the side of the first connecting segment L1 away from the substrate, and the sixth connecting segment L6 is located on the side of the fifth connecting segment L5 away from the substrate. The second connecting segment L2, the third connecting segment L3, and the fifth connecting segment L5 can be located in the fourth conductive layer, and the sixth connecting segment can be located in the fifth conductive layer.

[0189] In an exemplary implementation, such as Figure 20 As shown, the first segment L41 is located on the side of the third connecting segment L3 closer to the substrate, the second segment L42 is located on the side of the first segment away from the substrate, and the third segment L43 is located on the side of the second segment closer to the substrate. Exemplarily, the first segment L41 may be located in at least one of the first conductive layer and the second conductive layer, the second segment L42 may be located in at least one of the fourth conductive layer and the fifth conductive layer, and the third segment L43 may be located in at least one of the first conductive layer and the second conductive layer.

[0190] In an exemplary implementation, such as Figure 20 As shown, the display area is also provided with signal connection lines CL. The signal connection lines CL are electrically connected to the initial connection lines of the third sub-segment L43 and the second signal line, respectively. The signal connection lines CL are located on the side of the second sub-segment L42 closest to the substrate. The signal connection lines CL can be located in either the first conductive layer or the second conductive layer.

[0191] In an exemplary implementation, such as Figure 20As shown, the first power line PL1 located in the bonding area B1 has an opening V on the side near the display area, and the second sub-segment L42 extends to the opening V of the first power line PL1.

[0192] In an exemplary embodiment, Figure 21 This is a partial schematic diagram of the binding area. (See attached diagram.) Figure 21 As shown, the bonding area also includes: the first connecting line H-1 to the N+2 connecting line H-(N+2), the nth connecting line is electrically connected to the nth power supply line, the N+1th power supply line is electrically connected to the first initial power supply line, and the N+2th power supply line is electrically connected to the third initial power supply line. The driver chip area includes: the first pin P-1 to the P-(N+2) pins, the i-th connecting line is electrically connected to the i-th pin Pi, where i is a positive integer greater than or equal to 1 and less than or equal to N+2. Figure 21 This explanation uses N=2 as an example.

[0193] In an exemplary embodiment, the first connection line to the N+2th connection line may be located in the fifth conductive layer, and the first pin P-1 to the P-(N+2)th pin may be located in the fourth conductive layer.

[0194] In an exemplary implementation, such as Figure 21 As shown, the bonding area also features virtual interconnect lines (DUL). The DUL ensures the uniformity of etching on the display substrate.

[0195] In an exemplary embodiment, the virtual connection line (DUL) can be set on the same layer as the first to N+2th connection lines.

[0196] In an exemplary embodiment, the resistance of the signal line mentioned in this disclosure can be achieved by adjusting the width of the signal line.

[0197] This disclosure also provides a display device, including a display substrate.

[0198] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0199] In exemplary embodiments, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application.

[0200] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0201] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0202] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate having a display area and a non-display area, characterized in that, The display area is provided with sub-pixels arranged in an array, multiple first signal lines, multiple first initial signal lines, and multiple second initial signal lines. The non-display area is provided with a first power supply line to an Nth power supply line. The first signal lines extend at least partially along a first direction, the first initial signal lines and the second initial signal lines extend along the first direction, and any one of the first power supply lines to the Nth power supply line extends at least partially along a second direction. The first direction and the second direction intersect. The first signal line is electrically connected to the sub-pixel and is configured to provide an initial signal to the sub-pixel; The display area is divided into M display sub-areas arranged along the second direction. First signal lines within the same display sub-area are connected to the same power supply line, and first signal lines in at least two display sub-areas are connected to different power supply lines. M, N 2; When the first signal line is the second initial signal line, the second initial signal lines located in different display sub-areas are independent of each other, M=K or 2K-1, where K is the number of times the second initial signal line effectively initializes the first electrode of the light-emitting device within the target duration. The effective initialization refers to the second initial signal line adjusting the first electrode of the light-emitting device from the first signal to the second signal. The voltage value of the first signal is different from the voltage value of the second signal. The second signal is the signal transmitted by the second initial signal line. The target duration is equal to the duration of one display frame.

2. The display substrate according to claim 1, characterized in that, The sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to drive the light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The light-emitting device includes a first electrode. The first initial signal line is configured to provide an initial signal to one of the source and drain electrodes of the driving transistor. The second initial signal line is configured to provide an initial signal to the first electrode of the light-emitting device. The first signal line includes either the first initial signal line or the second initial signal line.

3. The display substrate according to claim 2, characterized in that, The display area is also provided with a plurality of third initial signal lines extending along the first direction, the third initial signal lines being configured to provide an initial signal to another electrode in the source and drain electrodes of the driving transistor; The first signal line includes any one of the first initial signal line, the second initial signal line, and the third initial signal line.

4. The display substrate according to claim 1, characterized in that, When M=K, the m-th display sub-region includes: sub-pixels in rows (m-1)*X / K+1 to rows m*X / K, 1 m M and X represent the total number of rows of sub-pixels included in the display area.

5. The display substrate according to claim 4, characterized in that, N=M, the second initial signal line of the nth display sub-area is electrically connected to the nth power supply line, 1 n N; The voltage values ​​of the signals from the first power supply line to the Nth power supply line are the same.

6. The display substrate according to claim 1, characterized in that, When M=2K-1, there is a blanking region between two adjacent display frames; the a-th sub-pixel group includes: sub-pixels from row (X*a / K)-Y+1 to row (X*a / K)+Y, where X is the total number of rows of sub-pixels included in the display area, and Y is the ratio of the duration in the blanking region to the duration of display of a row of sub-pixels. The first sub-pixel group to the (K-1)th sub-pixel group are located in different display sub-regions.

7. The display substrate according to claim 4, characterized in that, When M=2K-1, the second initial signal line of the odd-numbered display sub-area is electrically connected to the first power supply line, and the second initial signal line of the even-numbered display sub-area is electrically connected to the second power supply line. The voltage value of the signal on the first power supply line is less than the voltage value of the signal on the second power supply line.

8. The display substrate according to claim 3, characterized in that, The number of any one of the first to the Nth power supply lines is two, and they are located on opposite sides of the display area.

9. The display substrate according to claim 3, characterized in that, The display area is also provided with multiple first initial connection lines, multiple second initial connection lines, and multiple third initial connection lines; any one of the first initial connection lines, the second initial connection lines, and the third initial connection lines extends at least partially along the second direction; The first initial connection lines located in different display sub-areas are spaced apart, the second initial connection lines located in different display sub-areas are spaced apart, the third initial connection lines located in different display sub-areas are spaced apart, the first initial connection lines and the first initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other, the second initial connection lines and the second initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other, and the third initial connection lines and the third initial signal lines located in the same display sub-area form a mesh structure and are electrically connected to each other; The non-display area is further provided with: a first initial power supply line and a third initial power supply line extending at least partially along the second direction, wherein the first initial power supply line is connected to a first initial signal line located in all sub-display areas, and the third initial power supply line is connected to a third initial signal line located in all sub-display areas; The number of the first initial power supply lines is two, and they are respectively located on opposite sides of the display area. The number of the third initial power supply lines is two, and they are respectively located on opposite sides of the display area. The first power supply lines to the Nth power supply line, the first initial power supply line and the third initial power supply line located on the same side of the display area are arranged along the first direction.

10. The display substrate according to claim 9, characterized in that, include: A substrate and a driving structure layer disposed on the substrate, the driving structure layer comprising: a pixel driving circuit, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line to an Nth power supply line, a first initial power supply line, and a third initial power supply line; Any one of the first power supply lines to the Nth power supply line is disposed on the same layer as the first initial power supply line and the third initial power supply line, and is located on the side of any one of the first initial signal line, the second initial signal line and the third initial signal line away from the substrate.

11. The display substrate according to claim 10, characterized in that, The non-display area includes: a binding area located on one side of the display area and a border area located on the other side of the display area; the non-display area is also provided with at least one second signal line. The second signal line is electrically connected to two first initial power supply lines located on both sides of the display area and a first initial connection line located in the display area, or to two third initial power supply lines located on both sides of the display area and a third initial connection line located in the display area. Any one of the first power supply line to the Nth power supply line, the first initial power supply line and the third initial power supply line is located in the border area and the bonding area, and the second signal line is located in the bonding area.

12. The display substrate according to claim 11, characterized in that, The non-display area also includes a test pin group disposed on the side of the bonding area away from the display area; The second signal line includes: a first connecting segment, a second connecting segment, a third connecting segment, a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, and a seventh connecting segment, wherein any one of the first connecting segment, the third connecting segment, and the seventh connecting segment extends at least partially along the first direction, and any one of the second connecting segment, the fourth connecting segment, the fifth connecting segment, and the sixth connecting segment extends at least partially along the second direction; With the second signal line electrically connected to two first initial power supply lines located on both sides of the display area and a first initial connection line located in the display area, one end of the first connection segment is electrically connected to one end of one of the first initial power supply lines, the other end of the first connection segment is electrically connected to the middle section of the second connection segment, one end of the second connection segment is electrically connected to one end of the third connection segment, the other end of the third connection segment is electrically connected to one end of the fifth connection segment, one end of the fourth connection segment is electrically connected to the middle section of the third connection segment, the other end of the fourth connection segment is electrically connected to the first initial connection line, the other end of the fifth connection segment is electrically connected to one end of the sixth connection segment, the other end of the sixth connection segment is electrically connected to the test pin group, one end of the seventh connection segment is electrically connected to the middle section of the fifth connection segment, and the other end of the seventh connection segment is electrically connected to another first initial power supply line. With the second signal line electrically connected to two third initial power supply lines located on both sides of the display area and a third initial connection line located in the display area, one end of the first connection segment is electrically connected to one end of one of the third initial power supply lines, the other end of the first connection segment is electrically connected to the middle section of the second connection segment, one end of the second connection segment is electrically connected to one end of the third connection segment, the other end of the third connection segment is electrically connected to one end of the fifth connection segment, one end of the fourth connection segment is electrically connected to the middle section of the third connection segment, the other end of the fourth connection segment is electrically connected to the third initial connection line, the other end of the fifth connection segment is electrically connected to one end of the sixth connection segment, the other end of the sixth connection segment is electrically connected to the test pin group, one end of the seventh connection segment is electrically connected to the middle section of the fifth connection segment, and the other end of the seventh connection segment is electrically connected to another third initial power supply line.

13. The display substrate according to claim 12, characterized in that, The non-display area further includes: a first power line and a second power line, wherein the first power line is electrically connected to the pixel driving circuit and configured to provide a power signal to the pixel driving circuit, and the second power line is electrically connected to the second electrode of the light-emitting device and configured to provide a power signal to the second electrode of the light-emitting device; the bonding area includes: a first fan-out area, a bending area, a second fan-out area, a first circuit area, a third fan-out area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area; the first power line and the second power line are located in the bonding area and the border area; The first connecting segment, the second connecting segment, the third connecting segment, the fifth connecting segment, the sixth connecting segment, and the seventh connecting segment are all located on the side of the second fan-out area away from the display area. The first connecting segment and the seventh connecting segment are located on the side of the third connecting segment away from the display area and are located in any one of the first circuit area, the third fan-out area, and the driver chip area. Any one of the second connecting segment and the fifth connecting segment is at least partially located in the first circuit area, the third fan-out area, the driver chip area, and the bonding pin area. The sixth connecting segment is located in the bonding pin area. The fourth connecting segment is located on the side of the first circuit area closer to the display area and is at least partially located in the first fan-out area, the bending area, and the second fan-out area. The orthographic projections of the first connecting segment and the seventh connecting segment on the substrate at least partially overlap with the orthographic projections of the first power line and the second power line on the substrate, respectively; the orthographic projection of the fourth connecting segment on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

14. The display substrate according to claim 13, characterized in that, The fourth connection segment includes: a first sub-segment, a second sub-segment, and a third sub-segment arranged sequentially along the direction close to the display area, and a third signal line located in the display area; The first sub-segment is electrically connected to both the third connecting segment and the second sub-segment, and the third sub-segment is electrically connected to the second sub-segment. The first segment is at least partially located in the second fan-out region, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate. The second segment is at least partially located in the bending region, and the third segment is at least partially located in the first fan-out region.

15. The display substrate according to claim 14, characterized in that, The first connecting segment and the seventh connecting segment are located on the side of the first power line or the second power line closer to the substrate. The second connecting segment, the third connecting segment, the fifth connecting segment, and the sixth connecting segment are located on the side of the first connecting segment away from the substrate. The first sub-segment is located on the side of the third connecting segment closer to the substrate. The second sub-segment is located on the side of the first sub-segment away from the substrate. The third sub-segment is located on the side of the second sub-segment closer to the substrate. The sixth connecting segment is located on the side of the fifth connecting segment away from the substrate.

16. The display substrate according to claim 15, characterized in that, The display area is also provided with signal connection lines, which are electrically connected to the initial connection lines connected to the third sub-segment and the second signal line, respectively. The signal connection lines are single-layer structures and are located on the side of the second sub-segment closer to the substrate.

17. The display substrate according to claim 14, characterized in that, An opening is provided on the side of the first power line located in the bonding area near the display area, and the second segment extends to the opening of the first power line.

18. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 17.

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