Display substrate, manufacturing method thereof and display device

Abstract

The application provides a display substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The display substrate comprises a plurality of pixel regions on a substrate, wherein the pixel region comprises a light-emitting region and a non-light-emitting region; a driving circuit is arranged in the pixel region; the driving circuit comprises a storage capacitor and a transistor; the transistor comprises a driving transistor; the transistor comprises an active layer, a gate insulating layer, a gate metal layer, a first insulating layer and a source-drain metal layer which are stacked from the side away from the substrate; the first electrode of the storage capacitor is arranged in the same layer as the active layer, and the second electrode of the storage capacitor is arranged on the side of the first electrode close to the substrate; the gate of the driving transistor is connected with the first electrode through a connecting electrode penetrating through the first insulating layer; and in the extension direction of the gate of the driving transistor, the connecting electrode is directly in contact with the first electrode. The technical scheme can improve the aperture ratio of the display product.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display substrate, its manufacturing method, and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display devices have been listed as a promising next-generation display technology due to their advantages such as being thin, light, having a wide viewing angle, being actively emitting light, having continuously adjustable emission colors, having low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple manufacturing process, high luminous efficiency, and being flexible in display.

[0003] In large-size OLED display products, the wiring is dense and the thin-film transistors occupy a large space, which affects the aperture ratio of the display products. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display substrate and its manufacturing method, and a display device, which can improve the aperture ratio of display products.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide the following technical solutions:

[0006] On one hand, a display substrate is provided, including a plurality of pixel regions located on a substrate, the pixel regions including light-emitting regions and non-light-emitting regions; a driving circuit is disposed in the pixel regions; the driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors are located in the non-light-emitting regions; for each pixel region, the plurality of transistors include: a switching transistor, a driving transistor and a sensing transistor;

[0007] The transistor includes an active layer, a gate insulating layer, a gate metal layer, a first insulating layer, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate.

[0008] The gate of the driving transistor is connected to the first electrode through a connection electrode that penetrates the first insulating layer; the connection electrode is in direct contact with the first electrode in the extending direction of the gate of the driving transistor.

[0009] In some embodiments, in the extension direction of the gate of the driving transistor, the orthographic projection of the connection portion of the connecting electrode and the first electrode on the substrate is greater than the orthographic projection of the connection portion of the gate of the driving transistor and the first electrode on the substrate.

[0010] In some embodiments, the connection electrode and the orthographic projection of the gate of the driving transistor onto the substrate do not overlap in the extension direction of the gate of the driving transistor.

[0011] In some embodiments, the pixel region includes a first region located on the side of the first via near the gate of the driving transistor and a second region located on the side of the first via away from the gate of the driving transistor, wherein the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the gate on the substrate.

[0012] In some embodiments, the display substrate further includes a light-shielding layer located on the side of the first electrode near the substrate and including a cutout portion, wherein the orthographic projection of the cutout portion on the substrate overlaps with the orthographic projection of the second region on the substrate.

[0013] In some embodiments, the orthographic projection of the cutout portion on the substrate covers the orthographic projection of the first via on the substrate.

[0014] In some embodiments, the connection electrode includes a first connection portion located within the first via, and the side surface of the gate near the first via is in direct contact with the side surface of the first connection portion near the gate.

[0015] In some embodiments, the display substrate further includes a second via penetrating the first insulating layer, wherein the area of ​​the orthographic projection of the second via on the substrate is greater than the area of ​​the orthographic projection of the first via on the substrate.

[0016] In some embodiments, the orthogonal projection of the gate on the substrate is smaller than the orthogonal projection of the gate insulating layer on the substrate.

[0017] In some embodiments, the display substrate further includes:

[0018] A transparent conductive layer located on the side of the light-shielding layer near the substrate forms the second electrode of the storage capacitor.

[0019] In some embodiments, the light-shielding layer and the transparent conductive layer are disposed adjacent to each other and in direct contact.

[0020] In some embodiments, the connection electrodes are fabricated using source / drain metal layers.

[0021] In some embodiments, the display substrate further includes:

[0022] Passivation layer on the side away from the substrate;

[0023] A color filter unit located on the side of the passivation layer away from the substrate.

[0024] Embodiments of the present invention also provide a display device, including a display substrate as described above.

[0025] Embodiments of the present invention also provide a method for manufacturing a display substrate, the display substrate including a plurality of pixel regions located on a substrate, the pixel regions including light-emitting regions and non-light-emitting regions; a driving circuit is disposed in the pixel regions; the driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors are located in the non-light-emitting regions; for each pixel region, the plurality of transistors include: a switching transistor, a driving transistor and a sensing transistor;

[0026] The transistor includes an active layer, a gate insulating layer, a gate metal layer, a first insulating layer, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate.

[0027] The manufacturing method includes:

[0028] A connection electrode is formed to connect the gate of the driving transistor and the first electrode of the storage capacitor. A first insulating layer is spaced between the connection electrode and the first electrode. The connection electrode is connected to the first electrode through a first via penetrating the first insulating layer. In the extension direction of the gate of the driving transistor, the connection electrode is in direct contact with the first electrode.

[0029] A light-shielding layer is formed in the non-light-emitting area. The light-shielding layer is located on the side of the first electrode close to the substrate. The light-shielding layer includes a cutout portion. The orthographic projection of the cutout portion on the substrate does not overlap with the orthographic projection of the gate on the substrate.

[0030] The embodiments of the present invention have the following beneficial effects:

[0031] In the above scheme, the connecting electrode is in direct contact with the first electrode in the extension direction of the gate of the driving transistor. In this way, the gate does not need to extend to the first via, which can reduce the area occupied by the gate of the driving transistor. Since the gate is opaque, the area of ​​the opaque part of the pixel area can be reduced, and the part of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product. Attached Figure Description

[0032] Figure 1 This is a planar schematic diagram of the existing pixel area;

[0033] Figure 2 for Figure 1 Schematic diagram of the cross section in the BB direction;

[0034] Figure 3 and Figure 6 This is a planar schematic diagram of the pixel region according to an embodiment of the present invention;

[0035] Figure 4 and Figure 5 for Figure 3 Schematic diagram of the cross section in the BB direction;

[0036] Figure 7 and Figure 8 for Figure 6 Schematic diagram of the cross section in the DD direction;

[0037] Figures 9-15 This is a schematic diagram illustrating the process of fabricating a display substrate according to an embodiment of the present invention.

[0038] Figure Labels

[0039] 01 Substrate

[0040] 02 Transparent conductive layer

[0041] 03 Light-shielding layer

[0042] 04 Buffer Layer

[0043] 05 Active Layer Materials

[0044] 06 First Insulation Layer

[0045] 07 Passivation layer

[0046] 08 Organic Insulation Layer

[0047] 09 Gate insulation layer

[0048] 10 gate

[0049] 11 Connecting electrodes

[0050] 12 Source / Drain Metal Layers

[0051] 21 First Through Hole

[0052] 22. Openwork section

[0053] 23 Second via

[0054] 24 Source Pole

[0055] 25 Drain

[0056] 111 First connecting part Detailed Implementation

[0057] To make the technical problems, technical solutions and advantages of the embodiments of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0058] In related technologies, the display substrate includes multiple pixel regions located on a substrate, such as... Figure 1 and Figure 2 As shown, the pixel region includes a light-emitting region A and a non-light-emitting region G. A driving circuit is disposed in the pixel region. The driving circuit includes a storage capacitor and multiple transistors. The multiple transistors are located in the non-light-emitting region G. For each pixel region, the multiple transistors include a switching transistor, a driving transistor, and a sensing transistor. The transistors include an active layer, a gate insulating layer 09, a gate metal layer, a first insulating layer 06, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer and is made of active layer material 05. The second electrode of the storage capacitor is made of transparent conductive layer 02. The gate 10 of the driving transistor is connected to the first electrode of the storage capacitor through a connection electrode 11 made of the source / drain metal layer. The connection electrode 11 is located in a via penetrating the first insulating layer 06, and the gate 10 also extends to the via. Figure 1 As shown in the dashed box (C), the area of ​​the non-light-emitting region G gate 10 is relatively large. Since the gate is opaque, the area of ​​the opaque part of the non-light-emitting region G is relatively large, resulting in a low aperture ratio of the display product.

[0059] The embodiments of the present invention provide a display substrate and a method for manufacturing the same, as well as a display device, which can improve the aperture ratio of display products.

[0060] Embodiments of the present invention provide a display substrate, such as... Figures 3-8 As shown, the image includes multiple pixel regions located on a substrate 01, each pixel region including a light-emitting region A and a non-light-emitting region; a driving circuit is disposed in each pixel region; the driving circuit includes a storage capacitor and multiple transistors; the multiple transistors are located in the non-light-emitting region; for each pixel region, the multiple transistors include a switching transistor, a driving transistor, and a sensing transistor;

[0061] The transistor includes an active layer, a gate insulating layer 09, a gate metal layer, a first insulating layer 06, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate 01.

[0062] The gate 10 of the driving transistor is connected to the first electrode through a connection electrode 11 penetrating the first via 21 of the first insulating layer 06; in the extending direction of the gate 10 of the driving transistor (i.e. Figure 3 In the x-direction shown, the connecting electrode 11 is in direct contact with the first electrode.

[0063] In this embodiment, the connecting electrode is in direct contact with the first electrode in the extension direction of the gate of the driving transistor. This way, the gate does not need to extend to the first via, which can reduce the area occupied by the gate of the driving transistor. Since the gate is opaque, the area of ​​the opaque part of the pixel area can be reduced, and the part of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0064] In some embodiments, in the extending direction of the gate 10 of the driving transistor, the orthographic projection of the connection portion of the connecting electrode 11 and the first electrode on the substrate 01 is greater than the orthographic projection of the connection portion of the gate 10 of the driving transistor and the first electrode on the substrate 01. This can reduce the area occupied by the gate of the driving transistor. Since the gate is opaque, the area of ​​the opaque portion of the pixel area can be reduced, and the portion of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0065] In some embodiments, in the extending direction of the gate 10 of the driving transistor, such as Figures 6-8 As shown, the orthographic projections of the connecting electrode 11 and the gate 10 of the driving transistor on the substrate do not overlap, which reduces the area occupied by the gate 10 of the driving transistor. Since the gate 10 is opaque, the area of ​​the opaque part of the pixel area can be reduced, and the part of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0066] In some embodiments, such as Figure 3 and Figure 6 As shown, the pixel region includes a first region Q1 located on the side of the first via 21 near the gate of the driving transistor and a second region Q2 located on the side of the first via 21 away from the gate of the driving transistor. The orthographic projection of the second region Q2 on the substrate does not overlap with the orthographic projection of the gate 10 on the substrate.

[0067] In this way, the gate 10 is located only in the first region Q1, which can reduce the area occupied by the gate 10. Since the gate is opaque, the area of ​​the opaque part of the non-light-emitting region G can be reduced, and the part of the non-light-emitting region G without the gate can be made transparent, thereby improving the aperture ratio of the display product.

[0068] In some embodiments, such as Figure 5 and Figure 8 As shown, the display substrate further includes:

[0069] A light-shielding layer 03 is located in the non-light-emitting region G. The light-shielding layer 03 is located on the side of the first electrode close to the substrate 01. The light-shielding layer 03 includes a cutout portion 22. The orthographic projection of the cutout portion 22 on the substrate 01 overlaps with the orthographic projection of the second region Q2 on the substrate.

[0070] In this embodiment, the light-shielding layer 03 can prevent light from shining onto the active layer and affecting the performance of the thin-film transistor; such as Figure 6 As shown, a cutout portion 22 of the light-shielding layer is provided at the position corresponding to the second region Q2. In this way, there is no gate 10 or light-shielding layer 22 blocking the light at the position of the cutout portion 22, and the position of the cutout portion 22 is light-transmitting, which can improve the aperture ratio of the display product.

[0071] In some embodiments, in order to maximize the aperture ratio of the display product, the orthographic projection of the cutout portion 22 on the substrate coincides with the orthographic projection of the second region Q2 on the substrate. In this way, the second region Q2 does not have the gate 10 and the light-shielding layer 22 that block light, and the second region Q2 can be set as the aperture area of ​​the pixel area.

[0072] In some embodiments, such as Figure 7 As shown, the orthogonal projection of the cutout portion 22 on the substrate 01 can also cover the orthogonal projection of the first via 21 on the substrate 01. In this way, even if excessive etching occurs, the connection electrode 11 and the light-shielding layer 03 can be prevented from conducting. On the other hand, the aperture ratio of the display product can be improved.

[0073] Of course, such as Figure 4 and Figure 8 As shown, the light-shielding layer 03 may also exclude the perforated portion 22.

[0074] In a specific example, such as Figures 3-8 and Figure 15 As shown, the display substrate of this embodiment includes a substrate 01, which can be a flexible substrate or a rigid substrate. The rigid substrate can be a quartz substrate or a glass substrate. The display substrate also includes components located on the substrate 01:

[0075] The transparent conductive layer 02 can be made of ITO or IZO. Since the transparent conductive layer 02 can transmit light, it will not affect the aperture ratio of the display product. The transparent conductive layer 02 can be made into the second electrode of the storage capacitor.

[0076] The light-shielding layer 03 can prevent light from shining on the active layer and affecting the performance of the thin film transistor. The light-shielding layer 03 can be made of an opaque metal, such as Mo. The light-shielding layer 03 is disposed adjacent to the transparent conductive layer 02 and is in direct contact. It can be connected in parallel with the transparent conductive layer 02 to improve the conductivity of the second electrode.

[0077] The buffer layer 04 can be made of oxides, nitrides, or oxynitrogen compounds. Specifically, the material of the buffer layer 04 can be SiNx, SiOx, or Si(ON)x, and the buffer layer 04 can also be made of Al2O3. The buffer layer 04 can be a single-layer structure, or a two-layer or multi-layer structure, such as a two-layer structure composed of silicon nitride and silicon oxide.

[0078] The active layer and the first electrode are made of active layer material 05;

[0079] The gate insulating layer 09 can be made of oxide, nitride, or oxynitride compound. Specifically, the material of the gate insulating layer 09 can be SiNx, SiOx, or Si(ON)x, and Al2O3 can also be used. The gate insulating layer 09 can be a single-layer structure, or a two-layer or multi-layer structure, such as a two-layer structure composed of silicon nitride and silicon oxide.

[0080] Gate 10 is made of a gate metal layer, which can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The gate metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc.

[0081] The first insulating layer 06 can be made of oxide, nitride, or oxynitrogen compound. Specifically, the material of the first insulating layer 06 can be SiNx, SiOx, or Si(ON)x. The first insulating layer 06 can also be made of Al2O3. The first insulating layer 06 can be a single-layer structure, or a two-layer or multi-layer structure, such as a two-layer structure composed of silicon nitride and silicon oxide.

[0082] The connecting electrode 11 is made of a source / drain metal layer. The source / drain metal layer can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The source / drain metal layer can be a single-layer structure or a multi-layer structure. Multi-layer structures include Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc.

[0083] The passivation layer 07 can be an oxide, nitride, or oxynitride compound. Specifically, the material of the passivation layer 07 can be SiNx, SiOx, or Si(ON)x, and Al2O3 can also be used. The passivation layer 07 can be a single-layer structure, or a two-layer or multi-layer structure, such as a two-layer structure composed of silicon nitride and silicon oxide.

[0084] Organic insulating layer 08 can be made of organic resin.

[0085] In this embodiment, a connection electrode 11 is formed from the source / drain metal layer. The connection electrode 11 is used to connect the gate 10 and the first electrode. The connection electrode 11 is connected to the first electrode through a first via 21 penetrating the first insulating layer 06. Figure 8 As shown, the connection electrode 11 includes a first connection portion 111 located within the first via; the gate 10 extends from the region where the thin-film transistor is located to the first via 21, but does not overlap with the first via 21, the length of the gate 10 is shortened, and the area of ​​the gate 10 is reduced, as shown. Figure 7 and Figure 8 As shown, at the sidewall of the first via 21, the side surface of the gate 10 near the first via 21 directly contacts the side surface of the first connection portion 111 near the gate 10. Through this sidewall overlap, the gate 10 is electrically connected to the first electrode, eliminating the need for the gate 10 to extend into the first via 21, thus reducing the size of the first via 21; as... Figure 6 As shown, it is possible to achieve a gate-free region 10 in region E. In this region, the light-shielding layer 03 can be hollowed out, so that a transparent structure can be formed in region E. Region E can also be used as a pixel aperture region. In this way, the pixel aperture region can be increased from region A to region A+E, thereby improving the aperture ratio of the display product.

[0086] In some embodiments, the display substrate further includes a second via penetrating the first insulating layer, the second via being used to connect conductive film layers located on both sides of the first insulating layer, such as... Figure 14 As shown, the second via 23 is used to connect the active layer and the source 24 and drain 25. The area of ​​the orthogonal projection of the second via 23 on the substrate is larger than the area of ​​the orthogonal projection of the first via 21 on the substrate. In this way, the area occupied by the first via 21 is relatively small, which can expand the area of ​​the second region and thus improve the aperture ratio of the display product.

[0087] In some embodiments, such as Figure 15 As shown, the orthographic projection of the gate 10 on the substrate is smaller than the orthographic projection of the gate insulating layer 09 on the substrate. This is because the active layer conductor process affects the activity of the transistor channel. Therefore, the area of ​​the gate insulating layer 09 is larger than the area of ​​the gate 10 to ensure the characteristics of the transistor.

[0088] In some embodiments, a color filter unit may be provided on the side of the passivation layer 07 away from the substrate, for example, a color filter unit may be provided between the passivation layer 07 and the organic insulating layer 08, which enables color display of the display substrate.

[0089] Embodiments of the present invention also provide a display device, including a display substrate as described above.

[0090] The display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the above-described structure of the display device does not constitute a limitation on the display device; the display device may include more or fewer of the aforementioned components, or combine certain components, or arrange different components. In embodiments of the present invention, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television set, a wearable electronic device, a navigation display device, etc.

[0091] The display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0092] Embodiments of the present invention also provide a method for manufacturing a display substrate, such as... Figures 3-8 As shown, the image includes multiple pixel regions located on a substrate 01, each pixel region including a light-emitting region A and a non-light-emitting region; a driving circuit is disposed in each pixel region; the driving circuit includes a storage capacitor and multiple transistors; the multiple transistors are located in the non-light-emitting region; for each pixel region, the multiple transistors include a switching transistor, a driving transistor, and a sensing transistor;

[0093] The transistor includes an active layer, a gate insulating layer 09, a gate metal layer, a first insulating layer 06, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate 01.

[0094] The manufacturing method includes:

[0095] A connection electrode is formed connecting the gate of the driving transistor and the first electrode of the storage capacitor. A first insulating layer 06 is spaced between the connection electrode 11 and the first electrode 10. The connection electrode 11 is connected to the first electrode through a first via penetrating the first insulating layer 06. This connection is made in the extending direction of the gate of the driving transistor (i.e.,...). Figure 3 In the x-direction shown, the connecting electrode 11 is in direct contact with the first electrode 06.

[0096] In this embodiment, the connecting electrode is in direct contact with the first electrode in the extension direction of the gate of the driving transistor. This way, the gate does not need to extend to the first via, which can reduce the area occupied by the gate of the driving transistor. Since the gate is opaque, the area of ​​the opaque part of the pixel area can be reduced, and the part of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0097] In some embodiments, in the extending direction of the gate 10 of the driving transistor, the orthographic projection of the connection portion of the connecting electrode 11 and the first electrode on the substrate 01 is greater than the orthographic projection of the connection portion of the gate 10 of the driving transistor and the first electrode on the substrate 01. This can reduce the area occupied by the gate of the driving transistor. Since the gate is opaque, the area of ​​the opaque portion of the pixel area can be reduced, and the portion of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0098] In some embodiments, in the extending direction of the gate 10 of the driving transistor, such as Figures 6-8 As shown, the orthographic projections of the connecting electrode 11 and the gate 10 of the driving transistor on the substrate do not overlap, which reduces the area occupied by the gate 10 of the driving transistor. Since the gate 10 is opaque, the area of ​​the opaque part of the pixel area can be reduced, and the part of the pixel area without a gate can be made transparent, thereby improving the aperture ratio of the display product.

[0099] In some embodiments, such as Figure 3 and Figure 6 As shown, the pixel region includes a first region Q1 located on the side of the first via 21 near the gate of the driving transistor and a second region Q2 located on the side of the first via 21 away from the gate of the driving transistor. The orthographic projection of the second region Q2 on the substrate does not overlap with the orthographic projection of the gate 10 on the substrate.

[0100] In this way, the gate 10 is located only in the first region Q1, which can reduce the area occupied by the gate 10. Since the gate is opaque, the area of ​​the opaque part of the non-light-emitting region G can be reduced, and the part of the non-light-emitting region G without the gate can be made transparent, thereby improving the aperture ratio of the display product.

[0101] In some embodiments, such as Figure 5 and Figure 8 As shown, the manufacturing method further includes:

[0102] A light-shielding layer 03 is formed in the non-light-emitting area. The light-shielding layer 03 is located on the side of the first electrode close to the substrate. The light-shielding layer 03 includes a cutout portion 22. The orthographic projection of the cutout portion 22 on the substrate does not overlap with the orthographic projection of the gate 10 on the substrate. Further, the orthographic projection of the cutout portion 22 on the substrate 01 overlaps with the orthographic projection of the second region Q2 on the substrate.

[0103] In this embodiment, the light-shielding layer 03 can prevent light from shining onto the active layer and affecting the performance of the thin-film transistor; such as Figure 6 As shown, a cutout portion 22 of the light-shielding layer is provided at the position corresponding to the second region Q2. In this way, there is no gate 10 or light-shielding layer 22 blocking the light at the position of the cutout portion 22, and the position of the cutout portion 22 is light-transmitting, which can improve the aperture ratio of the display product.

[0104] In some embodiments, in order to maximize the aperture ratio of the display product, the orthographic projection of the cutout portion 22 on the substrate coincides with the orthographic projection of the second region Q2 on the substrate. In this way, the second region Q2 does not have the gate 10 and the light-shielding layer 22 that block light, and the second region Q2 can be set as the aperture area of ​​the pixel area.

[0105] In some embodiments, such as Figure 7 As shown, the orthogonal projection of the cutout portion 22 on the substrate 01 can also cover the orthogonal projection of the first via 21 on the substrate 01. In this way, even if excessive etching occurs, the connection electrode 11 and the light-shielding layer 03 can be prevented from conducting. On the other hand, the aperture ratio of the display product can be improved.

[0106] Of course, such as Figure 4 and Figure 8 As shown, the light-shielding layer 03 may also not include the cutout portion 22, so that the surface of the light-shielding layer 03 is flat, which can provide a flat surface for subsequent processes.

[0107] In a specific example, such as Figures 9-15 As shown ( Figures 9-15 for Figure 3 (A cross-sectional diagram in the OO direction), this embodiment includes the following steps:

[0108] Step 1, as follows Figure 9 As shown, a substrate 01 is provided, and a transparent conductive layer 02 is formed on the substrate 01;

[0109] The substrate can be a glass substrate or a quartz substrate. Specifically, a thickness of approximately [thickness missing] is deposited on the substrate by sputtering or thermal evaporation. The transparent conductive layer can be ITO, IZO or other transparent metal oxides.

[0110] Step 2, as follows Figure 10 As shown, a light-shielding layer 03 is formed on the substrate after step 1 is completed;

[0111] Specifically, a thickness of approximately [thickness missing] can be deposited on the substrate after step 1 using sputtering or thermal evaporation methods. The metal layer is used as the light-shielding layer 03. The light-shielding layer 03 can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The light-shielding layer 03 can be a single-layer structure or a multi-layer structure. Multi-layer structures include Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc.

[0112] The light-blocking layer can be a single layer or it can include perforated sections.

[0113] Step 3, as follows Figure 11 As shown, a buffer layer 04 is formed on the substrate after step 2 is completed;

[0114] Specifically, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit a thickness of [thickness value missing] on the substrate after step 2. The buffer layer 04 can be made of oxides, nitrides or oxygen-nitrogen compounds, and the corresponding reaction gases are SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0115] Step 4, as follows Figure 12 As shown, an active layer is formed on the substrate after step 3 is completed;

[0116] Specifically, an active layer material 05 can be deposited on the substrate and etched to form a patterned active layer. A portion of the active layer material 05 can be conductively processed to form the first electrode.

[0117] Step 5, as follows Figure 13 As shown, a gate insulating layer 09 and a gate 10 are formed on the substrate after step 4 is completed;

[0118] Specifically, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit a thickness of [thickness value missing] on the substrate after step 4. The gate insulating layer can be made of oxide, nitride or oxygen-nitrogen compound, and the corresponding reaction gases are SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0119] Specifically, a thickness of approximately [thickness missing] can be deposited on a substrate with a gate insulating layer formed by sputtering or thermal evaporation. The gate metal layer can be made of metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, and W, or alloys of these metals. The gate metal layer can be a single-layer or multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, or Mo\Al\Mo. A photoresist layer is coated on the gate metal layer. The photoresist is exposed using a mask, creating areas where the photoresist is retained and areas where it is not retained. The retained areas correspond to the area containing the gate pattern, while the unretained areas correspond to the areas outside the pattern. A development process is performed to completely remove the photoresist in the unretained areas, while the photoresist thickness in the retained areas remains unchanged. Finally, an etching process completely removes the gate metal film in the unretained areas, and the remaining photoresist is stripped away to form the gate pattern.

[0120] After the gate is formed, the gate insulating layer can be dry-etched to form a via through the gate insulating layer, exposing the first electrode.

[0121] Step 6, as follows Figure 14 As shown, a first insulating layer 06 is formed on the substrate after step 5 is completed;

[0122] Specifically, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit a thickness of [thickness value missing] on the substrate after step 5. The first insulating layer 06 can be an oxide, nitride, or oxygen-nitrogen compound, and the corresponding reaction gas is SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0123] The first insulating layer 06 is dry-etched to form a via that penetrates the first insulating layer. This via is connected to a via in the gate insulating layer, exposing the first electrode.

[0124] Step 7, as follows Figure 15 As shown, a pattern of source / drain metal layers is formed on the substrate after step 6.

[0125] Specifically, a layer with a thickness of approximately [thickness missing] can be deposited on the substrate after step 6 using magnetron sputtering, thermal evaporation, or other film deposition methods. The source / drain metal layer can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The source / drain metal layer can be a single-layer or multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the source / drain metal layer. The photoresist is exposed using a mask to form areas where the photoresist is not retained and areas where it is retained. The areas where the photoresist is retained correspond to the areas containing the patterns of the source electrode 24, drain electrode 25, and connecting electrode 11, while the areas where the photoresist is not retained correspond to the areas outside the aforementioned patterns. A development process is performed to completely remove the photoresist in the areas where the photoresist is not retained, while the photoresist thickness in the areas where the photoresist is retained remains unchanged. An etching process is then used to completely etch away the source / drain metal layer in the areas where the photoresist is not retained, and the remaining photoresist is stripped off to form the source electrode 24, drain electrode 25, and connecting electrode 11. The connecting electrode 11 is used to connect the gate electrode 10 and the first electrode.

[0126] The transistor can be fabricated through steps 1-7 described above. Then, a passivation layer, an organic insulating layer, and a color filter unit are formed on the substrate from steps 1-7 to obtain the display substrate of this embodiment, such as... Figures 3-8 As shown.

[0127] In this embodiment, a connection electrode 11 is formed from the source / drain metal layer. The connection electrode 11 is used to connect the gate 10 and the first electrode. The connection electrode 11 is connected to the first electrode through a first via 21 penetrating the first insulating layer 06. Figure 8 As shown, the connection electrode 11 includes a first connection portion 111 located within the first via; the gate 10 extends from the region where the thin-film transistor is located to the first via 21, but does not overlap with the first via 21, the length of the gate 10 is shortened, and the area of ​​the gate 10 is reduced, as shown. Figure 7 and Figure 8 As shown, at the sidewall of the first via 21, the side surface of the gate 10 near the first via 21 directly contacts the side surface of the first connection portion 111 near the gate 10. Through this sidewall overlap, the gate 10 is electrically connected to the first electrode, eliminating the need for the gate 10 to extend into the first via 21, thus reducing the size of the first via 21; as... Figure 6 As shown, it is possible to achieve a gate-free region 10 in region E. In this region, the light-shielding layer 03 can be hollowed out, so that a transparent structure can be formed in region E. Region E can also be used as a pixel aperture region. In this way, the pixel aperture region can be increased from region A to region A+E, thereby improving the aperture ratio of the display product.

[0128] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0129] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0130] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0131] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0132] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0133] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each component in the drawings do not reflect true scale.

[0134] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, It includes multiple pixel regions located on a substrate, wherein the pixel regions include light-emitting regions and non-light-emitting regions; A driving circuit is provided in the pixel area; The driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors are located in a non-light-emitting area; for each pixel area, the plurality of transistors include: a switching transistor, a driving transistor, and a sensing transistor; The transistor includes an active layer, a gate insulating layer, a gate metal layer, a first insulating layer, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate. The gate of the driving transistor is connected to the first electrode through a connection electrode that penetrates the first insulating layer; the connection electrode is in direct contact with the first electrode in the extending direction of the gate of the driving transistor. The connection electrode includes a first connection portion located within the first via, the side surface of the gate near the first via is in direct contact with the side surface of the first connection portion near the gate, and the gate and the first connection portion overlap in a sidewall manner.

2. The display substrate according to claim 1, characterized in that, In the extension direction of the gate of the driving transistor, the orthographic projection of the connection portion between the connecting electrode and the first electrode on the substrate is greater than the orthographic projection of the connection portion between the gate of the driving transistor and the first electrode on the substrate.

3. The display substrate according to claim 2, characterized in that, In the extending direction of the gate of the driving transistor, the connection electrode and the orthographic projection of the gate of the driving transistor on the substrate do not overlap.

4. The display substrate according to claim 3, characterized in that, The pixel region includes a first region located on the side of the first via near the gate of the driving transistor and a second region located on the side of the first via away from the gate of the driving transistor, wherein the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the gate on the substrate.

5. The display substrate according to claim 4, characterized in that, The display substrate further includes a light-shielding layer, which is located on the side of the first electrode near the substrate and includes a cutout portion. The orthographic projection of the cutout portion on the substrate overlaps with the orthographic projection of the second region on the substrate.

6. The display substrate according to claim 5, characterized in that, The orthogonal projection of the cutout portion on the substrate covers the orthogonal projection of the first via on the substrate.

7. The display substrate according to claim 1, characterized in that, The display substrate further includes a second via penetrating the first insulating layer, wherein the area of ​​the orthogonal projection of the second via on the substrate is greater than the area of ​​the orthogonal projection of the first via on the substrate.

8. The display substrate according to claim 1, characterized in that, The orthogonal projection of the gate on the substrate is smaller than the orthogonal projection of the gate insulating layer on the substrate.

9. The display substrate according to claim 5, characterized in that, The display substrate further includes: A transparent conductive layer located on the side of the light-shielding layer near the substrate forms the second electrode of the storage capacitor.

10. The display substrate according to claim 9, characterized in that, The light-shielding layer is disposed adjacent to the transparent conductive layer and is in direct contact with it.

11. The display substrate according to claim 1, characterized in that, The connection electrodes are fabricated using source / drain metal layers.

12. The display substrate according to claim 1, characterized in that, The display substrate further includes: Passivation layer on the side away from the substrate; A color filter unit located on the side of the passivation layer away from the substrate.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-12.

14. A method for manufacturing a display substrate, characterized in that, The display substrate includes a plurality of pixel regions located on a substrate, and the pixel regions include light-emitting regions and non-light-emitting regions; A driving circuit is provided in the pixel area; The driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors are located in a non-light-emitting area; for each pixel area, the plurality of transistors include: a switching transistor, a driving transistor, and a sensing transistor; The transistor includes an active layer, a gate insulating layer, a gate metal layer, a first insulating layer, and a source / drain metal layer stacked on the side away from the substrate. The first electrode of the storage capacitor is disposed on the same layer as the active layer, and the second electrode of the storage capacitor is located on the side of the first electrode closer to the substrate. The manufacturing method includes: A connection electrode is formed to connect the gate of the driving transistor and the first electrode of the storage capacitor. A first insulating layer is spaced between the connection electrode and the first electrode. The connection electrode is connected to the first electrode through a first via penetrating the first insulating layer. The connection electrode is in direct contact with the first electrode in the extension direction of the gate of the driving transistor. The connection electrode includes a first connection portion located in the first via. The side surface of the gate near the first via is in direct contact with the side surface of the first connection portion near the gate. The gate and the first connection portion overlap with each other on their sidewalls. A light-shielding layer is formed in the non-light-emitting area. The light-shielding layer is located on the side of the first electrode close to the substrate. The light-shielding layer includes a cutout portion. The orthographic projection of the cutout portion on the substrate does not overlap with the orthographic projection of the gate on the substrate.

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