Method and controller for controlling memory operations

Abstract

A method and controller for controlling memory operations in which a plurality of data sets are stored in or read from a memory by first storing or reading the most significant bit of each data set, and subsequently storing or reading the next most significant bit of each data set.

Description

Technical Field

[0001] This disclosure relates to methods, controllers, devices, and circuits for controlling memory operations, and particularly to controlling read and write operations.

[0002] This application claims priority under the Paris Convention for UK Patent Application No. 2100653.1, the contents of which are incorporated herein by reference. Background Technology

[0003] New radio access technologies, such as the 3GPP 5G New Radio “NR”, enable significant increases in throughput, such as multi-gigabit over-the-air (MTB) rates. For example, designing hardware capable of handling such rates is challenging for baseband system-on-chip (SoC) designers.

[0004] In particular, recent technological advancements are associated with increased storage requirements (e.g., for Hybrid ARQ (HARQ) or retransmission mechanisms that are in operation) and increased transfer rates to memory (e.g., off-chip double data rate (DDR) memory).

[0005] While these challenges are currently particularly relevant to 5G, they are expected to be more relevant to future technologies.

[0006] Therefore, there is a need to provide a device that can improve memory operation, especially the management of write and read operations in memory. Summary of the Invention

[0007] The invention is defined in the appended independent claims. Further sub-implementations of the invention are defined in the appended dependent claims.

[0008] According to a first aspect of this disclosure, a method for controlling memory operations is provided, the method comprising identifying a plurality of datasets to be stored in memory, each dataset comprising two or more bits ordered from most significant bit to least significant bit; storing in memory a first plurality of bits selected from the bits of the plurality of datasets, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of the stored data of each dataset define a storage portion of each dataset; and storing in memory a further plurality of bits selected from the bits of the plurality of datasets, wherein the further plurality of bits are selected by selecting one or more consecutive additional bits of each dataset, said further plurality of bits being outside the storage portion and including the most significant bit outside the storage portion of each dataset. Thus, write operations can be controlled in a manner particularly helpful in controlling and / or minimizing the effects of congestion on memory operations.

[0009] According to a second aspect of this disclosure, a method for controlling memory operations is provided, the method comprising: identifying a plurality of datasets to be read from memory, each dataset comprising two or more bits ordered from most significant bit to least significant bit; reading from memory a first plurality of bits selected from the bits of the plurality of datasets, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of the read from each dataset define a read portion of each dataset; and reading from memory a further plurality of bits selected from the bits of the plurality of datasets, wherein the further plurality of bits are selected by selecting one or more consecutive additional bits of each dataset, the additional plurality of bits being outside the read portion and including the most significant bit outside the read portion of each dataset. Thus, write operations can be controlled in a manner particularly helpful in controlling and / or minimizing the effects of congestion on memory operations.

[0010] According to a third aspect of this disclosure, a controller for controlling memory operations is provided, the controller being configured to identify a plurality of datasets to be stored in memory, each dataset comprising two or more bits ordered from most significant bit to least significant bit; to store in memory a first plurality of bits selected from the bits of the plurality of datasets, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of the storage of each dataset define a storage portion of each dataset; and to store in memory a further plurality of bits selected from the bits of the plurality of datasets, wherein the further plurality of bits are selected by selecting one or more consecutive additional bits of each dataset, the additional bits being outside the storage portion and including the most significant bit outside the storage portion of each dataset.

[0011] According to a fourth aspect of this disclosure, a controller is provided for controlling memory operations, the controller being configured to identify a plurality of datasets to be read from memory, each dataset comprising two or more bits ordered from most significant bit to least significant bit; to read from memory a first plurality of bits selected from the bits of the plurality of datasets, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of the read of each dataset define a read portion of each dataset; and to read from memory a further plurality of bits selected from the bits of the plurality of datasets, wherein the further plurality of bits are selected by selecting one or more consecutive additional bits of each dataset, the additional plurality of bits being outside the read portion and including the most significant bit outside the read portion of each dataset.

[0012] According to a fifth aspect of this disclosure, a controller system is provided, including a write controller according to the third aspect above and a read controller according to the fourth aspect above.

[0013] Therefore, methods and controllers for controlling memory operations have been provided, wherein multiple datasets are stored in or read from memory by first storing or reading the most significant bit of each dataset and then storing or reading the second most significant bit of each dataset. Attached Figure Description

[0014] A more complete evaluation of this disclosure will be better understood when considered in conjunction with the accompanying drawings, by referring to the exemplary description below, in which the same reference numerals denote the same or corresponding parts in several views.

[0015] Figure 1 An example of a retransmission mechanism is shown;

[0016] Figure 2A and 2B Examples illustrate the HARQ buffers after different transmissions;

[0017] Figure 3 An example decoding chain is shown at the wireless receiver;

[0018] Figures 4A to 4D Example communication with the HARQ buffer during retransmission is shown;

[0019] Figure 5 An example structure of a wireless receiver is shown;

[0020] Figure 6A An example arrangement for processing LLR samples stored in a HARQ buffer is shown;

[0021] Figure 6B An example compression method for reducing LLR size is shown;

[0022] Figure 7 An example HARQ buffer is shown;

[0023] Figures 8A to 8C This shows the process during transmission and retransmission. Figure 7 An example of buffer usage;

[0024] Figure 9 An example controller according to this disclosure is shown;

[0025] Figures 10A to 10C An example use of the HARQ buffer according to this disclosure is shown;

[0026] Figure 11 Another example of a HARQ buffer is shown;

[0027] Figure 12 It shows Figure 11 Another view of the HARQ buffer;

[0028] Figures 13A to 13C This shows the process during transmission and retransmission. Figure 11 An example of buffer usage;

[0029] Figure 14 It shows the use of Figure 11 Examples of buffers;

[0030] Figure 15 An example method of this disclosure is shown for storage in memory;

[0031] Figure 16 An example method of this disclosure for reading from memory is shown;

[0032] Figure 17 An example delay detection arrangement according to this disclosure is shown;

[0033] Figure 18 An exemplary memory reordering technique is shown in an LLR write operation;

[0034] Figure 19 An exemplary memory reordering technique is shown in an LLR read operation;

[0035] Figure 20 An example of bit sorting in memory is shown;

[0036] Figure 21 An example soft combination operation using a partial LLR sample is shown; and

[0037] Figure 22 An example of "filling" is shown for a portion of the LLR sample. Detailed Implementation

[0038] This disclosure includes exemplary arrangements that fall within the scope of the claims, and may also include exemplary arrangements that may not fall within the scope of the claims but which may help to understand the teachings and techniques provided herein.

[0039] Most radio access technology communication systems should include two features of wireless nodes (e.g., mobile terminals, base stations, remote radio heads, relays, etc.) to manage errors in transmission: (1) error correction mechanisms and (2) retransmission mechanisms.

[0040] As those skilled in the art will understand, error correction mechanisms typically involve transmitting parity bits along with the bits to be transmitted (here referred to as "information bits"). Parity bits may include Cyclic Redundancy Check (CRC) bits, which can be used to determine whether a received transmission contains any errors. Parity bits may also include Forward Error Correction (FEC) bits, which can be used to recover the bits of the original transmission (e.g., the original information bits) even if the received bits contain errors.

[0041] If an error exists in the received bits (and, if FEC is available, the error cannot be corrected), the receiver can report a transmission failure, and a retransmission mechanism can then be used to obtain a successful transmission. In some cases, retransmission will involve retransmitting the same transmission, while in others, retransmission may include sending a different transmission, which may be completely different from the first transmission or may at least partially overlap with the first transmission.

[0042] Figure 1 An example of a retransmission mechanism corresponding to the latter case is shown. At the top, all the bits that can be transmitted are defined (hereinafter referred to as "coded bits"). Coded bits typically include a portion containing the information bits, and optionally include a portion containing one or more parity bits (e.g., CRC and / or FEC bits).

[0043] In this example, the transmitter can transmit a total of 8 bits of information (e.g., the actual data to be transmitted) and 16 bits of parity. It should be understood that these values ​​are merely illustrative, and the number of information and / or parity bits can vary appropriately depending on transmission parameters, communication standards, or any other relevant factors. For example, in 5G NR, a coded block is expected to include 25,344 coded bits. Those skilled in the art will understand that the teachings provided in this disclosure apply equally to these and other situations.

[0044] In current mobile telecommunications networks, such as 5G NR networks, the configuration of retransmission attempts sending different coded bit selections compared to previous transmissions is sometimes referred to as "incremental redundancy." Using this terminology, the first transmission is sometimes identified as "RV0" (redundancy version 0), the first retransmission as "RV1," the second retransmission as "RV2," and so on. In 5G NR, a HARQ cycle with incremental redundancy can be extended to up to four transmissions (e.g., RV0 to RV3) before the redundancy check (CRC test) passes or fails. While this terminology is used extensively in this disclosure, those skilled in the art will understand that the invention is not limited to applications in 5G NR or generally not limited to 3GPP communications, but can be applied to other situations.

[0045] Back Figure 1For example, the encoded bits consist of 24 bits, and 12 bits can be transmitted at a time. In the first transmission RV0, all the information (8 bits) and some parity bits (4 bits) are transmitted. In the second transmission (first retransmission) RV1, only the parity bits (12 bits) are transmitted. In the third transmission (second retransmission) RV2, a mixture of information bits (4 bits) and parity bits (8 bits) is sent. Those skilled in the art will be able to understand how to select the information bits and parity bits to be transmitted in each transmission or retransmission, which is beyond the scope of this disclosure.

[0046] To facilitate understanding of the different benefits and trade-offs associated with each example arrangement provided herein, examples of this disclosure have been provided in general order to correspond to... Figure 1 Examples. However, those skilled in the art will understand that this disclosure is not limited to... Figure 1 This is an example, and can be used equally for other examples.

[0047] Figure 2A and 2B This shows an example view of the HARQ buffer after multiple transmissions, corresponding to Figure 1 Examples. It is worth noting that the numbers 2A and 2B can be viewed from either a physical or logical perspective, as will be clarified below.

[0048] After the first transmission, the buffer for the encoded bits will contain the contents received from the transmitted bits. In this example, the transmission will correspond to the eight (8) information bits and four (4) parity bits transmitted. After this transmission, the buffer or memory for receiving the transmission will have some, but not all, of the received encoded bits.

[0049] Assuming the first transmission fails, the second transmission will send the 12 remaining parity bits. Therefore, the receiver will receive all the encoded bits via either the first or second transmission. Consequently, the buffer or memory used for transmission will contain information for each encoded bit. Assuming the device still cannot decode the encoded bits even after the second transmission, then... Figure 1 As shown, a third transmission will be sent. After the second transmission, the receiver will receive some coded bits twice; in this case, the coded bits are sent in the third transmission (the second retransmission). This is in Figure 2A The thick lines outside the received encoded bits are used to illustrate this.

[0050] exist Figure 2B The same example is shown in the figure, which illustrates the same buffer, but in a linear fashion, with memory resources allocated to code bits, from code bit 0 to code bit 23.

[0051] As those skilled in the art will know, when the same coded bit is received more than once, a receiver can use various received versions of the coded bit in different ways. In one example, the receiver could use the last one, the one considered "better" or "stronger," or it could use a soft summation of the received contents. In reality, the coded bit is either 0 or 1, but it is transmitted via physical (analog) signals, allowing the receiver to correlate the received transmission with a fraction indicating whether the code is closer to 0 or 1. By combining the fractions from more than one transmission, any interference or other factors that may have degraded the transmission of the coded bit typically do not affect two transmissions of the same coded bit in a similar way. Therefore, by combining the fractions of the coded bit from two or more transmissions, the reliability of the expected fraction is increased compared to the fraction of any single transmission of the same coded bit. In other words, as a result of the soft combination of two or more transmissions, the expected probability of decoding is increased.

[0052] Figure 3 An example decoding chain at a wireless receiver is shown, similar to those found in 5G communication nodes. The signal from the receiver, the "RF receiver," is passed to a Fast Fourier Transform (FFT) equation. The signal can then be adjusted based on channel estimation, using an equalizer before demodulation. Information about the received transmission is written to memory before reaching the decoder, the "LDPC decoder," which attempts to decode the received signal, in case it is needed after further transmission. Information can also be read from memory, for example, if any information from one or more previous transmissions was previously stored in memory. The decoder can then attempt to decode the coded bits using information from the current transmission, or from any previously related transmissions that may already be stored in memory. If a CRC check fails, this indicates that decoding was unsuccessful. This can, for example, lead to further transmissions of the same or related coded bits. If decoding is successful, the information is passed to further components and possible layers for processing.

[0053] This disclosure focuses on memory operations, Figure 3 In the examples, memory operations are particularly related to read and write operations to the HARQ buffer. Therefore, a more detailed description will now follow. Figure 3 This part.

[0054] The demodulator outputs the log-likelihood ratio (LLR) that the LDPC decoder can use. From one perspective, the LLR can be viewed as a fraction associated with the coded bit and represents the probability that the coded bit is 0 or 1. In mobile networks, the LLR tends to be 8 bits long, although other lengths can also be used. The fraction is typically represented on a scale from -1 to 1, where a fraction of -1 represents a coded bit value of 0, and a fraction of 1 represents a coded bit value of 1.

[0055] Figures 4A to 4DExample communication with the HARQ buffer during retransmission is shown. Figure 4 illustrates a transfer to and from the HARQ LLR buffer as the transmission proceeds from the first transfer (RV0) to the fourth transfer (RV3). Each transfer is expected to correspond to a memory read or write operation.

[0056] like Figure 4A As shown, in RV0, the transition corresponds to writing the newly received LLR into the HARQ buffer.

[0057] like Figure 4B As shown, in RV1, these stored LLRs are retrieved and combined with newly received LLRs. The newly combined LLRs and / or RV1 LLRs are also written back to memory. Therefore, the expected transfer corresponds to two or more times the number of LLRs: one set of LLRs is read, and at least one set of LLRs (RV1 LLRs and / or combined LLRs) is written.

[0058] like Figure 4C As shown, a similar process occurs in RV2. The number of LLRs read can vary depending on whether the arrangement is configured to write one or both of the LLRs used for retransmission and the combined LLRs used for all transmissions on each retransmission. If each set of LLRs is written on each transmission (and therefore on each retransmission), then the LLRs of RV0 and RV1 are read. Additionally, the LLRs of RV2 are written to memory. Therefore, the expected transfer corresponds to three times or more of the number of LLRs: reading two sets of LLRs and writing at least one set of LLRs (the LLRs of RV1 and / or the combined LLRs). In the case of only reading the combined LLRs, the expected transfer corresponds to two times or more of the number of LLRs.

[0059] like Figure 4D As shown, in RV3, the previous LLR is read, but the new LLR is not written back because the HARQ loop will terminate regardless of whether the decoding is successful. In the case of reading combined LLRs, one set of LLRs is read from memory, but in the case of reading each previously transferred LLR, three sets of LLRs are read, namely the LLRs of RV0, RV1, and RV2, which can then be combined with the LLR of RV3.

[0060] It is worth noting that when combining LLRs from all transmissions, storing only the combined LLRs may be beneficial, thereby reducing the amount of data to be transferred with each retransmission. However, it is also conceivable that in some cases, not all LLRs will be combined, resulting in each set of LLRs being stored separately. While the required storage resources and transfers increase, this arrangement can also improve the decoding rate. For example, the decoder can rate or score the quality or reliability of the LLRs (e.g., by checking if one of the (re)transmissions is corrupted by an unscheduled transmission from another terminal, checking if one of the (re)transmissions is interrupted by a low-latency transmission, and / or checking the level of interference associated with the (re)transmission, etc.) to assess how useful the LLR is expected and / or increase decoding attempts by trying to decode the encoded bits using different transmission combinations (e.g., RV0+RV2+RV3, RV0+RV1, etc.). In other words, a HARQ arrangement can involve storing a combined LLR from a transmission or previous transmissions and / or each set of LLRs, and those skilled in the art can determine which option is best suited for a particular system or environment based on factors such as processing power, memory capacity, and / or device cost.

[0061] Under normal circumstances, the expected air throughput is maximized when the number of HARQ retransmissions remains below 20% of all transmissions, i.e., 80% of transmissions do not exceed RV0. Under adverse conditions, such as sudden interference, HARQ retransmissions can extend to RV3. In this case, the amount of data transferred to and / or from the HARQ buffer may increase threefold compared to the amount transferred to RV0.

[0062] Furthermore, with the increase in data rates on the air interface, such as those offered by newer radio technologies like 5G NR, this results in an increase in the amount of data that needs to be moved to or from memory.

[0063] It should also be noted that, without any additional memory optimization, the HARQ LLR bit rate of an N-bit LLR is expected to be N times the over-the-air throughput. For example, for a 5G NR system capable of achieving 5Gb / s throughput (measured by the number of coded bits transmitted over the air) and an 8-bit LLR (without compression or optimization of the LLR), such a system could generate 40Gb / s of HARQ LLR samples, resulting in a peak HARQ LLR buffer throughput of 120Gb / s in the example above. Adapting to such high data rates could require a large and expensive amount of memory. Additionally or alternatively, this could lead to an oversupply of memory resources to accommodate the HARQ LLR buffer bandwidth demands, where these peak demands are rarely used or needed.

[0064] Figure 5An example architecture for a wireless receiver is shown, illustrating HARQ processing within a System-on-Chip (SoC) environment. In this example, HARQ LLR samples are stored in off-chip DDR memory. The HARQ buffer manager coordinates the transfer of LLR samples to or from DDR memory via the Network-on-Chip (NoC) and the DDR controller. DDR memory is typically expected to be a pooled or shared resource utilized by many other functions of a device that includes HARQ functionality (e.g., the receiver). For example, from... Figure 3 or Figure 5 Data in other parts of the data path shown can be stored there and read from there. Additionally or alternatively, code executed by various on-chip processors can also write and read data in DDR.

[0065] Access to DDR can be arbitrated by the NoC and DDR controller functions. However, when multiple functions request access simultaneously, the peak load may significantly exceed the load supported by the DDR subsystem. In this situation, the requesting function may be delayed, waiting for the DDR transaction to complete, potentially slowing processing speed to the point where the data path cannot complete critical processing operations in a timely manner. Therefore, ensuring that the HARQ system can utilize storage functions in a timely manner is a crucial factor in designing a HARQ system. Furthermore, in situations such as... Figure 5 In the system shown, HARQ LLR memory accounts for a large portion of the overall DDR memory bandwidth budget. This disclosure provides techniques and teachings illustrating how to adjust memory requirements to operate within the constraints of available DDR memory bandwidth, and these techniques can be applied to situations where memory requirements are HARQ LLR requirements.

[0066] One way to reduce memory requirements when handling LLRs is to reduce the amount of data to be stored. With this in mind, some systems use linear logarithmic compression systems to reduce the size of stored LLR samples. Figure 6A An example arrangement for handling LLR samples stored in a HARQ buffer is shown, along with a method for compressing HARQ LLR samples using a fixed compression function, a log-linear approach, and a HARQ buffer manager. Compressed LLR sample write and read operations can then be processed. In this example, the size of the LLR samples is reduced from 8 bits to 6 bits before being sent to memory for storage. Therefore, a 25% size reduction can be achieved, thus reducing memory requirements.

[0067] Figure 6B An example compression method for reducing LLR size is shown, where the compression amount can be configured using the Q_Norm parameter or as input to linear logarithmic compression and decompression functions. This compression and decompression functionality can be used, for example, in... Figure 6AIn the arrangement. Although this type of compression is a lossy compression method (as opposed to lossless compression methods), the impact of the loss is expected to be acceptable due to the nature of the LLR samples and their expected distribution and magnitude. In other words, for using a simple logarithmic quantizer Figure 6B With a fixed compression function, simulations show that it is possible to downquantize to 6 bits without significantly affecting the performance of the LDPC decoder.

[0068] While this arrangement can help reduce the amount of data to be stored and retrieved to 75% of the original amount, further improvements are expected as over-the-air data rates become visible or anticipated to increase, which could help reduce reliance on adding more memory to such systems.

[0069] As those skilled in the art will understand, increasing the compression level of the log-linear function may result in a loss of unwanted levels in the decompressed LLR samples. That is, this could have a greater impact on the ability to decode encoded bits using LLR, potentially leading to undesirable levels. Furthermore, one option involves adding more memory (e.g., more DDR), allowing read and write operations to be distributed across two or more memories, thereby reducing the likelihood of experiencing latency when memory operations peak. However, this option comes with an increase in device cost, which is disadvantageous in low-cost devices.

[0070] Therefore, it would be helpful to provide additional or alternative technologies for managing memory operations.

[0071] Figure 7 An example HARQ buffer is shown. When storing LLR samples (also referred to here as LLR), the HARQ buffer is expected to operate in a manner similar to... Figure 7 The organization is as shown. That is, for any ongoing decoding attempt, the HARQ buffer will have storage resources organized by coded bits, where, for each coded bit, the memory resources include multiple bits corresponding to the LLR sample to be stored. In this example, for consistency with other examples here, there are 24 coded bits, as those skilled in the art will know that the techniques presented here can be equally applied to more or fewer coded bits. Furthermore, this example assumes that the LLR sample to be stored in and read from memory is a 6-bit sample (e.g., because the LLR is 6-bit encoded, because it is 8-bit encoded and has been compressed to 6 bits, etc.). Those skilled in the art will also understand that the same techniques can be applied to LLR samples with more or fewer bits (or more generally, data to be stored in or read from memory).

[0072] In this disclosure, the term LLR(x,y) will refer to an LLR sample of coded bit x, where for that LLR sample, the LLR(x,y) bit is located at position y. For example, in Figure 7 In the example, bits LLR(3,0)...LLR(3,5) correspond to LLR samples with bit 3 encoded.

[0073] Figures 8A to 8C It shows Figure 7 The buffer is used in the example during transmission and retransmission; that is, in the example with three transmissions RV0...RV2, there are two retransmissions. For clarity, only the coded bits 0-1, 14-15, and 23 are shown, but this example follows the... Figure 1 The same transmission coding selection mode as shown in Figure 2. Therefore, Figure 8A The examples (after receiving RV0), 8B (after receiving RV1), and 8C (after receiving RV2) correspond to respectively Figure 2B Steps 1, 2, and 3.

[0074] Figure 9 An example controller according to this disclosure is shown, such as a HARQ buffer manager / adaptive compression subsystem. This controller can be used, for example, in conjunction with a HARQ buffer manager. For write management, Figure 9 The controller includes:

[0075] The "write LLR bit re-ordering" function is configured to select the LLR sample bits to write, and specifically, the order in which the LLR sample bits are written. This function is configured using the parameter Q_Write (i.e., Q_write), which can be derived from the memory's performance score or load control parameters.

[0076] - The "HARQ buffer header builder" function is configured to consider parameter Q(RV) based on the write step.

[0077] -Write function ( Figure 9 The "Issue burst writes" function sends write commands, typically in bursts (though not always). The write function can also receive acknowledgments when data has been written, and in some cases, when data cannot be written to memory.

[0078] The controller includes image reading and management capabilities, and also includes the following common functions:

[0079] - A latency monitor that can monitor latency in memory operations (in other cases, additionally or alternatively, one or more other types of memory performance) and can output an indication of congestion level.

[0080] - A compression controller that can configure compression levels based on one or more of the following: congestion or latency levels at memory, buffer size, number of transmissions or retransmissions, and policy or policy updates.

[0081] According to this example, when latency and / or congestion are detected at memory (e.g., by the delay between a read or write instruction and a read or write acknowledgment), the number of bits to be written to (or read from) memory can be reduced. Furthermore, according to the techniques provided herein, instead of simply reducing the number of bits written to (or read from) memory, the selection of the bits to be written to (or read from) memory is determined based on the most significant bit of each dataset or word or LLR sample to be stored in memory.

[0082] exist Figure 9 In the example, as DDR memory access becomes congested, read / write operations can be shortened to a portion of the LLR buffer containing the more significant bits of the LLR samples. In other words, adaptive compression can operate by allowing LLR samples to flow into and out of DDR memory, where the most significant bits are grouped together, then the less significant bits are grouped together, and so on.

[0083] Therefore, even if the writing (or reading) of multiple datasets, words, or LLR samples is interrupted before their completion, the most significant bit of each dataset, word, or LLR sample will be written (or read) before the least significant bit of that dataset, word, or LLR sample. When this technique is used for datasets like LLR datasets or other datasets that may have similar characteristics, the amount of data to be stored or accessed can be reduced while still storing or accessing the most important parts of the data.

[0084] It's worth noting that while such an arrangement might not offer additional benefits in cases where the data is more "random," since the LLR is a fraction on a -1 to 1 scale, the most significant bit already indicates whether the fraction is positive or negative, even without using other bits. The next significant bit will indicate whether the fraction is higher or lower than 0.5 (or -0.5 if the fraction is negative), and so on. Therefore, due to the nature of the LLR, even if the quality of the fraction is lower when only some bits are used, using the most significant bit first still provides useful information. Thus, it is expected that using truncated or incomplete but still useful information is beneficial, as it may help avoid overall decoding failures (which could otherwise occur due to unmanaged congestion).

[0085] Figures 10A to 10CAn example of using a HARQ buffer according to this disclosure is shown, in an example using a header. This example can be used, for example, with... Figure 9 The controller, and follows the... Figure 1 The same transfer pattern as shown in Figure 2. In this example, it is assumed that congestion is detected at the memory, such that at RV0, the write is interrupted after writing 7 bits of each 8-bit LLR; at RV1, the write is interrupted after writing 4 bits of the LLR; and at RV2, the write is interrupted after writing 6 bits of the LLR. As those skilled in the art will understand, these values ​​are merely illustrative, and any value between 0 and 8 can be used to determine how many bits to save for each LLR for each transfer. Furthermore, this example is based on an uncompressed LLR stored, but the same teachings and techniques apply equally to compressed LLR samples, such as those compressed to 6 bits.

[0086] Figure 10A The HARQ buffer is shown after storing the seven most significant bits for each LLR sample. When... Figure 8A Upon comparison, it can be seen that for the same coded bit, LLR data exists, but not all LLR bits are stored. Specifically, for coded bit 0, LLR bits LLR(0,0) to LLR(0,6) are stored, but LLR(0,7) is not stored to save bandwidth for transfers to memory. In this example, the HARQ buffer also includes a header that can indicate to RV0 how many LLR bits have been stored. For example, the header portion of RV0 can indicate a value of 7 (for seven stored bits), a value of 1 (for one unstored bit), or another value indicating the number of bits that have been stored (or unstored). It is understandable that... Figures 10A to 10C The header section may not be drawn to scale because header section RV0 (or any one of RV1 to RV3) may include more than one bit.

[0087] In examples using headers, shortened LLR samples can be marked in the header, for example, in the Q(RV) value indicating how many bits are stored. Depending on how the memory operates and is designed, this can help reduce the likelihood of subsequent read operations attempting to access invalid samples (e.g., the complete LLR sample when only a partial LLR sample is stored). Therefore, in some cases, the number of memory read errors can be avoided or reduced.

[0088] same, Figure 10B The buffer after storing the next set of LLRs is shown. In this example, the write is interrupted at bit 4, so that for each received encoded bit n, LLR bits LLR(n,0) to LLR(n,3) are stored, while LLR(n,4) to LLR(n,7) are not stored. Figure 10BAs shown, the memory will only store the three most significant bits of coded bits 14, 15, and 23 (as well as other coded bits received in RV1). The header will also include an indication of which four bits are stored for each LLR sample in RV1.

[0089] Figure 10C This describes the content received and stored after RV2. For the LLR sample corresponding to the second retransmission of RV2, 6 bits of each LLR sample are stored. For example... Figure 10C As shown, for at least coded bits 0 and 14, some LLR information will be received twice. It should be understood that... Figure 10C The representation is merely illustrative, and LLR bits may not be overwritten by closer bits (and because they correspond to LLR bits, they will be carefully assigned 0 or 1 values). For example, as mentioned above, LLR samples from different transmissions can be stored separately or combined such that a combined version is stored, with or without the corresponding LLR sample. For example, for coded bit 14, one LLR sample stores 3 bits from the original LLR sample, while another sample stores only 4 bits from the original LLR sample. Therefore, in total, the HARQ subsystem will only be able to use the seven original bits from the two different LLR samples. Several techniques are provided below that can be used when using partial LLR samples for soft merging or for other operations where the full LLR sample is expected.

[0090] Therefore, for different transmissions or retransmissions, a different number of LLR bits can be stored each time (or the same number of bits can be stored appropriately). Once a portion of each LLR sample, including the most significant bits of the LLR sample, is stored, the system effectively stores a partial LLR sample, not the complete original LLR sample. When, or if, an LLR sample is needed, the stored information corresponds to a portion of the original LLR sample, not the complete LLR sample. However, in some cases, the decoder may require the complete LLR sample to function. In such cases, different methods (alone or in combination) can be used to complete the LLR information to achieve a usable size. See below. Figure 21 and 22 This describes a technique for “filling” partial LLR samples, which can be used to use partial LLR samples for soft merging or other operations where full LLR samples are desired.

[0091] Figure 21An example soft-combining operation using a partial LLR sample is illustrated. In this example, an LLR sample from RV2 is received and soft-combined with an LLR sample from RV1 (or soft-combined after receiving RV1, depending on the implementation). In this example, the LLR sample read from memory is not a full-size LLR sample; for example, it is only a 4-bit sample, rather than a log-compressed 6-bit sample or a full-size 8-bit sample (e.g., depending on how this particular system operates). Regardless of the reason why the LLR sample is a partial sample instead of a full sample (e.g., because only 4 bits were initially stored, because only 4 bits can be read, etc.), the system is expected to soft-combine the partial LLR sample with the full LLR sample.

[0092] LLR samples can be filled, for example, by adding information to the LLR portions that are not yet stored (“empty portions”). This can be done by adding bits to the empty portions, for example, by filling the empty portions based on one or more of the following: all empty bits are set to 0, all empty bits are set to 1, random bits are set to 0 or 1, or bits are set according to a pattern, the first (most significant) bit of the empty portion is set to 1 and all other bits are set to 0 (also known as “rounding up”), the first bit of the empty portion is set to 0 and all other bits are set to 1 (also known as “rounding down”), and so on. Example patterns include the “0-1-0-1-0-1-…” pattern, the “1-0-1-0-1-0-…” pattern, or any other pattern deemed appropriate.

[0093] Figure 22 The diagram shows an example of "padding" a partial LLR sample using the "round up" technique. It can be seen that the RV1 LLR sample is missing four bits, and additional bits will be added when this (partial four-bit) LLR sample is intended to be used as a complete (here, 8-bit) LLR sample. To round up the four-bit sample to an eight-bit sample, the most significant bit of the empty or missing portion is padded with "1", while any remaining bits are padded with "0". Using this technique, a complete LLR sample can be obtained where the difference or error relative to the original LLR sample can be minimized, and the average performance of the padding is expected to be satisfactory.

[0094] Back Figure 21Once the LLR sample is rounded up to the full-size LLR sample, it can be soft-combined with the input RV2 LLR sample, and the soft-combined LLR can be passed to the decoder to attempt decoding the transmission. The soft-combined LLR sample and / or RV2 LLR sample can then be stored in memory. This can include truncating the LLR sample, for example using log-linear compression and / or any techniques provided herein to manage memory load and operations. It is worth noting that this padding technique can be used in conjunction with other techniques, such as log-linear compression and decompression techniques. For example, consider a case where a 6-bit LLR sample is expected to be written after being compressed from 8 bits to 6 bits using log-linear compression, and read before being decompressed back to 8 bits using log-linear decompression. In this case, padding can be used to fill the remaining LLR sample to 6 bits. Figure 22 In this example, padding will add a "1" to the most significant bit of the missing portion and a "0" to the last 6 bits. The padded bits can then be passed to a log-linear decompressor to obtain the full 8-bit size usable by the system.

[0095] Figure 21 The arrangement is an illustrative example and the padding can be implemented differently depending on how the system operates. As those skilled in the art will understand, information can be added to memory later (e.g., if memory load allows within a suitable time frame), can be added by the HARQ (or memory operations) manager when or after reading stored LLR samples, and / or by the decoder or any other user of the LLR samples.

[0096] In other cases, the decoder can be configured to operate using partial LLR samples, where this is considered as part of the decoding process, such that the partial LLR samples do not need to be complete, for example, having the same size as the original LLR samples.

[0097] It should be noted that, if provided, header bits can be stored in any suitable manner, such as separately from the LLR sample memory resource, at the end of the LLR memory resource, in the middle of the LLR memory resource, together with it, or distributed throughout the resource, etc. Headers from different transmissions can also be stored separately from each other. For example, the header of RV0 can be stored in a location associated with the information stored in the LLR sample memory of transmission RV0, and the header of RV1 can be stored in a location associated with the information stored in the LLR sample memory of transmission RV1.

[0098] Since the most significant bit of each LLR sample is stored first, the storage of an LLR sample (or any other type of data) can be stopped before it is completed, while still retaining useful information through the most significant bit of each LLR sample (or other type of data). In this case, using the techniques disclosed herein may be preferred while controlling the load on the memory, particularly how to manage the limited read and write bandwidth of the memory.

[0099] As those skilled in the art will understand, this type of memory operation is particularly useful for certain types of data, such as LLR samples, but may not be helpful for other types of data. For example, this method of storing data may be unsuitable if it is not expected that the most significant bit is more helpful than the least significant bit (e.g., if the data is encoded as a random number).

[0100] Figure 11 Another example of a HARQ buffer is shown. In this example, the buffer consists of the most significant bit (an LLR sample in this case) of the data to be stored. For example, Figure 11 The first part of the buffer with the header "LLR(n,0)" can store the most significant bit (corresponding to the coded bit n) of each LLR sample. This can be done for each LLR sample for every possible coded bit, or for each LLR sample received in a particular transmission (see below for example). Figure 20 (Discussion).

[0101] For example, once the most significant bit of each LLR sample has been stored in LLR(n,0), the second most significant bit of the LLR sample can be stored in LLR(n,1) – assuming the write operation is not interrupted, for example, due to increased latency in memory operations.

[0102] By arranging information according to the most significant bit of each LLR sample (or other type of data word) to be stored, memory operations can be simplified when using the techniques discussed here. Specifically, the bits to be stored in memory can be arranged in a manner corresponding to or similar to... Figure 11 The sequence is stored in memory.

[0103] Figure 12 It shows Figure 11 Another view of the HARQ buffer. As shown in the figure, the entire LLR for each encoded bit of the received LLR sample can be determined according to, for example... Figure 11 The memory bits of the organization shown are reconstructed. This can be achieved by reordering the stored bits in a mirror manner.

[0104] Figures 13A to 13C This illustrates the use of during transmission and retransmission. Figure 11An example of a buffer receiving data. Although Figures 13A to 13C The example transfers from RV0 to RV2 may not correspond to the actual contents of the HARQ buffer; they schematically show which LLR bits have been saved after the transfer.

[0105] like Figure 13A As shown, after RV0, the seven most significant bits of each (8-bit) LLR sample of each received coded bit are stored. As mentioned above, in this example, the write operation stops after RV0 (7 bits), RV1 (4 bits), and RV2 (6 bits). It should be understood that this is merely an illustrative example, and more or fewer bits can be stored in each transmission, and in conventional mobile networks, the number of transmissions can vary from RV0 only to up to RV3, or more generally, to any number of transmissions deemed appropriate.

[0106] Following the same example as above, then store the four most significant bits of the LLR sample corresponding to the encoded bits of RV1 in the second transmission (first retransmission), as follows: Figure 13B As shown.

[0107] Then, as Figure 13C As shown, the six most significant bits of the LLR sample of the encoded bits used for the third transmission RV2 are stored in memory.

[0108] According to the technique presented in this article, the most significant bit of an LLR sample (or other dataset to be stored) is prioritized. This results in the most significant bit (e.g., Figure 13C In the memory portion associated with LLR(n,0)), the lower significant bit (e.g. Figure 13C Compared to LLR(n,5) or even lower LLR(n,7), a larger bit density is received once or multiple times.

[0109] Figure 14 It shows the storage as such Figure 11 , 12 Or the example data used in the buffer arrangement shown in 13A-13C. Similarly, from... Figure 14As can be seen in the examples, the information density of the more significant bits increases compared to the less significant bits. Depending on which coded bit is transmitted in which transmission and how many LLR bits are written for each corresponding transmission, there will be a different amount of LLR information for each coded bit and each transmission. The flexibility provided by the teachings and techniques of this disclosure improves responsiveness and adaptability when the memory used to store LLR information experiences latency or overload. Therefore, in some cases, although complete LLR information is missing, some LLR information will be preserved, and the selection of which LLR information to preserve will facilitate the processing of the transmission, rather than losing the entire set of LLR samples due to the inability to write in time. Thus, dynamic compression of LLR is tailored to respond to memory conditions and prioritizes the most important parts of the LLR samples (or other datasets) to be stored.

[0110] Furthermore, the same teachings and techniques can be applied in a mirror manner to reading bits stored in memory. For example, the most significant bit of each LLR sample would be read first. Thus, even if the read operation is interrupted before all available LLR sample bits are read, the system is expected to have (i) at least some information about the LLR of each coded bit, and (ii) at least the most significant bit of each LLR sample of each coded bit transmitted in each transmission.

[0111] Therefore, even if the read operation is interrupted before completion, the risk of the interruption preventing the entire decoding operation from being completed is reduced. Similar to the benefits provided by the memory write techniques discussed here, mirrored read techniques reduce the risk of memory failure, at least in part due to the prioritization of reading the most significant bit first and the successive attempts to read (or write) the most significant bit of each LLR sample before proceeding to read the less significant bits (for each LLR sample).

[0112] It will also be understood that while write and / or read operations may be interrupted (e.g., due to DDR scheduling or prioritization from one or more HARQ operations, channel estimator operations, other network operations, or other memory operations), write and / or read operations can also be configured based on monitoring of memory operations.

[0113] For example, in one arrangement, write and / or read operations will be configured to write or read only a portion of the LLR sample in memory, which will help reduce the amount of data transfer to and / or from memory. The size of the portion to be written or read may, for example, depend on the monitoring or status of the memory.

[0114] In this scenario, better control over the amount of data transferred to and / or from memory is expected, and controlled partial write / read operation management is expected to result in fewer errors (compared to a situation where all operations attempt to complete in the hope of finishing before an interrupt, such as an interrupt caused by a contention for memory access). Furthermore, this operational pattern of reducing write or read operations in a planned manner is expected to cause fewer errors for other functions using the same memory.

[0115] Table 1 below shows an example compression strategy table that can be used by the controller to reduce the number of bits to be written to or read from memory based on the measured congestion level. Therefore, the controller can be configured based on two or more levels and can reduce the amount of data to be written to and / or read from memory based on the expected load on the memory. In the specific example in Table 1, there are eight different congestion levels, but it should be understood that more or fewer congestion or load levels can be used.

[0116]

[0117] Table 1

[0118] This table would be well-suited for an arrangement where, when memory load allows, it is anticipated that 6 bits will be written to or read from memory (e.g., in the case of a normally written or read 6-bit compressed LLR). Those skilled in the art will understand that the specific values ​​in Table 1 can therefore be adjusted based on any suitable parameters, such as the size of the data to be written or read, the number of load levels, the severity of the load levels or the congestion level reflected by the levels, memory properties (e.g., how the memory behaves when the load increases and how operational errors affect the memory), etc.

[0119] It is understandable that the amount of compression to be used may depend on one or more of the following factors: the state of the memory, the latency level associated with the memory, the number of transfers, etc. For example, in Table 1, the components associated with the memory itself are reflected by congestion or load levels (level 1 to level 8), and the amount of compression is further indexed based on the combination or type of operation (read or write) and the transfer number (RV0 to RV3 in this example).

[0120] In this example, when experiencing the same level of congestion, the compression level for read operations is typically the same as or higher than that for write operations (i.e., less data is written or read). This is expected to produce better results because the amount of reads that can be completed will be limited by the amount of writes that have already been completed. However, it should be understood that in some cases, the same level of compression can be configured for read and write operations, and more compression can be configured for read operations compared to write operations. This can be determined based on, for example, the performance of the specific memory (e.g., read and / or write speeds), the usage of the specific memory (e.g., the type of read or write operations from "competing" memory users), etc.

[0121] Based on the experienced congestion level, the amount of compression implemented for read and / or write operations can be configured using one or more of the following: a control processor for the controller, a configuration file, a remote element, messages received from a remote device or a device including memory, etc. In some cases, the controller can be configured with different combinations of congestion levels and compression levels, and can receive instructions to use a specific combination and / or determine which specific combinations to use.

[0122] Based on this configuration, and for each memory read or write operation, a compression level (e.g., the desired word length) is determined that is associated with the currently estimated congestion level, and this compression level can be used in the adaptive compression function.

[0123] In one example, a corresponding reporting table can be used to record a count of each entry (e.g., the number of operations using this read / write configuration, RV level, and congestion level), thus allowing measurement of the frequency of each entry's occurrence. This information, in turn, can be used by, for example, a controller tuning operation for adaptive compression and / or reported to higher layers. In some examples, once more information about how the system is used is obtained, the compression level and / or the granularity of each level can be adjusted. For example, if the records show that many operations are performed around one or more specific regions in the table above, and operations outside those regions are less frequent, the granularity of the congestion level and / or compression level around that cluster can be increased to a finer granularity. In some cases, this can also be used in conjunction with a reduced granularity outside the cluster for less frequent operations. Adjustments to the compression strategy can be made alternatively or additionally along with adjustments to other system functions and / or different operating modes. For example, in some systems or operating modes, a higher-performance equalizer can be configured, which will require greater access to memory. In this case, the compression level can be reduced, which is expected to result in better decoding performance. Depending on which other functions access memory and whether and how memory access by any of these functions is controlled, different functions can be configured or different functions can be prioritized in order to control memory operation.

[0124] Figure 15 An example method for storing information in memory according to this disclosure is illustrated. In S1501, multiple datasets to be stored in memory are identified. A dataset may, for example, be an LLR word set of LLR samples, which will be written to memory for future use. Then, in S1502, one or more consecutive first bits of each dataset, including the most significant bit of each dataset, are selected and stored in memory. In S1503, one or more consecutive additional bits of each dataset are selected. One or more consecutive additional bits are selected outside the storage portion of each dataset, including the most significant bit outside the storage portion. In other words, for each dataset with the remaining portion (i.e., the portion of each dataset that has not yet been written), and any optional subsequent bits, such as a second most significant bit, one or more consecutive additional bits can be considered as selected. The additional bits selected from the multiple datasets are then stored in memory.

[0125] Alternatively, the method may return to step S1503, for example, until the entire dataset has been written (the write operation has been completed) or until a predetermined number of bits have been written for each dataset—for example, based on Table 1 above.

[0126] Because of this arrangement and this data writing that does not follow the actual organization of the dataset, writes can be performed in a way that reduces the risk of errors if interrupted before completion. This is especially useful for data where the most significant bit of each dataset is more important for its meaning and use compared to the less significant bits in the same dataset.

[0127] Similarly, the same teachings apply to read operations, such as... Figure 16 The diagram illustrates an example method for reading from memory. First, in step S1601, multiple datasets to be read from memory are identified. A dataset could be, for example, a set of LLR words from LLR samples already written to memory, and will be read to attempt to decode the received transmission. In S1602, one or more consecutive first bits are selected for each dataset, including the most significant bit of each dataset. The selected bits can then be read from memory. In S1603, one or more additional consecutive bits are selected for each dataset, outside the read portion (the portion read in S1602), and include the most significant bit outside the read portion of each dataset. Multiple additional bits can then be read from memory.

[0128] Optionally, the method may return to step S1603 and select additional bits from the portion that has not yet been read. In some cases, the method will return to step S1603 until all written bits have been read (e.g., in a telecommunications system, a complete LLR word or sample, or partial bits if the write operation was previously truncated), or until a stop condition is met, for example, if the desired number of bits have been read from memory (e.g., derived from Table 1 above or any other suitable configuration or determination).

[0129] Because this arrangement and the reading of this data do not follow the actual organization of the dataset, the reading can be performed in a way that reduces the risk of errors if it is interrupted before completion. This is especially useful for data whose meaning and use are more important when the most significant bits of each dataset are compared to the less significant bits in the same dataset.

[0130] Figure 17 An example latency detection arrangement according to this disclosure is shown. This example illustrates an implementation for obtaining an estimate of memory load or congestion by measuring the predicted latency of memory operations. Figure 17The example function can output a memory (DDR) congestion indication. It includes a timer that starts at the beginning of each DDR read or write burst and stops when the DDR transaction completes or a timeout expires (where the timeout or timer can be configured internally). A single complete LLR buffer read or write may require hundreds of DDR read or write bursts, and this timer measures the DDR latency for each burst. Utilizing... Figure 17 In example terminology, a write event begins with a "write burst" and is acknowledged with a "write acknowledgment" once it terminates. A read event begins with a "read request" and is marked by a "read burst." It is expected that in many systems, a "write acknowledgment" or "read burst" should always occur, even if the write or read operation is interrupted (in which case, these events may sometimes be delayed before they occur relative to the interruption time).

[0131] In this example, a filter (which may be configurable, for example) is included to smooth the latency measurement, thereby avoiding premature compression. In some cases, a filter may not be included, and the latency data may be provided to the controller (which may or may not apply any data processing to the data, such as applying a filter-like process or any other processing, before using the data to control read or write operations).

[0132] Example natural language code for a timer could be, for example:

[0133]

[0134] Example natural language code for using a filter could be:

[0135]

[0136] Figure 18An exemplary memory reordering technique in an LLR write operation is illustrated. This reordering technique can be used to implement the techniques provided herein. For example, LLR samples can be written to the LLR reordering memory in transposed order, instead of reading input bits in the relevant order for each dataset (in this example, LLR words or samples). For example, if it is expected that bits to be stored in memory (e.g., DDR) will be read row by row as they are acquired, the LLR samples can be stored in the reordering memory in a column-by-column manner. Thus, using the example of DDR memory, the reordering memory is read row by row when enough samples have been read to form a DDR write burst (typically 512 bits). As a result, bits of equal importance are grouped together, and the highest importance bit is read before bits of lower importance. The number of rows written can be controlled by the controller, for example, using a compression parameter Q_Write, which can be dynamically updated by the controller based on DDR congestion. In some cases, the number of rows written and / or the write operation may also be interrupted by other operations contending for memory access. Upon completion (with or without interruption), the Q(RV) value may be included in the HARO, buffer header, and stored, for example, in DDR memory.

[0137] The implementation of the technique discussed here can be simplified by transposing the dataset in the buffer memory relative to the order in which intermediate memory is read to write data to final memory (e.g., DDR), and this additional step provides an efficient implementation of the technique. In this example, reading bits to be stored row by row (in intermediate memory) can be associated with storing data words column by column (in intermediate memory), and similarly, reading bits to be stored column by column (in intermediate memory) can be associated with storing data words row by row (in intermediate memory).

[0138] Figure 19 An exemplary memory reordering technique is shown in an LLR read operation. This reflects... Figure 18 The discussion involves reading bits from memory in one direction and associating them with a dataset read in the transposed direction. In this example, bits are read row by row in DDR memory and stored in intermediate memory, from which the dataset can be reconstructed by reading column by column.

[0139] In such Figure 9 In the system shown, the number of lines read can be controlled by the decompression parameter Q_read, which can be dynamically updated by the compression controller based on DDR congestion and the associated HARQ buffer header Q(RV) value.

[0140] It should be understood that in some cases, bits may not be available to obtain a complete DDR sample (e.g., if the write is truncated or interrupted). Furthermore, in some cases, the write itself may be truncated or interrupted. Therefore, as mentioned above, in some cases, an incomplete LLR sample can sometimes be obtained by filling in the unread portions of the LLR (because they were not previously stored and / or because they were not read).

[0141] Although Figure 18 and 19 The diagram illustrates data represented as a two-dimensional array, but it should be understood that this is a schematic representation, and appropriate data structures may be implemented differently in other situations. For example, as... Figure 20 The diagram illustrates an example of bit ordering in memory, where data can be stored in a list or table (e.g., a one-dimensional array). In this case, once data from the dataset (e.g., LLR samples) has been provided to memory in the expected order, the data will be rearranged in the appropriate order within memory. In this scenario, data can be read from memory starting at the beginning of the data structure until the end is reached or the read operation is interrupted. This is similar to... Figure 18 and 19 The data is written to and read from, but different data structures are used. Those skilled in the art will also understand that other suitable data structures can also be used.

[0142] While the example implementation here primarily relies on writing or reading the next most significant bit of a dataset before performing an operation on the bit at the same position on the next dataset (or, if already on the last dataset, the next significant bit in the first dataset), it should be understood that more than one bit can be written or read from each dataset or LLR sample at a time. For example, the system could utilize pairs of bits and write / read two bits of each word in each loop (unless only one bit remains in a word). In other cases, a variable number of bits can be used, chosen between 1 and a suitable number n.

[0143] From one perspective, LLR samples can be viewed as datasets, and in some cases, each dataset is a bit word W. i It has N ordered bits W i (0) to W i (N-1), where N > 2. In some examples, this is achieved by first reading or writing each word W. i All W i (0), then read or write all W i (1), all W i(2) etc., until the stopping condition is met and / or until the operation is interrupted. In instances where more than one bit is read or written at a time, the dataset can be read or written as follows: First, all W... i (0,1), then all W i (2,3), etc. In another example, the dataset can be read or written as follows: W i (0,1); then W i (2); then W i (3,4,5), etc. This can be based on a predetermined pattern or dynamically adjusted if appropriate.

[0144] Those skilled in the art will understand that, although some of the examples above have been illustrated with two retransmissions (up to RV2), the number of retransmissions may be more or less than two, and the same teachings and techniques will apply equally to such cases. It should also be noted that while the techniques disclosed herein will find specific applications in the telecommunications field, and are not limited to these specific application areas, for example, with the use of 5G or New Radio (NR).

[0145] Similarly, while these techniques are intended for use in systems employing incremental redundancy, they can also be used in other arrangements that do not employ incremental redundancy or even any redundancy at all. Some of the technical advantages of these techniques are particularly suitable for data such as LLR data, but other types of data can share similar characteristics and are therefore also well-suited to the techniques discussed here.

[0146] It should be understood that the teachings and techniques provided herein can be applied to any suitable memory, such as a single memory provided using a single device or multiple storage devices. The memory can also be distributed across multiple devices and / or can be virtual memory. In some illustrative examples, the memory can be provided as double data rate "DDR" memory, such as synchronous dynamic random access memory "SDRAM". As will be understood, some of the example features discussed above, while useful in conjunction with the techniques provided herein, should not be construed as limiting the scope of this disclosure. For example, the use of a linear logarithmic compression step is optional.

[0147] Furthermore, the teachings and techniques presented in this article are expected to be particularly useful when using DDR memory, but other types of memory can also be used when implementing these teachings and techniques.

[0148] The invention is defined in the appended claims and is not limited to the examples discussed and shown in the specification and drawings. This disclosure includes exemplary arrangements that fall within the scope of the claims (and other arrangements may also fall within the scope of the appended claims), and may also include exemplary arrangements that do not necessarily fall within the scope of the claims but contribute to understanding the teachings and techniques provided herein.

[0149] Example aspects of this disclosure are given in the following numbered clauses:

[0150] Clause 1. A method for controlling memory operation, the method comprising:

[0151] Identify multiple datasets to be stored in memory, each dataset consisting of two or more bits sorted from most significant bit to least significant bit;

[0152] A first plurality of bits selected from the bits of the plurality of datasets are stored in memory, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of each dataset define the storage portion of each dataset; and

[0153] Multiple additional bits selected from bits of multiple datasets are stored in memory, wherein the multiple additional bits are selected by selecting one or more consecutive additional bits of each dataset, the multiple additional bits being outside the storage portion and including the most significant bit outside the storage portion of each dataset.

[0154] Clause 2. The method according to Clause 1 further includes, when a stop event is detected, stopping the step of storing the additional bits before completing the step of storing the additional bits.

[0155] Clause 3. The method according to Clause 1 or 2, wherein the method further includes

[0156] After the step of storing multiple additional bits, the storage portion for each dataset is updated to include one or more consecutive additional bits stored for each dataset;

[0157] Repeat the steps of storing additional bits and updating until a stopping criterion is met, wherein the stopping criterion includes one or more of the following:

[0158] Each of the multiple datasets is stored entirely in memory, and

[0159] A stop event was detected.

[0160] Clause 4. The method described in Clause 2 or 3, wherein the stop event is triggered by one or more of the following:

[0161] The stop parameter is satisfied, which indicates the number of times the step of repeatedly storing additional bits is repeated;

[0162] The instruction to stop storing multiple datasets in memory;

[0163] The memory load was detected to be higher than a threshold; and

[0164] The memory latency performance was detected to be higher than the threshold.

[0165] Clause 5. The method according to any one of Clauses 2 to 4 further includes, upon detection of a stop event, and upon detection that the storage of the first dataset among a plurality of datasets has been interrupted.

[0166] Clause 6. The method according to Clause 5, wherein the indication includes an indication of the number of bits of the first dataset already stored in memory.

[0167] Clause 7. The method according to any one of Clauses 2 to 6 further includes

[0168] Measuring memory performance; and

[0169] Set the stop parameters based on the measured performance.

[0170] The stop event is triggered by at least satisfying the stop parameters.

[0171] Clause 8. The method according to any of the preceding clauses, wherein selecting one or more consecutive first bits of each dataset comprises selecting only the most significant bit of each dataset as one or more consecutive first bits of each dataset.

[0172] Clause 9. The method according to any of the preceding clauses, wherein selecting one or more consecutive additional bits of each dataset comprises selecting only the most significant bits outside the storage portion of each dataset as one or more consecutive additional bits of each dataset.

[0173] Clause 10. The method according to any of the preceding clauses, wherein each dataset is at least one of the following:

[0174] Log-likelihood ratio "LLR";

[0175] Associated with the encoding bits;

[0176] Representation of the expected value of the encoded bits.

[0177] Clause 11. The method according to any of the preceding clauses, wherein each dataset is a bit word Wi having N ordered bits Wi(0) to Wi(N-1), where N is greater than or equal to 2.

[0178] Clause 12. The method described pursuant to Clause 11 further includes:

[0179] Receive L bits, where L is greater than or equal to 2.

[0180] Multiple bit words are stored in a reordering memory, wherein each bit word is stored in a corresponding row or column of the L rows or columns of the reordering memory;

[0181] The reordered memory is read sequentially by reading column by column or row by row, and the read bits are stored in memory.

[0182] Clause 13. The method described pursuant to Clause 11 or 12 further includes:

[0183] Receive L bits from W0 to WL-1, where L is greater than or equal to 2.

[0184] Storing multiple bit words in a reordered memory with L multiplied by N memory bits M(j) from position j=0 to position j = N×L-1 includes storing each bit word Wi in the reordered memory by storing bit Wi(k) in memory position M(i+k×L).

[0185] Read memory bits M(j) sequentially from j=0 and store the read memory bits in memory.

[0186] Clause 14. The method according to Clause 12 or 13 further includes stopping the reading and storing the read bits in memory when the stop criterion is met.

[0187] Clause 15. The method according to any of the preceding clauses, wherein the memory is a double data rate “DDR” synchronous dynamic random access memory “SDRAM”.

[0188] Clause 16. A method for controlling memory operation, the method comprising:

[0189] Identify multiple datasets to be read from memory, each dataset consisting of two or more bits sorted from most significant bit to least significant bit;

[0190] Read a first plurality of bits selected from bits of a plurality of datasets from memory, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of each dataset read define a portion of the read for each dataset; and

[0191] Read additional bits selected from bits of multiple datasets from memory, wherein the additional bits are selected by selecting one or more consecutive additional bits of each dataset, the additional bits being outside the read portion and including the most significant bit outside the read portion of each dataset.

[0192] Clause 17. The method according to Clause 16 further includes, when a stop event is detected, stopping the reading of additional bits before completing that step.

[0193] Clause 18. The method according to Clause 16 or 17, wherein the method further includes

[0194] After the step of reading multiple additional bits, update the read portion for each dataset to include one or more consecutive additional bits read for each dataset;

[0195] Repeat the steps of reading additional bits and updating until a stopping criterion is met, where the stopping criterion includes one or more of the following:

[0196] Read each and every one of multiple datasets completely from memory.

[0197] A stop event was detected.

[0198] Clause 19. The method described in Clause 17 or 18, wherein the stop event is triggered by one or more of the following:

[0199] The stop parameter is satisfied, which indicates the number of times the step for repeatedly reading additional bits is repeated;

[0200] The instruction to stop reading multiple datasets from memory;

[0201] The memory load was detected to be higher than the threshold;

[0202] The memory latency performance was detected to be higher than a threshold; and

[0203] Based on the indicator, it was determined that an earlier step of storing multiple datasets had been interrupted, and that the first portion of the multiple datasets stored during the earlier step had been fully read.

[0204] Clause 20. The method according to any one of Clauses 17 to 19 further includes, upon detecting a stop event, associating the value with bits of a plurality of datasets not yet read from memory to generate a complete dataset.

[0205] Clause 21. The method according to any one of Clauses 16 to 20, wherein selecting one or more consecutive first bits of each dataset comprises selecting only the most significant bit of each dataset as one or more consecutive first bits of each dataset.

[0206] Clause 22. The method according to any one of Clauses 16 to 21, wherein selecting one or more consecutive additional bits of each dataset comprises selecting only the most significant bits outside the read portion of each dataset as one or more consecutive additional bits of each dataset.

[0207] Clause 23. The method according to any one of Clauses 16 to 22, wherein, upon detection that an earlier step of storing multiple datasets has been interrupted and that portions of the multiple datasets stored during the earlier step have all been read, a value is associated with bits of the multiple datasets other than the first portion to generate a complete dataset.

[0208] Clause 24. The method according to any one of Clauses 16 to 23, wherein each dataset is at least one of the following:

[0209] Log-likelihood ratio "LLR";

[0210] Associated with the encoding bits;

[0211] Representation of the expected value of the encoded bits.

[0212] Clause 25. The method according to any one of Clauses 16 to 24, wherein each dataset is a bit word Wi having N ordered bits Wi(0) to Wi(N-1), where N is greater than or equal to 2.

[0213] Clause 26. The method pursuant to Clause 25 also includes:

[0214] Receive L bits, where L is greater than or equal to 2.

[0215] When bit words are stored in memory in column-by-column or column-by-column order, the stored bits are read sequentially and stored in the reordering memory by writing the read bits into the reordering memory in row-by-row or column-by-column order respectively, thereby storing each bit word in the corresponding row or column of the L rows or L columns of the reordering memory.

[0216] Clause 27. The method according to Clause 25 or 26 further includes stopping the reading and storing the read bits in a reordered memory when the stop criterion is met.

[0217] Clause 28. The method according to any one of Clauses 16 to 27, wherein the memory is a double data rate “DDR” synchronous dynamic random access memory “SDRAM”.

[0218] Clause 29. A controller for controlling memory operations, the controller being configured to:

[0219] Identify multiple datasets to be stored in memory, each dataset consisting of two or more bits sorted from most significant bit to least significant bit;

[0220] The memory stores a first plurality of bits selected from bits of a plurality of datasets, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of each dataset define a storage portion of each dataset; and

[0221] Multiple additional bits selected from bits of multiple datasets are stored in memory, wherein the multiple additional bits are selected by selecting one or more consecutive additional bits of each dataset, the additional bits being outside the storage portion and including the most significant bit outside the storage portion of each dataset.

[0222] Clause 30. The controller as described in Clause 29, wherein the controller is further configured to implement the method described in any one of Clauses 2 to 15.

[0223] Clause 31. A controller for controlling memory operations, the controller being configured to:

[0224] Identify multiple datasets to be read from memory, each dataset consisting of two or more bits sorted from most significant bit to least significant bit;

[0225] Read a first plurality of bits selected from bits of a plurality of datasets from memory, wherein the first plurality of bits are selected by selecting one or more consecutive first bits of each dataset, including the most significant bit of each dataset, wherein the one or more consecutive first bits of each dataset read define a portion of the read for each dataset; and

[0226] Read additional bits selected from bits of multiple datasets from memory, wherein the additional bits are selected by selecting one or more consecutive additional bits of each dataset, the additional bits being outside the read portion and including the most significant bit outside the read portion of each dataset.

[0227] Clause 32. The controller as described in Clause 31, wherein the controller is further configured to implement the method described in any one of Clauses 16 to 28.

[0228] Clause 33. A controller system comprising:

[0229] Read the controller according to clauses 29 or 30; and

[0230] Write controller according to clause 31 or 32.

Claims

1. A method of controlling memory operations, the method comprising: identifying a plurality of data sets to be stored in a memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; storing, in the memory, a first plurality of bits selected from the bits of the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more contiguous first bits of each data set, including the most significant bit of each data set, wherein the one or more contiguous first bits of each data set stored define a stored portion of the each data set; and storing, in the memory, in contiguity with the first plurality of bits, a further plurality of bits selected from the bits of the plurality of data sets, wherein the further plurality of bits is selected by selecting one or more contiguous further bits of each data set, the further plurality of bits being outside the stored portion and including the most significant bit outside the stored portion of each data set.

2. The method of claim 1, further comprising, upon detecting a stop event, stopping the storing of the further plurality of bits prior to completion of the storing of the further plurality of bits.

3. The method of claim 1 or 2, wherein the method further comprises updating, after the storing of the further plurality of bits, the stored portion of each data set to include the one or more contiguous further bits of each data set stored; repeating the storing of the further plurality of bits and the updating until a stop criterion is met, wherein the stop criterion comprises one or more of: each of the plurality of data sets is completely stored in the memory, and a stop event is detected.

4. The method of claim 2, wherein the stop event is triggered by one or more of: a stop parameter is met, the stop parameter indicating a number of repetitions of the storing of the further plurality of bits to be repeated; an instruction to stop storing the plurality of data sets in the memory; a detection that a load of the memory is above a threshold; and a detection that a latency performance of the memory is above a threshold.

5. The method of claim 2, further comprising, upon detecting a stop event, and upon detecting that a first data set of the plurality of data sets has not been completely stored in the memory, storing an indication that storage of the first data set has been interrupted.

6. The method of claim 5, wherein the indication comprises an indication of a number of bits of the first data set that have been stored in the memory.

7. The method of claim 2, further comprising measuring a performance of the memory; and setting a stop parameter based on the measured performance, wherein the stop event is triggered at least by the stop parameter being met.

8. The method of claim 1 or 2, wherein selecting the one or more contiguous first bits of each data set comprises selecting only the most significant bit of each data set as the one or more contiguous first bits of each data set.

9. The method of claim 1 or 2, wherein selecting the one or more contiguous further bits of each data set comprises selecting only the most significant bit outside the stored portion of each data set as the one or more contiguous further bits of each data set.

10. The method of claim 1 or 2, wherein each data set is at least one of: a log likelihood ratio "LLR"; associated with an encoded bit; a representation of an expected value of an encoded bit.

11. The method of claim 1 or 2, wherein, the memory is a double data rate "DDR" synchronous dynamic random access memory "SDRAM".

12. A method of controlling memory operations, the method comprising: identifying a plurality of data sets to be read from a memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; reading, from the memory, a first plurality of bits selected from the bits of the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more contiguous first bits of each data set, including the most significant bit of each data set, wherein the one or more contiguous first bits of each data set read defines a read portion of each data set; and reading, from the memory, a further plurality of bits stored contiguously with the first plurality of bits and selected from the bits of the plurality of data sets, wherein the further plurality of bits is selected by selecting one or more contiguous further bits of each data set, the further plurality of bits being outside the read portion and including the most significant bit outside the read portion of each data set.

13. The method of claim 12, further comprising, when a stop event is detected, stopping the step of reading the further plurality of bits before the step of reading the further plurality of bits is completed.

14. The method of claim 12 or 13, wherein the method further comprises after the step of reading the further plurality of bits, updating the read portion for each data set to include the one or more contiguous further bits of each data set read; repeating the step of reading the further plurality of bits and the updating step until a stop criterion is met, wherein the stop criterion comprises one or more of: sufficient reading of each of the plurality of data sets from the memory and detecting a stop event.

15. The method of claim 13, wherein the stop event is triggered by one or more of: satisfying a stop parameter, the stop parameter indicating a number of repetitions of the step of reading the further plurality of bits to repeat; an instruction to stop reading the plurality of data sets from the memory; detecting that a load of the memory is above a threshold; detecting that a latency performance of the memory is above a threshold; and based on an indicator, determining that an earlier step of storing the plurality of data sets has been interrupted and that a first portion of the plurality of data sets stored during the earlier step has been fully read.

16. The method of claim 13, further comprising, when a stop event is detected, associating a value with bits of the plurality of data sets that have not been read from the memory to generate a complete data set.

17. The method of claim 12, wherein selecting the one or more contiguous first bits of each data set comprises selecting only the most significant bit of each data set as the one or more contiguous first bits of each data set. ​ 18. The method of claim 12, wherein selecting one or more contiguous further bits of each data set comprises selecting only the most significant bits outside of a read portion of each data set as the one or more contiguous further bits of each data set.

19. The method of claim 12, wherein, associating values with bits of the plurality of data sets outside of the first portion to generate a complete data set when it is detected that the early step of storing the plurality of data sets has been interrupted and the first portion of the plurality of data sets stored during the early step has been entirely read.

20. The method of claim 12, wherein each data set is at least one of: a log likelihood ratio "LLR"; associated with an encoded bit; a representation of an expected value of an encoded bit.

21. A controller for controlling memory operations, the controller comprising a processor that, when executing processor-executable code, implements a method comprising: identifying a plurality of data sets to be stored in a memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; storing in the memory a first plurality of bits selected from the bits of the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more contiguous first bits of each data set, including the most significant bit of each data set, wherein the one or more contiguous first bits of each data set stored define a stored portion of each data set; and storing in the memory, contiguously with the first plurality of bits, a further plurality of bits selected from the bits of the plurality of data sets, wherein the further plurality of bits is selected by selecting one or more contiguous further bits of each data set, the further bits being outside of the stored portion and including the most significant bit outside of the stored portion of each data set.

22. The controller of claim 21, wherein, the processor, when executing the processor-executable code, also implements the method of any of claims 2 to 11.

23. A controller for controlling memory operations, the controller comprising a processor that, when executing processor-executable code, implements a method comprising: identifying a plurality of data sets to be read from a memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; reading from the memory a first plurality of bits selected from the bits of the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more contiguous first bits of each data set, including the most significant bit of each data set, wherein the one or more contiguous first bits of each data set read define a read portion of each data set; and reading from the memory, contiguously stored with the first plurality of bits and selected from the bits of the plurality of data sets, a further plurality of bits, wherein the further plurality of bits is selected by selecting one or more contiguous further bits of each data set, the further plurality of bits being outside of the read portion and including the most significant bit outside of the read portion of each data set.

24. The controller of claim 23, wherein, the processor, when executing the processor-executable code, also implements the method of any of claims 12 to 20.

25. A controller system comprising: a read controller according to claim 21 or 22; and A write controller according to claim 23 or 24.

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