A single signal source h-bridge driving circuit

Abstract

The application discloses a single-signal-source H-bridge driving circuit, comprising a complementary PWM generating circuit, a first hardware dead zone control circuit and a second hardware dead zone control circuit; the complementary PWM generating circuit comprises a first exclusive OR gate circuit and a second exclusive OR gate circuit, and is used for converting a single PWM signal into two-way complementary signals; the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, and is used for outputting a first driving PWM signal and a second driving PWM signal to obtain a first dead zone control time; the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, and is used for outputting a third driving PWM signal and a fourth driving PWM signal to obtain a second dead zone control time. The application can realize single-PWM-signal driving of an H-bridge, and can realize adjustable dead zone control time based on the cooperation of an inverter circuit and a delay circuit.

Description

Technical Field

[0001] This invention relates to the technical field of circuit design, and in particular to a single-signal-source H-bridge drive circuit. Background Technology

[0002] Traditional H-bridge drivers generally have the following solutions: First, the MCU or DSP directly outputs four complementary dead-time PWM waveforms. This solution relies on the performance of the MCU or DSP, requires at least four I / O ports, and the MCU or DSP must support at least four PWM functions, resulting in high cost. Furthermore, since it is implemented in software, there is a risk of software crashes. Second, traditional hardware driver solutions generally require the MCU or DSP to directly output two PWM waveforms, which also suffers from high cost. Third, integrated H-bridge driver solutions. These solutions have a lower operating frequency, and the dead time cannot be freely modified, resulting in high cost. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a single-signal-source H-bridge driving circuit, which realizes the operation of a single PWM wave driving the H-bridge based on an XOR gate circuit, an inverter circuit, and a delay circuit, thereby reducing hardware costs. Furthermore, the dead-time control is adjustable based on the inverter circuit and the delay circuit for dead-time control.

[0004] To solve the above-mentioned technical problems, the present invention provides a single-signal-source H-bridge driving circuit, including: a complementary PWM generation circuit, a first hardware dead-time control circuit, and a second hardware dead-time control circuit.

[0005] The complementary PWM generation circuit includes a first XOR gate circuit and a second XOR gate circuit. The PWM signal is input into the first XOR gate circuit and the second XOR gate circuit respectively to obtain a first PWM signal and a second PWM signal. The first PWM signal and the second PWM signal are complementary PWM signals.

[0006] The first hardware dead-time control circuit includes a first inverter circuit, a first delay circuit, a second inverter circuit, and a second delay circuit. Based on the first inverter circuit and the first delay circuit, the input first PWM signal is inverted and delayed to output a first drive PWM signal. Based on the second inverter circuit and the second delay circuit, the input first PWM signal is inverted and delayed to output a second drive PWM signal. Based on the first delay time of the first drive PWM signal and the second delay time of the second drive PWM signal, the first dead-time control time is obtained.

[0007] The second hardware dead-time control circuit includes a third inverter circuit, a third delay circuit, a fourth inverter circuit, and a fourth delay circuit. Based on the third inverter circuit and the third delay circuit, the input second PWM signal is inverted and delayed. Based on the third delay time, a third drive PWM signal is output. Based on the fourth inverter circuit and the fourth delay circuit, the input second PWM signal is inverted and delayed. Based on the fourth delay time, a fourth drive PWM signal is output. Based on the third delay time of the third drive PWM signal and the fourth delay time of the fourth drive PWM signal, the second dead-time control time is obtained.

[0008] In one embodiment, the first inverter circuit and the first delay circuit invert and delay the input first PWM signal to output a first driving PWM signal, specifically including:

[0009] The first PWM signal is inverted by the first inverter circuit to obtain a first inverted PWM signal. The first inverted PWM signal is delayed by the first delay circuit to obtain a first delayed PWM signal. The first delayed PWM signal is inverted by the first inverter circuit to obtain a first driving PWM signal.

[0010] In one embodiment, the first XOR gate circuit includes a first XOR gate input terminal, a second XOR gate input terminal, a first XOR gate power supply terminal, a first XOR gate output terminal, and a first resistor;

[0011] The input terminal of the first XOR gate is connected to the output terminal of the PWM signal, the input terminal of the second XOR gate is connected to the first terminal of the first resistor, and the second terminal of the first resistor and the power supply terminal of the first XOR gate are respectively connected to the power supply.

[0012] In one embodiment, the second XOR gate circuit includes a third XOR gate input terminal, a fourth XOR gate input terminal, a first XOR gate ground terminal, and a second XOR gate output terminal;

[0013] The third XOR gate input is connected to the PWM signal output, and the fourth XOR gate input and the first XOR gate ground are grounded.

[0014] In one embodiment, the first hardware dead-time control circuit includes a first inverter circuit and a first delay circuit. The first inverter circuit includes a first inverter input terminal, a first inverter output terminal, a second inverter input terminal, and a second inverter output terminal. The first delay circuit includes a first diode, a second resistor, and a first capacitor.

[0015] The input terminal of the first inverter is connected to the output terminal of the second XOR gate. The output terminal of the first inverter is connected to the cathode of the first diode and the first terminal of the second resistor. The anode of the first diode is connected to the second terminal of the second resistor. The first terminal of the first capacitor is connected to the anode of the first diode and the second terminal of the second resistor. The second terminal of the first capacitor is grounded. The input terminal of the second inverter is connected to the first terminal of the first capacitor, the anode of the first diode, and the second terminal of the second resistor.

[0016] In one embodiment, the first hardware dead-time control circuit includes a second inverter circuit and a second delay circuit, wherein the second inverter circuit includes a third inverter input terminal, a third inverter output terminal, a fourth inverter input terminal, and a fourth inverter output terminal, and the second delay circuit includes a second diode, a third resistor, and a second capacitor.

[0017] The input terminal of the third inverter is connected to the output terminal of the second XOR gate. The output terminal of the third inverter is connected to the positive terminal of the second diode and the first terminal of the third resistor. The negative terminal of the second diode is connected to the second terminal of the third resistor. The first terminal of the second capacitor is connected to the negative terminal of the second diode and the second terminal of the third resistor. The second terminal of the second capacitor is grounded. The input terminal of the fourth inverter is connected to the first terminal of the second capacitor, the negative terminal of the second diode, and the second terminal of the third resistor.

[0018] In one embodiment, the second hardware dead-time control circuit includes a third inverter circuit and a third delay circuit, wherein the third inverter circuit includes a fifth inverter input terminal, a fifth inverter output terminal, a sixth inverter input terminal and a sixth inverter output terminal, and the third delay circuit includes a third diode, a fourth resistor and a third capacitor;

[0019] The input terminal of the fifth inverter is connected to the output terminal of the first XOR gate. The output terminal of the fifth inverter is connected to the negative terminal of the third diode and the first terminal of the fourth resistor. The positive terminal of the third diode is connected to the second terminal of the fourth resistor. The first terminal of the third capacitor is connected to the positive terminal of the third diode and the second terminal of the fourth resistor. The second terminal of the third capacitor is grounded. The input terminal of the sixth inverter is connected to the first terminal of the third capacitor, the positive terminal of the third diode, and the second terminal of the fourth resistor.

[0020] In one embodiment, the second hardware dead-time control circuit includes a fourth inverter circuit and a fourth delay circuit, wherein the fourth inverter circuit includes a seventh inverter input terminal, a seventh inverter output terminal, an eighth inverter input terminal and an eighth inverter output terminal, and the fourth delay circuit includes a fourth diode, a fifth resistor and a fourth capacitor;

[0021] The input terminal of the seventh inverter is connected to the output terminal of the first XOR gate. The output terminal of the seventh inverter is connected to the positive terminal of the fourth diode and the first terminal of the fifth resistor. The negative terminal of the fourth diode is connected to the second terminal of the fifth resistor. The first terminal of the fourth capacitor is connected to the negative terminal of the fourth diode and the second terminal of the fifth resistor. The second terminal of the fourth capacitor is grounded. The input terminal of the eighth inverter is connected to the first terminal of the fourth capacitor, the negative terminal of the fourth diode, and the second terminal of the fifth resistor.

[0022] In one embodiment, the H-bridge driving circuit with a single signal source provided by the present invention further includes an H-bridge inverter circuit, wherein the H-bridge inverter circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor.

[0023] In one embodiment, the first driving PWM signal is used to drive the first MOSFET, the second driving PWM signal is used to drive the second MOSFET, the third driving PWM signal is used to drive the third MOSFET, and the fourth driving PWM signal is used to drive the fourth MOSFET.

[0024] This invention provides a single-signal-source H-bridge driving circuit, which, compared with the prior art, has the following advantages:

[0025] The H-bridge driver circuit includes a complementary PWM generation circuit, a first hardware dead-time control circuit, and a second hardware dead-time control circuit. The complementary PWM generation circuit includes a first XOR gate circuit and a second XOR gate circuit, used to convert a single PWM signal into two complementary signals. The first hardware dead-time control circuit includes a first inverter circuit, a first delay circuit, a second inverter circuit, and a second delay circuit. It outputs a first driving PWM signal based on the first inverter circuit and the first delay circuit, and outputs a second driving PWM signal based on the second inverter circuit and the second delay circuit. The first dead-time control time is obtained based on the first delay time of the first driving PWM signal and the second delay time of the second driving PWM signal. The second hardware dead-time control circuit includes a third inverter circuit, a third delay circuit, a fourth inverter circuit, and a fourth delay circuit. It outputs a third driving PWM signal based on the third inverter circuit and the third delay circuit, and outputs a fourth driving PWM signal based on the fourth inverter circuit and the fourth delay circuit. The fourth dead-time control time is obtained based on the third delay time of the third driving PWM signal and the fourth delay time of the fourth driving PWM signal. Compared with the prior art, the technical solution of the present invention is based on XOR gate circuit, inverter circuit and delay circuit to realize the operation of H bridge by a single PWM wave, which reduces hardware cost. Moreover, the dead time control is achieved by using inverter circuit in conjunction with delay circuit to control dead time, so that the dead time control time is adjustable. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of an embodiment of an H-bridge driving circuit with a single signal source provided by the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of a complementary PWM generation circuit according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic representation of the truth value of an XOR gate according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the first hardware dead-time control circuit structure according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the second hardware dead-time control circuit structure according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of inverter parameters according to an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1

[0034] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of an H-bridge driver circuit with a single signal source provided by the present invention, as shown below. Figure 1 As shown, the circuit includes a complementary PWM generation circuit 11, a first hardware dead-time control circuit 12, and a second hardware dead-time control circuit 13, as detailed below:

[0035] The complementary PWM generation circuit 11 includes a first XOR gate circuit 111 and a second XOR gate circuit 112. The PWM signal is input to the first XOR gate circuit 111 and the second XOR gate circuit 112 respectively to obtain a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are complementary PWM signals.

[0036] The first hardware dead-time control circuit 12 includes a first inverter circuit 121, a first delay circuit 122, a second inverter circuit 123, and a second delay circuit 124. Based on the first inverter circuit 121 and the first delay circuit 122, the input first PWM signal is inverted and delayed to output a first drive PWM signal. Based on the second inverter circuit 123 and the second delay circuit 124, the input first PWM signal is inverted and delayed to output a second drive PWM signal. Based on the first delay time of the first drive PWM signal and the second delay time of the second drive PWM signal, the first dead-time control time is obtained.

[0037] The second hardware dead-time control circuit 13 includes a third inverter circuit 131, a third delay circuit 132, a fourth inverter circuit 133, and a fourth delay circuit 134. Based on the third inverter circuit 131 and the third delay circuit 132, the input second PWM signal is inverted and delayed. Based on the third delay time, a third drive PWM signal is output. Based on the fourth inverter circuit 133 and the fourth delay circuit 134, the input second PWM signal is inverted and delayed. Based on the fourth delay time, a fourth drive PWM signal is output. Based on the third delay time of the third drive PWM signal and the fourth delay time of the fourth drive PWM signal, the second dead-time control time is obtained.

[0038] In one embodiment, the complementary PWM generation circuit 11 includes a first XOR gate circuit 111 and a second XOR gate circuit 112, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of a complementary PWM generation circuit.

[0039] In one embodiment, the complementary PWM generation circuit 11 further includes a PWM signal output terminal for outputting a PWM signal.

[0040] In one embodiment, the first XOR gate circuit 111 includes a first XOR gate input terminal 1A, a second XOR gate input terminal 1B, a first XOR gate power supply terminal VCC, a first XOR gate output terminal 1Y, and a first resistor R1; wherein, the first XOR gate input terminal 1A is connected to the PWM signal output terminal, the second XOR gate input terminal 1B is connected to the first end of the first resistor R1, the second end of the first resistor R1 and the first XOR gate power supply terminal VCC are respectively connected to the power supply, and the first XOR gate output terminal 1Y is used to output a first PWM signal.

[0041] In one embodiment, the second XOR gate circuit 112 includes a third XOR gate input terminal 2A, a fourth XOR gate input terminal 2B, a first XOR gate ground terminal GND, and a second XOR gate output terminal 2Y; wherein, the third XOR gate input terminal 2A is connected to the PWM signal output terminal, the fourth XOR gate input terminal 2B and the first XOR gate ground terminal GND are grounded, and the second XOR gate output terminal 2Y is used to output a second PWM signal.

[0042] In one embodiment, as shown in the schematic diagram of the complementary PWM generation circuit, since the PWM signal is input to the input terminals 1A and 2A of two XOR gate circuits based on the PWM output terminal, and the other input terminals 1B and 2B of the two XOR gates are connected to the power supply and ground respectively, the output terminals 1Y and 2Y of the two XOR gates can output two complementary PWM waveforms, such as... Figure 3 As shown, Figure 3 This is the true value representation of the XOR gate; and because both complementary PWM signals are converted by the XOR gate, they have the same time delay and the phase difference is very small.

[0043] In one embodiment, two complementary and phase-synchronized first PWM signals and second PWM signals output by the complementary PWM generation circuit 11 are configured such that one signal enters the first hardware dead-time control circuit 12, and the other PWM signal enters the second hardware dead-time control circuit. Preferably, the first PWM signal can be configured to enter the first hardware dead-time control circuit 12, and the second PWM signal can be configured to enter the second hardware dead-time control circuit; alternatively, the first PWM signal can be configured to enter the second hardware dead-time control circuit, and the second PWM signal can be configured to enter the first hardware control circuit.

[0044] In one embodiment, the first hardware dead-time control circuit 12 includes a first inverter circuit 121, a first delay circuit 122, a second inverter circuit 123, and a second delay circuit 124, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of the first hardware dead-time control circuit.

[0045] In one embodiment, the first inverter circuit 121 includes a first inverter input terminal 1211, a first inverter output terminal 1212, a second inverter input terminal 1213, and a second inverter output terminal 1214, and the first delay circuit 122 includes a first diode D1, a second resistor R2, and a first capacitor C1.

[0046] In one embodiment, the first inverter input terminal 1211 is connected to the second XOR gate output terminal 2Y, the first inverter output terminal 1212 is connected to the negative terminal of the first diode D1 and the first terminal of the second resistor R2, the positive terminal of the first diode D1 is connected to the second terminal of the second resistor R2, the first terminal of the first capacitor C1 is connected to the positive terminal of the first diode D1 and the second terminal of the second resistor R2, the second terminal of the first capacitor C1 is grounded, and the second inverter input terminal 1213 is connected to the first terminal of the first capacitor C1, the positive terminal of the first diode D1 and the second terminal of the second resistor R2.

[0047] In one embodiment, the first inverter circuit 121 and the first delay circuit 122 invert and delay the input first PWM signal to output a first driving PWM signal. Specifically, the first inverter circuit 121 performs a first inversion process on the first PWM signal to obtain a first inverted PWM signal, the first delay circuit 122 performs a delay process on the first inverted PWM signal to obtain a first delayed PWM signal, and the first inverter circuit 121 performs a second inversion process on the first delayed PWM signal to obtain the first driving PWM signal.

[0048] In one embodiment, the second inverter circuit 123 includes a third inverter input terminal 1231, a third inverter output terminal 1232, a fourth inverter input terminal 1233, and a fourth inverter output terminal 1234, and the second delay circuit 124 includes a second diode D2, a third resistor R3, and a second capacitor C2.

[0049] In one embodiment, the third inverter input terminal 1231 is connected to the second XOR gate output terminal 2Y, the third inverter output terminal 1232 is connected to the positive terminal of the second diode D2 and the first terminal of the third resistor R3, the negative terminal of the second diode D2 is connected to the second terminal of the third resistor R3, the first terminal of the second capacitor C2 is connected to the negative terminal of the second diode D2 and the second terminal of the third resistor R3, the second terminal of the second capacitor C2 is grounded, and the fourth inverter input terminal 1233 is connected to the first terminal of the second capacitor C2, the negative terminal of the second diode D2 and the second terminal of the third resistor R3.

[0050] In one embodiment, the second inverter circuit 123 and the second delay circuit 124 invert and delay the input first PWM signal to output a second driving PWM signal. Specifically, the second inverter circuit 123 performs a third inversion process on the first PWM signal to obtain a second inverted PWM signal, the second delay circuit 124 performs a delay process on the second inverted PWM signal to obtain a second delayed PWM signal, and the second inverter circuit 123 performs a fourth inversion process on the second delayed PWM signal to obtain a second driving PWM signal.

[0051] In one embodiment, the second hardware dead-time control circuit 13 includes a third inverter circuit 131, a third delay circuit 132, a fourth inverter circuit 133, and a fourth delay circuit 134, as follows: Figure 5 As shown, Figure 5 This is a schematic diagram of the second hardware dead-time control circuit.

[0052] In one embodiment, the third inverter circuit 131 includes a fifth inverter input terminal 1311, a fifth inverter output terminal 1312, a sixth inverter input terminal 1313, and a sixth inverter output terminal 1314, and the third delay circuit 132 includes a third diode D3, a fourth resistor R4, and a third capacitor C3.

[0053] In one embodiment, the fifth inverter input terminal 1311 is connected to the first XOR gate output terminal 1Y, the fifth inverter output terminal 1312 is connected to the negative terminal of the third diode D3 and the first terminal of the fourth resistor R4, the positive terminal of the third diode D3 is connected to the second terminal of the fourth resistor R4, the first terminal of the third capacitor C3 is connected to the positive terminal of the third diode D3 and the second terminal of the fourth resistor R4, the second terminal of the third capacitor C3 is grounded, and the sixth inverter input terminal 1313 is connected to the first terminal of the third capacitor C3, the positive terminal of the third diode D3 and the second terminal of the fourth resistor R4.

[0054] In one embodiment, the third inverter circuit 131 and the third delay circuit 132 invert and delay the input second PWM signal to output a third driving PWM signal. Specifically, the third inverter circuit 131 performs a fifth inversion process on the second PWM signal to obtain a third inverted PWM signal, the third delay circuit 132 performs a delay process on the third inverted PWM signal to obtain a third delayed PWM signal, and the third inverter circuit 131 performs a sixth inversion process on the third delayed PWM signal to obtain a third driving PWM signal.

[0055] In one embodiment, the fourth inverter circuit 133 includes a seventh inverter input terminal 1331, a seventh inverter output terminal 1332, an eighth inverter input terminal 1333, and an eighth inverter output terminal 1334, and the fourth delay circuit includes a fourth diode D4, a fifth resistor R5, and a fourth capacitor C4.

[0056] In one embodiment, the seventh inverter input terminal 1331 is connected to the first XOR gate output terminal 1Y, the seventh inverter output terminal 1332 is connected to the positive terminal of the fourth diode D4 and the first terminal of the fifth resistor R5, the negative terminal of the fourth diode D4 is connected to the second terminal of the fifth resistor R5, the first terminal of the fourth capacitor C4 is connected to the negative terminal of the fourth diode D4 and the second terminal of the fifth resistor R5, the second terminal of the fourth capacitor C4 is grounded, and the eighth inverter input terminal 1333 is connected to the first terminal of the fourth capacitor C4, the negative terminal of the fourth diode D4 and the second terminal of the fifth resistor R5.

[0057] In one embodiment, the fourth inverter circuit 133 and the fourth delay circuit 134 invert and delay the input second PWM signal to output a fourth driving PWM signal. Specifically, the fourth inverter circuit 133 performs a seventh inversion process on the second PWM signal to obtain a fourth inverted PWM signal, the fourth delay circuit 134 performs a delay process on the fourth inverted PWM signal to obtain a fourth delayed PWM signal, and the fourth inverter circuit 133 performs a fourth inversion process on the fourth delayed PWM signal to obtain a fourth driving PWM signal.

[0058] The first hardware dead-time control circuit 12 can be applied to the wireless charging function of the hearing aid charging case. The working process of the first hardware dead-time control circuit 12 is explained as follows:

[0059] In one embodiment, for the first inverter circuit 121 and the first delay circuit 122: the first PWM signal output from the output terminal 2Y of the second XOR gate is input to the first inverter circuit 121 based on the input terminal 1211 of the first inverter, and the first inverted PWM signal is output based on the output terminal 1212 of the first inverter. The output first inverted PWM signal is connected to the second inverter circuit 123 through the first delay circuit 122, which includes the second resistor R2, the first capacitor C1, and the first diode D1, so that the second inverter circuit 123 shapes the waveform of the first inverted PWM signal into a square wave as the final first driving PWM signal, thus avoiding the problem of overshoot in the output waveform.

[0060] When the first PWM signal input to the first inverter input terminal 1211 is a low-level signal, the first inverted PWM signal output through the first inverter circuit 121 is a high-level signal. At this time, the first capacitor C1 in the first delay circuit 122 needs to be charged. Therefore, the first capacitor C1 needs to be charged through the first inverter output terminal 1212. The first inverter output terminal 1212 cannot change abruptly. At this time, the voltage waveform of the first capacitor C1 is a slow, sinusoidal rising curve.

[0061] When the first PWM signal input to the first inverter input terminal 1211 is a high-level signal, the first inverted PWM signal output through the first inverter circuit 121 is a low-level signal. At this time, the first capacitor C1 in the first delay circuit 122 needs to be discharged. Therefore, the first inverter output terminal 1212 needs to be discharged through the first capacitor C1. The first inverter output terminal 1212 cannot change abruptly. At this time, the voltage waveform of the first capacitor C1 is a slow, sinusoidal downward curve.

[0062] When the first inverter output terminal 1212 charges the first capacitor C1, the first diode D1 is reverse-biased and cut off, so current flows through the second resistor R2; when the first capacitor C1 discharges the first inverter output terminal 1212, the first diode D1 is forward-biased and flows through the first diode D1. Therefore, for the first inverter circuit 121 and the first delay circuit 122, the voltage waveform of their capacitors exhibits the characteristics of slow rise and fast fall.

[0063] It can be seen that in the first inverter circuit 121 and the first delay circuit 122, when the input first PWM signal is a high-level signal, based on its slow rise and fast fall characteristics, the output first drive PWM signal will flip along with the first PWM signal as it flips; while when the input first PWM signal is a low-level signal, as the first PWM signal flips, the output first drive PWM signal will respond to the flip of the first PWM signal with a first delay time, wherein the first delay time is the rising edge delay time of the first drive PWM signal.

[0064] In one embodiment, the formula for calculating the first delay time is as follows:

[0065]

[0066] In the formula, U tH The minimum high-level input voltage U of the inverter IHmin U t0 The lowest output voltage U of the inverter is the low level. OLmin U O The lowest output voltage U of the inverter at its high level OHmin The inverter parameters can be based on Figure 6 Make a selection. Figure 6 This is a schematic diagram of inverter parameters.

[0067] In one embodiment, for the second inverter circuit 123 and the second delay circuit 124: when the first PWM signal input to the third inverter input terminal 1231 is a low-level signal, the second inverted PWM signal output through the second inverter circuit 123 is a high-level signal. At this time, the second capacitor C2 in the second delay circuit 124 needs to be charged. Therefore, the second capacitor C2 needs to be charged through the third inverter output terminal 1232. The third inverter output terminal 1232 cannot change abruptly. At this time, the voltage waveform of the second capacitor C2 is a slow, sinusoidal rising curve.

[0068] When the first PWM signal input to the third inverter input terminal 1231 is a high-level signal, the second inverted PWM signal output through the second inverter circuit 123 is a low-level signal. At this time, the second capacitor C2 in the second delay circuit 124 needs to be discharged. Therefore, the third inverter output terminal 1232 needs to be discharged through the second capacitor C2. The second inverter output terminal 1232 cannot change abruptly. At this time, the voltage waveform of the second capacitor C2 is a slow, sinusoidal downward curve.

[0069] When the second capacitor C2 discharges to the output terminal 1232 of the third inverter, the second diode D2 is reverse-biased and cut off, so current flows through the third resistor R3; when the output terminal 1232 of the third inverter charges the second capacitor C2, the second diode D2 is forward-biased and flows through the second diode D2. Therefore, for the second inverter circuit 123 and the second delay circuit 124, the voltage waveform of their capacitors exhibits the characteristics of fast rise and slow fall.

[0070] It can be seen that in the second inverter circuit 123 and the second delay circuit 124, when the input first PWM signal is a low-level signal, based on its fast rise and slow fall characteristics, the output second drive PWM signal will flip along with the first PWM signal while the signal is flipping; and when the input first PWM signal is a high-level signal, when the first PWM signal flips, the output second drive PWM signal will respond to the flipping of the first PWM signal with a second delay time, wherein the second delay time response is the falling edge delay time of the second drive PWM signal.

[0071] In one embodiment, the formula for calculating the second delay time is as follows:

[0072]

[0073] In the formula, U tL The lowest level input voltage U of the inverter ILmax U t0 The lowest output voltage U of the inverter is the low level. OLmin U I The minimum high-level input voltage U of the inverter IHmin The inverter parameters can be based on Figure 6 Make a selection. Figure 6 This is a schematic diagram of inverter parameters.

[0074] In one embodiment, the dead time of the first hardware dead time control circuit 12 is the sum of the first delay time and the second delay time; and based on the calculation formula of the first delay time and the second delay time, it can be seen that by changing the parameters of the resistor and capacitor in the circuit, the dead time can be adjusted, making the control of the dead time more convenient.

[0075] In one embodiment, by coordinating the threshold voltage limit of the inverter and the different rise and fall rates of the capacitor voltage, the two drive PWM signals output by the first hardware dead-time control circuit 12 can be controlled to have a fixed dead time.

[0076] In one embodiment, since the second hardware dead-time control circuit and the first hardware dead-time control circuit 12 have the same circuit structure and the same working process, they will not be described in detail here.

[0077] In one embodiment, the system further includes an H-bridge inverter circuit, wherein the H-bridge inverter circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. Specifically, the first MOS transistor and the third MOS transistor are PMOS transistors, the second MOS transistor and the fourth MOS transistor are NMOS transistors, and the PMOS transistor is turned on at a low level, while the NMOS transistor is turned on at a high level.

[0078] In one embodiment, the first driving PWM signal is used to drive the first MOSFET, the second driving PWM signal is used to drive the second MOSFET, the third driving PWM signal is used to drive the third MOSFET, and the fourth driving PWM signal is used to drive the fourth MOSFET; thus, a single PWM signal drives multiple MOSFETs to turn on or off through the H-bridge driving circuit.

[0079] In summary, this invention discloses a single-signal-source H-bridge driving circuit, a complementary PWM generation circuit, a first hardware dead-time control circuit, and a second hardware dead-time control circuit. The complementary PWM generation circuit includes a first XOR gate circuit and a second XOR gate circuit, used to convert a single PWM signal into two complementary signals. The first hardware dead-time control circuit includes a first inverter circuit, a first delay circuit, a second inverter circuit, and a second delay circuit, used to output a first driving PWM signal and a second driving PWM signal to obtain a first dead-time control time. The second hardware dead-time control circuit includes a third inverter circuit, a third delay circuit, a fourth inverter circuit, and a fourth delay circuit, used to output a third driving PWM signal and a fourth driving PWM signal to obtain a second dead-time control time. This invention can realize the operation of an H-bridge driven by a single PWM signal, and based on the inverter circuit and the delay circuit, the dead-time control time is adjustable.

[0080] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A single-signal-source H-bridge driving circuit, characterized in that, include: Complementary PWM generation circuit, first hardware dead-time control circuit, and second hardware dead-time control circuit; The complementary PWM generation circuit includes a first XOR gate circuit and a second XOR gate circuit. The PWM signal is input into the first XOR gate circuit and the second XOR gate circuit respectively to obtain a first PWM signal and a second PWM signal. The first PWM signal and the second PWM signal are complementary PWM signals. The first hardware dead-time control circuit includes a first inverter circuit, a first delay circuit, a second inverter circuit, and a second delay circuit. Based on the first inverter circuit and the first delay circuit, the input first PWM signal is inverted and delayed to output a first drive PWM signal. Based on the second inverter circuit and the second delay circuit, the input first PWM signal is inverted and delayed to output a second drive PWM signal. Based on the first delay time of the first drive PWM signal and the second delay time of the second drive PWM signal, the first dead-time control time is obtained. The second hardware dead-time control circuit includes a third inverter circuit, a third delay circuit, a fourth inverter circuit, and a fourth delay circuit. Based on the third inverter circuit and the third delay circuit, the input second PWM signal is inverted and delayed. Based on the third delay time, a third drive PWM signal is output. Based on the fourth inverter circuit and the fourth delay circuit, the input second PWM signal is inverted and delayed. Based on the fourth delay time, a fourth drive PWM signal is output. Based on the third delay time of the third drive PWM signal and the fourth delay time of the fourth drive PWM signal, the second dead-time control time is obtained.

2. The H-bridge driving circuit with a single signal source as described in claim 1, characterized in that, The first inverter circuit and the first delay circuit invert and delay the input first PWM signal to output the first drive PWM signal, specifically including: The first PWM signal is inverted by the first inverter circuit to obtain a first inverted PWM signal. The first inverted PWM signal is delayed by the first delay circuit to obtain a first delayed PWM signal. The first delayed PWM signal is inverted by the first inverter circuit to obtain a first driving PWM signal.

3. The H-bridge driving circuit with a single signal source as described in claim 1, characterized in that, The first XOR gate circuit includes a first XOR gate input terminal, a second XOR gate input terminal, a first XOR gate power supply terminal, a first XOR gate output terminal, and a first resistor; The input terminal of the first XOR gate is connected to the output terminal of the PWM signal, the input terminal of the second XOR gate is connected to the first terminal of the first resistor, and the second terminal of the first resistor and the power supply terminal of the first XOR gate are respectively connected to the power supply.

4. The H-bridge driving circuit with a single signal source as described in claim 1, characterized in that, The second XOR gate circuit includes a third XOR gate input terminal, a fourth XOR gate input terminal, a first XOR gate ground terminal, and a second XOR gate output terminal; The third XOR gate input is connected to the PWM signal output, and the fourth XOR gate input and the first XOR gate ground are grounded.

5. The H-bridge driving circuit with a single signal source as described in claim 4, characterized in that, The first hardware dead-time control circuit includes a first inverter circuit and a first delay circuit. The first inverter circuit includes a first inverter input terminal, a first inverter output terminal, a second inverter input terminal, and a second inverter output terminal. The first delay circuit includes a first diode, a second resistor, and a first capacitor. The input terminal of the first inverter is connected to the output terminal of the second XOR gate. The output terminal of the first inverter is connected to the cathode of the first diode and the first terminal of the second resistor. The anode of the first diode is connected to the second terminal of the second resistor. The first terminal of the first capacitor is connected to the anode of the first diode and the second terminal of the second resistor. The second terminal of the first capacitor is grounded. The input terminal of the second inverter is connected to the first terminal of the first capacitor, the anode of the first diode, and the second terminal of the second resistor.

6. The H-bridge driving circuit with a single signal source as described in claim 4, characterized in that, The first hardware dead-time control circuit includes a second inverter circuit and a second delay circuit. The second inverter circuit includes a third inverter input terminal, a third inverter output terminal, a fourth inverter input terminal, and a fourth inverter output terminal. The second delay circuit includes a second diode, a third resistor, and a second capacitor. The input terminal of the third inverter is connected to the output terminal of the second XOR gate. The output terminal of the third inverter is connected to the positive terminal of the second diode and the first terminal of the third resistor. The negative terminal of the second diode is connected to the second terminal of the third resistor. The first terminal of the second capacitor is connected to the negative terminal of the second diode and the second terminal of the third resistor. The second terminal of the second capacitor is grounded. The input terminal of the fourth inverter is connected to the first terminal of the second capacitor, the negative terminal of the second diode, and the second terminal of the third resistor.

7. The H-bridge driving circuit with a single signal source as described in claim 3, characterized in that, The second hardware dead-time control circuit includes a third inverter circuit and a third delay circuit. The third inverter circuit includes a fifth inverter input terminal, a fifth inverter output terminal, a sixth inverter input terminal, and a sixth inverter output terminal. The third delay circuit includes a third diode, a fourth resistor, and a third capacitor. The input terminal of the fifth inverter is connected to the output terminal of the first XOR gate. The output terminal of the fifth inverter is connected to the negative terminal of the third diode and the first terminal of the fourth resistor. The positive terminal of the third diode is connected to the second terminal of the fourth resistor. The first terminal of the third capacitor is connected to the positive terminal of the third diode and the second terminal of the fourth resistor. The second terminal of the third capacitor is grounded. The input terminal of the sixth inverter is connected to the first terminal of the third capacitor, the positive terminal of the third diode, and the second terminal of the fourth resistor.

8. The H-bridge driving circuit with a single signal source as described in claim 3, characterized in that, The second hardware dead-time control circuit includes a fourth inverter circuit and a fourth delay circuit. The fourth inverter circuit includes a seventh inverter input terminal, a seventh inverter output terminal, an eighth inverter input terminal, and an eighth inverter output terminal. The fourth delay circuit includes a fourth diode, a fifth resistor, and a fourth capacitor. The input terminal of the seventh inverter is connected to the output terminal of the first XOR gate. The output terminal of the seventh inverter is connected to the positive terminal of the fourth diode and the first terminal of the fifth resistor. The negative terminal of the fourth diode is connected to the second terminal of the fifth resistor. The first terminal of the fourth capacitor is connected to the negative terminal of the fourth diode and the second terminal of the fifth resistor. The second terminal of the fourth capacitor is grounded. The input terminal of the eighth inverter is connected to the first terminal of the fourth capacitor, the negative terminal of the fourth diode, and the second terminal of the fifth resistor.

9. The H-bridge driving circuit with a single signal source as described in claim 1, characterized in that, It also includes an H-bridge inverter circuit, wherein the H-bridge inverter circuit includes a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET.

10. The H-bridge driving circuit with a single signal source as described in claim 9, characterized in that, The first driving PWM signal is used to drive the first MOSFET, the second driving PWM signal is used to drive the second MOSFET, the third driving PWM signal is used to drive the third MOSFET, and the fourth driving PWM signal is used to drive the fourth MOSFET.

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