Integrated circuit and power module

Abstract

The present application provides an integrated circuit capable of reducing noise effects and operating with appropriate driving capability. It includes: a signal output circuit outputting a timing signal; a first holding circuit inputting a first voltage corresponding to the temperature of a first switching element and the timing signal, holding the first voltage for a first period after the timing signal is input, and outputting the first voltage after the first period; a second holding circuit inputting a second voltage corresponding to the temperature of a second switching element and the timing signal, holding the second voltage for a second period after the timing signal is input, and outputting the second voltage after the second period; a first control circuit controlling the switching of the first switching element based on the first voltage and a first driving signal with a first driving capability corresponding to the temperature of the first switching element; and a second control circuit controlling the switching of the second switching element based on the second voltage and a second driving signal with a second driving capability corresponding to the temperature of the second switching element.

Description

Technical Field

[0001] This invention relates to integrated circuits and power modules. Background Technology

[0002] An IPM (Intelligent Power Module) for a power conversion device is known, which includes a semiconductor chip comprising switching elements such as IGBTs, a diode for temperature sensing, and an integrated circuit (IC) that drives the switching elements based on the detection result of the diode. (For example, see Patent Documents 1-3).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-110677

[0006] Patent Document 2: Japanese Patent Application Publication No. 2013-219633

[0007] Patent Document 3: Japanese Patent Application Publication No. 2018-157670 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] In the IPMs described in Patent Documents 1-3, the driving capability of the switching element is adjusted based on the diode voltage (in other words, the temperature of the switching element). Furthermore, the impact of noise generated during the driving of the switching element on the voltage of the diodes on the same chip is suppressed.

[0010] However, when multiple semiconductor chips as described above are provided for a load (when there are multiple combinations of switching elements and diodes), the noise generated when driving the switching element of one semiconductor chip can sometimes affect the voltage of the diode of another semiconductor chip (generating noise in the voltage).

[0011] The present invention was made in view of the above-mentioned problems, and its object is to provide an integrated circuit and power module that can reduce the impact of noise and operate with appropriate driving capability.

[0012] Technical means for solving technical problems

[0013] The integrated circuit of the present invention, mainly used to solve the above-mentioned problems, includes: a signal output circuit that outputs a timing signal indicating a first timing for switching of a first switching element and a second timing for switching of a second switching element; a first holding circuit that is input with a first voltage corresponding to the temperature of the first switching element and the timing signal, holds the first voltage for a first period after the timing signal is input, and outputs the input first voltage after the first period has elapsed; and a second holding circuit that is input with a second voltage corresponding to the temperature of the second switching element and the timing signal, and holds the first voltage for a first period after the timing signal is input. The circuit comprises: a first control circuit that holds the second voltage for a second period after input, and outputs the input second voltage after the second period; a first control circuit that controls the switching of the first switching element based on the first voltage output from the first holding circuit and a first drive signal for driving the first switching element, with a first drive capability corresponding to the temperature of the first switching element; and a second control circuit that controls the switching of the second switching element based on the second voltage output from the second holding circuit and a second drive signal for driving the second switching element, with a second drive capability corresponding to the temperature of the second switching element.

[0014] Invention Effects

[0015] According to the present invention, an integrated circuit and a power module can be provided that can both reduce the impact of noise and operate with appropriate driving capability. Attached Figure Description

[0016] Figure 1 This is a block diagram showing the overall structure of power module 1.

[0017] Figure 2 This is a block diagram illustrating an example of the structure on the lower arm side.

[0018] Figure 3 This is a circuit diagram illustrating an example of the structure of the edge detection circuit 10.

[0019] Figure 4 This is a waveform diagram showing an example of the waveforms of the signals in the edge detection circuit 10.

[0020] Figure 5 This is a circuit diagram showing an example of the structure of the control circuit 40X.

[0021] Figure 6 This is a diagram showing the relationship between the operation of the drive capability adjustment circuit 50X.

[0022] Figure 7 This is a waveform diagram showing an example of the action waveform of the lower arm side of power module 1.

[0023] Figure 8 This is a block diagram illustrating an example of the structure on the upper arm side.

[0024] Figure 9 This is a block diagram showing a modified example of the structure on the upper arm side. Detailed Implementation

[0025] Based on the description in this specification and the accompanying drawings, at least the following matters are clearly defined.

[0026] ======This implementation method======

[0027] <<<Overall Structure of Power Module 1>>>

[0028] Figure 1 This is a block diagram showing the overall structure of the power module 1 in this embodiment.

[0029] The power module 1 in this embodiment is an IPM (Intelligent Power Module) that drives a three-phase motor 7 as a load based on an instruction from a microcomputer 2. The power module 1 includes semiconductor chips 4U, 4V, 4W, 4X, 4Y, 4Z, LVIC 3, and HVIC 3U, 3V, and 3W.

[0030] Semiconductor chip 4U includes a U-phase switching element 5U and a diode 6U for detecting the temperature of the switching element 5U. Similarly, semiconductor chips 4V, 4W, 4X, 4Y, and 4Z each include switching elements 5V, 5W, 5X, 5Y, and 5Z for each phase (V phase, W phase, X phase, Y phase, W phase), and diodes 6V, 6W, 6X, 6Y, and 6Z for temperature detection.

[0031] In this embodiment, an IGBT (Insulated Gate Bipolar Transistor) is used as the switching element 5U, 5V, 5W, 5X, 5Y, and 5Z. However, it is not limited to an IGBT; for example, it can also be a bipolar transistor or a MOS transistor.

[0032] HVIC 3U, 3V, and 3W are integrated circuits (ICs) that switch the upper arm switching elements 5U, 5V, and 5W of the bridge circuit according to the drive signals InU, InV, and InW input from the microcomputer 2.

[0033] LVIC 3 is an integrated circuit (IC) that switches the switching elements 5X, 5Y, and 5Z on the lower arm of a bridge circuit according to the drive signals InX, InY, and InZ input from the microcomputer 2.

[0034] <<Structural Examples of the Lower Arm Side>>

[0035] Figure 2 This is a block diagram illustrating an example of the structure on the lower arm side.

[0036] like Figure 2 As shown, semiconductor chips 4X, 4Y, 4Z and LVIC 3 are disposed on the lower arm side of power module 1.

[0037] <Structure of Semiconductor Chips>

[0038] As described above, semiconductor chip 4X includes switching element 5X and diode 6X within the same chip.

[0039] Switching element 5X is used to drive the three-phase motor 7. Switching element 5X is turned on and off according to the signal OutX applied to the gate from LVIC 3. When switching element 5X is on, current flows from the collector to the emitter (ground).

[0040] Diode 6X is a temperature sensing diode used to detect the temperature of a chip (more specifically, the operating temperature of the switching element 5X). In semiconductor chip 4X, diode 6X is positioned corresponding to switching element 5X (within a suitable temperature sensing area), with its cathode grounded and its anode connected to the constant current source 20X of LVIC 3. By providing a constant current from the constant current source 20X of LVIC 3 to diode 6X, a temperature-corresponding voltage (forward voltage) is generated in diode 6X. Therefore, based on the voltage generated in diode 6X, the operating temperature of switching element 5X can be detected using the temperature dependence of diode 6X. Figure 2 For simplification, the diode 6X in the semiconductor chip 4X is set to one, but it is not limited to this. For example, multiple diodes 6X can be connected in series.

[0041] Semiconductor chips 4Y and 4Z have the same structure as semiconductor chip 4X, so their description is omitted.

[0042] Furthermore, any one of semiconductor chips 4X, 4Y, and 4Z (here designated semiconductor chip 4X) is equivalent to the "first semiconductor chip". Additionally, the switching element 5X disposed in semiconductor chip 4X is equivalent to the "first switching element", and diode 6X is equivalent to the "first diode". Furthermore, the output (voltage TiX) of diode 6X is equivalent to the "first voltage".

[0043] In addition, any one other than the first semiconductor chip (here, semiconductor chip 4Y) corresponds to the "second semiconductor chip". Further, the switching element 5Y provided in the semiconductor chip 4Y corresponds to the "second switching element", and the diode 6Y corresponds to the "second diode". Further, the output (voltage TiY) of the diode 6Y corresponds to the "second voltage".

[0044] <Structure of LVIC3>

[0045] LVIC 3 has a function of adjusting the driving capabilities of the switching elements 5X, 5Y, and 5Z according to the operating temperatures of the respective switching elements 5X, 5Y, 5Z (voltages of the diodes 6X, 6Y, 6Z). As Figure 2 shown, LVIC3 includes an edge detection circuit 10, constant current sources 20X, 20Y, 20Z, sample-and-hold circuits 30X, 30Y, 30Z, and control circuits 40X, 40Y, 40Z. In addition, circuits other than the edge detection circuit 10 in the above circuits are provided corresponding to the semiconductor chips 4X, 4Y, 4Z (X-phase, Y-phase, Z-phase), respectively. Since the structures of the above respective circuits (circuits other than the edge detection circuit 10) are the same in each phase, the part corresponding to the X-phase (semiconductor chip 4X: the first semiconductor chip) will be mainly described below, and other descriptions will be omitted.

[0046] The edge detection circuit 10 detects the falling edges and rising edges of the drive signals InX, InY, InZ input from the microcomputer 2 to LVIC 3, and outputs a signal Hold including pulses having a prescribed pulse width according to the detection results. In the present embodiment, the edge detection circuit 10 corresponds to the "signal output circuit", and the signal Hold corresponds to the "timing signal" indicating the timing for switching the switching elements 5X, 5Y, 5Z. In addition, the details of the edge detection circuit 10 will be described later.

[0047] The constant current source 20X generates a prescribed constant current from the power supply voltage VCC and supplies it to the anode of the diode 6X.

[0048] The sample-and-hold circuit 30X has a function of holding the output (voltage TiX) of the diode 6X for a certain period based on the signal Hold. Specifically, the output (voltage TiX) of the diode 6X and the signal Hold are input to the sample-and-hold circuit 30X. Then, the sample-and-hold circuit 30X holds the voltage TiX for a certain period (first period) corresponding to the pulse width after the pulse of the signal Hold (described later) is input, and after a certain period, directly outputs the input voltage TiX. That is, the output (voltage ToX) of the sample-and-hold circuit 30X is fixed during the generation period of the pulse of the signal Hold, and is the same as the output (voltage TiX) of the diode 6X during other periods (refer to Figure 6Despite Figure 2 Not shown in the figure, but as Figure 5 As shown, a resistor 21 and a capacitor 22 are provided between the sample-and-hold circuit 30X and the anode of the diode 6X. The resistor 21 and the capacitor 22 constitute a filter for removing noise.

[0049] The control circuit 40X is a circuit that controls the switching of the switching element 5X based on the voltage ToX output from the sample-and-hold circuit 30X and the drive signal InX used to drive the switching element 5X, with a drive capability suitable for the temperature of the switching element 5X. In this embodiment, the control circuit 40X includes a drive capability adjustment circuit 50X and a drive circuit 60X.

[0050] The drive capability adjustment circuit 50X adjusts the drive capability of the drive circuit 60X to the switching element 5X (specifically, the magnitude of the drive current supplied from the drive circuit 60X to the switching element 5X) based on the output of the diode 6X (in this embodiment, the output of the sample and hold circuit 30X).

[0051] The drive circuit 60X drives the switching element 5X with a drive capability corresponding to the output of the drive capability adjustment circuit 50X based on the drive signal InX. An example of the structure of the control circuit 40X (drive capability adjustment circuit 50X, drive circuit 60X) will be described later.

[0052] In this embodiment, the X-phase control circuit 40X corresponds to the "first control circuit," the sample-and-hold circuit 30X corresponds to the "first holding circuit," and the voltage ToX corresponds to the "first voltage." Additionally, the drive signal InX corresponds to the "first drive signal." Similarly, the Y-phase control circuit 40Y corresponds to the "second control circuit," the sample-and-hold circuit 30Y corresponds to the "second holding circuit," and the voltage ToY corresponds to the "second voltage." Furthermore, the drive signal InY corresponds to the "second drive signal."

[0053] In this embodiment, the power module 1, for example, detects the temperature of the switching element 5X of the semiconductor chip 4X via diode 6X and adjusts the driving capability of the switching element 5X based on the result. In this case, to accurately detect the temperature of the switching element 5X, it is necessary to accurately detect the voltage of diode 6X. However, due to the current flowing when switching element 5X is switched, noise is sometimes generated, and this noise is superimposed on the signal connecting diode 6X and LVIC 3 (noise is generated in the voltage TiX of diode 6X). Furthermore, noise may also be generated in the voltages (voltages TiY, TiZ) of diodes 6Y and 6Z of another chip. Similarly, when switching elements of other chips (e.g., switching elements 5Y and 5Z) are switched, noise may sometimes be generated in the output of diode 6X (see reference). Figure 6Therefore, when multiple switching elements are used for a load, not only the diodes on the same chip as the switching element to be driven, but also the diodes on other chips will be affected by noise. Moreover, this noise may cause the switching element to fail to operate with proper drive capability.

[0054] Therefore, in this embodiment, by setting the edge detection circuit 10 and the sample-and-hold circuits 30X, 30Y, and 30Z, the noise impact on the same chip and other chips when driving each switching element is reduced, and the chip can operate with appropriate driving capability.

[0055] <<Edge Detection Circuit 10>>>

[0056] Figure 3 This is a circuit diagram illustrating an example of the structure of the edge detection circuit 10. Figure 4 This is a waveform diagram showing an example of the waveforms of the signals in the edge detection circuit 10.

[0057] like Figure 3 As shown, the edge detection circuit 10 includes pulse generation circuits 11X, 11Y, 11Z and OR gate circuit 12.

[0058] The drive signal InX is input to the pulse generation circuit 11X. Then, the pulse generation circuit 11X outputs a pulse signal O1 containing pulses with a specified pulse width, based on changes in the drive signal InX (logic level switching). For example, in... Figure 4 At time T1, the drive signal InX drops from a high level (hereinafter referred to as H level) to a low level (hereinafter referred to as L level). The pulse generation circuit 11X detects the falling edge of the drive signal InX and outputs a pulse signal O1, which includes a pulse with a pulse width from time T2 to time T3. In other words, the pulse generation circuit 11X delays the start timing of the pulse of the pulse signal O1 relative to the switching timing of the logic level of the drive signal InX. The start timing and pulse width (duration) of the pulse of the pulse signal O1 are determined according to the noise generation conditions (see reference). Figure 6 It is predetermined.

[0059] Similarly, the drive signal InY is input to the pulse generation circuit 11Y. Then, the pulse generation circuit 11Y outputs a pulse signal O2 containing pulses with a specified pulse width based on changes in the drive signal InY (switching of logic levels). For example, in... Figure 4At time T4, the drive signal InY drops from level H to level L. The pulse generation circuit 11Y detects the falling edge of the drive signal InY and outputs a pulse signal O2, which contains a pulse with a pulse width from time T5 to time T6. In other words, the pulse generation circuit 11Y delays the start timing of the pulse of the pulse signal O2 relative to the switching timing of the logic level of the drive signal InY.

[0060] Similarly, the drive signal InZ is input to the pulse generation circuit 11Z. Then, the pulse generation circuit 11Z outputs a pulse signal O3 containing pulses with a specified pulse width, based on changes in the drive signal InZ (logic level switching). Additionally, the pulse generation circuit 11Z sets the pulse start timing of the pulse signal O3. Figure 4 The switching timing of time T8 relative to the logic level of the drive signal InZ (in the context of the time interval T8). Figure 4 The time T7 in the middle is delayed.

[0061] In this embodiment, the pulse generation circuit 11X corresponds to the "first pulse generation circuit", and the pulse signal O1 corresponds to the "first pulse signal". Furthermore, the pulse generation period of the pulse signal O1 (from time T2 to time T3) corresponds to the "first period".

[0062] In this embodiment, the pulse generation circuit 11Y corresponds to the "second pulse generation circuit", and the pulse signal O2 corresponds to the "second pulse signal". Furthermore, the pulse generation period of the pulse signal O2 (from time T5 to time T6) corresponds to the "second period".

[0063] OR gate 12 is a circuit that performs a logical OR operation on pulse signals O1, O2, and O3, and outputs the signal Hold; it is equivalent to an "output circuit." Figure 4 As shown, the signal Hold output from OR gate 12 is the superposition of the pulses O1, O2, and O3. In other words, signal Hold is the timing signal indicating the switching of switching elements 5X, 5Y, and 5Z. For example, in Figure 4 In the signal Hold, the pulse from time T2 to time T3 represents the timing of the switching element 5X switching due to the change in the drive signal InX at time T1; this timing is equivalent to "first timing". Additionally, the pulse from time T5 to time T6 represents the timing of the switching element 5Y switching due to the change in the drive signal InY at time T4; this timing is equivalent to "second timing". In this embodiment ( Figure 4In this circuit, pulses are generated when the drive signals InX, InY, and InZ change from high level to low level (when each switching element is turned on), and pulses are also generated when the drive signals InX, InY, and InZ change from low level to high level (when each switching element is turned off). Alternatively, pulses can be generated only when the signal changes from high level to low level (when each switching element is turned on).

[0064] Thus, in this embodiment, the pulse generation circuits 11X, 11Y, and 11Z delay the start timing of the pulse relative to the switching timing of the logic levels of the drive signals InX, InY, and InZ. Therefore, by generating pulses during periods prone to noise, the impact of noise can be effectively reduced.

[0065] Furthermore, the pulse width of the Hold signal (pulse signals O1 to O3) is shorter than the conduction periods of switching elements 5X, 5Y, and 5Z, respectively. This shortens the time before the detection results of diodes 6X, 6Y, and 6Z are reflected in the adjustment of the drive capability (described later).

[0066] Alternatively, a delay circuit can be provided after the OR gate circuit 12 to delay the Hold signal output from the OR gate circuit 12, without requiring the pulse generation circuits 11X, 11Y, and 11Z to have a delay function. In this case, the effect of noise can also be effectively reduced.

[0067] <<Control Circuit 40X>>

[0068] Figure 5 This is a circuit diagram illustrating an example of the structure of the control circuit 40X. As described above, the control circuit 40X is a circuit that controls the switching of the switching element 5X based on the voltage ToX output from the sample-and-hold circuit 30X and the drive signal InX, with a drive capability suitable for the temperature of the switching element 5X, and the control circuit 40X includes a drive capability adjustment circuit 50X and a drive circuit 60X.

[0069] <Drive Capability Adjustment Circuit 50X>

[0070] The drive capability adjustment circuit 50X is used to adjust the drive capability of the switching element 5X based on the detection result of the diode 6X. Specifically, when the voltage of the diode 6X is low (when the temperature is high), the drive circuit 60X is controlled to increase the drive capability of the switching element 5X; conversely, when the voltage of the diode 6X is high (when the temperature is low), the drive circuit 60X is controlled to decrease the drive capability of the switching element 5X. The drive capability adjustment circuit 50X in this embodiment includes comparators 51 and 52, a selection circuit 54, resistors R1 to R4, and switches SW1 to SW3.

[0071] The voltage ToX output from the sample-and-hold circuit 30X is applied to the inverting input terminal (- terminal) of comparator 51, and the reference voltage Vref1 is applied to the inverting input terminal (+ terminal) of comparator 51. The reference voltage Vref1 is the forward voltage of diode 6X at a temperature between high and medium temperatures (e.g., 110 degrees Celsius). Then, when the voltage at the - terminal (voltage ToX) is higher than the voltage at the + terminal (reference voltage Vref1), comparator 51 outputs an L-level signal, and when the voltage at the - terminal (voltage ToX) is lower than the voltage at the + terminal (reference voltage Vref1), comparator 51 outputs an H-level signal.

[0072] The voltage ToX output from the sample-and-hold circuit 30X is applied to the inverting input terminal (- terminal) of comparator 52, and the reference voltage Vref2 is applied to the inverting input terminal (+ terminal) of comparator 52. Furthermore, the reference voltage Vref2 is a voltage (< reference voltage Vref1) that is the forward voltage of diode 6X at the boundary temperature between medium and low temperatures (e.g., 90 degrees Celsius). Then, when the voltage at the - terminal (voltage ToX) is higher than the voltage at the + terminal (reference voltage Vref2), comparator 52 outputs an L-level signal; when the voltage at the - terminal (voltage ToX) is lower than the voltage at the + terminal (reference voltage Vref2), comparator 52 outputs an H-level signal.

[0073] Selection circuit 54 turns on any one of switches SW1 to SW3 based on the outputs of comparator 51 and comparator 52. The selection method of this selection circuit 44 will be described later. Through this selection, the driving capability of drive circuit 60X to switch element 5X is adjusted.

[0074] Resistors R1 to R4 are connected in series between the power supply voltage VCC2 (e.g., 5V) and ground.

[0075] One end of switch SW1 is connected to the junction between resistors R1 and R2. One end of switch SW2 is connected to the junction between resistors R2 and R3. One end of switch SW3 is connected to the junction between resistors R3 and R4. The other ends of switches SW1, SW2, and SW3 are connected to the non-inverting input terminal (+ terminal) of operational amplifier 61 in the drive circuit 60X described later.

[0076] <Driver Circuit 60X>

[0077] The drive circuit 60X is a circuit that switches (turns on and off) the switching element 5X based on the drive signal InX. Furthermore, the drive circuit 60X drives the switching element with a drive capability corresponding to the output of the drive capability adjustment circuit 50X.

[0078] The driving circuit 60X includes an operational amplifier 61, NMOS transistors 62-64, PMOS transistors 65 and 66, and a resistor 67.

[0079] The output of the drive capability adjustment circuit 50X is applied to the non-inverting input terminal (+ terminal) of operational amplifier 61. The inverting input terminal (- terminal) of operational amplifier 61 is connected to one end of resistor 67 and the source of NMOS transistor 62. Thus, operational amplifier 61 controls NMOS transistor 62, causing the voltage at the - terminal to become the voltage at the + terminal (the output voltage of drive capability adjustment circuit 50X).

[0080] The drain of NMOS transistor 62 is connected to the drain of PMOS transistor 65, and the gate of NMOS transistor 62 is connected to the drain of NMOS transistor 64.

[0081] The drain of NMOS transistor 63 is connected to the drain of PMOS transistor 66. Additionally, a drive signal InX is applied to the gates of NMOS transistors 63 and 64. Furthermore, the sources of NMOS transistors 63 and 64 and the other end of resistor 67 are grounded.

[0082] PMOS transistors 65 and 66 form a current mirror circuit. Furthermore, the drain of PMOS transistor 66 is connected to the gate of switching element 5X. Therefore, a current corresponding to the current flowing through PMOS transistor 66 flows through PMOS transistor 65 and NMOS transistor 62.

[0083] Next, the operation of the drive circuit 60X will be explained.

[0084] When the drive signal InX applied to the gates of NMOS transistors 63 and 64 is at level H, NMOS transistors 63 and 64 are turned on. Consequently, NMOS transistor 62 is turned off, and PMOS transistors 65 and 66, which constitute the current mirror circuit, are also turned off. Furthermore, when NMOS transistor 63 is turned on, it releases charge from the gate of switching element 5X, thus turning off switching element 5X.

[0085] On the other hand, when the drive signal InX applied to the gates of NMOS transistors 63 and 64 is at level L, NMOS transistors 63 and 64 are turned off. Therefore, NMOS transistor 62 turns on, and PMOS transistors 65 and 66, which constitute the current mirror circuit, also turn on. Additionally, NMOS transistor 63 turns off, and PMOS transistor 66 turns on, thereby supplying charge to the gate of switching element 5X, and turning on switching element 5X.

[0086] As described above, the current corresponding to the current flowing through the NMOS transistor 62 flows from the PMOS transistor 66 through the switching element 5X. Furthermore, the operational amplifier 61 controls the NMOS transistor 62 such that the voltage at its negative terminal (the source voltage of the NMOS transistor 62) becomes the voltage at its positive terminal (the output voltage of the drive capability adjustment circuit 50X). More specifically, the voltage generated in the resistor 67 based on the current flowing through the NMOS transistor 62 is applied to the negative terminal of the operational amplifier 61, which controls the current flowing through the NMOS transistor 62 such that the voltage difference between the positive and negative terminals is zero. As a result, the current flowing through the NMOS transistor 62 is determined by the positive terminal voltage and the resistance value of the resistor R67; if the positive terminal voltage increases, the current flowing through the NMOS transistor 62 increases proportionally (voltage-to-current conversion). That is, the current supplied from the PMOS transistor 66 to the switching element 5X is determined by the voltage applied to the positive terminal of the operational amplifier 61. In this embodiment, as described below, if the temperature increases, the voltage at the positive terminal of the operational amplifier 61 increases, and the current flowing through the NMOS transistor 62 (and the PMOS transistor 66) increases.

[0087] <<Adjustment of Driving Capabilities>>

[0088] The on-resistance of each switching element (e.g., switching element 5X) has temperature characteristics; the higher the temperature, the greater the on-resistance.

[0089] If we assume that the current supplied from LVIC 3 to the gate of switching element 5X is constant and independent of temperature, then the driving capability (current supply capability) for driving switching element 5X is insufficient at high temperatures and excessive at low temperatures. That is, at high temperatures, the on-time (switching time) becomes longer, while at low temperatures, the on-time becomes shorter (the higher the temperature, the longer the on-time of switching element 5X).

[0090] Therefore, the drive capability adjustment circuit 50X of this embodiment adjusts the drive capability of the drive circuit 60X to the switching element 5X according to the detection result of the diode 6X.

[0091] Specifically, at low temperatures, the driving capability (current supply capability) of switching element 5X is reduced, and at high temperatures, the driving capability (current supply capability) of switching element 5X is increased. Thus, the current supplied to switching element 5X is adjusted according to temperature. The driving capability adjustment circuits 50Y and 50Z are implemented in the same way.

[0092] In this embodiment, the reference voltage Vref1 is set to correspond to the output voltage (forward voltage) of diode 6X when the temperature of switching element 5X is 90 degrees Celsius. The reference voltage Vref2 is set to correspond to the voltage (forward voltage) of diode 6X when the temperature of switching element 5X is 110 degrees Celsius. Furthermore, as described above, diode 6X has a negative temperature characteristic; its voltage decreases as the temperature rises and increases as the temperature falls. In the following description, the case where the voltage ToX applied to the - terminal of comparator 51, 52 of sample-and-hold circuit 30X is the same as the voltage TiX of diode 6X will be explained.

[0093] Figure 6 This is a diagram showing the relationship between the operation of the drive capability adjustment circuit 50X.

[0094] When the operating temperature of the switching element 5X is low (below 90 degrees Celsius), such as Figure 6 As shown, voltage ToX (voltage TiX) is higher than reference voltages Vref1 and Vref2. Therefore, the outputs of comparators 51 and 52 both become low (L level). At this time (when the outputs of comparators 51 and 52 are both low level), selection circuit 54 turns on switch SW1. Consequently, the voltage (low voltage) resulting from the voltage division of power supply voltage VCC2 through resistors R1-R3 and R4 is applied to the + terminal of operational amplifier 61.

[0095] As a result, the current flowing through the NMOS transistor 62 decreases, and the current supplied from the PMOS transistor 56 to the switching element 5X also decreases (lower driving capability).

[0096] Furthermore, when the operating temperature of the switching element 5X is 90–110 degrees Celsius, such as Figure 6 As shown, the voltage ToX (voltage TiX) is lower than the reference voltage Vref1 but higher than the reference voltage Vref2. Therefore, the output of comparator 51 becomes high level (H), and the output of comparator 52 becomes low level (L). In this case (the output of comparator 51 is high level, and the output of comparator 52 is low level), the selection circuit 54 turns on switch SW2. As a result, the voltage (intermediate voltage) obtained by dividing the power supply voltage VCC2 through resistors R1, R2, R3, and R4 is applied to the positive terminal of operational amplifier 61.

[0097] As a result, the current flowing through the NMOS transistor 62 becomes moderate, and the current supplied from the PMOS transistor 56 to the switching element 5X also becomes moderate (medium driving capability).

[0098] When the operating temperature of the switching element 5X is high (above 110 degrees Celsius), such as Figure 6As shown, voltage ToX (voltage TiX) is lower than reference voltages Vref1 and Vref2. Therefore, the outputs of comparators 51 and 52 both become H level. At this time (when the outputs of comparators 51 and 52 are both H level), selection circuit 54 turns on switch SW3. As a result, the voltage (high voltage) obtained by dividing the power supply voltage VCC2 through resistors R1 and R2-R4 is applied to the + terminal of operational amplifier 61.

[0099] As a result, the current flowing through the NMOS transistor 62 increases, and the current supplied from the PMOS transistor 56 to the switching element 5X also increases (greater driving capability).

[0100] Therefore, in this embodiment, the control circuit 40X of the power module 1 adjusts the driving capability of the switching element 5X according to the temperature of the switching element 5X. The driving capability corresponding to the temperature of the switching element 5X is equivalent to "first driving capability". Similarly, the control circuit 40Y adjusts the driving capability of the switching element 5Y according to the temperature of the switching element 5Y. The driving capability corresponding to the temperature of the switching element 5Y is equivalent to "second driving capability". The control circuit 40Z adjusts the driving capability of the switching element 5Z according to the temperature of the switching element 5Z.

[0101] The methods for adjusting drive capability are not limited to those mentioned above; any method can be used.

[0102] <<Power Module 1 Action Waveform>>

[0103] Figure 7 This is a waveform diagram showing an example of the action waveform of the lower arm side of power module 1.

[0104] Figure 7 An example is shown when the drive signal InX (drive signal for switch element 5X) and drive signal InY (drive signal for switch element 5Y) change.

[0105] For example, at time T1, the drive signal InX switches (falls) from H level to L level. In response, the signal OutX output from drive circuit 60X changes from L level to H level, and switch element 5X turns on. When switch element 5X is driven, noise is generated in the voltage TiX of diode 6X on the same chip from time T2 to time T3. Furthermore, during this period (from time T2 to time T3), noise is also generated in the voltage TiY of diode 6Y on a chip other than the same chip (semiconductor chip 4Y in the figure). Additionally, although not shown, noise is similarly generated in the voltage TiZ of diode 6Z. Thus, if noise is present in voltages TiX, TiY, and TiZ, the accuracy of the drive capability adjustment circuits 50X, 50Y, and 50Z is reduced. For example, the outputs of comparators 51 and 52 may switch due to noise, making it impossible to select the appropriate switch (cannot turn on) among switches SW1 to SW3 by selection circuit 54.

[0106] Therefore, in this embodiment, an edge detection circuit 10 and sample-and-hold circuits 30X to 30Z are provided. The sample-and-hold circuit 30X holds the voltage TiX immediately preceding the pulse generation period of the signal Hold from the edge detection circuit 10 (times T2 to T3), and outputs the input voltage TiX during other periods (periods when no pulse is generated). Thus, the effect (noise) of the anode potential fluctuation of diode 6X is not reflected in the voltage ToX output from the sample-and-hold circuit 30X (noise is removed).

[0107] Furthermore, the sample-and-hold circuits 30Y and 30Z also perform the same processing based on the signal Hold, so that the noise generated in diodes 6Y and 6Z is not reflected in the voltages ToY and ToZ. Therefore, when the switching element 5X is turned on, even if noise is generated in diodes 6X, 6Y, and 6Z, the noise is not reflected in the outputs (voltages ToX, ToY, ToZ) of each sample-and-hold circuit 30X, 30Y, and 30Z.

[0108] Additionally, at time T4, the drive signal InY switches (falls) from H level to L level. In response, the signal OutY output from drive circuit 60Y changes from L level to H level, and switching element 5Y turns on. During this time, from time T5 to time T6, noise is generated in the voltage TiY of diode 6Y, the voltage TiX of diode 6X (and the voltage TiZ of diode 6Z). Even in this case, because the same processing as at times T2 to T3 is performed using the pulse of signal Hold during the period from time T5 to time T6, the noise is not reflected in the outputs (voltages ToX, ToY, ToZ) of each sample-and-hold circuit 30X, 30Y, and 30Z. Although not shown in the figure, the same applies when the level of drive signal InZ changes (when switching element 5Z is driven).

[0109] Therefore, even if noise is generated in the outputs of diodes 6X, 6Y, and 6Z due to the driving of any one of the switching elements 5X, 5Y, and 5Z, the effects of all noise can be prevented from being reflected by the holding action of the edge detection circuit 10 and the sample-and-hold circuits 30X, 30Y, and 30Z.

[0110] Therefore, it can reduce the impact of noise and operate with appropriate driving capability.

[0111] Furthermore, this example illustrates the noise suppression when the drive signal InX switches from H level to L level (when each switching element is on). The same process is performed when the drive signal InX switches from L level to H level (when each switching element is off), thus preventing noise from being reflected. Alternatively, noise suppression can be performed only when the drive signal InX switches from H level to L level (when each switching element is on).

[0112] <<Examples of structures on the upper arm side>>

[0113] Although the structure of the lower arm side has been described in the above embodiments, the present invention can also be applied to the upper arm side. Hereinafter, since the lower arm side has the shape of the above embodiments, the description will be omitted, and the necessary parts on the upper arm side will be described instead.

[0114] Figure 8 This is a block diagram illustrating an example of the structure on the upper arm side.

[0115] like Figure 8 As shown, on the upper arm side, HVIC 3U, 3V, and 3W and semiconductor chips 4U, 4V, and 4W are respectively installed for the three phases (U phase, V phase, and W phase). In addition, level shifting circuits 100U, 100V, and 100W are respectively installed in HVIC 3U, 3V, and 3Z.

[0116] Semiconductor chips 4U, 4V, and 4W each have switching elements 5U, 5V, and 5W, and diodes 6U, 6V, and 6W, respectively. These structures are identical to those on the lower arm sides (semiconductor chips 4X, 4Y, and 4Z), and therefore descriptions are omitted. However, the switching elements 5U, 5V, and 5Z included in semiconductor chips 4U, 4V, and 4W, respectively, supply power to the three-phase motor 7 on the emitter side when a high-voltage power supply (e.g., 600V) is applied to the collector and turned on.

[0117] Any one of the semiconductor chips 4U, 4V, and 4W (here semiconductor chip 4U) is equivalent to "the first semiconductor chip", while any one of the others (here semiconductor chip 4V) is equivalent to "the second semiconductor chip".

[0118] Furthermore, the switching element 5U disposed in the semiconductor chip 4U is equivalent to the "first switching element", and the diode 6U is equivalent to the "first diode". In addition, the output (voltage TiX) of the diode 6U is equivalent to the "first voltage".

[0119] Furthermore, the 5V switching element is equivalent to the "second switching element," and the 6V diode is equivalent to the "first diode." Additionally, the output (voltage TiX) of the 6V diode is equivalent to the "second voltage."

[0120] The HVIC 3U includes a level shifting circuit 100U, an edge detection circuit 10U, a constant current source 20U, a sample-and-hold circuit 30U, and a control circuit 40U (including a drive capability adjustment circuit 50U and a drive circuit 60U). The HVIC 3V and 3W have the same structure. Furthermore, the HVIC 3U is equivalent to the "first integrated circuit," and the HVIC 3V is equivalent to the "second integrated circuit."

[0121] Level shifting circuit 100U converts (shifts) the voltage level of the drive signal InU output from microcomputer 2 to a voltage level that can drive the switching element 5U, and outputs drive signal InU1. Similarly, level shifting circuits 100V and 100W convert the levels of drive signals InV and InW output from microcomputer 2, and output drive signals InV1 and InW1 respectively. Level shifting circuit 100U is equivalent to the "first level shifting circuit", drive signal InU is equivalent to the "first drive signal", and drive signal InU1 is equivalent to the "level-shifted first drive signal". Level shifting circuit 100V is equivalent to the "second level shifting circuit", drive signal InV is equivalent to the "second drive signal", and drive signal InV1 is equivalent to the "level-shifted second drive signal".

[0122] Edge detection circuits 10U, 10V, and 10W have the same structure as edge detection circuit 10, detecting the edges of each signal from drive signals InU1, InV1, and InW1 and outputting the signal Hold. For example... Figure 8 As shown, edge detection circuits 10U, 10V, and 10W are respectively installed in HVIC 3U, 3V, and 3W on the upper arm side. Edge detection circuit 10U is equivalent to the "first signal output circuit", and edge detection circuit 10V is equivalent to the "second signal output circuit". In addition, the signal Hold is equivalent to the "timing signal".

[0123] The sample-and-hold circuit 30U and control circuit 40U (drive capability adjustment circuit 50U and drive circuit 60U) have the same structure as those on the lower arm side, so their description is omitted. Additionally, the structures of HVIC 3V and 3W are also the same as HVIC3U, so their description is omitted. The sample-and-hold circuit 30U is equivalent to the "first holding circuit," and the control circuit 40U is equivalent to the "first control circuit." The sample-and-hold circuit 30V is equivalent to the "second holding circuit," and the control circuit 40V is equivalent to the "second control circuit."

[0124] By adopting such a structure, even on the upper arm side, the impact of noise can be reduced, and movement can be performed with appropriate driving power.

[0125] <<Examples of Deformations on the Upper Arm Side>>

[0126] Figure 9 This is a block diagram illustrating a modified example of the structure on the upper arm side. Figure 9 In the middle, in with Figure 8 The same labels are used to mark parts with the same structure, and the descriptions are omitted. Figure 9 The power module 200 shown includes HVIC300U, 300V, and 300W. The difference between HVIC300U, 300V, and 300W and HVIC 3U, 3V, and 3W is that they do not have separate level shifting circuits 100U, 100V, and 100W.

[0127] In this modified example, the level shifting circuits 100U, 100V, and 100W are located outside the power module 200. Thus, the level shifting circuits 100U, 100V, and 100W can be located outside the power module 200 (HVIC 300U, 300V, 300W).

[0128] ===Summary===

[0129] The above describes a power module 1 according to one embodiment of the present invention. The LVIC 3 on the lower arm side includes an edge detection circuit 10, sample-and-hold circuits 30X, 30Y, and 30Z, and control circuits 40X, 40Y, and 40Z. The edge detection circuit 10 outputs a signal Hold indicating the timing of switching elements 5X, 5Y, and 5Z. The voltage TiX of diode 6X corresponding to the temperature of switching element 5X and the signal Hold are input to the sample-and-hold circuit 30X. The sample-and-hold circuit 30X holds the voltage TiX for a specified period after the pulse input of the signal Hold, and outputs the input voltage TiX after the specified period (the same applies to sample-and-hold circuits 30Y and 30Z). The control circuit 40X controls the switching of switching element 5X with a driving capability corresponding to the temperature of switching element 5X based on the voltage ToX output from the sample-and-hold circuit 30X and the drive signal InX used to drive switching element 5X (the same applies to control circuits 40Y and 40Z). Therefore, it can reduce the impact of noise in each phase and operate with appropriate driving capability.

[0130] In addition, the edge detection circuit 10 outputs a signal Hold indicating the timing of the on and off of the switching elements 5X, 5Y, and 5Z, respectively. Thus, the timing of the on and off of the switching elements 5X, 5Y, and 5Z can suppress the noise generated in the outputs of diodes 6X, 6Y, and 6Z.

[0131] The edge detection circuit 10 includes: a pulse generation circuit 11X, which outputs a pulse signal O1 containing a pulse with a pulse width of a certain duration based on a drive signal InX; a pulse generation circuit 11Y, which outputs a pulse signal O2 containing a pulse with a pulse width of a certain duration based on a drive signal InY; a pulse generation circuit 11Z, which outputs a pulse signal O3 containing a pulse with a pulse width of a certain duration based on a drive signal InZ; and an OR gate circuit 12, which outputs a logical OR of the pulse signals O1, O2, and O3 as a signal Hold. Thus, a signal Hold indicating the timing of switching the switching elements 5X, 5Y, and 5Z can be generated.

[0132] Furthermore, the pulse generation circuit 11X delays the start timing (time T2) of the pulse signal O1 relative to the switching timing (time T1) of the logic level of the drive signal InX. The pulse generation circuit 11Y delays the start timing (time T5) of the pulse signal O2 relative to the switching timing (time T4) of the logic level of the drive signal InY. The pulse generation circuit 11Z delays the start timing (time T8) of the pulse signal O3 relative to the switching timing (time T7) of the logic level of the drive signal InZ. Therefore, pulses can be generated during periods prone to noise, effectively reducing the impact of noise.

[0133] Alternatively, a delay circuit can be provided after the OR gate circuit 12 to delay the Hold signal output from the OR gate circuit 12, without giving the pulse generation circuits 11X, 11Y, and 11Z a delay function. In this case, pulses can be generated during periods prone to noise, effectively reducing the impact of noise.

[0134] Furthermore, the pulse width of the Hold signal (pulse signals O1 to O3) is shorter than the conduction periods of switching elements 5X, 5Y, and 5Z, respectively. This reduces the time that the detection results of diodes 6X, 6Y, and 6Z are not reflected in the adjustment of the drive capability.

[0135] As a lower arm side structure, the power module 1 includes: a semiconductor chip 4X having a switching element 5X and a diode 6X that outputs a voltage TiX corresponding to the temperature of the switching element 5X; a semiconductor chip 4Y having a switching element 5Y and a diode 6Y that outputs a voltage TiY corresponding to the temperature of the switching element 5Y; a semiconductor chip 4Z having a switching element 5Z and a diode 6Z that outputs a voltage TiZ corresponding to the temperature of the switching element 5Z; and the aforementioned LVIC 3 for driving the switching elements 5X, 5Y, and 5Z. This reduces the impact of noise in each phase and allows operation with appropriate driving capability.

[0136] Furthermore, as part of the upper arm side structure, the power module 1 also includes: a semiconductor chip 4U having a switching element 5U and a diode 6U that outputs a voltage TiU corresponding to the temperature of the switching element 5U; and an HVIC 3U for driving the switching element 5U, the HVIC 3U including a level shifting circuit 100U for shifting the level of the drive signal InU used to drive the switching element 5U. Similarly, the V and W phases also include semiconductor chips 4V and HVIC 3V, and semiconductor chips 4W and HVIC 3W. HVIC 3U, 3V, and 3W are respectively equipped with edge detection circuits 10U, 10V, and 10W, sample-and-hold circuits 30U, 30V, and 30W, and control circuits 40U, 40V, and 40W. This reduces the impact of noise on the upper arm side and allows operation with appropriate drive capability.

[0137] The above embodiments are provided to facilitate understanding of the present invention, and are not intended to limit or restrict its interpretation. Furthermore, the present invention can be modified or improved without departing from its spirit, and its equivalents are naturally included.

[0138] Label Explanation

[0139] 1 Power Module

[0140] 2. Microcomputer

[0141] 3 LVIC

[0142] 3U, 3V, 3W HVIC

[0143] 4X, 4Y, 4Z, 4U, 4V, 4W semiconductor chips

[0144] 5X, 5Y, 5Z, 5U, 5V, 5W switching elements

[0145] 6X, 6Y, 6Z, 6U, 6V, 6W diodes

[0146] 7 Three-phase motor

[0147] 10, 10U, 10V, 10W Edge Detection Circuit

[0148] 11X, 11Y, 11Z pulse generation circuit

[0149] 12 OR gate circuits

[0150] 20X, 20Y, 20Z, 20U, 20V, 20W constant current source

[0151] 21 Resistor

[0152] 22 Capacitors

[0153] 30X, 30Y, 30Z, 30U, 30V, 30W Sample and Hold Circuits

[0154] 40X, 40Y, 40Z, 40U, 40V, 40W control circuit

[0155] 50X, 50Y, 50Z, 50U, 50V, 50W drive capability adjustment circuit

[0156] Comparators 51 and 52

[0157] 54 Selection Circuit

[0158] 60X, 60Y, 60Z, 60U, 60V, 60W drive circuits

[0159] 61 Operational Amplifier

[0160] 62, 63, 64 NMOS transistors

[0161] 65, 66 PMOS transistors

[0162] 67 Resistor

[0163] 100U, 100V, 100W Level Shifting Circuit

[0164] 200 power module

[0165] 300U, 300V, 300W HVIC

[0166] resistors R1 to R4

[0167] SW1~SW3 switches

[0168] InX, InY, InZ, InU, InV, InW drive signals

[0169] InU1, InV1, InW1 drive signals

[0170] O1, O2, O3 pulse signals.

Claims

1. An integrated circuit, characterized in that, include: A signal output circuit that outputs a timing signal indicating the first timing of the switching of the first switching element and the second timing of the switching of the second switching element. A first holding circuit is input with a first voltage corresponding to the temperature of the first switching element and a timing signal. After the timing signal is input, the first voltage is held for a first period, and after the first period has elapsed, the input first voltage is output. The second holding circuit is input with a second voltage corresponding to the temperature of the second switching element and the timing signal, holds the second voltage for a second period after the timing signal is input, and outputs the input second voltage after the second period has elapsed; A first control circuit controls the switching of the first switching element based on the first voltage output from the first holding circuit and a first drive signal for driving the first switching element, with a first drive capability corresponding to the temperature of the first switching element. as well as The second control circuit controls the switching of the second switching element based on the second voltage output from the second holding circuit and the second drive signal for driving the second switching element, with a second drive capability corresponding to the temperature of the second switching element.

2. The integrated circuit as described in claim 1, characterized in that, The signal output circuit outputs a timing signal indicating the timing of the first switching element and the second switching element being turned on and off, respectively.

3. The integrated circuit as described in claim 1 or 2, characterized in that, The signal output circuit includes: A first pulse generation circuit generates a first pulse signal based on the first drive signal, the first pulse signal comprising a pulse having the pulse width of the first period; A second pulse generation circuit generates a second pulse signal based on the second drive signal, the second pulse signal comprising a pulse having the pulse width of the second period; and The output circuit outputs the first pulse signal and the second pulse signal as the timing signal.

4. The integrated circuit as described in claim 3, characterized in that, The first pulse generation circuit delays the start timing of the first period of the first pulse signal relative to the switching timing of the logic level of the first drive signal. The second pulse generation circuit delays the start timing of the second period of the second pulse signal relative to the switching timing of the logic level of the second drive signal.

5. The integrated circuit as described in claim 3, characterized in that, It includes a delay circuit for delaying the timing signal output from the output circuit.

6. The integrated circuit as described in any one of claims 1 to 5, characterized in that, The first and second periods are shorter than the periods during which the first and second switching elements are each turned on.

7. A power module, comprising: A first semiconductor chip having a first switching element and a first diode that outputs a first voltage corresponding to the temperature of the first switching element; The second semiconductor chip has a second switching element and a second diode that outputs a second voltage corresponding to the temperature of the second switching element; as well as An integrated circuit, which drives the first switching element and the second switching element. The integrated circuit includes: A signal output circuit that outputs a timing signal indicating a first timing for the switching of the first switching element and a second timing for the switching of the second switching element; A first holding circuit is input with the first voltage and the timing signal, holds the first voltage for a first period after the timing signal is input, and outputs the input first voltage after the first period has elapsed; A second holding circuit is input with the second voltage and the timing signal, holds the second voltage for a second period after the timing signal is input, and outputs the input second voltage after the second period has elapsed; A first control circuit drives the first switching element with a first driving capability corresponding to the temperature of the first switching element based on the first voltage output from the first holding circuit and a first driving signal for driving the first switching element. as well as The second control circuit drives the second switching element with a second driving capability corresponding to the temperature of the second switching element based on the second voltage output from the second holding circuit and a second driving signal for driving the second switching element.

8. A power module, comprising: A first semiconductor chip having a first switching element and a first diode that outputs a first voltage corresponding to the temperature of the first switching element; A first integrated circuit that drives the first switching element and includes a first level shifting circuit that shifts the level of a first driving signal for driving the first switching element. The second semiconductor chip has a second switching element and a second diode that outputs a second voltage corresponding to the temperature of the second switching element; as well as The second integrated circuit drives the second switching element and includes a second level shifting circuit for shifting the level of a second drive signal used to drive the second switching element. The first integrated circuit includes: The first signal output circuit outputs a timing signal that indicates the first switching element is switching and the second switching element is switching. A first holding circuit is input with the first voltage and the timing signal, holds the first voltage for a first period after the timing signal is input, and outputs the input first voltage after the first period has elapsed; as well as A first control circuit controls the switching of the first switching element based on the first voltage output from the first holding circuit and the first drive signal after level shifting, with a first drive capability corresponding to the temperature of the first switching element. The second integrated circuit includes: The second signal output circuit that outputs the timing signal; A second holding circuit is input with the second voltage and the timing signal, holds the second voltage for a second period after the timing signal is input, and outputs the input second voltage after the second period has elapsed; The second control circuit controls the switching of the second switching element with a second driving capability corresponding to the temperature of the second switching element, based on the second voltage output from the second holding circuit and the second driving signal after level shifting.

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